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Janosch
2022-10-10 12:39:30 +01:00
parent 0e8e1e4db6
commit 2327ae7aab
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libopencm3/include/libopencm3/cm3/assert.h
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/** @defgroup debugging Debugging
@ingroup CM3_defines
@brief Macros and functions to aid in debugging
@version 1.0.0
@date 25 September 2012
Two preprocessor defines control the behavior of assertion check macros in
this module. They allow the choice between generated code size and ease of
debugging.
If NDEBUG is defined, all assertion checks are disabled and macros do not
generate any code.
If CM3_ASSERT_VERBOSE is defined, information regarding the position of
assertion checks will be stored in the binary, allowing for more
informative error messages, but also significantly increased code size. As
default assertion checks do not use this information it is only useful if
the application linked with libopencm3 defines its own
cm3_assert_failed_verbose() implementation.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_CM3_ASSERT_H
#define LIBOPENCM3_CM3_ASSERT_H
#include <libopencm3/cm3/common.h>
#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))
#ifdef NDEBUG
# define cm3_assert(expr) (void)0
# define cm3_assert_not_reached() do { } while (1)
#else
# ifdef CM3_ASSERT_VERBOSE
# define cm3_assert(expr) do { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, #expr); \
} \
} while (0)
# define cm3_assert_not_reached() \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, 0)
# else
/** @brief Check if assertion is true.
*
* If NDEBUG macro is defined, this macro generates no code. Otherwise
* cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
* is false.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to check if function
* arguments are within expected ranges and stop execution in case an
* unexpected state is reached.
*
* @param expr expression to check */
# define cm3_assert(expr) do { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed(); \
} \
} while (0)
/** @brief Check if unreachable code is reached.
*
* If NDEBUG macro is defined, this macro generates code for an infinite loop.
* Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
* the macro is ever reached.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to stop execution if an
* unreachable portion of code is reached. */
# define cm3_assert_not_reached() cm3_assert_failed()
# endif
#endif
BEGIN_DECLS
/** @brief Called on a failed assertion.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device. */
void cm3_assert_failed(void) __attribute__((__noreturn__));
/** @brief Called on a failed assertion with verbose messages enabled.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device.
*
* @param file File name where the failed assertion occurred
* @param line Line number where the failed assertion occurred
* @param func Name of the function where the failed assertion occurred
* @param assert_expr Expression that evaluated to false (can be NULL) */
void cm3_assert_failed_verbose(const char *file, int line, const char *func,
const char *assert_expr) __attribute__((__noreturn__));
END_DECLS
#endif
/**@}*/
libopencm3/include/libopencm3/cm3/common.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_COMMON_H
#define LIBOPENCM3_CM3_COMMON_H
#ifdef __cplusplus
/* Declarations need wrapping for C++ */
# define BEGIN_DECLS extern "C" {
# define END_DECLS }
#elif defined(__ASSEMBLER__)
/* skipping for assembly */
#define BEGIN_DECLS .if 0
#define END_DECLS .endif
#else
/* And nothing for C */
# define BEGIN_DECLS
# define END_DECLS
#endif
/* Full-featured deprecation attribute with fallback for older compilers. */
#ifdef __GNUC__
# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))
# else
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated))
# endif
#else
# define LIBOPENCM3_DEPRECATED(x)
#endif
#if defined (__ASSEMBLER__)
#define MMIO8(addr) (addr)
#define MMIO16(addr) (addr)
#define MMIO32(addr) (addr)
#define MMIO64(addr) (addr)
#define BBIO_SRAM(addr, bit) \
(((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
#define BBIO_PERIPH(addr, bit) \
(((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
#else
#include <stdint.h>
#include <stdbool.h>
/* Generic memory-mapped I/O accessor functions */
#define MMIO8(addr) (*(volatile uint8_t *)(addr))
#define MMIO16(addr) (*(volatile uint16_t *)(addr))
#define MMIO32(addr) (*(volatile uint32_t *)(addr))
#define MMIO64(addr) (*(volatile uint64_t *)(addr))
/* Generic bit-band I/O accessor functions */
#define BBIO_SRAM(addr, bit) \
MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
#define BBIO_PERIPH(addr, bit) \
MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
#endif
/* Generic bit definition */
#define BIT0 (1<<0)
#define BIT1 (1<<1)
#define BIT2 (1<<2)
#define BIT3 (1<<3)
#define BIT4 (1<<4)
#define BIT5 (1<<5)
#define BIT6 (1<<6)
#define BIT7 (1<<7)
#define BIT8 (1<<8)
#define BIT9 (1<<9)
#define BIT10 (1<<10)
#define BIT11 (1<<11)
#define BIT12 (1<<12)
#define BIT13 (1<<13)
#define BIT14 (1<<14)
#define BIT15 (1<<15)
#define BIT16 (1<<16)
#define BIT17 (1<<17)
#define BIT18 (1<<18)
#define BIT19 (1<<19)
#define BIT20 (1<<20)
#define BIT21 (1<<21)
#define BIT22 (1<<22)
#define BIT23 (1<<23)
#define BIT24 (1<<24)
#define BIT25 (1<<25)
#define BIT26 (1<<26)
#define BIT27 (1<<27)
#define BIT28 (1<<28)
#define BIT29 (1<<29)
#define BIT30 (1<<30)
#define BIT31 (1<<31)
#endif
libopencm3/include/libopencm3/cm3/cortex.h
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/** @defgroup CM3_cortex_defines Cortex Core Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
/**@{*/
#include <stdbool.h>
#include <stdint.h>
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__asm__ volatile ("CPSIE I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__asm__ volatile ("CPSID I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
* Disable the HardFault mask and enable fault interrupt globally
*/
static inline void cm_enable_faults(void)
{
__asm__ volatile ("CPSIE F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable faults
*
* Mask the HardFault interrupt globally
*/
static inline void cm_disable_faults(void)
{
__asm__ volatile ("CPSID F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if interrupts are masked
*
* Checks, if interrupts are masked (disabled).
*
* @returns true, if interrupts are disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_interrupts(void)
{
register uint32_t result;
__asm__ volatile ("MRS %0, PRIMASK" : "=r" (result));
return result;
}
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked
*
* Checks, if HardFault interrupt is masked (disabled).
*
* @returns bool true, if HardFault interrupt is disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_faults(void)
{
register uint32_t result;
__asm__ volatile ("MRS %0, FAULTMASK" : "=r" (result));
return result;
}
#endif
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts
*
* This function switches the mask of the interrupts. If mask is true, the
* interrupts will be disabled. The result of this function can be used for
* restoring previous state of the mask.
*
* @param[in] mask uint32_t New state of the interrupt mask
* @returns uint32_t old state of the interrupt mask
*/
__attribute__((always_inline))
static inline uint32_t cm_mask_interrupts(uint32_t mask)
{
register uint32_t old;
__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
__asm__ __volatile__("" : : : "memory");
__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
return old;
}
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt
*
* This function switches the mask of the HardFault interrupt. If mask is true,
* the HardFault interrupt will be disabled. The result of this function can be
* used for restoring previous state of the mask.
*
* @param[in] mask uint32_t New state of the HardFault interrupt mask
* @returns uint32_t old state of the HardFault interrupt mask
*/
__attribute__((always_inline))
static inline uint32_t cm_mask_faults(uint32_t mask)
{
register uint32_t old;
__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
__asm__ __volatile__ ("" : : : "memory");
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
#endif
/**@}*/
/*===========================================================================*/
/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
*
* @brief Atomic operation support
*
* @ingroup CM3_cortex_defines
*/
/**@{*/
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline uint32_t __cm_atomic_set(uint32_t *val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) \
__val = (state), \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val)
#endif /* !defined(__DOXYGEN) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare block
*
* This macro disables interrupts for the next command or block of code. The
* interrupt mask is automatically restored after exit of the boundary of the
* code block. Therefore restore of interrupt is done automatically after call
* of return or goto control sentence jumping outside of the block.
*
* @warning The usage of sentences break or continue is prohibited in the block
* due to implementation of this macro!
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* Basic usage of atomic block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // access value as atomic
* } // interrupts is restored automatically
* @endcode
*
* Use of return inside block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t allocval(void)
* {
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
for (uint32_t __CM_SAVER(true), __my = true; __my; __my = false)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare context
*
* This macro disables interrupts in the current block of code from the place
* where it is defined to the end of the block. The interrupt mask is
* automatically restored after exit of the boundary of the code block.
* Therefore restore of interrupt is done automatically after call of return,
* continue, break, or goto control sentence jumping outside of the block.
*
* @note This function is intended for use in for- cycles to enable the use of
* break and contine sentences inside the block, and for securing the atomic
* reader-like functions.
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* Basic usage of atomic context
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* for (int i=0;i < 100; i++) {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value += 100; // access value as atomic
* if ((value % 16) == 0) {
* break; // restore interrupts and break cycle
* }
* } // interrupts is restored automatically
* @endcode
*
* Usage of atomic context inside atomic reader fcn.
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t getnextval(void)
* {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value = value + 3; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_CONTEXT()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_CONTEXT() uint32_t __CM_SAVER(true)
#endif /* defined(__DOXYGEN__) */
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/doc-cm3.h
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/** @mainpage libopencm3 Core CM3
@version 1.0.0
@date 14 September 2012
API documentation for Cortex M3 core features.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup CM3_defines CM3 Defines
@brief Defined Constants and Types for Cortex M3 core features
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup CM3_files Cortex Core Peripheral APIs
* APIs for Cortex Core peripherals
*/
libopencm3/include/libopencm3/cm3/dwt.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_DWT_H
#define LIBOPENCM3_CM3_DWT_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
/**
* @defgroup cm_dwt Cortex-M Data Watch and Trace unit.
* @ingroup CM3_defines
* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
* See "ARMv7-M Architecture Reference Manual"
* and "ARMv6-M Architecture Reference Manual"
* The DWT is an optional debug unit that provides watchpoints, data tracing,
* and system profiling for the processor.
* @{
*/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/** DWT Control register
* Purpose Provides configuration and status information for the DWT block, and
* used to control features of the block
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define DWT_CTRL MMIO32(DWT_BASE + 0x00)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/**
* DWT_CYCCNT register
* Cycle Count Register (Shows or sets the value of the processor cycle
* counter, CYCCNT)
* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
* CYCCNT wraps to zero.
*
* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
* is in Debug state.
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
* register, DWT_CTRL.
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
* register is UNK/SBZP.
*/
#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
/** DWT_CPICNT register
* Purpose Counts additional cycles required to execute multi-cycle
* instructions and instruction fetch stalls.
* Usage constraints: The counter initializes to 0 when software enables its
* counter overflow event by
* setting the DWT_CTRL.CPIEVTENA bit to 1.
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
* register, DWT_CTRL.
* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
* include the profiling counters, this register is UNK/SBZP.
*/
#define DWT_CPICNT MMIO32(DWT_BASE + 0x08)
#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
#define DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
#define DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
#define DWT_PCSR MMIO32(DWT_BASE + 0x1C)
#define DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16)
#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16)
#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16)
/* CoreSight Lock Status Register for this peripheral */
#define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */
#define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* --- DWT_CTRL values ---------------------------------------------------- */
#define DWT_CTRL_NUMCOMP_SHIFT 28
#define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define DWT_CTRL_NOTRCPKT (1 << 27)
#define DWT_CTRL_NOEXTTRIG (1 << 26)
#define DWT_CTRL_NOCYCCNT (1 << 25)
#define DWT_CTRL_NOPRFCCNT (1 << 24)
#define DWT_CTRL_CYCEVTENA (1 << 22)
#define DWT_CTRL_FOLDEVTENA (1 << 21)
#define DWT_CTRL_LSUEVTENA (1 << 20)
#define DWT_CTRL_SLEEPEVTENA (1 << 19)
#define DWT_CTRL_EXCEVTENA (1 << 18)
#define DWT_CTRL_CPIEVTENA (1 << 17)
#define DWT_CTRL_EXCTRCENA (1 << 16)
#define DWT_CTRL_PCSAMPLENA (1 << 12)
#define DWT_CTRL_SYNCTAP_SHIFT 10
#define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT)
#define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT)
#define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT)
#define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT)
#define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT)
#define DWT_CTRL_CYCTAP (1 << 9)
#define DWT_CTRL_POSTCNT_SHIFT 5
#define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT)
#define DWT_CTRL_POSTPRESET_SHIFT 1
#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT)
/**
* CYCCNTENA Enables the Cycle counter.
* 0 = Disabled, 1 = Enabled
* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
*/
#define DWT_CTRL_CYCCNTENA (1 << 0)
#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
/* --- DWT_MASK(x) values -------------------------------------------------- */
#define DWT_MASKx_MASK 0x0F
/* --- DWT_FUNCTION(x) values ---------------------------------------------- */
#define DWT_FUNCTIONx_MATCHED (1 << 24)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define DWT_FUNCTIONx_DATAVADDR1_SHIFT 16
#define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT)
#define DWT_FUNCTIONx_DATAVADDR0_SHIFT 12
#define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT)
#define DWT_FUNCTIONx_DATAVSIZE_SHIFT 10
#define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
#define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
#define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
#define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
#define DWT_FUNCTIONx_LNK1ENA (1 << 9)
#define DWT_FUNCTIONx_DATAVMATCH (1 << 8)
#define DWT_FUNCTIONx_CYCMATCH (1 << 7)
#define DWT_FUNCTIONx_EMITRANGE (1 << 5)
#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
#define DWT_FUNCTIONx_FUNCTION 15
#define DWT_FUNCTIONx_FUNCTION_DISABLED 0
/* Those defined only on ARMv6 */
#if defined(__ARM_ARCH_6M__)
#define DWT_FUNCTIONx_FUNCTION_PCWATCH 4
#define DWT_FUNCTIONx_FUNCTION_DWATCH_R 5
#define DWT_FUNCTIONx_FUNCTION_DWATCH_W 6
#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW 7
#endif /* defined(__ARM_ARCH_6M__)*/
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
bool dwt_enable_cycle_counter(void);
uint32_t dwt_read_cycle_counter(void);
END_DECLS
/**@}*/
#endif /* LIBOPENCM3_CM3_DWT_H */
libopencm3/include/libopencm3/cm3/fpb.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_FPB_H
#define LIBOPENCM3_CM3_FPB_H
/**
* @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit
* @ingroup CM3_defines
* @{
*/
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
#error "Flash Patch and Breakpoint not available in CM0"
#endif
/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
/* --- FPB registers ------------------------------------------------------- */
/* Flash Patch Control (FPB_CTRL) */
#define FPB_CTRL MMIO32(FPB_BASE + 0)
/* Flash Patch Remap (FPB_REMAP) */
#define FPB_REMAP MMIO32(FPB_BASE + 4)
/* Flash Patch Comparator (FPB_COMPx) */
#define FPB_COMP (&MMIO32(FPB_BASE + 8))
/* CoreSight Lock Status Register for this peripheral */
#define FPB_LSR MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */
#define FPB_LAR MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */
/* --- FPB_CTRL values ----------------------------------------------------- */
/* Bits [31:15]: Reserved, read as zero, writes ignored */
#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12)
#define FPB_CTRL_NUM_LIT_MASK (0xf << 8)
#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4)
/* Bits [3:2]: Reserved */
#define FPB_CTRL_KEY (1 << 1)
#define FPB_CTRL_ENABLE (1 << 0)
/* --- FPB_REMAP values ---------------------------------------------------- */
/* TODO */
/* --- FPB_COMPx values ---------------------------------------------------- */
#define FPB_COMP_REPLACE_REMAP (0x0 << 30)
#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30)
#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30)
#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30)
#define FPB_COMP_REPLACE_MASK (0x3 << 30)
/* Bit 29: Reserved */
/* TODO */
/* Bit 1: Reserved */
#define FPB_COMP_ENABLE (1 << 0)
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/itm.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_ITM_H
#define LIBOPENCM3_CM3_ITM_H
/**
* @defgroup cm_itm Cortex-M Instrumentation Trace Macrocell (ITM)
* @ingroup CM3_defines
* @{
*/
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
#error "Instrumentation Trace Macrocell not available in CM0"
#endif
/* --- ITM registers ------------------------------------------------------- */
/* Stimulus Port x (ITM_STIM<sz>(x)) */
#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4)))
#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4)))
#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4)))
/* Trace Enable ports (ITM_TER[x]) */
#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
/* Trace Privilege (ITM_TPR) */
#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
/* Trace Control (ITM_TCR) */
#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
/* CoreSight Lock Status Register for this peripheral */
#define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */
#define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */
/* --- ITM_STIM values ----------------------------------------------------- */
/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
/* Bits 31:1 - RAZ */
#define ITM_STIM_FIFOREADY (1 << 0)
/* --- ITM_TER values ------------------------------------------------------ */
/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
/* --- ITM_TPR values ------------------------------------------------------ */
/*
* Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
* 0: User access allowed to stimulus ports
* 1: Privileged access only to stimulus ports
*/
/* --- ITM_TCR values ------------------------------------------------------ */
/* Bits 31:24 - Reserved */
#define ITM_TCR_BUSY (1 << 23)
#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
/* Bits 15:10 - Reserved */
#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
/* Bits 7:5 - Reserved */
#define ITM_TCR_SWOENA (1 << 4)
#define ITM_TCR_TXENA (1 << 3)
#define ITM_TCR_SYNCENA (1 << 2)
#define ITM_TCR_TSENA (1 << 1)
#define ITM_TCR_ITMENA (1 << 0)
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/memorymap.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
#define LIBOPENCM3_CM3_MEMORYMAP_H
/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
/* Private peripheral bus - Internal */
#define PPBI_BASE (0xE0000000U)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* ITM: Instrumentation Trace Macrocell */
#define ITM_BASE (PPBI_BASE + 0x0000)
/* DWT: Data Watchpoint and Trace unit */
#define DWT_BASE (PPBI_BASE + 0x1000)
/* FPB: Flash Patch and Breakpoint unit */
#define FPB_BASE (PPBI_BASE + 0x2000)
#endif
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define TPIU_BASE (PPBI_BASE + 0x40000)
#endif
/* --- SCS: System Control Space --- */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* ITR: Interrupt Type Register */
#define ITR_BASE (SCS_BASE + 0x0000)
#endif
/* SYS_TICK: System Timer */
#define SYS_TICK_BASE (SCS_BASE + 0x0010)
/* NVIC: Nested Vector Interrupt Controller */
#define NVIC_BASE (SCS_BASE + 0x0100)
/* SCB: System Control Block */
#define SCB_BASE (SCS_BASE + 0x0D00)
/* MPU: Memory protection unit */
#define MPU_BASE (SCS_BASE + 0x0D90)
/* Those defined only on CM0*/
#if defined(__ARM_ARCH_6M__)
/* DEBUG: Debug control and configuration */
#define DEBUG_BASE (SCS_BASE + 0x0DF0)
#endif
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* STE: Software Trigger Interrupt Register */
#define STIR_BASE (SCS_BASE + 0x0F00)
/* ID: ID space */
#define ID_BASE (SCS_BASE + 0x0FD0)
#endif
/**
* @defgroup coresight_registers Coresight Registers
* @{
* CoreSight Lock Status Registers and Lock Access Registers are
* documented for the DWT, ITM, FPB and TPIU peripherals
*/
#define CORESIGHT_LSR_OFFSET 0xfb4
#define CORESIGHT_LAR_OFFSET 0xfb0
/** CoreSight Lock Status Register lock status bit */
#define CORESIGHT_LSR_SLK (1<<1)
/** CoreSight Lock Status Register lock availability bit */
#define CORESIGHT_LSR_SLI (1<<0)
/** CoreSight Lock Access key, common for all */
#define CORESIGHT_LAR_KEY 0xC5ACCE55
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/mpu.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_mpu_defines Cortex-M MPU Defines
*
* @brief <b>libopencm3 Cortex Memory Protection Unit</b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*
* The MPU is available as an option in both ARMv6-M and ARMv7-M, but it has
* more features in v7, particularly in the available attributes.
*
* For more information see the ARM Architecture reference manuals.
*/
/**@{*/
#ifndef LIBOPENCM3_MPU_H
#define LIBOPENCM3_MPU_H
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
/** @defgroup CM3_mpu_registers MPU Registers
* @ingroup CM3_mpu_defines
*
*@{*/
/** MPU_TYPE is always available, even if the MPU is not implemented */
#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
#define MPU_RNR MMIO32(MPU_BASE + 0x08)
#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
#define MPU_RASR MMIO32(MPU_BASE + 0x10)
/**@}*/
/* --- MPU values ---------------------------------------------------------- */
/** @defgroup CM3_mpu_type MPU TYPE register fields
* @ingroup CM3_mpu_defines
* The MPU_TYPE register is always available, even if the MPU is not implemented.
* In that case, the DREGION field will read as 0.
*@{*/
/** v6m/v7m only support a unified MPU (IREGION always 0) */
#define MPU_TYPE_IREGION_LSB 16
#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
/** DREGION is non zero if the MPU is available */
#define MPU_TYPE_DREGION_LSB 8
#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
/** v6m/v7m only support a unifed MPU (Separate always 0) */
#define MPU_TYPE_SEPARATE (1<<0)
/**@}*/
/** @defgroup CM3_mpu_ctrl MPU CTRL register fields
* @ingroup CM3_mpu_defines
* Defines for the Control Register.
*@{*/
#define MPU_CTRL_PRIVDEFENA (1<<2)
#define MPU_CTRL_HFNMIENA (1<<1)
#define MPU_CTRL_ENABLE (1<<0)
/**@}*/
/** @defgroup CM3_mpu_rnr MPU RNR register fields
* @ingroup CM3_mpu_defines
* Defines for the Region Number Register.
*@{*/
#define MPU_RNR_REGION_LSB 0
#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
/**@}*/
/** @defgroup CM3_mpu_rbar MPU RBAR register fields
* @ingroup CM3_mpu_defines
* Defines for the Region Base Address Register.
*@{*/
/** minimum size supported is by writing all ones to ADDR, then reading back */
#define MPU_RBAR_ADDR 0xFFFFFFE0
#define MPU_RBAR_VALID (1<<4)
#define MPU_RBAR_REGION_LSB 0
#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
/**@}*/
/** @defgroup CM3_mpu_rasr MPU RASR register fields
* @ingroup CM3_mpu_defines
* Defines for the Region Attribute and Size Register.
*@{*/
#define MPU_RASR_ATTRS_LSB 16
#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
#define MPU_RASR_SRD_LSB 8
#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
#define MPU_RASR_SIZE_LSB 1
#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
#define MPU_RASR_ENABLE (1 << 0)
/** @defgroup mpu_rasr_attributes MPU RASR Attributes
* @ingroup CM3_mpu_rasr
* Not all attributes are available on v6m.
*
*@{*/
#define MPU_RASR_ATTR_XN (1 << 28)
#define MPU_RASR_ATTR_AP (7 << 24)
#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
#define MPU_RASR_ATTR_TEX (7 << 19)
#define MPU_RASR_ATTR_S (1 << 18)
#define MPU_RASR_ATTR_C (1 << 17)
#define MPU_RASR_ATTR_B (1 << 16)
#define MPU_RASR_ATTR_SCB (7 << 16)
/**@}*/
/**@}*/
/* --- MPU functions ------------------------------------------------------- */
BEGIN_DECLS
END_DECLS
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/nvic.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_nvic_defines Cortex-M NVIC Defines
*
* @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
*
* @date 18 August 2012
*
* LGPL License Terms @ref lgpl_license
*/
/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
/** @defgroup nvic_registers NVIC Registers
* @{
*/
/** ISER: Interrupt Set Enable Registers
* @note 8 32bit Registers
* @note Single register on CM0
*/
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
((iser_id) * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
/** ICER: Interrupt Clear Enable Registers
* @note 8 32bit Registers
* @note Single register on CM0
*/
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
((icer_id) * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
/** ISPR: Interrupt Set Pending Registers
* @note 8 32bit Registers
* @note Single register on CM0
*/
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
((ispr_id) * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
/** ICPR: Interrupt Clear Pending Registers
* @note 8 32bit Registers
* @note Single register on CM0
*/
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
((icpr_id) * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** IABR: Interrupt Active Bit Register
* @note 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
((iabr_id) * 4))
#endif
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
/** IPR: Interrupt Priority Registers
* @note 240 8bit Registers
* @note 32 8bit Registers on CM0, requires word access
*/
#if defined(__ARM_ARCH_6M__)
#define NVIC_IPR32(ipr_id) MMIO32(NVIC_BASE + 0x300 + \
((ipr_id) * 4))
#else
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
(ipr_id))
#endif
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE)
#endif
/**@}*/
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M0, M3 and M4 System Interrupts */
/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts
@ingroup CM3_nvic_defines
IRQ numbers -3 and -6 to -9 are reserved
@{*/
#define NVIC_NMI_IRQ -14
#define NVIC_HARD_FAULT_IRQ -13
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define NVIC_MEM_MANAGE_IRQ -12
#define NVIC_BUS_FAULT_IRQ -11
#define NVIC_USAGE_FAULT_IRQ -10
#endif
/* irq numbers -6 to -9 are reserved */
#define NVIC_SV_CALL_IRQ -5
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define DEBUG_MONITOR_IRQ -4
#endif
/* irq number -3 reserved */
#define NVIC_PENDSV_IRQ -2
#define NVIC_SYSTICK_IRQ -1
/**@}*/
/* @note User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
BEGIN_DECLS
void nvic_enable_irq(uint8_t irqn);
void nvic_disable_irq(uint8_t irqn);
uint8_t nvic_get_pending_irq(uint8_t irqn);
void nvic_set_pending_irq(uint8_t irqn);
void nvic_clear_pending_irq(uint8_t irqn);
uint8_t nvic_get_irq_enabled(uint8_t irqn);
void nvic_set_priority(uint8_t irqn, uint8_t priority);
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
uint8_t nvic_get_active_irq(uint8_t irqn);
void nvic_generate_software_interrupt(uint16_t irqn);
#endif
void reset_handler(void);
void nmi_handler(void);
void hard_fault_handler(void);
void sv_call_handler(void);
void pend_sv_handler(void);
void sys_tick_handler(void);
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void mem_manage_handler(void);
void bus_fault_handler(void);
void usage_fault_handler(void);
void debug_monitor_handler(void);
#endif
END_DECLS
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/scb.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H
/**
* @defgroup cm_scb Cortex-M System Control Block
* @ingroup CM3_defines
*
* The System Control Block is a section of the System Control Space.
* Other members of the SCS are, for instance, DWT, ITM, SYSTICKK.
* The exact details of the SCB are defined in the "Architecture Reference
* Manual" for either ARMv7-M or ARMV6-m.
* @{
*/
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/** @defgroup cm_scb_registers SCB Registers
* @ingroup cm_scb
* @{
*/
/** CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/** ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/** VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/** AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/** SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/** CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/** System Handler Priority 8 bits Registers, SHPR1/2/3.
* @note: 12 8bit Registers
* @note: 2 32bit Registers on CM0, requires word access,
* (shpr1 doesn't actually exist)
*/
#if defined(__ARM_ARCH_6M__)
#define SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
#else
#define SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
#endif
/** SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/** DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/** HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/** MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/** BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/** AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/** ID_PFR0: Processor Feature Register 0 */
#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
/** ID_PFR1: Processor Feature Register 1 */
#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
/** ID_DFR0: Debug Features Register 0 */
#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
/** ID_AFR0: Auxiliary Features Register 0 */
#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
/** ID_MMFR0: Memory Model Feature Register 0 */
#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
/** ID_MMFR1: Memory Model Feature Register 1 */
#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
/** ID_MMFR2: Memory Model Feature Register 2 */
#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
/** ID_MMFR3: Memory Model Feature Register 3 */
#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
/** ID_ISAR0: Instruction Set Attributes Register 0 */
#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
/** ID_ISAR1: Instruction Set Attributes Register 1 */
#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
/** ID_ISAR2: Instruction Set Attributes Register 2 */
#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
/** ID_ISAR3: Instruction Set Attributes Register 3 */
#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
/** ID_ISAR4: Instruction Set Attributes Register 4 */
#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
/** CPACR: Coprocessor Access Control Register */
#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
/** FPCCR: Floating-Point Context Control Register */
#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
/** FPCAR: Floating-Point Context Address Register */
#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
/** FPDSCR: Floating-Point Default Status Control Register */
#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
/** MVFR0: Media and Floating-Point Feature Register 0 */
#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
/** MVFR1: Media and Floating-Point Feature Register 1 */
#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
#endif
/**@}*/
/* --- SCB values ---------------------------------------------------------- */
/**
* @defgroup cm3_scb_cpuid_values SCB_CPUID Values
* @{
*/
/** Implementer[31:24]: Implementer code */
#define SCB_CPUID_IMPLEMENTER_LSB 24
#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
/** Variant[23:20]: Variant number */
#define SCB_CPUID_VARIANT_LSB 20
#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
/** Constant[19:16]
* Reads as 0xF (ARMv7-M) M3, M4
* Reads as 0xC (ARMv6-M) M0, M0+
*/
#define SCB_CPUID_CONSTANT_LSB 16
#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
/** PartNo[15:4]: Part number of the processor */
#define SCB_CPUID_PARTNO_LSB 4
#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
/** Revision[3:0]: Revision number */
#define SCB_CPUID_REVISION_LSB 0
#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
/**@}*/
/**
* @defgroup cm3_scb_icsr_values SCB_ICSR Values
* @{
*/
/** NMIPENDSET: NMI set-pending bit */
#define SCB_ICSR_NMIPENDSET (1 << 31)
/* Bits [30:29]: reserved - must be kept cleared */
/** PENDSVSET: PendSV set-pending bit */
#define SCB_ICSR_PENDSVSET (1 << 28)
/** PENDSVCLR: PendSV clear-pending bit */
#define SCB_ICSR_PENDSVCLR (1 << 27)
/** PENDSTSET: SysTick exception set-pending bit */
#define SCB_ICSR_PENDSTSET (1 << 26)
/** PENDSTCLR: SysTick exception clear-pending bit */
#define SCB_ICSR_PENDSTCLR (1 << 25)
/* Bit 24: reserved - must be kept cleared */
/** Bit 23: reserved for debug - reads as 0 when not in debug mode */
#define SCB_ICSR_ISRPREEMPT (1 << 23)
/** ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
#define SCB_ICSR_ISRPENDING (1 << 22)
/** VECTPENDING[21:12] Pending vector */
#define SCB_ICSR_VECTPENDING_LSB 12
#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
/** RETOBASE: Return to base level */
#define SCB_ICSR_RETOBASE (1 << 11)
/* Bits [10:9]: reserved - must be kept cleared */
/** VECTACTIVE[8:0] Active vector */
#define SCB_ICSR_VECTACTIVE_LSB 0
#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
/**@}*/
/**
* @defgroup cm3_scb_vtor_values SCB_VTOR Values
* @{
*/
/* IMPLEMENTATION DEFINED */
#if defined(__ARM_ARCH_6M__)
#define SCB_VTOR_TBLOFF_LSB 7
#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
#elif defined(CM1)
/* VTOR not defined there */
#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
/* inconsistent datasheet - LSB could be 11 */
/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
#define SCB_VTOR_TBLOFF_LSB 9
#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
#endif
/**@}*/
/**
* @defgroup cm3_scb_aicr_values SCB_AICR Values
* @{
*/
/** VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
/** ENDIANNESS Data endianness bit */
#define SCB_AIRCR_ENDIANESS (1 << 15)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bits [14:11]: reserved - must be kept cleared */
/** PRIGROUP[10:8]: Interrupt priority grouping field */
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_SHIFT 8
/* Bits [7:3]: reserved - must be kept cleared */
#endif
/** SYSRESETREQ System reset request */
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
/** VECTCLRACTIVE clears state information for exceptions */
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** VECTRESET cause local system reset */
#define SCB_AIRCR_VECTRESET (1 << 0)
#endif
/**@}*/
/**
* @defgroup cm3_scb_scr_values SCB_SCR Values
* @{
*/
/* Bits [31:5]: reserved - must be kept cleared */
/** SEVONPEND Send Event on Pending bit */
#define SCB_SCR_SEVONPEND (1 << 4)
/* Bit 3: reserved - must be kept cleared */
/** SLEEPDEEP implementation defined */
#define SCB_SCR_SLEEPDEEP (1 << 2)
/** SLEEPONEXIT sleep when exiting ISR */
#define SCB_SCR_SLEEPONEXIT (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/**@}*/
/**
* @defgroup cm3_scb_ccr_values SCB_CCR Values
* @{
*/
/* Bits [31:10]: reserved - must be kept cleared */
/** STKALIGN set to zero to break things :) */
#define SCB_CCR_STKALIGN (1 << 9)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/** BFHFNMIGN set to attempt ignoring faults in handlers */
#define SCB_CCR_BFHFNMIGN (1 << 8)
/* Bits [7:5]: reserved - must be kept cleared */
/** DIV_0_TRP set to trap on divide by zero*/
#define SCB_CCR_DIV_0_TRP (1 << 4)
#endif
/** UNALIGN_TRP set to trap on unaligned */
#define SCB_CCR_UNALIGN_TRP (1 << 3)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bit 2: reserved - must be kept cleared */
/** USERSETMPEND set to allow unprivileged access to STIR */
#define SCB_CCR_USERSETMPEND (1 << 1)
/** NONBASETHRDENA set to allow non base priority threads */
#define SCB_CCR_NONBASETHRDENA (1 << 0)
#endif
/**@}*/
/* These numbers are designed to be used with the SCB_SHPR() macro */
/* SCB_SHPR1 */
#define SCB_SHPR_PRI_4_MEMMANAGE 0
#define SCB_SHPR_PRI_5_BUSFAULT 1
#define SCB_SHPR_PRI_6_USAGEFAULT 2
#define SCB_SHPR_PRI_7_RESERVED 3
/* SCB_SHPR2 */
#define SCB_SHPR_PRI_8_RESERVED 4
#define SCB_SHPR_PRI_9_RESERVED 5
#define SCB_SHPR_PRI_10_RESERVED 6
#define SCB_SHPR_PRI_11_SVCALL 7
/* SCB_SHPR3 */
#define SCB_SHPR_PRI_12_RESERVED 8
#define SCB_SHPR_PRI_13_RESERVED 9
#define SCB_SHPR_PRI_14_PENDSV 10
#define SCB_SHPR_PRI_15_SYSTICK 11
/* --- SCB_SHCSR values ---------------------------------------------------- */
/* Bits [31:19]: reserved - must be kept cleared */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* USGFAULTENA: Usage fault enable */
#define SCB_SHCSR_USGFAULTENA (1 << 18)
/* BUSFAULTENA: Bus fault enable */
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
/* MEMFAULTENA: Memory management fault enable */
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
#endif
/* SVCALLPENDED: SVC call pending */
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* BUSFAULTPENDED: Bus fault exception pending */
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
/* MEMFAULTPENDED: Memory management fault exception pending */
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
/* USGFAULTPENDED: Usage fault exception pending */
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
/* SYSTICKACT: SysTick exception active */
#define SCB_SHCSR_SYSTICKACT (1 << 11)
/* PENDSVACT: PendSV exception active */
#define SCB_SHCSR_PENDSVACT (1 << 10)
/* Bit 9: reserved - must be kept cleared */
/* MONITORACT: Debug monitor active */
#define SCB_SHCSR_MONITORACT (1 << 8)
/* SVCALLACT: SVC call active */
#define SCB_SHCSR_SVCALLACT (1 << 7)
/* Bits [6:4]: reserved - must be kept cleared */
/* USGFAULTACT: Usage fault exception active */
#define SCB_SHCSR_USGFAULTACT (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* BUSFAULTACT: Bus fault exception active */
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
/* MEMFAULTACT: Memory management fault exception active */
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
/* --- SCB_CFSR values ----------------------------------------------------- */
/* Bits [31:26]: reserved - must be kept cleared */
/* DIVBYZERO: Divide by zero usage fault */
#define SCB_CFSR_DIVBYZERO (1 << 25)
/* UNALIGNED: Unaligned access usage fault */
#define SCB_CFSR_UNALIGNED (1 << 24)
/* Bits [23:20]: reserved - must be kept cleared */
/* NOCP: No coprocessor usage fault */
#define SCB_CFSR_NOCP (1 << 19)
/* INVPC: Invalid PC load usage fault */
#define SCB_CFSR_INVPC (1 << 18)
/* INVSTATE: Invalid state usage fault */
#define SCB_CFSR_INVSTATE (1 << 17)
/* UNDEFINSTR: Undefined instruction usage fault */
#define SCB_CFSR_UNDEFINSTR (1 << 16)
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
#define SCB_CFSR_BFARVALID (1 << 15)
/* Bits [14:13]: reserved - must be kept cleared */
/* STKERR: Bus fault on stacking for exception entry */
#define SCB_CFSR_STKERR (1 << 12)
/* UNSTKERR: Bus fault on unstacking for a return from exception */
#define SCB_CFSR_UNSTKERR (1 << 11)
/* IMPRECISERR: Imprecise data bus error */
#define SCB_CFSR_IMPRECISERR (1 << 10)
/* PRECISERR: Precise data bus error */
#define SCB_CFSR_PRECISERR (1 << 9)
/* IBUSERR: Instruction bus error */
#define SCB_CFSR_IBUSERR (1 << 8)
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
#define SCB_CFSR_MMARVALID (1 << 7)
/* Bits [6:5]: reserved - must be kept cleared */
/* MSTKERR: Memory manager fault on stacking for exception entry */
#define SCB_CFSR_MSTKERR (1 << 4)
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
#define SCB_CFSR_MUNSTKERR (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* DACCVIOL: Data access violation flag */
#define SCB_CFSR_DACCVIOL (1 << 1)
/* IACCVIOL: Instruction access violation flag */
#define SCB_CFSR_IACCVIOL (1 << 0)
/* --- SCB_HFSR values ----------------------------------------------------- */
/* DEBUG_VT: reserved for debug use */
#define SCB_HFSR_DEBUG_VT (1 << 31)
/* FORCED: Forced hard fault */
#define SCB_HFSR_FORCED (1 << 30)
/* Bits [29:2]: reserved - must be kept cleared */
/* VECTTBL: Vector table hard fault */
#define SCB_HFSR_VECTTBL (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_MMFAR values ---------------------------------------------------- */
/* MMFAR [31:0]: Memory management fault address */
/* --- SCB_BFAR values ----------------------------------------------------- */
/* BFAR [31:0]: Bus fault address */
/* --- SCB_CPACR values ---------------------------------------------------- */
/* CPACR CPn: Access privileges values */
#define SCB_CPACR_NONE 0 /* Access denied */
#define SCB_CPACR_PRIV 1 /* Privileged access only */
#define SCB_CPACR_FULL 3 /* Full access */
/* CPACR [20:21]: Access privileges for coprocessor 10 */
#define SCB_CPACR_CP10 (1 << 20)
/* CPACR [22:23]: Access privileges for coprocessor 11 */
#define SCB_CPACR_CP11 (1 << 22)
#endif
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS
struct scb_exception_stack_frame {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
} __attribute__((packed));
#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
do { \
asm volatile ("mov %[frameptr], sp" \
: [frameptr]"=r" (f)); \
} while (0)
void scb_reset_system(void) __attribute__((noreturn));
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_reset_core(void) __attribute__((noreturn));
void scb_set_priority_grouping(uint32_t prigroup);
#endif
END_DECLS
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/scs.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_SCS_H
#define LIBOPENCM3_CM3_SCS_H
/**
* @defgroup cm_scs Cortex-M System Control Space
* @ingroup CM3_defines
* The System Control Space (SCS) is a memory-mapped 4KB address space that
* provides 32-bit registers for configuration, status reporting and control.
* The SCS registers divide into the following groups:
* - system control and identification
* - the CPUID processor identification space
* - system configuration and status
* - fault reporting
* - a system timer, SysTick
* - a Nested Vectored Interrupt Controller (NVIC)
* - a Protected Memory System Architecture (PMSA)
* - system debug.
*
* Most portions of the SCS are covered by their own header files, eg
* systick.h, dwt.h, scb.h, itm.h, fpb.h
* @{
*/
/** @defgroup cm_scs_registers SCS Registers
* @ingroup cm_scs
* @{
*/
/**
* Debug Halting Control and Status Register (DHCSR).
*
* Purpose Controls halting debug.
* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
* the system is running with halting debug enabled is UNPREDICTABLE.
* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
* when S_HALT is set to 0.
* - When C_DEBUGEN is set to 0, the processor ignores the values of all other
* bits in this register.
* - For more information about the use of DHCSR see Debug stepping on page
* C1-824.
* Configurations Always implemented.
*/
#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
/**
* Debug Core Register Selector Register (DCRSR).
*
* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
* registers, special-purpose registers, and Floating-point extension
* registers. A write to DCRSR specifies the register to transfer, whether the
* transfer is a read or a write, and starts the transfer.
* Usage constraints: Only accessible in Debug state.
* Configurations Always implemented.
*
*/
#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
/**
* Debug Core Register Data Register (DCRDR)
*
* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
* provides debug access to the ARM core registers, special-purpose registers,
* and Floating-point extension registers. The DCRDR is the data register for
* these accesses.
* - Used on its own, the DCRDR provides a message passing resource between an
* external debugger and a debug agent running on the processor.
* Note:
* The architecture does not define any handshaking mechanism for this use of
* DCRDR.
* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
* particular transfers using the DCRSR and DCRDR.
* Configurations Always implemented.
*
*/
#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
/**
* Debug Exception and Monitor Control Register (DEMCR).
*
* Purpose Manages vector catch behavior and DebugMonitor handling when
* debugging.
* Usage constraints:
* - Bits [23:16] provide DebugMonitor exception control.
* - Bits [15:0] provide Debug state, halting debug, control.
* Configurations Always implemented.
*
*/
#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
/**@}*/
/* Debug Halting Control and Status Register (DHCSR) */
#define SCS_DHCSR_DBGKEY 0xA05F0000
#define SCS_DHCSR_C_DEBUGEN 0x00000001
#define SCS_DHCSR_C_HALT 0x00000002
#define SCS_DHCSR_C_STEP 0x00000004
#define SCS_DHCSR_C_MASKINTS 0x00000008
#define SCS_DHCSR_C_SNAPSTALL 0x00000020
#define SCS_DHCSR_S_REGRDY 0x00010000
#define SCS_DHCSR_S_HALT 0x00020000
#define SCS_DHCSR_S_SLEEP 0x00040000
#define SCS_DHCSR_S_LOCKUP 0x00080000
#define SCS_DHCSR_S_RETIRE_ST 0x01000000
#define SCS_DHCSR_S_RESET_ST 0x02000000
/* Debug Core Register Selector Register (DCRSR) */
#define SCS_DCRSR_REGSEL_MASK 0x0000001F
#define SCS_DCRSR_REGSEL_XPSR 0x00000010
#define SCS_DCRSR_REGSEL_MSP 0x00000011
#define SCS_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */
/* Bits 31:25 - Reserved */
#define SCS_DEMCR_TRCENA (1 << 24)
/* Bits 23:20 - Reserved */
#define SCS_DEMCR_MON_REQ (1 << 19)
#define SCS_DEMCR_MON_STEP (1 << 18)
#define SCS_DEMCR_VC_MON_PEND (1 << 17)
#define SCS_DEMCR_VC_MON_EN (1 << 16)
/* Bits 15:11 - Reserved */
#define SCS_DEMCR_VC_HARDERR (1 << 10)
#define SCS_DEMCR_VC_INTERR (1 << 9)
#define SCS_DEMCR_VC_BUSERR (1 << 8)
#define SCS_DEMCR_VC_STATERR (1 << 7)
#define SCS_DEMCR_VC_CHKERR (1 << 6)
#define SCS_DEMCR_VC_NOCPERR (1 << 5)
#define SCS_DEMCR_VC_MMERR (1 << 4)
/* Bits 3:1 - Reserved */
#define SCS_DEMCR_VC_CORERESET (1 << 0)
/* CoreSight Lock Status Register for this peripheral */
#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
/* CoreSight Lock Access Register for this peripheral */
#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/sync.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_SYNC_H
#define LIBOPENCM3_CM3_SYNC_H
#include "common.h"
BEGIN_DECLS
void __dmb(void);
/* Implements synchronisation primitives as discussed in the ARM document
* DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M
* Architecture Reference Manual.
*/
/* --- Exclusive load and store instructions ------------------------------- */
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);
/* --- Convenience functions ----------------------------------------------- */
/* Here we implement some simple synchronisation primitives. */
typedef uint32_t mutex_t;
#define MUTEX_UNLOCKED 0
#define MUTEX_LOCKED 1
void mutex_lock(mutex_t *m);
uint32_t mutex_trylock(mutex_t *m);
void mutex_unlock(mutex_t *m);
#endif
END_DECLS
#endif
libopencm3/include/libopencm3/cm3/systick.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_systick_defines Cortex-M SysTick Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*
* @date 19 August 2012
*
* System Control Space (SCS) => System timer register support in the SCS.
* To configure SysTick, load the interval required between SysTick events to
* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
* the SysTick Control and Status register, is activated on the transition from
* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
* period of 100, write 99 to the SysTick Reload Value register. The SysTick
* Reload Value register supports values between 0x1 and 0x00FFFFFF.
*
* If you want to use SysTick to generate an event at a timed interval, for
* example 1ms, you can use the SysTick Calibration Value Register to scale
* your value for the Reload register. The SysTick Calibration Value Register
* is a read-only register that contains the number of pulses for a period of
* 10ms, in the TENMS field, bits[23:0].
*
* This register also has a SKEW bit. Bit[30] == 1 indicates that the
* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
*
* LGPL License Terms @ref lgpl_license
*/
/**@{*/
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/** SysTick Control and Status Register (CSR).
* Controls the system timer and provides status data.
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00)
/** SysTick Reload Value Register (RVR).
* Reads or clears the value that will be loaded to the counter.
* Usage constraints:
* - Any write to the register clears the register to zero.
* - The counter does not provide read-modify-write protection.
* - Unsupported bits are read as zero
* Configurations Always implemented.
*/
#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04)
/** SysTick Current Value Register (CVR).
* Holds the current value of the counter.
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08)
/** SysTick Calibration Value Register(Read Only) (CALIB)
* Reads the calibration value and parameters for SysTick.
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
/** @defgroup STK_CSR_VALUES STK_CSR Values
* @{
*/
/** COUNTFLAG
* Indicates whether the counter has counted to 0 since the last read of this
* register:
* 0 = Timer has not counted to 0
* 1 = Timer has counted to 0.
*/
#define STK_CSR_COUNTFLAG (1 << 16)
#define STK_CSR_CLKSOURCE_LSB 2
/** CLKSOURCE: Clock source selection
* for 0, SysTick uses the IMPLEMENTATION DEFINED external reference clock.
* for 1, SysTick uses the processor clock.
* If no external clock is provided, this bit reads as 1 and ignores writes.
*/
#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB)
/** @defgroup systick_clksource Clock source selection
@ingroup CM3_systick_defines
@{*/
#if defined(__ARM_ARCH_6M__)
#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB)
#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
#else
#define STK_CSR_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB)
#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
#endif
/**@}*/
/** TICKINT: SysTick exception request enable */
#define STK_CSR_TICKINT (1 << 1)
/** ENABLE: Counter enable */
#define STK_CSR_ENABLE (1 << 0)
/**@}*/
/** @defgroup STK_RVR_VALUES STK_RVR Values
* @{
*/
/** RELOAD[23:0]: RELOAD value */
#define STK_RVR_RELOAD 0x00FFFFFF
/**@}*/
/** @defgroup STK_RVR_VALUES STK_RVR Values
* @{
*/
/** CURRENT[23:0]: Current counter value */
#define STK_CVR_CURRENT 0x00FFFFFF
/**@}*/
/** @defgroup STK_CALIB_VALUES STK_CALIB Values
* @{
*/
/** NOREF: NOREF flag
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
* is implemented:
* 0 = The reference clock is implemented.
* 1 = The reference clock is not implemented.
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
* 1 and cannot be cleared to 0.
*/
#define STK_CALIB_NOREF (1 << 31)
/** SKEW: SKEW flag
* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
* 0 = 10ms calibration value is exact.
* 1 = 10ms calibration value is inexact, because of the clock frequency
*/
#define STK_CALIB_SKEW (1 << 30)
/* Bits [29:24] Reserved, must be kept cleared. */
/** TENMS Calibration value for 10ms.
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
* (100Hz) timing, subject to system clock skew errors. If this field is zero,
* the calibration value is not known.
*/
#define STK_CALIB_TENMS 0x00FFFFFF
/**@}*/
/* --- Function Prototypes ------------------------------------------------- */
BEGIN_DECLS
void systick_set_reload(uint32_t value);
bool systick_set_frequency(uint32_t freq, uint32_t ahb);
uint32_t systick_get_reload(void);
uint32_t systick_get_value(void);
void systick_set_clocksource(uint8_t clocksource);
void systick_interrupt_enable(void);
void systick_interrupt_disable(void);
void systick_counter_enable(void);
void systick_counter_disable(void);
uint8_t systick_get_countflag(void);
void systick_clear(void);
uint32_t systick_get_calib(void);
END_DECLS
#endif
/**@}*/
libopencm3/include/libopencm3/cm3/tpiu.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_TPIU_H
#define LIBOPENCM3_CM3_TPIU_H
/**
* @defgroup cm_tpiu Cortex-M Trace Port Interface Unit (TPIU)
* @ingroup CM3_defines
* @{
*/
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
#error "Trace Port Interface Unit not available in CM0"
#endif
/* --- TPIU registers ------------------------------------------------------ */
/* Supported Synchronous Port Size (TPIU_SSPSR) */
#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
/* Current Synchronous Port Size (TPIU_CSPSR) */
#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
/* Asynchronous Clock Prescaler (TPIU_ACPR) */
#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
/* Selected Pin Protocol (TPIU_SPPR) */
#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
/* Formatter and Flush Status Register (TPIU_FFSR) */
#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
/* Formatter and Flush Control Register (TPIU_FFCR) */
#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
/* (TPIU_DEVID) */
#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
/* CoreSight Lock Status Register for this peripheral */
#define TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */
#define TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */
/* --- TPIU_ACPR values ---------------------------------------------------- */
/* Bits 31:16 - Reserved */
/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
/* --- TPIU_SPPR values ---------------------------------------------------- */
/* Bits 31:2 - Reserved */
#define TPIU_SPPR_SYNC (0x0)
#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
#define TPIU_SPPR_ASYNC_NRZ (0x2)
/* --- TPIU_FFSR values ---------------------------------------------------- */
/* Bits 31:4 - Reserved */
#define TPIU_FFSR_FTNONSTOP (1 << 3)
#define TPIU_FFSR_TCPRESENT (1 << 2)
#define TPIU_FFSR_FTSTOPPED (1 << 1)
#define TPIU_FFSR_FLINPROG (1 << 0)
/* --- TPIU_FFCR values ---------------------------------------------------- */
/* Bits 31:9 - Reserved */
#define TPIU_FFCR_TRIGIN (1 << 8)
/* Bits 7:2 - Reserved */
#define TPIU_FFCR_ENFCONT (1 << 1)
/* Bit 0 - Reserved */
/* --- TPIU_DEVID values ---------------------------------------------------- */
/* Bits 31:16 - Reserved */
/* Bits 15:12 - Implementation defined */
#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
/* Bit 9 - RAZ, indicated that trace data and clock are supported */
#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
/* Bits 5:0 - Implementation defined */
/**@}*/
#endif
libopencm3/include/libopencm3/cm3/vector.h
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Definitions for handling vector tables.
*
* This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
* (from the EFM32 documentation at
* http://www.energymicro.com/downloads/datasheets), and was seen analogously
* in other ARM implementations' libopencm3 files.
*
* The structure of the vector table is implemented independently of the system
* vector table starting at memory position 0x0, as it can be relocated to
* other memory locations too.
*
* The exact size of a vector interrupt table depends on the number of
* interrupts IRQ_COUNT, which is defined per family.
*/
#ifndef LIBOPENCM3_VECTOR_H
#define LIBOPENCM3_VECTOR_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/nvic.h>
/** Type of an interrupt function. Only used to avoid hard-to-read function
* pointers in the efm32_vector_table_t struct. */
typedef void (*vector_table_entry_t)(void);
typedef struct {
unsigned int *initial_sp_value; /**< Initial stack pointer value. */
vector_table_entry_t reset;
vector_table_entry_t nmi;
vector_table_entry_t hard_fault;
vector_table_entry_t memory_manage_fault; /* not in CM0 */
vector_table_entry_t bus_fault; /* not in CM0 */
vector_table_entry_t usage_fault; /* not in CM0 */
vector_table_entry_t reserved_x001c[4];
vector_table_entry_t sv_call;
vector_table_entry_t debug_monitor; /* not in CM0 */
vector_table_entry_t reserved_x0034;
vector_table_entry_t pend_sv;
vector_table_entry_t systick;
vector_table_entry_t irq[NVIC_IRQ_COUNT];
} vector_table_t;
/* Common symbols exported by the linker script(s): */
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
extern vector_table_t vector_table;
#endif