From fada3b0cbace11511e42cf9e2748e2d93771c37a Mon Sep 17 00:00:00 2001 From: johannes Date: Mon, 23 Jan 2023 11:30:16 +0100 Subject: [PATCH] using submodules --- .gitmodules | 6 + libopencm3 | 1 + libopencm3/.gitignore | 68 - libopencm3/.travis.yml | 17 - libopencm3/COPYING.GPL3 | 676 -- libopencm3/COPYING.LGPL3 | 165 - libopencm3/HACKING | 85 - libopencm3/HACKING_COMMON_DOC | 76 - libopencm3/Makefile | 124 - libopencm3/README.md | 198 - libopencm3/debian/changelog | 12 - libopencm3/debian/compat | 1 - libopencm3/debian/control | 21 - libopencm3/debian/gbp.conf | 6 - libopencm3/debian/rules | 21 - libopencm3/debian/source/format | 1 - libopencm3/debian/source/local-options | 1 - libopencm3/doc/Doxyfile | 21 - libopencm3/doc/Doxyfile_common | 1809 ----- libopencm3/doc/HACKING | 106 - libopencm3/doc/Makefile | 64 - libopencm3/doc/README | 34 - libopencm3/doc/efm32ezr32wg/doxy.custom | 1 - libopencm3/doc/efm32g/doxy.custom | 1 - libopencm3/doc/efm32gg/doxy.custom | 1 - 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| 32 - libopencm3/include/libopencm3/sam/pio.h | 34 - libopencm3/include/libopencm3/sam/pm.h | 24 - libopencm3/include/libopencm3/sam/pmc.h | 32 - libopencm3/include/libopencm3/sam/pwm.h | 109 - libopencm3/include/libopencm3/sam/scif.h | 24 - libopencm3/include/libopencm3/sam/smc.h | 32 - libopencm3/include/libopencm3/sam/tc.h | 52 - libopencm3/include/libopencm3/sam/uart.h | 85 - libopencm3/include/libopencm3/sam/usart.h | 242 - libopencm3/include/libopencm3/sam/wdt.h | 57 - libopencm3/include/libopencm3/stm32/adc.h | 44 - libopencm3/include/libopencm3/stm32/can.h | 681 -- libopencm3/include/libopencm3/stm32/cec.h | 28 - .../libopencm3/stm32/common/adc_common_v1.h | 429 - .../stm32/common/adc_common_v1_multi.h | 379 - .../libopencm3/stm32/common/adc_common_v2.h | 264 - .../stm32/common/adc_common_v2_multi.h | 187 - .../stm32/common/adc_common_v2_single.h | 86 - .../libopencm3/stm32/common/crc_common_all.h | 125 - .../include/libopencm3/stm32/common/crc_v2.h | 107 - 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libopencm3/include/libopencm3/stm32/dma2d.h | 30 - libopencm3/include/libopencm3/stm32/dmamux.h | 28 - libopencm3/include/libopencm3/stm32/dsi.h | 27 - libopencm3/include/libopencm3/stm32/exti.h | 50 - libopencm3/include/libopencm3/stm32/f0/adc.h | 198 - libopencm3/include/libopencm3/stm32/f0/cec.h | 125 - .../include/libopencm3/stm32/f0/comparator.h | 124 - libopencm3/include/libopencm3/stm32/f0/crc.h | 38 - libopencm3/include/libopencm3/stm32/f0/dac.h | 117 - libopencm3/include/libopencm3/stm32/f0/dma.h | 38 - .../include/libopencm3/stm32/f0/doc-stm32f0.h | 36 - libopencm3/include/libopencm3/stm32/f0/exti.h | 43 - .../include/libopencm3/stm32/f0/flash.h | 120 - libopencm3/include/libopencm3/stm32/f0/gpio.h | 75 - libopencm3/include/libopencm3/stm32/f0/i2c.h | 38 - .../include/libopencm3/stm32/f0/irq.json | 39 - libopencm3/include/libopencm3/stm32/f0/iwdg.h | 38 - .../include/libopencm3/stm32/f0/memorymap.h | 122 - libopencm3/include/libopencm3/stm32/f0/pwr.h | 67 - libopencm3/include/libopencm3/stm32/f0/rcc.h | 587 -- libopencm3/include/libopencm3/stm32/f0/rtc.h | 36 - libopencm3/include/libopencm3/stm32/f0/spi.h | 36 - .../include/libopencm3/stm32/f0/st_usbfs.h | 27 - .../include/libopencm3/stm32/f0/syscfg.h | 121 - .../include/libopencm3/stm32/f0/timer.h | 37 - libopencm3/include/libopencm3/stm32/f0/tsc.h | 159 - .../include/libopencm3/stm32/f0/usart.h | 72 - libopencm3/include/libopencm3/stm32/f1/adc.h | 425 - libopencm3/include/libopencm3/stm32/f1/bkp.h | 211 - libopencm3/include/libopencm3/stm32/f1/crc.h | 38 - libopencm3/include/libopencm3/stm32/f1/dac.h | 37 - libopencm3/include/libopencm3/stm32/f1/dma.h | 37 - .../include/libopencm3/stm32/f1/doc-stm32f1.h | 36 - libopencm3/include/libopencm3/stm32/f1/exti.h | 42 - .../include/libopencm3/stm32/f1/flash.h | 121 - libopencm3/include/libopencm3/stm32/f1/gpio.h | 979 --- libopencm3/include/libopencm3/stm32/f1/i2c.h | 37 - .../include/libopencm3/stm32/f1/irq.json | 75 - libopencm3/include/libopencm3/stm32/f1/iwdg.h | 39 - .../include/libopencm3/stm32/f1/memorymap.h | 128 - libopencm3/include/libopencm3/stm32/f1/pwr.h | 37 - libopencm3/include/libopencm3/stm32/f1/rcc.h | 726 -- libopencm3/include/libopencm3/stm32/f1/rtc.h | 176 - libopencm3/include/libopencm3/stm32/f1/spi.h | 37 - .../include/libopencm3/stm32/f1/st_usbfs.h | 27 - .../include/libopencm3/stm32/f1/timer.h | 56 - .../include/libopencm3/stm32/f1/usart.h | 37 - libopencm3/include/libopencm3/stm32/f2/crc.h | 38 - .../include/libopencm3/stm32/f2/crypto.h | 36 - libopencm3/include/libopencm3/stm32/f2/dac.h | 37 - libopencm3/include/libopencm3/stm32/f2/dma.h | 37 - .../include/libopencm3/stm32/f2/doc-stm32f2.h | 37 - libopencm3/include/libopencm3/stm32/f2/exti.h | 42 - .../include/libopencm3/stm32/f2/flash.h | 49 - libopencm3/include/libopencm3/stm32/f2/gpio.h | 37 - libopencm3/include/libopencm3/stm32/f2/hash.h | 36 - libopencm3/include/libopencm3/stm32/f2/i2c.h | 41 - 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libopencm3/include/libopencm3/stm32/f3/gpio.h | 38 - .../include/libopencm3/stm32/f3/hrtim.h | 37 - libopencm3/include/libopencm3/stm32/f3/i2c.h | 37 - .../include/libopencm3/stm32/f3/irq.json | 88 - libopencm3/include/libopencm3/stm32/f3/iwdg.h | 38 - .../include/libopencm3/stm32/f3/memorymap.h | 134 - libopencm3/include/libopencm3/stm32/f3/pwr.h | 55 - libopencm3/include/libopencm3/stm32/f3/rcc.h | 638 -- libopencm3/include/libopencm3/stm32/f3/rtc.h | 40 - libopencm3/include/libopencm3/stm32/f3/spi.h | 36 - .../include/libopencm3/stm32/f3/st_usbfs.h | 27 - .../include/libopencm3/stm32/f3/syscfg.h | 41 - .../include/libopencm3/stm32/f3/timer.h | 39 - .../include/libopencm3/stm32/f3/usart.h | 57 - libopencm3/include/libopencm3/stm32/f4/adc.h | 200 - libopencm3/include/libopencm3/stm32/f4/crc.h | 38 - .../include/libopencm3/stm32/f4/crypto.h | 97 - libopencm3/include/libopencm3/stm32/f4/dac.h | 36 - libopencm3/include/libopencm3/stm32/f4/dcmi.h | 229 - libopencm3/include/libopencm3/stm32/f4/dma.h | 37 - .../include/libopencm3/stm32/f4/dma2d.h | 30 - .../include/libopencm3/stm32/f4/doc-stm32f4.h | 36 - libopencm3/include/libopencm3/stm32/f4/dsi.h | 31 - libopencm3/include/libopencm3/stm32/f4/exti.h | 42 - .../include/libopencm3/stm32/f4/flash.h | 47 - libopencm3/include/libopencm3/stm32/f4/fmc.h | 35 - libopencm3/include/libopencm3/stm32/f4/gpio.h | 37 - libopencm3/include/libopencm3/stm32/f4/hash.h | 36 - libopencm3/include/libopencm3/stm32/f4/i2c.h | 65 - .../include/libopencm3/stm32/f4/irq.json | 98 - libopencm3/include/libopencm3/stm32/f4/iwdg.h | 39 - .../include/libopencm3/stm32/f4/lptimer.h | 46 - libopencm3/include/libopencm3/stm32/f4/ltdc.h | 31 - .../include/libopencm3/stm32/f4/memorymap.h | 173 - libopencm3/include/libopencm3/stm32/f4/pwr.h | 88 - .../include/libopencm3/stm32/f4/quadspi.h | 159 - libopencm3/include/libopencm3/stm32/f4/rcc.h | 1106 --- libopencm3/include/libopencm3/stm32/f4/rng.h | 23 - libopencm3/include/libopencm3/stm32/f4/rtc.h | 45 - libopencm3/include/libopencm3/stm32/f4/spi.h | 37 - .../include/libopencm3/stm32/f4/syscfg.h | 41 - .../include/libopencm3/stm32/f4/timer.h | 39 - .../include/libopencm3/stm32/f4/usart.h | 37 - libopencm3/include/libopencm3/stm32/f7/adc.h | 194 - libopencm3/include/libopencm3/stm32/f7/crc.h | 36 - libopencm3/include/libopencm3/stm32/f7/dac.h | 36 - libopencm3/include/libopencm3/stm32/f7/dma.h | 34 - .../include/libopencm3/stm32/f7/dma2d.h | 30 - .../include/libopencm3/stm32/f7/doc-stm32f7.h | 36 - libopencm3/include/libopencm3/stm32/f7/dsi.h | 31 - libopencm3/include/libopencm3/stm32/f7/exti.h | 33 - .../include/libopencm3/stm32/f7/flash.h | 101 - libopencm3/include/libopencm3/stm32/f7/fmc.h | 38 - libopencm3/include/libopencm3/stm32/f7/gpio.h | 37 - libopencm3/include/libopencm3/stm32/f7/i2c.h | 36 - .../include/libopencm3/stm32/f7/irq.json | 111 - libopencm3/include/libopencm3/stm32/f7/iwdg.h | 36 - .../include/libopencm3/stm32/f7/lptimer.h | 46 - libopencm3/include/libopencm3/stm32/f7/ltdc.h | 31 - .../include/libopencm3/stm32/f7/memorymap.h | 171 - libopencm3/include/libopencm3/stm32/f7/pwr.h | 297 - libopencm3/include/libopencm3/stm32/f7/rcc.h | 965 --- libopencm3/include/libopencm3/stm32/f7/rng.h | 23 - libopencm3/include/libopencm3/stm32/f7/spi.h | 37 - .../include/libopencm3/stm32/f7/syscfg.h | 36 - .../include/libopencm3/stm32/f7/timer.h | 42 - .../include/libopencm3/stm32/f7/usart.h | 60 - libopencm3/include/libopencm3/stm32/flash.h | 50 - libopencm3/include/libopencm3/stm32/fsmc.h | 311 - libopencm3/include/libopencm3/stm32/g0/adc.h | 328 - libopencm3/include/libopencm3/stm32/g0/crc.h | 31 - libopencm3/include/libopencm3/stm32/g0/dma.h | 34 - .../include/libopencm3/stm32/g0/dmamux.h | 172 - .../include/libopencm3/stm32/g0/doc-stm32g0.h | 36 - libopencm3/include/libopencm3/stm32/g0/exti.h | 57 - .../include/libopencm3/stm32/g0/flash.h | 297 - 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delete mode 100644 libopeninv/src/my_fp.c delete mode 100644 libopeninv/src/my_string.c delete mode 100644 libopeninv/src/param_save.cpp delete mode 100644 libopeninv/src/params.cpp delete mode 100644 libopeninv/src/picontroller.cpp delete mode 100644 libopeninv/src/printf.cpp delete mode 100644 libopeninv/src/sine_core.cpp delete mode 100644 libopeninv/src/stm32_can.cpp delete mode 100644 libopeninv/src/stm32scheduler.cpp delete mode 100644 libopeninv/src/terminal.cpp delete mode 100644 libopeninv/src/terminalcommands.cpp diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..9d3d04c --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "libopencm3"] + path = libopencm3 + url = git@github.com:jsphuebner/libopencm3.git +[submodule "libopeninv"] + path = libopeninv + url = git@github.com:jsphuebner/libopeninv.git diff --git a/libopencm3 b/libopencm3 new file mode 160000 index 0000000..6106e23 --- /dev/null +++ b/libopencm3 @@ -0,0 +1 @@ +Subproject commit 6106e237e501378d6b2c9d6210a3259f17984e6c diff --git a/libopencm3/.gitignore b/libopencm3/.gitignore deleted file mode 100644 index 062c517..0000000 --- a/libopencm3/.gitignore +++ /dev/null @@ -1,68 +0,0 @@ -*.d -*.o -*.bin -*.hex -*.list -*.srec -*.a -*.elf -lib/*.ld -# (except this one!) -!lib/cortex-m-generic.ld -*.stylecheck -*.swp -\#* -.\#* -*~ -*.map -*.log -*.pyc -html/ -latex/ -*.pdf -*.tag -.DS_Store -# These are generated -include/libopencm3/**/nvic.h -include/libopencm3/**/**/nvic.h -# (not these three though...) -!include/libopencm3/cm3/nvic.h -!include/libopencm3/dispatch/nvic.h -!include/libopencm3/lm4f/nvic.h -lib/**/vector_nvic.c -lib/**/**/vector_nvic.c -# (not this one either) -!lib/dispatch/vector_nvic.c -DoxygenLayout.xml -doc/*/Doxyfile -doc/*/DoxygenLayout_*.xml -# (annnd, not these two templates either) -!doc/templates/DoxygenLayout_Device.xml -!doc/templates/DoxygenLayout_Root.xml -doc/*/doxy.sourcelist -include/libopencmsis/efm32/ -include/libopencmsis/gd32/ -include/libopencmsis/lm3s/ -include/libopencmsis/lpc13xx/ -include/libopencmsis/lpc17xx/ -include/libopencmsis/lpc43xx/ -include/libopencmsis/msp432/ -include/libopencmsis/pac55xx/ -include/libopencmsis/sam/ -include/libopencmsis/stm32/ -include/libopencmsis/swm050/ -include/libopencmsis/vf6xx/ - -# Editor/IDE config files -nbproject/ -.idea/ -.project -locm3.sublime-workspace -.cproject -.settings - -# cscope databases -cscope.out - -# build droppings -.stamp_failure* diff --git a/libopencm3/.travis.yml b/libopencm3/.travis.yml deleted file mode 100644 index 7323ee1..0000000 --- a/libopencm3/.travis.yml +++ /dev/null @@ -1,17 +0,0 @@ -language: c -script: - - make - - make -C tests/gadget-zero - -addons: - apt: - sources: - - sourceline: 'ppa:team-gcc-arm-embedded/ppa' - packages: - - gcc-arm-embedded - -notifications: - irc: - channels: - - "chat.freenode.net#libopencm3" - use_notice: true diff --git a/libopencm3/COPYING.GPL3 b/libopencm3/COPYING.GPL3 deleted file mode 100644 index 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Such new -versions will be similar in spirit to the present version, but may -differ in detail to address new problems or concerns. - - Each version is given a distinguishing version number. If the -Library as you received it specifies that a certain numbered version -of the GNU Lesser General Public License "or any later version" -applies to it, you have the option of following the terms and -conditions either of that published version or of any later version -published by the Free Software Foundation. If the Library as you -received it does not specify a version number of the GNU Lesser -General Public License, you may choose any version of the GNU Lesser -General Public License ever published by the Free Software Foundation. - - If the Library as you received it specifies that a proxy can decide -whether future versions of the GNU Lesser General Public License shall -apply, that proxy's public statement of acceptance of any version is -permanent authorization for you to choose that version for the -Library. diff --git a/libopencm3/HACKING b/libopencm3/HACKING deleted file mode 100644 index 1ecc48a..0000000 --- a/libopencm3/HACKING +++ /dev/null @@ -1,85 +0,0 @@ ------------------------------------------------------------------------------- -HACKING ------------------------------------------------------------------------------- - -Coding style ------------- - -The whole library is programmed using the Linux kernel coding style, see -https://www.kernel.org/doc/html/latest/process/coding-style.html for details. - -Please use the same style for any code contributions, thanks! - -Amendments to the Linux kernel coding style -------------------------------------------- - -1) We use the stdint types. The linux kernel accepts the abbreviated types (u8, - s8, u16 and so on) for legacy reasons. We should in general not introduce - things like types ourselves as long as they are not necessary to make our - job possible of refining the hardware and make it easier to be used. stdint - is a standard and it is not in the scope of our project to introduce a new - type standard. - -2) Based on the same logic as in (1) we do not use __packed and __aligned - definitions, it is not our job to add compiler extensions. If we need to - deal with compiler incompatibility we will do that the same way we are - dealing with the deprecated attribute by introducing a normal macro that is - not in the compiler reserved keyword space. - -3) We accept to write an empty body busy waiting while loop like this: - while (1); - there is no need to put the colon on the next line as per linux kernel - style. - -4) We always add brackets around bodies of if, while and for statements, even - if the body contains only one expression. It is dangerous to not have them - as it easily happens that one adds a second expression and is hunting for - hours why the code is not working just because of a missing bracket pair. - -Development guidelines ----------------------- - - - Every new file added must have the usual license header, see the - existing files for examples. - - - In general, please try to keep the register and bit naming as close - as possible to the official vendor datasheets. Among other reasons, this - makes it easier for users to find what they're looking for in the - datasheets, programming manuals, and application notes. - - - All register definitions should follow the following naming conventions: - - - The #define names should be all-caps, parts are separated by - an underscore. - - - The name should be of the form SUBSYSTEM_REGISTER_BIT, e.g. - ADC_CR2_DMA, where ADC is the subsystem name, CR2 is the register NAME, - and DMA is the name of the bit in the register that is defined. - - - All subsystem-specific function names should be prefixed with the - subsystem name. For example, gpio_set_mode() or rcc_osc_on(). - - - Please consistently use the stdint types. - - - Variables that are used to store register values read from registers or - to be stored in a register should be named reg8, reg16, reg32 etc. - - - For examples on using libopencm3 see the libopencm3-examples repository. - - - Doxygen is used to generate API docs, please follow that style for function - and definition commentary where possible. - -Tips and tricks ---------------- - -SublimeText users: - - - The project contains a sublime project description file with some basic - settings provided to make hacking on libopencm3 easier. - - - Recommended SublimeText plugins when hacking on libopencm3: - - - TrailingSpaces: Show and trim trailing line spaces. - - - SublimeLinter: Run checkpatch.pl in the background while you write your - code and indicate possible coding style issues on the fly. diff --git a/libopencm3/HACKING_COMMON_DOC b/libopencm3/HACKING_COMMON_DOC deleted file mode 100644 index b0fa4b3..0000000 --- a/libopencm3/HACKING_COMMON_DOC +++ /dev/null @@ -1,76 +0,0 @@ -Files for each peripheral (examples given for STM32 GPIO) ---------------------------------------------------------- - -In include/libopencm3/stm32. -A "dispatch" header to point to the subfamily header (gpio.h) - -In include/libopencm3/stm32/f* -A file with defines that are specific to the subfamily, and an include of -needed common header files (gpio.h). - -In include/libopencm3/stm32/common -A file with defines common to all subfamilies. Includes the cm3 common header -(gpio_common_all.h). - -In include/libopencm3/stm32/common -May be one other file with defines common to a subgroup of devices. -This includes the file common to all (gpio_common_f24.h). - -In lib/stm32/f* -A file with functions specific to the subfamily. Includes the "dispatch" header -and any common headers needed (gpio.c). - -In lib/stm32/common -Has functions common to all subfamilies. Includes the "dispatch" header -(gpio_common_all.c). - -In lib/stm32/common -May be one other file with functions common to a group of subfamilies. Includes -the "dispatch" header and the file common to all (gpio_common_f24.h). - -Makefiles in lib/stm32/f? have the common object files added and the -common directory added to VPATH. - -NOTE: The common source files MUST have the "dispatch" header so that -compilation will use the specific defines for the subfamily being compiled. -These can differ between subfamilies. - -NOTE: The common source files must have a line of the form - -#ifdef LIBOPENCM3_xxx_H - -where xxx is the associated peripheral name. This prevents the common files -from being included accidentally into a user's application. This however -causes doxygen to skip processing of the remainder of the file. Thus a - -@cond ... @endcond - -directive must be placed around the statement to prevent doxygen from -processing it. This works only for doxygen 1.8.4 or later. At the present -time most distros have an earlier buggy version. - -Documentation -------------- - -In include/libopencm3/stm32/f* -A file doc-stm32f*.h contains a definition of the particular family grouping. -This grouping will appear in the main index of the resulting document with all -documentation under it. - -All header files for a peripheral (common or otherwise) will subgroup under a -name which is the same in all families (such as gpio_defines). The peripheral -header file in include/libopencm3/stm32/f* will then include this group as a -subgroup under the specific family group. Doxygen is run separately for each -family so there is no danger of accidentally including the wrong stuff. - -Similarly for the source files for a peripheral which will subgroup under a -same name (such as gpio_files). The peripheral source file in lib/stm32/f* -will include this as a subgroup under the specific family group. - -DOXYFILE for a particular family will list the family specific and common files -(headers and source) that are to be included. The result (in the long run) will -be that all peripherals will appear under the same family grouping in the -documentation, even if they are identical over a number of families. That is -probably most useful to end users who only need to see the documentation for -one family. - diff --git a/libopencm3/Makefile b/libopencm3/Makefile deleted file mode 100644 index f8fff0b..0000000 --- a/libopencm3/Makefile +++ /dev/null @@ -1,124 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -PREFIX ?= arm-none-eabi- - -STYLECHECK := scripts/checkpatch.pl -STYLECHECKFLAGS := --no-tree -f --terse --mailback - -TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ - stm32/l0 stm32/l1 stm32/l4 \ - stm32/g0 stm32/g4 \ - stm32/h7 \ - gd32/f1x0 \ - lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \ - lm3s lm4f msp432/e4 \ - efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \ - efm32/ezr32wg \ - sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \ - sam/d \ - vf6xx \ - swm050 \ - pac55xx - -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -# Do not print "Entering directory ...". -MAKEFLAGS += --no-print-directory -endif - -# Avoid the use of shell find, for windows compatibility -IRQ_DEFN_FILES := $(foreach TARGET,$(TARGETS),$(wildcard include/libopencm3/$(TARGET)/irq.json)) -STYLECHECKFILES := $(wildcard include/*/*.h include/*/*/*.h include/*/*/*/*.h) -STYLECHECKFILES += $(wildcard lib/*/*.h lib/*/*/*.h lib/*/*/*/*.h) -STYLECHECKFILES += $(wildcard lib/*/*.c lib/*/*/*.c lib/*/*/*/*.c) - -all: build - -build: lib - -%.genhdr: - @printf " GENHDR $*\n"; - $(Q)./scripts/irq2nvic_h ./$*; - -%.cleanhdr: - @printf " CLNHDR $*\n"; - $(Q)./scripts/irq2nvic_h --remove ./$* - -LIB_DIRS:=$(wildcard $(addprefix lib/,$(TARGETS))) -$(LIB_DIRS): $(IRQ_DEFN_FILES:=.genhdr) - $(Q)$(RM) .stamp_failure_$(subst /,_,$@) - @printf " BUILD $@\n"; - $(Q)$(MAKE) --directory=$@ PREFIX="$(PREFIX)" || \ - echo "Failure building: $@: code: $$?" > .stamp_failure_$(subst /,_,$@) - -lib: $(LIB_DIRS) - $(Q)$(RM) .stamp_failure_tld - $(Q)for failure in .stamp_failure_*; do \ - [ -f $$failure ] && cat $$failure >> .stamp_failure_tld || true; \ - done; - $(Q)[ -f .stamp_failure_tld ] && cat .stamp_failure_tld && exit 1 || true; - -html doc: - $(Q)$(MAKE) -C doc html TARGETS="$(TARGETS)" - -clean: $(IRQ_DEFN_FILES:=.cleanhdr) $(LIB_DIRS:=.clean) $(EXAMPLE_DIRS:=.clean) doc.clean styleclean genlinktests.clean - -%.clean: - $(Q)if [ -d $* ]; then \ - printf " CLEAN $*\n"; \ - $(MAKE) -C $* clean || exit $?; \ - fi; - $(Q)$(RM) .stamp_failure_*; - - -stylecheck: $(STYLECHECKFILES:=.stylecheck) -styleclean: $(STYLECHECKFILES:=.styleclean) - -# the cat is due to multithreaded nature - we like to have consistent chunks of text on the output -%.stylecheck: % - $(Q)if ! grep -q "* It was generated by the irq2nvic_h script." $* ; then \ - $(STYLECHECK) $(STYLECHECKFLAGS) $* > $*.stylecheck; \ - if [ -s $*.stylecheck ]; then \ - cat $*.stylecheck; \ - else \ - rm -f $*.stylecheck; \ - fi; \ - fi; - -%.styleclean: - $(Q)rm -f $*.stylecheck; - - -LDTESTS :=$(wildcard ld/tests/*.data) - -genlinktests: $(LDTESTS:.data=.ldtest) -genlinktests.clean: - $(Q)rm -f $(LDTESTS:.data=.out) - -%.ldtest: - @if ./scripts/genlinktest.sh $* >/dev/null; then\ - printf " TEST OK : $*\n"; \ - else \ - printf " TEST FAIL : $*\n"; \ - fi; - - -.PHONY: build lib $(LIB_DIRS) doc clean generatedheaders cleanheaders stylecheck genlinktests genlinktests.clean diff --git a/libopencm3/README.md b/libopencm3/README.md deleted file mode 100644 index f733f91..0000000 --- a/libopencm3/README.md +++ /dev/null @@ -1,198 +0,0 @@ -README -====== -[![Build Status](https://travis-ci.org/libopencm3/libopencm3.svg?branch=master)](https://travis-ci.org/libopencm3/libopencm3) - -[![Gitter channel](https://badges.gitter.im/libopencm3/discuss.svg)](https://gitter.im/libopencm3/discuss) - -The libopencm3 project aims to create an open-source firmware library for -various ARM Cortex-M microcontrollers. - -Currently (at least partly) supported microcontrollers: - - - ST STM32 F0xx/F1xx/F2xx/F30x/F37x/F4xx/F7xx/H7xx series - - ST STM32 G0xx G4xx L0xx L1xx L4xx series - - Atmel SAM3A/3N/3S/3U/3X series, as well as SAMDxx and friends - - NXP LPC1311/13/17/42/43 - - Stellaris LM3S series (discontinued, without replacement) - - TI (Tiva) LM4F series (continuing as TM4F, pin and peripheral compatible) - - EFM32 Gecko series (only core support) - - Freescale Vybrid VF6xx - - Qorvo (formerly ActiveSemi) PAC55XX - - Synwit SWM050 - -The library is written completely from scratch based on the vendor datasheets, -programming manuals, and application notes. The code is meant to be used -with a GCC toolchain for ARM (arm-elf or arm-none-eabi), flashing of the -code to a microcontroller can be done using the OpenOCD ARM JTAG software. - - -Status and API --------------- - -The libopencm3 project is currently work in progress. Not all subsystems -of the microcontrollers are supported, yet. - -**IMPORTANT**: The API of the library is _NOT_ yet considered stable! Please do - not rely on it, yet! Changes to function names, macro names, etc. - can happen at any time without prior notice! - -_TIP_: Include this repository as a Git submodule in your project to make sure - your users get the right version of the library to compile your project. - For how that can be done refer to the libopencm3-examples repository. - -Prerequisites -------------- - -Building requires Python (Some code is generated). - -**For Ubuntu/Fedora:** - - - An arm-none-eabi/arm-elf toolchain. - -**For Windows:** - - Download and install: - - - msys - http://sourceforge.net/projects/mingw/files/MSYS/Base/msys-core/msys-1.0.11/MSYS-1.0.11.exe - - Python - http://www.python.org/ftp/python/2.7/python-2.7.msi (any 2.7 release) - - arm-none-eabi/arm-elf toolchain (for example this one https://launchpad.net/gcc-arm-embedded) - -Run msys shell and set the path without standard Windows paths, so Windows programs such as 'find' won't interfere: - - export PATH="/c//Python27:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin" - -After that you can navigate to the folder where you've extracted libopencm3 and build it. - -Toolchain ---------- - -The most heavily tested toolchain is "gcc-arm-embedded" -https://launchpad.net/gcc-arm-embedded - -Other toolchains _should_ work, but they have not been nearly as well tested. -Toolchains targeting Linux, such as "gcc-arm-linux-gnu" or the like are -_not_ appropriate. - -_NOTE_ We recommend that you use gcc-arm-embedded version 4.8 2014q3 or newer -to build all platforms covered by libopencm3 successfully. - -Building --------- - - $ make - -If you have an arm-elf toolchain (uncommon) you may want to override the -toolchain prefix (arm-none-eabi is the default) - - $ PREFIX=arm-elf make - -For a more verbose build you can use - - $ make V=1 - -Fine-tuning the build ---------------------- - -The build may be fine-tuned with a limited number of parameters, by specifying -them as environment variables, for example: - - $ VARIABLE=value make - -* `FP_FLAGS` - Control the floating-point ABI - - If the Cortex-M core supports a hard float ABI, it will be compiled with - the best floating-point support by default. In cases where this is not desired, the - behavior can be specified by setting `FP_FLAGS`. - - Currently, M4F cores default to `-mfloat-abi=hard -mfpu=fpv4-sp-d16`, and - M7 cores defaults to double precision `-mfloat-abi=hard -mfpu=fpv5-d16` if available, - and single precision `-mfloat-abi=hard -mfpu=fpv5-sp-d16` otherwise. - Other architectures use no FP flags, in otherwords, traditional softfp. - - You may find which FP_FLAGS you can use in a particular architecture in the readme.txt - file shipped with the gcc-arm-embedded package. - - Examples: - - $ FP_FLAGS="-mfloat-abi=soft" make # No hardfloat - $ FP_FLAGS="-mfloat-abi=hard -mfpu=magic" make # New FPU we don't know of - -* `CFLAGS` - Add to or supersede compiler flags - - If the library needs to be compiled with additional flags, they can be - passed to the build system via the environment variable `CFLAGS`. The - contents of `CFLAGS` will be placed after all flags defined by the build - system, giving the user a way to override any default if necessary. - - Examples: - - $ CFLAGS="-fshort-wchar" make # Compile lib with 2 byte wide wchar_t - -Example projects ----------------- - -The libopencm3 community has written and is maintaining a huge collection of -examples, displaying the capabilities and uses of the library. You can find all -of them in the libopencm3-examples repository: - -https://github.com/libopencm3/libopencm3-examples - -If you just wish to test your toolchain and build environment, a collection of -mini blink projects is available too. This covers _many_ more boards, but, as -the name suggests, only demonstrates blinking LEDs. - - -https://github.com/libopencm3/libopencm3-miniblink - -Installation ------------- - -Simply pass -I and -L flags to your own project. See the -[libopencm3-template](https://github.com/libopencm3/libopencm3-template) -repository for a template repository using this library as a Git submodule, -the most popular method of use. The libopencm3-examples is another -example of this. - -It is strongly advised that you do not attempt to install this library to any -path inside your toolchain itself. While this means you don't have to include -any `-I` or `-L` flags in your projects, it is _very_ easy to confuse a multi-library -linker from picking the right versions of libraries. Common symptoms are -hardfaults caused by branches into ARM code. You can use `arm-none-eabi-objdump` -to check for this in your final ELF file. You have been warned. - -Coding style and development guidelines ---------------------------------------- - -See HACKING. - - -License -------- - -The libopencm3 code is released under the terms of the GNU Lesser General -Public License (LGPL), version 3 or later. - -See COPYING.GPL3 and COPYING.LGPL3 for details. - -Community ---------- - - * Our [![Gitter channel](https://badges.gitter.im/libopencm3/discuss.svg)](https://gitter.im/libopencm3/discuss) - * Our IRC channel on the freenode IRC network is called #libopencm3 - -Mailing lists -------------- - - * Developer mailing list (for patches and discussions): - https://lists.sourceforge.net/lists/listinfo/libopencm3-devel - - * Commits mailing list (receives one mail per `git push`): - https://lists.sourceforge.net/lists/listinfo/libopencm3-commits - - -Website -------- - - * http://libopencm3.org - * http://sourceforge.net/projects/libopencm3/ - diff --git a/libopencm3/debian/changelog b/libopencm3/debian/changelog deleted file mode 100644 index dc7e2fb..0000000 --- a/libopencm3/debian/changelog +++ /dev/null @@ -1,12 +0,0 @@ -libopencm3 (0.0~20130110+git20bfcaeb1-1) UNRELEASED; urgency=low - - * Merged current upstream state - - started indicating upstream revision in debian version number - - -- Christian M. Amsüss Thu, 10 Jan 2013 11:43:09 +0100 - -libopencm3 (0) UNRELEASED; urgency=low - - * First packaging attempt to see where it installs - - -- Christian M. Amsüss Wed, 18 Apr 2012 11:20:37 +0200 diff --git a/libopencm3/debian/compat b/libopencm3/debian/compat deleted file mode 100644 index ec63514..0000000 --- a/libopencm3/debian/compat +++ /dev/null @@ -1 +0,0 @@ -9 diff --git a/libopencm3/debian/control b/libopencm3/debian/control deleted file mode 100644 index cbb79ce..0000000 --- a/libopencm3/debian/control +++ /dev/null @@ -1,21 +0,0 @@ -Source: libopencm3 -Priority: optional -Maintainer: Christian M. Amsüss -Build-Depends: debhelper (>= 9), - gcc-arm-none-eabi, - arm-none-eabi-libc, - binutils-multiarch, -Standards-Version: 3.9.3 -Section: fixme -Homepage: http://www.libopencm3.org/ - -Package: libopencm3 -Section: fixme -Architecture: all -Depends: ${misc:Depends} -Description: firmware library for ARM Cortex-M3 microcontrollers - The libopencm3 library provides the base code for running software without an - operating system on ARM Cortex-M3 microcontrollers, and contains both system - initialization routines and periphery implementation. - . - It supports the STM32, TX03, SAM3U and LPC1000 families of chips. diff --git a/libopencm3/debian/gbp.conf b/libopencm3/debian/gbp.conf deleted file mode 100644 index 6f75524..0000000 --- a/libopencm3/debian/gbp.conf +++ /dev/null @@ -1,6 +0,0 @@ -[DEFAULT] -debian-branch = debian - -# so far, this is configured to only build binary packages and not source -# packages; without a release tarball and in the current stage of packaging, -# that'd be unnecessary diff --git a/libopencm3/debian/rules b/libopencm3/debian/rules deleted file mode 100755 index 7b1bfe2..0000000 --- a/libopencm3/debian/rules +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/make -f - -# DH_VERBOSE=1 - -%: - dh $@ - -# libopencm3's build system uses the variable PREFIX different from usual -# build systems (usually, it'd be /usr; here, it is arm-none-eabi), and use -# DESTDIR for what is usually ${DESTDIR}/${PREFIX}. there are no generated -# files that get their paths hardcoded, so ${PREFIX} alone is not needed -# anyway. -LIBOPENCM3OPTS=DESTDIR=$(CURDIR)/debian/libopencm3/usr/ - -override_dh_auto_build: - # we're not compiling in a debian sense -- and the normal flags make - # things break - CFLAGS= CPPFLAGS= LDFLAGS= $(MAKE) $(LIBOPENCM3OPTS) - -override_dh_auto_install: - $(MAKE) $(LIBOPENCM3OPTS) install diff --git a/libopencm3/debian/source/format b/libopencm3/debian/source/format deleted file mode 100644 index 163aaf8..0000000 --- a/libopencm3/debian/source/format +++ /dev/null @@ -1 +0,0 @@ -3.0 (quilt) diff --git a/libopencm3/debian/source/local-options b/libopencm3/debian/source/local-options deleted file mode 100644 index 7423a2d..0000000 --- a/libopencm3/debian/source/local-options +++ /dev/null @@ -1 +0,0 @@ -single-debian-patch diff --git a/libopencm3/doc/Doxyfile b/libopencm3/doc/Doxyfile deleted file mode 100644 index f9c0a5a..0000000 --- a/libopencm3/doc/Doxyfile +++ /dev/null @@ -1,21 +0,0 @@ -# Doxygen include file to generate top level entry document - -# 14 September 2012 -# (C) Ken Sarkies - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ./Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -INPUT = ../include/libopencm3/docmain.dox - -LAYOUT_FILE = DoxygenLayout.xml - -GENERATE_LATEX = NO - diff --git a/libopencm3/doc/Doxyfile_common b/libopencm3/doc/Doxyfile_common deleted file mode 100644 index aeeea20..0000000 --- a/libopencm3/doc/Doxyfile_common +++ /dev/null @@ -1,1809 +0,0 @@ -# Doxyfile 1.8.2 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project. -# -# All text after a hash (#) is considered a comment and will be ignored. -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" "). - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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By default -# anonymous namespaces are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to -# do proper type resolution of all parameters of a function it will reject a -# match between the prototype and the implementation of a member function even -# if there is only one candidate or it is obvious which candidate to choose -# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen -# will still accept a match between prototype and implementation in such cases. - -STRICT_PROTO_MATCHING = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = NO - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or macro consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and macros in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. To create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = DoxygenLayout.xml - -# The CITE_BIB_FILES tag can be used to specify one or more bib files -# containing the references data. This must be a list of .bib files. The -# .bib extension is automatically appended if omitted. Using this command -# requires the bibtex tool to be installed. See also -# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style -# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this -# feature you need bibtex and perl available in the search path. - -CITE_BIB_FILES = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# The WARN_NO_PARAMDOC option can be enabled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = doxygen.log - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh -# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py -# *.f90 *.f *.for *.vhd *.vhdl - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should be -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. -# Note that relative paths are relative to the directory from which doxygen is -# run. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or -# directories that are symbolic links (a Unix file system feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = */*.d - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty or if -# non of the patterns match the file name, INPUT_FILTER is applied. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file -# pattern. A pattern will override the setting for FILTER_PATTERN (if any) -# and it is also possible to disable source filtering for a specific pattern -# using *.ext= (so without naming a filter). This option only has effect when -# FILTER_SOURCE_FILES is enabled. - -FILTER_SOURCE_PATTERNS = - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C, C++ and Fortran comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. Note that when using a custom header you are responsible -# for the proper inclusion of any scripts and style sheets that doxygen -# needs, which is dependent on the configuration options used. -# It is advised to generate a default header using "doxygen -w html -# header.html footer.html stylesheet.css YourConfigFile" and then modify -# that header. Note that the header is subject to change so you typically -# have to redo this when upgrading to a newer version of doxygen or when -# changing the value of configuration settings such as GENERATE_TREEVIEW! - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If left blank doxygen will -# generate a default style sheet. Note that it is recommended to use -# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this -# tag will in the future become obsolete. - -HTML_STYLESHEET = - -# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional -# user-defined cascading style sheet that is included after the standard -# style sheets created by doxygen. Using this option one can overrule -# certain style aspects. This is preferred over using HTML_STYLESHEET -# since it does not replace the standard style sheet and is therefor more -# robust against future updates. Doxygen will copy the style sheet file to -# the output directory. - -HTML_EXTRA_STYLESHEET = - -# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or -# other source files which should be copied to the HTML output directory. Note -# that these files will be copied to the base HTML output directory. Use the -# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these -# files. In the HTML_STYLESHEET file, use the file name only. Also note that -# the files will be copied as-is; there are no commands or markers available. - -HTML_EXTRA_FILES = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the style sheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. - -HTML_DYNAMIC_SECTIONS = NO - -# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of -# entries shown in the various tree structured indices initially; the user -# can expand and collapse entries dynamically later on. Doxygen will expand -# the tree to such a level that at most the specified number of entries are -# visible (unless a fully collapsed tree already exceeds this amount). -# So setting the number of entries 1 will produce a full collapsed tree by -# default. 0 is a special value representing an infinite number of entries -# and will result in a full expanded tree by default. - -HTML_INDEX_NUM_ENTRIES = 100 - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely -# identify the documentation publisher. This should be a reverse domain-name -# style string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) -# at top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. Since the tabs have the same information as the -# navigation tree you can set this option to NO if you already set -# GENERATE_TREEVIEW to YES. - -DISABLE_INDEX = NO - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. -# Since the tree basically has the same information as the tab index you -# could consider to set DISABLE_INDEX to NO when enabling this option. - -GENERATE_TREEVIEW = YES - -# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values -# (range [0,1..20]) that doxygen will group on one line in the generated HTML -# documentation. Note that a value of 0 will completely suppress the enum -# values from appearing in the overview section. - -ENUM_VALUES_PER_LINE = 4 - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax -# (see http://www.mathjax.org) which uses client side Javascript for the -# rendering instead of using prerendered bitmaps. Use this if you do not -# have LaTeX installed or if you want to formulas look prettier in the HTML -# output. When enabled you may also need to install MathJax separately and -# configure the path to it using the MATHJAX_RELPATH option. - -USE_MATHJAX = NO - -# When MathJax is enabled you need to specify the location relative to the -# HTML output directory using the MATHJAX_RELPATH option. The destination -# directory should contain the MathJax.js script. For instance, if the mathjax -# directory is located at the same level as the HTML output directory, then -# MATHJAX_RELPATH should be ../mathjax. The default value points to -# the MathJax Content Delivery Network so you can quickly see the result without -# installing MathJax. -# However, it is strongly recommended to install a local -# copy of MathJax from http://www.mathjax.org before deployment. - -MATHJAX_RELPATH = http://www.mathjax.org/mathjax - -# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension -# names that should be enabled during MathJax rendering. - -MATHJAX_EXTENSIONS = - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvantages are that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4 - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for -# the generated latex document. The footer should contain everything after -# the last chapter. If it is left blank doxygen will generate a -# standard footer. Notice: only use this tag if you know what you are doing! - -LATEX_FOOTER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = YES - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = YES - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -# The LATEX_BIB_STYLE tag can be used to specify the style to use for the -# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See -# http://en.wikipedia.org/wiki/BibTeX for more info. - -LATEX_BIB_STYLE = plain - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load style sheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# pointed to by INCLUDE_PATH will be searched when a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __attribute__(x)= BEGIN_DECLS END_DECLS - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition that -# overrules the definition found in the source code. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all references to function-like macros -# that are alone on a line, have an all uppercase name, and do not end with a -# semicolon, because these will confuse the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. For each -# tag file the location of the external documentation should be added. The -# format of a tag file without this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths -# or URLs. Note that each tag file must have a unique name (where the name does -# NOT include the path). If a tag file is not located in the directory in which -# doxygen is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = NO - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option also works with HAVE_DOT disabled, but it is recommended to -# install and use dot, since it yields more powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will use the Helvetica font for all dot files that -# doxygen generates. When you want a differently looking font you can specify -# the font name using DOT_FONTNAME. You need to make sure dot is able to find -# the font, which can be done by putting it in a standard location or by setting -# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the -# directory containing the font. - -DOT_FONTNAME = Helvetica - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the Helvetica font. -# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to -# set the path where dot can find it. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = NO - -# If the UML_LOOK tag is enabled, the fields and methods are shown inside -# the class node. If there are many fields or methods and many nodes the -# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS -# threshold limits the number of items for each type to make the size more -# managable. Set this to 0 for no limit. Note that the threshold may be -# exceeded by 50% before the limit is enforced. - -UML_LIMIT_NUM_FIELDS = 10 - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = NO - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = YES - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will generate a graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are svg, png, jpg, or gif. -# If left blank png will be used. If you choose svg you need to set -# HTML_FILE_EXTENSION to xhtml in order to make the SVG files -# visible in IE 9+ (other browsers do not have this requirement). - -DOT_IMAGE_FORMAT = png - -# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to -# enable generation of interactive SVG images that allow zooming and panning. -# Note that this requires a modern browser other than Internet Explorer. -# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you -# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files -# visible. Older versions of IE do not have SVG support. - -INTERACTIVE_SVG = NO - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The MSCFILE_DIRS tag can be used to specify one or more directories that -# contain msc files that are included in the documentation (see the -# \mscfile command). - -MSCFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES - diff --git a/libopencm3/doc/HACKING b/libopencm3/doc/HACKING deleted file mode 100644 index 1c82336..0000000 --- a/libopencm3/doc/HACKING +++ /dev/null @@ -1,106 +0,0 @@ -libopencm3 Documentation -12 October 2012 (C) K Sarkies ------------------------------ - -Each family and subfamily of devices has a separate directory and configuration -files. Doxygen is run independently on each of these and the result is -integrated under a single HTML page. -Due to relative referencing used in the files, the directory -structure is important and should be maintained. -The Makefile will automatically generate the list of input files based on the -current library makefiles, so you _must_ have run built the library itself first. - -Each of the subdirectories has a configuration file, a layout file and -subdirectories for the documentation. Doxygen is intended to be run inside -these subdirectories. The Makefile will handle this in the appropriate -order. - -Markup ------- - -Each family has been given a group name that will allow subgrouping of API -functions and defines in the documentation. - -The header and source files for each peripheral in each family must have a -heading section in which an @defgroup defines the group name for the particular -peripheral. This group name will be the same across all families as each one -is documented separately. Thus for a peripheral xxx the header will have a -group name xxx_defines and the source file will have xxx_file. This will allow -the group to appear separately. An @ingroup must be provided to place the group -as a subgroup of the appropriate family grouping. Note that @file is not used. - -The heading section must include the version number and date and authors names -plus a license reference. Any documentation specific to the family can be -included here. If there are common files included then their documentation will -appear in a separate section. - -Common header and source files that are included into a number of families must -have an @addgroup to include its documentation into the appropriate peripheral -group. These headings may include authors and any specific descriptions but the -date and version number must be omitted as it will be included from the family -files. There must not be any reference to family groupings as these common files -will be incorporated into multiple family groups. - -The common files should not be included in an application explicitly. Also the -doxygen preprocessor must be enabled to ensure that all macros and defines are -included. This means that common header files need to have a section at the top -of the file of the type (eg for gpio_common_f24.h): - -/** @cond */ -#ifdef LIBOPENCM3_GPIO_H -/** @endcond */ - -and at the end of the file: - -/** @cond */ -#else -#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" -#endif -/** @endcond */ - -This will stop the compiler preprocessor from including the common header file -unless the device family header file has also been included. The doxygen -conditional clauses are needed to stop the doxygen preprocessor seeing this -statement and so excluding processing of the common file contents. - -/** @cond */ -#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H) -/** @endcond */ - -Each helper function must have a header with an @brief, and where appropriate -additional description, @parameter and @return elements. These latter must -describe the allowable parameter ranges preferably with reference to a suitable -define in the corresponding header file. - -The Doxyfile for a family must include input files from the header and source -subdirectories, as well as all needed common files. The common files can be -added separately or as an entire directory with exclusions of inappropriate -files. - -Doxyfiles ---------- - -Doxyfile_common holds global settings. - -OUTPUT_DIRECTORY blank so that the output is placed in the current directory. -RECURSIVE = NO -EXTERNAL_GROUPS = NO - -Each Doxyfile_include for a processor family has: - -@INCLUDE = ../Doxyfile_common -INPUT = specific directories needed, including /include/libopencm3/cm3 - in top directory to set the top level page and GNU license. -LAYOUT_FILE = DoxygenLayout_$processor.xml -WARN_LOGFILE = doxygen_$processor.log -TAGFILES = ../cm3/cm3.tag=../../cm3/html -GENERATE_TAGFILE = $processor.tag -PREDEFINED = list of macro definitions - -For the top level Doxyfile - -INPUT = ../include/libopencm3/docmain.dox to add in the main page text -LAYOUT_FILE = DoxygenLayout.xml -WARN_LOGFILE = doxygen.log -TAGFILES = cm3/cm3.tag=../cm3/html plus all families to be included. - diff --git a/libopencm3/doc/Makefile b/libopencm3/doc/Makefile deleted file mode 100644 index b638775..0000000 --- a/libopencm3/doc/Makefile +++ /dev/null @@ -1,64 +0,0 @@ -# Makefile to build libopencm3 documentation - -# 14 September 2012 -# (C) Ken Sarkies - -# setup TARGETS if not set for legacy and ease of debug. -TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 stm32/h7 \ - stm32/l0 stm32/l1 stm32/l4 \ - stm32/g0 stm32/g4 \ - gd32/f1x0 \ - efm32/g efm32/gg efm32/hg efm32/lg efm32/tg \ - efm32/wg efm32/ezr32wg \ - lm3s lm4f \ - msp432/e4 \ - lpc13xx lpc17xx lpc43xx \ - sam/3a sam/3n sam/3s sam/3u sam/3x \ - sam/d sam/4l \ - vf6xx \ - swm050 \ - pac55xx - - -TARGETS_DIRS = $(subst /,,$(TARGETS)) - -doc: html - - -DoxygenLayout.xml: templates/DoxygenLayout_Root.xml - ../scripts/gendoxylayout.py --template $< --out $@ $(TARGETS_DIRS) - -define gen_DOC_TARGET -DOC_TARGETS += doc_$(1) -CLEAN_TARGETS += clean_$(1) - -$(1)/: - @mkdir -p $$@ - -$(1)/doxy.sourcelist: $(1)/ - @../scripts/gendoxylist ../lib/$(TARGET_SRC_DIR) $(1) - -$(1)/Doxyfile: templates/Doxyfile_Device | $(1)/ - @cat $$< | sed s/#device#/$(1)/g > $$@ - -$(1)/DoxygenLayout_$(1).xml: templates/DoxygenLayout_Device.xml | $(1)/ - @../scripts/gendoxylayout.py --template $$< --out $$@ --target $(1) $$(TARGETS_DIRS) - -doc_$(1): $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$(1).xml - @(cd $(1); doxygen) - -clean_$(1): - @$(RM) -rf $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$1.xml $(1)/doxygen_$(1).log $(1)/html $(1)/$(1).tag - -endef - -$(foreach TARGET_SRC_DIR, $(TARGETS), $(eval $(call gen_DOC_TARGET,$(subst /,,$(TARGET_SRC_DIR))))) - -html: $(DOC_TARGETS) DoxygenLayout.xml - doxygen - -clean: $(CLEAN_TARGETS) - @rm -rf html/ DoxygenLayout.xml doxygen.log - -.PHONY: doc html $(DOC_TARGETS) $(CLEAN_TARGETS) - diff --git a/libopencm3/doc/README b/libopencm3/doc/README deleted file mode 100644 index a7ac627..0000000 --- a/libopencm3/doc/README +++ /dev/null @@ -1,34 +0,0 @@ -libopencm3 Documentation -14 September 2012 (C) K Sarkies -------------------------------- - -To generate all documentation run 'make doc' in the doc directory, or -for html documentation only run 'make html' (much faster). This runs doxygen -for each of the processor families then integrates the whole. - -Alternatively run 'make doc' in the top directory to make html documentation. -LaTeX and pdf documentation is currently very large in size. - -This requires doxygen v 1.8.2 or later. - -HTML, LaTeX, and pdf output can be produced. - -Generation of HTML ------------------- - -To view HTML, point a browser to libopencm3/doc/html/index.html. - -Generation of PDF ------------------ - -The pdf is generated via LaTeX. The pdf files are placed in the -doc directory. Each file contains all documentation for the core and common -features. The resulting files are huge. - - -Requirements ------------- -On Fedora 19, the following packages (at least!) are needed to build the pdf -output - - texlive texlive-sectsty texlive-tocloft texlive-xtab texlive-multirow diff --git a/libopencm3/doc/efm32ezr32wg/doxy.custom b/libopencm3/doc/efm32ezr32wg/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/efm32ezr32wg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/efm32g/doxy.custom b/libopencm3/doc/efm32g/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/efm32g/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/efm32gg/doxy.custom b/libopencm3/doc/efm32gg/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/efm32gg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/efm32hg/doxy.custom b/libopencm3/doc/efm32hg/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/efm32hg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/efm32lg/doxy.custom b/libopencm3/doc/efm32lg/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/efm32lg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/efm32tg/doxy.custom b/libopencm3/doc/efm32tg/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/efm32tg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/efm32wg/doxy.custom b/libopencm3/doc/efm32wg/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/efm32wg/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/gd32f1x0/doxy.custom b/libopencm3/doc/gd32f1x0/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/gd32f1x0/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/index.html b/libopencm3/doc/index.html deleted file mode 100644 index 7715877..0000000 --- a/libopencm3/doc/index.html +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - Documentation index

- - diff --git a/libopencm3/doc/lm3s/doxy.custom b/libopencm3/doc/lm3s/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/lm3s/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/lm4f/doxy.custom b/libopencm3/doc/lm4f/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/lm4f/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/lpc13xx/doxy.custom b/libopencm3/doc/lpc13xx/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/lpc13xx/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/lpc17xx/doxy.custom b/libopencm3/doc/lpc17xx/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/lpc17xx/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/lpc43xx/doxy.custom b/libopencm3/doc/lpc43xx/doxy.custom deleted file mode 100644 index 8b161c9..0000000 --- a/libopencm3/doc/lpc43xx/doxy.custom +++ /dev/null @@ -1,3 +0,0 @@ -# Empty file to satisfy doxygen include. -# this directory is for shared code between m3 and m4 cores of lpc43xx -# So needs no predefined arch macros diff --git a/libopencm3/doc/lpc43xxm0/doxy.custom b/libopencm3/doc/lpc43xxm0/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/lpc43xxm0/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/lpc43xxm4/doxy.custom b/libopencm3/doc/lpc43xxm4/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/lpc43xxm4/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/msp432e4/doxy.custom b/libopencm3/doc/msp432e4/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/msp432e4/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/pac55xx/doxy.custom b/libopencm3/doc/pac55xx/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/pac55xx/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/sam3a/doxy.custom b/libopencm3/doc/sam3a/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/sam3a/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/sam3n/doxy.custom b/libopencm3/doc/sam3n/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/sam3n/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/sam3s/doxy.custom b/libopencm3/doc/sam3s/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/sam3s/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/sam3u/doxy.custom b/libopencm3/doc/sam3u/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/sam3u/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/sam3x/doxy.custom b/libopencm3/doc/sam3x/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/sam3x/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/sam4l/doxy.custom b/libopencm3/doc/sam4l/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/sam4l/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/samd/doxy.custom b/libopencm3/doc/samd/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/samd/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/stm32f0/doxy.custom b/libopencm3/doc/stm32f0/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/stm32f0/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/stm32f1/doxy.custom b/libopencm3/doc/stm32f1/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/stm32f1/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/stm32f2/doxy.custom b/libopencm3/doc/stm32f2/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/stm32f2/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/stm32f3/doxy.custom b/libopencm3/doc/stm32f3/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32f3/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/stm32f4/doxy.custom b/libopencm3/doc/stm32f4/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32f4/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/stm32f7/doxy.custom b/libopencm3/doc/stm32f7/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32f7/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/stm32g0/doxy.custom b/libopencm3/doc/stm32g0/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/stm32g0/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/stm32g4/doxy.custom b/libopencm3/doc/stm32g4/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32g4/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/stm32h7/doxy.custom b/libopencm3/doc/stm32h7/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32h7/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/stm32l0/doxy.custom b/libopencm3/doc/stm32l0/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/stm32l0/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/stm32l1/doxy.custom b/libopencm3/doc/stm32l1/doxy.custom deleted file mode 100644 index 54f3dc9..0000000 --- a/libopencm3/doc/stm32l1/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7M__ diff --git a/libopencm3/doc/stm32l4/doxy.custom b/libopencm3/doc/stm32l4/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/stm32l4/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/doc/swm050/doxy.custom b/libopencm3/doc/swm050/doxy.custom deleted file mode 100644 index 56f73ff..0000000 --- a/libopencm3/doc/swm050/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_6M__ diff --git a/libopencm3/doc/templates/Doxyfile_Device b/libopencm3/doc/templates/Doxyfile_Device deleted file mode 100644 index 4efe6f5..0000000 --- a/libopencm3/doc/templates/Doxyfile_Device +++ /dev/null @@ -1,8 +0,0 @@ -@INCLUDE = ../Doxyfile_common -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist -@INCLUDE = doxy.custom -WARN_LOGFILE = doxygen_#device#.log -LAYOUT_FILE = DoxygenLayout_#device#.xml -GENERATE_TAGFILE = #device#.tag -ENABLE_PREPROCESSING = YES diff --git a/libopencm3/doc/templates/DoxygenLayout_Device.xml b/libopencm3/doc/templates/DoxygenLayout_Device.xml deleted file mode 100644 index 853301b..0000000 --- a/libopencm3/doc/templates/DoxygenLayout_Device.xml +++ /dev/null @@ -1,185 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/libopencm3/doc/templates/DoxygenLayout_Root.xml b/libopencm3/doc/templates/DoxygenLayout_Root.xml deleted file mode 100644 index e39594f..0000000 --- a/libopencm3/doc/templates/DoxygenLayout_Root.xml +++ /dev/null @@ -1,174 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/libopencm3/doc/vf6xx/doxy.custom b/libopencm3/doc/vf6xx/doxy.custom deleted file mode 100644 index 4789a76..0000000 --- a/libopencm3/doc/vf6xx/doxy.custom +++ /dev/null @@ -1 +0,0 @@ -PREDEFINED += __ARM_ARCH_7EM__ diff --git a/libopencm3/include/libopencm3/cm3/assert.h b/libopencm3/include/libopencm3/cm3/assert.h deleted file mode 100644 index 528eb0f..0000000 --- a/libopencm3/include/libopencm3/cm3/assert.h +++ /dev/null @@ -1,138 +0,0 @@ -/** @defgroup debugging Debugging -@ingroup CM3_defines - -@brief Macros and functions to aid in debugging - -@version 1.0.0 - -@date 25 September 2012 - -Two preprocessor defines control the behavior of assertion check macros in -this module. They allow the choice between generated code size and ease of -debugging. - -If NDEBUG is defined, all assertion checks are disabled and macros do not -generate any code. - -If CM3_ASSERT_VERBOSE is defined, information regarding the position of -assertion checks will be stored in the binary, allowing for more -informative error messages, but also significantly increased code size. As -default assertion checks do not use this information it is only useful if -the application linked with libopencm3 defines its own -cm3_assert_failed_verbose() implementation. - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Tomaz Solc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_CM3_ASSERT_H -#define LIBOPENCM3_CM3_ASSERT_H - -#include - -#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1)) - -#ifdef NDEBUG -# define cm3_assert(expr) (void)0 -# define cm3_assert_not_reached() do { } while (1) -#else -# ifdef CM3_ASSERT_VERBOSE -# define cm3_assert(expr) do { \ - if (CM3_LIKELY(expr)) { \ - (void)0; \ - } else { \ - cm3_assert_failed_verbose( \ - __FILE__, __LINE__, \ - __func__, #expr); \ - } \ - } while (0) -# define cm3_assert_not_reached() \ - cm3_assert_failed_verbose( \ - __FILE__, __LINE__, \ - __func__, 0) -# else -/** @brief Check if assertion is true. - * - * If NDEBUG macro is defined, this macro generates no code. Otherwise - * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion - * is false. - * - * The purpose of this macro is to aid in debugging libopencm3 and - * applications using it. It can be used for example to check if function - * arguments are within expected ranges and stop execution in case an - * unexpected state is reached. - * - * @param expr expression to check */ -# define cm3_assert(expr) do { \ - if (CM3_LIKELY(expr)) { \ - (void)0; \ - } else { \ - cm3_assert_failed(); \ - } \ - } while (0) -/** @brief Check if unreachable code is reached. - * - * If NDEBUG macro is defined, this macro generates code for an infinite loop. - * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if - * the macro is ever reached. - * - * The purpose of this macro is to aid in debugging libopencm3 and - * applications using it. It can be used for example to stop execution if an - * unreachable portion of code is reached. */ -# define cm3_assert_not_reached() cm3_assert_failed() -# endif -#endif - -BEGIN_DECLS - -/** @brief Called on a failed assertion. - * - * Halts execution in an infinite loop. This function never returns. - * - * Defined as a weak symbol, so applications can define their own - * implementation. Usually, a custom implementation of this function should - * report an error in some way (print a message to a debug console, display, - * LED, ...) and halt execution or reboot the device. */ -void cm3_assert_failed(void) __attribute__((__noreturn__)); - -/** @brief Called on a failed assertion with verbose messages enabled. - * - * Halts execution in an infinite loop. This function never returns. - * - * Defined as a weak symbol, so applications can define their own - * implementation. Usually, a custom implementation of this function should - * report an error in some way (print a message to a debug console, display, - * LED, ...) and halt execution or reboot the device. - * - * @param file File name where the failed assertion occurred - * @param line Line number where the failed assertion occurred - * @param func Name of the function where the failed assertion occurred - * @param assert_expr Expression that evaluated to false (can be NULL) */ -void cm3_assert_failed_verbose(const char *file, int line, const char *func, - const char *assert_expr) __attribute__((__noreturn__)); - -END_DECLS - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/cm3/common.h b/libopencm3/include/libopencm3/cm3/common.h deleted file mode 100644 index 04714e0..0000000 --- a/libopencm3/include/libopencm3/cm3/common.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_COMMON_H -#define LIBOPENCM3_CM3_COMMON_H - -#ifdef __cplusplus -/* Declarations need wrapping for C++ */ -# define BEGIN_DECLS extern "C" { -# define END_DECLS } -#elif defined(__ASSEMBLER__) -/* skipping for assembly */ -#define BEGIN_DECLS .if 0 -#define END_DECLS .endif -#else -/* And nothing for C */ -# define BEGIN_DECLS -# define END_DECLS -#endif - -/* Full-featured deprecation attribute with fallback for older compilers. */ - -#ifdef __GNUC__ -# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4) -# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x))) -# else -# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated)) -# endif -#else -# define LIBOPENCM3_DEPRECATED(x) -#endif - - -#if defined (__ASSEMBLER__) -#define MMIO8(addr) (addr) -#define MMIO16(addr) (addr) -#define MMIO32(addr) (addr) -#define MMIO64(addr) (addr) - -#define BBIO_SRAM(addr, bit) \ - (((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4) - -#define BBIO_PERIPH(addr, bit) \ - (((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) -#else - -#include -#include - -/* Generic memory-mapped I/O accessor functions */ -#define MMIO8(addr) (*(volatile uint8_t *)(addr)) -#define MMIO16(addr) (*(volatile uint16_t *)(addr)) -#define MMIO32(addr) (*(volatile uint32_t *)(addr)) -#define MMIO64(addr) (*(volatile uint64_t *)(addr)) - -/* Generic bit-band I/O accessor functions */ -#define BBIO_SRAM(addr, bit) \ - MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4) - -#define BBIO_PERIPH(addr, bit) \ - MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) -#endif - -/* Generic bit definition */ -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/libopencm3/include/libopencm3/cm3/cortex.h b/libopencm3/include/libopencm3/cm3/cortex.h deleted file mode 100644 index 6b4b026..0000000 --- a/libopencm3/include/libopencm3/cm3/cortex.h +++ /dev/null @@ -1,285 +0,0 @@ -/** @defgroup CM3_cortex_defines Cortex Core Defines - * - * @brief libopencm3 Defined Constants and Types for the Cortex Core - * - * @ingroup CM3_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Ben Gamari - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CORTEX_H -#define LIBOPENCM3_CORTEX_H - -/**@{*/ - -#include -#include - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Enable interrupts - * - * Disable the interrupt mask and enable interrupts globally - */ -static inline void cm_enable_interrupts(void) -{ - __asm__ volatile ("CPSIE I\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Disable interrupts - * - * Mask all interrupts globally - */ -static inline void cm_disable_interrupts(void) -{ - __asm__ volatile ("CPSID I\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Enable faults - * - * Disable the HardFault mask and enable fault interrupt globally - */ -static inline void cm_enable_faults(void) -{ - __asm__ volatile ("CPSIE F\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Disable faults - * - * Mask the HardFault interrupt globally - */ -static inline void cm_disable_faults(void) -{ - __asm__ volatile ("CPSID F\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Check if interrupts are masked - * - * Checks, if interrupts are masked (disabled). - * - * @returns true, if interrupts are disabled. - */ -__attribute__((always_inline)) -static inline bool cm_is_masked_interrupts(void) -{ - register uint32_t result; - __asm__ volatile ("MRS %0, PRIMASK" : "=r" (result)); - return result; -} - -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Check if Fault interrupt is masked - * - * Checks, if HardFault interrupt is masked (disabled). - * - * @returns bool true, if HardFault interrupt is disabled. - */ -__attribute__((always_inline)) -static inline bool cm_is_masked_faults(void) -{ - register uint32_t result; - __asm__ volatile ("MRS %0, FAULTMASK" : "=r" (result)); - return result; -} -#endif - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Mask interrupts - * - * This function switches the mask of the interrupts. If mask is true, the - * interrupts will be disabled. The result of this function can be used for - * restoring previous state of the mask. - * - * @param[in] mask uint32_t New state of the interrupt mask - * @returns uint32_t old state of the interrupt mask - */ -__attribute__((always_inline)) -static inline uint32_t cm_mask_interrupts(uint32_t mask) -{ - register uint32_t old; - __asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old)); - __asm__ __volatile__("" : : : "memory"); - __asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask)); - return old; -} - -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Mask HardFault interrupt - * - * This function switches the mask of the HardFault interrupt. If mask is true, - * the HardFault interrupt will be disabled. The result of this function can be - * used for restoring previous state of the mask. - * - * @param[in] mask uint32_t New state of the HardFault interrupt mask - * @returns uint32_t old state of the HardFault interrupt mask - */ -__attribute__((always_inline)) -static inline uint32_t cm_mask_faults(uint32_t mask) -{ - register uint32_t old; - __asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old)); - __asm__ __volatile__ ("" : : : "memory"); - __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask)); - return old; -} -#endif - -/**@}*/ - -/*===========================================================================*/ -/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines - * - * @brief Atomic operation support - * - * @ingroup CM3_cortex_defines - */ -/**@{*/ - -#if !defined(__DOXYGEN__) -/* Do not populate this definition outside */ -static inline uint32_t __cm_atomic_set(uint32_t *val) -{ - return cm_mask_interrupts(*val); -} - -#define __CM_SAVER(state) \ - __val = (state), \ - __save __attribute__((__cleanup__(__cm_atomic_set))) = \ - __cm_atomic_set(&__val) - -#endif /* !defined(__DOXYGEN) */ - - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Atomic Declare block - * - * This macro disables interrupts for the next command or block of code. The - * interrupt mask is automatically restored after exit of the boundary of the - * code block. Therefore restore of interrupt is done automatically after call - * of return or goto control sentence jumping outside of the block. - * - * @warning The usage of sentences break or continue is prohibited in the block - * due to implementation of this macro! - * - * @note It is safe to use this block inside normal code and in interrupt - * routine. - * - * Basic usage of atomic block - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * CM_ATOMIC_BLOCK() { // interrupts are masked in this block - * value = value * 1024 + 651; // access value as atomic - * } // interrupts is restored automatically - * @endcode - * - * Use of return inside block - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * uint64_t allocval(void) - * { - * CM_ATOMIC_BLOCK() { // interrupts are masked in this block - * value = value * 1024 + 651; // do long atomic operation - * return value; // interrupts is restored automatically - * } - * } - * @endcode - */ -#if defined(__DOXYGEN__) -#define CM_ATOMIC_BLOCK() -#else /* defined(__DOXYGEN__) */ -#define CM_ATOMIC_BLOCK() \ - for (uint32_t __CM_SAVER(true), __my = true; __my; __my = false) -#endif /* defined(__DOXYGEN__) */ - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Atomic Declare context - * - * This macro disables interrupts in the current block of code from the place - * where it is defined to the end of the block. The interrupt mask is - * automatically restored after exit of the boundary of the code block. - * Therefore restore of interrupt is done automatically after call of return, - * continue, break, or goto control sentence jumping outside of the block. - * - * @note This function is intended for use in for- cycles to enable the use of - * break and contine sentences inside the block, and for securing the atomic - * reader-like functions. - * - * @note It is safe to use this block inside normal code and in interrupt - * routine. - * - * Basic usage of atomic context - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * for (int i=0;i < 100; i++) { - * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block - * value += 100; // access value as atomic - * if ((value % 16) == 0) { - * break; // restore interrupts and break cycle - * } - * } // interrupts is restored automatically - * @endcode - * - * Usage of atomic context inside atomic reader fcn. - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * uint64_t getnextval(void) - * { - * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block - * value = value + 3; // do long atomic operation - * return value; // interrupts is restored automatically - * } - * @endcode - */ -#if defined(__DOXYGEN__) -#define CM_ATOMIC_CONTEXT() -#else /* defined(__DOXYGEN__) */ -#define CM_ATOMIC_CONTEXT() uint32_t __CM_SAVER(true) -#endif /* defined(__DOXYGEN__) */ - -/**@}*/ - - - -#endif diff --git a/libopencm3/include/libopencm3/cm3/doc-cm3.h b/libopencm3/include/libopencm3/cm3/doc-cm3.h deleted file mode 100644 index 1924b17..0000000 --- a/libopencm3/include/libopencm3/cm3/doc-cm3.h +++ /dev/null @@ -1,26 +0,0 @@ -/** @mainpage libopencm3 Core CM3 - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for Cortex M3 core features. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup CM3_defines CM3 Defines - -@brief Defined Constants and Types for Cortex M3 core features - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup CM3_files Cortex Core Peripheral APIs - * APIs for Cortex Core peripherals - */ - diff --git a/libopencm3/include/libopencm3/cm3/dwt.h b/libopencm3/include/libopencm3/cm3/dwt.h deleted file mode 100644 index 4b7d24c..0000000 --- a/libopencm3/include/libopencm3/cm3/dwt.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_DWT_H -#define LIBOPENCM3_CM3_DWT_H - -#include -#include - -/** - * @defgroup cm_dwt Cortex-M Data Watch and Trace unit. - * @ingroup CM3_defines - * System Control Space (SCS) => Data Watchpoint and Trace (DWT). - * See "ARMv7-M Architecture Reference Manual" - * and "ARMv6-M Architecture Reference Manual" - * The DWT is an optional debug unit that provides watchpoints, data tracing, - * and system profiling for the processor. - * @{ - */ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/** DWT Control register - * Purpose Provides configuration and status information for the DWT block, and - * used to control features of the block - * Usage constraints: There are no usage constraints. - * Configurations Always implemented. - */ -#define DWT_CTRL MMIO32(DWT_BASE + 0x00) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - -/** - * DWT_CYCCNT register - * Cycle Count Register (Shows or sets the value of the processor cycle - * counter, CYCCNT) - * When enabled, CYCCNT increments on each processor clock cycle. On overflow, - * CYCCNT wraps to zero. - * - * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. - * Usage constraints: The DWT unit suspends CYCCNT counting when the processor - * is in Debug state. - * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control - * register, DWT_CTRL. - * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this - * register is UNK/SBZP. -*/ -#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04) - -/** DWT_CPICNT register - * Purpose Counts additional cycles required to execute multi-cycle - * instructions and instruction fetch stalls. - * Usage constraints: The counter initializes to 0 when software enables its - * counter overflow event by - * setting the DWT_CTRL.CPIEVTENA bit to 1. - * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control - * register, DWT_CTRL. - * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not - * include the profiling counters, this register is UNK/SBZP. - */ -#define DWT_CPICNT MMIO32(DWT_BASE + 0x08) -#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) -#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) -#define DWT_LSUCNT MMIO32(DWT_BASE + 0x14) -#define DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) - -#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ - -#define DWT_PCSR MMIO32(DWT_BASE + 0x1C) -#define DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16) -#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16) -#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16) - -/* CoreSight Lock Status Register for this peripheral */ -#define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET) -/* CoreSight Lock Access Register for this peripheral */ -#define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET) - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- DWT_CTRL values ---------------------------------------------------- */ - -#define DWT_CTRL_NUMCOMP_SHIFT 28 -#define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - -#define DWT_CTRL_NOTRCPKT (1 << 27) -#define DWT_CTRL_NOEXTTRIG (1 << 26) -#define DWT_CTRL_NOCYCCNT (1 << 25) -#define DWT_CTRL_NOPRFCCNT (1 << 24) - -#define DWT_CTRL_CYCEVTENA (1 << 22) -#define DWT_CTRL_FOLDEVTENA (1 << 21) -#define DWT_CTRL_LSUEVTENA (1 << 20) -#define DWT_CTRL_SLEEPEVTENA (1 << 19) -#define DWT_CTRL_EXCEVTENA (1 << 18) -#define DWT_CTRL_CPIEVTENA (1 << 17) -#define DWT_CTRL_EXCTRCENA (1 << 16) -#define DWT_CTRL_PCSAMPLENA (1 << 12) - -#define DWT_CTRL_SYNCTAP_SHIFT 10 -#define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT) -#define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT) -#define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT) -#define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT) -#define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT) - -#define DWT_CTRL_CYCTAP (1 << 9) - -#define DWT_CTRL_POSTCNT_SHIFT 5 -#define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT) - -#define DWT_CTRL_POSTPRESET_SHIFT 1 -#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT) - -/** - * CYCCNTENA Enables the Cycle counter. - * 0 = Disabled, 1 = Enabled - * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. - */ -#define DWT_CTRL_CYCCNTENA (1 << 0) - -#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ - -/* --- DWT_MASK(x) values -------------------------------------------------- */ - -#define DWT_MASKx_MASK 0x0F - -/* --- DWT_FUNCTION(x) values ---------------------------------------------- */ - -#define DWT_FUNCTIONx_MATCHED (1 << 24) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - -#define DWT_FUNCTIONx_DATAVADDR1_SHIFT 16 -#define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT) - -#define DWT_FUNCTIONx_DATAVADDR0_SHIFT 12 -#define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT) - -#define DWT_FUNCTIONx_DATAVSIZE_SHIFT 10 -#define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) -#define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) -#define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) -#define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) - -#define DWT_FUNCTIONx_LNK1ENA (1 << 9) -#define DWT_FUNCTIONx_DATAVMATCH (1 << 8) -#define DWT_FUNCTIONx_CYCMATCH (1 << 7) -#define DWT_FUNCTIONx_EMITRANGE (1 << 5) - -#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ - -#define DWT_FUNCTIONx_FUNCTION 15 -#define DWT_FUNCTIONx_FUNCTION_DISABLED 0 - -/* Those defined only on ARMv6 */ -#if defined(__ARM_ARCH_6M__) - -#define DWT_FUNCTIONx_FUNCTION_PCWATCH 4 -#define DWT_FUNCTIONx_FUNCTION_DWATCH_R 5 -#define DWT_FUNCTIONx_FUNCTION_DWATCH_W 6 -#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW 7 - -#endif /* defined(__ARM_ARCH_6M__)*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -bool dwt_enable_cycle_counter(void); -uint32_t dwt_read_cycle_counter(void); - -END_DECLS - -/**@}*/ - -#endif /* LIBOPENCM3_CM3_DWT_H */ diff --git a/libopencm3/include/libopencm3/cm3/fpb.h b/libopencm3/include/libopencm3/cm3/fpb.h deleted file mode 100644 index d2f6505..0000000 --- a/libopencm3/include/libopencm3/cm3/fpb.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_FPB_H -#define LIBOPENCM3_CM3_FPB_H - -/** - * @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit - * @ingroup CM3_defines - * @{ - */ - -/* Those defined only on ARMv7 and above */ -#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) -#error "Flash Patch and Breakpoint not available in CM0" -#endif - -/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */ - -/* --- FPB registers ------------------------------------------------------- */ - -/* Flash Patch Control (FPB_CTRL) */ -#define FPB_CTRL MMIO32(FPB_BASE + 0) - -/* Flash Patch Remap (FPB_REMAP) */ -#define FPB_REMAP MMIO32(FPB_BASE + 4) - -/* Flash Patch Comparator (FPB_COMPx) */ -#define FPB_COMP (&MMIO32(FPB_BASE + 8)) - -/* CoreSight Lock Status Register for this peripheral */ -#define FPB_LSR MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET) -/* CoreSight Lock Access Register for this peripheral */ -#define FPB_LAR MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET) - - -/* TODO: PID, CID */ - -/* --- FPB_CTRL values ----------------------------------------------------- */ - -/* Bits [31:15]: Reserved, read as zero, writes ignored */ - -#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12) - -#define FPB_CTRL_NUM_LIT_MASK (0xf << 8) - -#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4) - -/* Bits [3:2]: Reserved */ - -#define FPB_CTRL_KEY (1 << 1) - -#define FPB_CTRL_ENABLE (1 << 0) - -/* --- FPB_REMAP values ---------------------------------------------------- */ - -/* TODO */ - -/* --- FPB_COMPx values ---------------------------------------------------- */ - -#define FPB_COMP_REPLACE_REMAP (0x0 << 30) -#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30) -#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30) -#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30) -#define FPB_COMP_REPLACE_MASK (0x3 << 30) - -/* Bit 29: Reserved */ - -/* TODO */ - -/* Bit 1: Reserved */ - -#define FPB_COMP_ENABLE (1 << 0) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/itm.h b/libopencm3/include/libopencm3/cm3/itm.h deleted file mode 100644 index dc711a0..0000000 --- a/libopencm3/include/libopencm3/cm3/itm.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_ITM_H -#define LIBOPENCM3_CM3_ITM_H - -/** - * @defgroup cm_itm Cortex-M Instrumentation Trace Macrocell (ITM) - * @ingroup CM3_defines - * @{ - */ - -/* Those defined only on ARMv7 and above */ -#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) -#error "Instrumentation Trace Macrocell not available in CM0" -#endif - -/* --- ITM registers ------------------------------------------------------- */ - -/* Stimulus Port x (ITM_STIM(x)) */ -#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4))) -#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4))) -#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4))) - -/* Trace Enable ports (ITM_TER[x]) */ -#define ITM_TER (&MMIO32(ITM_BASE + 0xE00)) - -/* Trace Privilege (ITM_TPR) */ -#define ITM_TPR MMIO32(ITM_BASE + 0xE40) - -/* Trace Control (ITM_TCR) */ -#define ITM_TCR MMIO32(ITM_BASE + 0xE80) - -/* CoreSight Lock Status Register for this peripheral */ -#define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET) -/* CoreSight Lock Access Register for this peripheral */ -#define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET) - -/* TODO: PID, CID */ - -/* --- ITM_STIM values ----------------------------------------------------- */ - -/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */ -/* Bits 31:1 - RAZ */ -#define ITM_STIM_FIFOREADY (1 << 0) - -/* --- ITM_TER values ------------------------------------------------------ */ - -/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */ - -/* --- ITM_TPR values ------------------------------------------------------ */ -/* - * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7 - * 0: User access allowed to stimulus ports - * 1: Privileged access only to stimulus ports - */ - -/* --- ITM_TCR values ------------------------------------------------------ */ - -/* Bits 31:24 - Reserved */ -#define ITM_TCR_BUSY (1 << 23) -#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16) -/* Bits 15:10 - Reserved */ -#define ITM_TCR_TSPRESCALE_NONE (0 << 8) -#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8) -#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8) -#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8) -#define ITM_TCR_TSPRESCALE_MASK (3 << 8) -/* Bits 7:5 - Reserved */ -#define ITM_TCR_SWOENA (1 << 4) -#define ITM_TCR_TXENA (1 << 3) -#define ITM_TCR_SYNCENA (1 << 2) -#define ITM_TCR_TSENA (1 << 1) -#define ITM_TCR_ITMENA (1 << 0) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/memorymap.h b/libopencm3/include/libopencm3/cm3/memorymap.h deleted file mode 100644 index 954328a..0000000 --- a/libopencm3/include/libopencm3/cm3/memorymap.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_MEMORYMAP_H -#define LIBOPENCM3_CM3_MEMORYMAP_H - -/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */ - -/* Private peripheral bus - Internal */ -#define PPBI_BASE (0xE0000000U) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* ITM: Instrumentation Trace Macrocell */ -#define ITM_BASE (PPBI_BASE + 0x0000) - -/* DWT: Data Watchpoint and Trace unit */ -#define DWT_BASE (PPBI_BASE + 0x1000) - -/* FPB: Flash Patch and Breakpoint unit */ -#define FPB_BASE (PPBI_BASE + 0x2000) -#endif - -/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */ - -#define SCS_BASE (PPBI_BASE + 0xE000) - -/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */ - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -#define TPIU_BASE (PPBI_BASE + 0x40000) -#endif - -/* --- SCS: System Control Space --- */ - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* ITR: Interrupt Type Register */ -#define ITR_BASE (SCS_BASE + 0x0000) -#endif - -/* SYS_TICK: System Timer */ -#define SYS_TICK_BASE (SCS_BASE + 0x0010) - -/* NVIC: Nested Vector Interrupt Controller */ -#define NVIC_BASE (SCS_BASE + 0x0100) - -/* SCB: System Control Block */ -#define SCB_BASE (SCS_BASE + 0x0D00) - -/* MPU: Memory protection unit */ -#define MPU_BASE (SCS_BASE + 0x0D90) - -/* Those defined only on CM0*/ -#if defined(__ARM_ARCH_6M__) -/* DEBUG: Debug control and configuration */ -#define DEBUG_BASE (SCS_BASE + 0x0DF0) -#endif - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* STE: Software Trigger Interrupt Register */ -#define STIR_BASE (SCS_BASE + 0x0F00) -/* ID: ID space */ -#define ID_BASE (SCS_BASE + 0x0FD0) -#endif - -/** - * @defgroup coresight_registers Coresight Registers - * @{ - * CoreSight Lock Status Registers and Lock Access Registers are - * documented for the DWT, ITM, FPB and TPIU peripherals - */ -#define CORESIGHT_LSR_OFFSET 0xfb4 -#define CORESIGHT_LAR_OFFSET 0xfb0 - -/** CoreSight Lock Status Register lock status bit */ -#define CORESIGHT_LSR_SLK (1<<1) -/** CoreSight Lock Status Register lock availability bit */ -#define CORESIGHT_LSR_SLI (1<<0) -/** CoreSight Lock Access key, common for all */ -#define CORESIGHT_LAR_KEY 0xC5ACCE55 - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/mpu.h b/libopencm3/include/libopencm3/cm3/mpu.h deleted file mode 100644 index d47abc6..0000000 --- a/libopencm3/include/libopencm3/cm3/mpu.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @defgroup CM3_mpu_defines Cortex-M MPU Defines - * - * @brief libopencm3 Cortex Memory Protection Unit - * - * @ingroup CM3_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * - * The MPU is available as an option in both ARMv6-M and ARMv7-M, but it has - * more features in v7, particularly in the available attributes. - * - * For more information see the ARM Architecture reference manuals. - */ -/**@{*/ - -#ifndef LIBOPENCM3_MPU_H -#define LIBOPENCM3_MPU_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ -/** @defgroup CM3_mpu_registers MPU Registers - * @ingroup CM3_mpu_defines - * - *@{*/ -/** MPU_TYPE is always available, even if the MPU is not implemented */ -#define MPU_TYPE MMIO32(MPU_BASE + 0x00) -#define MPU_CTRL MMIO32(MPU_BASE + 0x04) -#define MPU_RNR MMIO32(MPU_BASE + 0x08) -#define MPU_RBAR MMIO32(MPU_BASE + 0x0C) -#define MPU_RASR MMIO32(MPU_BASE + 0x10) -/**@}*/ - -/* --- MPU values ---------------------------------------------------------- */ - -/** @defgroup CM3_mpu_type MPU TYPE register fields - * @ingroup CM3_mpu_defines - * The MPU_TYPE register is always available, even if the MPU is not implemented. - * In that case, the DREGION field will read as 0. - *@{*/ -/** v6m/v7m only support a unified MPU (IREGION always 0) */ -#define MPU_TYPE_IREGION_LSB 16 -#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB) -/** DREGION is non zero if the MPU is available */ -#define MPU_TYPE_DREGION_LSB 8 -#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB) -/** v6m/v7m only support a unifed MPU (Separate always 0) */ -#define MPU_TYPE_SEPARATE (1<<0) -/**@}*/ - -/** @defgroup CM3_mpu_ctrl MPU CTRL register fields - * @ingroup CM3_mpu_defines - * Defines for the Control Register. - *@{*/ -#define MPU_CTRL_PRIVDEFENA (1<<2) -#define MPU_CTRL_HFNMIENA (1<<1) -#define MPU_CTRL_ENABLE (1<<0) -/**@}*/ - -/** @defgroup CM3_mpu_rnr MPU RNR register fields - * @ingroup CM3_mpu_defines - * Defines for the Region Number Register. - *@{*/ -#define MPU_RNR_REGION_LSB 0 -#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB) -/**@}*/ - -/** @defgroup CM3_mpu_rbar MPU RBAR register fields - * @ingroup CM3_mpu_defines - * Defines for the Region Base Address Register. - *@{*/ -/** minimum size supported is by writing all ones to ADDR, then reading back */ -#define MPU_RBAR_ADDR 0xFFFFFFE0 -#define MPU_RBAR_VALID (1<<4) -#define MPU_RBAR_REGION_LSB 0 -#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB) -/**@}*/ - -/** @defgroup CM3_mpu_rasr MPU RASR register fields - * @ingroup CM3_mpu_defines - * Defines for the Region Attribute and Size Register. - *@{*/ -#define MPU_RASR_ATTRS_LSB 16 -#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB) -#define MPU_RASR_SRD_LSB 8 -#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB) -#define MPU_RASR_SIZE_LSB 1 -#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB) -#define MPU_RASR_ENABLE (1 << 0) - -/** @defgroup mpu_rasr_attributes MPU RASR Attributes - * @ingroup CM3_mpu_rasr - * Not all attributes are available on v6m. - * - *@{*/ -#define MPU_RASR_ATTR_XN (1 << 28) -#define MPU_RASR_ATTR_AP (7 << 24) -#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24) -#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24) -#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24) -#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24) -#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24) -#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24) -#define MPU_RASR_ATTR_TEX (7 << 19) -#define MPU_RASR_ATTR_S (1 << 18) -#define MPU_RASR_ATTR_C (1 << 17) -#define MPU_RASR_ATTR_B (1 << 16) -#define MPU_RASR_ATTR_SCB (7 << 16) -/**@}*/ -/**@}*/ - -/* --- MPU functions ------------------------------------------------------- */ - -BEGIN_DECLS - - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/nvic.h b/libopencm3/include/libopencm3/cm3/nvic.h deleted file mode 100644 index c967f15..0000000 --- a/libopencm3/include/libopencm3/cm3/nvic.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/** @defgroup CM3_nvic_defines Cortex-M NVIC Defines - * - * @brief libopencm3 Cortex Nested Vectored Interrupt Controller - * - * @ingroup CM3_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ -/**@{*/ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/** @defgroup nvic_registers NVIC Registers - * @{ - */ - -/** ISER: Interrupt Set Enable Registers - * @note 8 32bit Registers - * @note Single register on CM0 - */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ - ((iser_id) * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/** ICER: Interrupt Clear Enable Registers - * @note 8 32bit Registers - * @note Single register on CM0 - */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ - ((icer_id) * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/** ISPR: Interrupt Set Pending Registers - * @note 8 32bit Registers - * @note Single register on CM0 - */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ - ((ispr_id) * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/** ICPR: Interrupt Clear Pending Registers - * @note 8 32bit Registers - * @note Single register on CM0 - */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ - ((icpr_id) * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/** IABR: Interrupt Active Bit Register - * @note 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ - ((iabr_id) * 4)) -#endif - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/** IPR: Interrupt Priority Registers - * @note 240 8bit Registers - * @note 32 8bit Registers on CM0, requires word access - */ -#if defined(__ARM_ARCH_6M__) -#define NVIC_IPR32(ipr_id) MMIO32(NVIC_BASE + 0x300 + \ - ((ipr_id) * 4)) -#else -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ - (ipr_id)) -#endif - -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/** STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) -#endif - -/**@}*/ - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M0, M3 and M4 System Interrupts */ -/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts -@ingroup CM3_nvic_defines - -IRQ numbers -3 and -6 to -9 are reserved -@{*/ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -#endif - -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -#define DEBUG_MONITOR_IRQ -4 -#endif - -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 -/**@}*/ - -/* @note User interrupts are family specific and are defined in a family - * specific header file in the corresponding subfolder. - */ - -#include - -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(uint8_t irqn); -void nvic_disable_irq(uint8_t irqn); -uint8_t nvic_get_pending_irq(uint8_t irqn); -void nvic_set_pending_irq(uint8_t irqn); -void nvic_clear_pending_irq(uint8_t irqn); -uint8_t nvic_get_irq_enabled(uint8_t irqn); -void nvic_set_priority(uint8_t irqn, uint8_t priority); - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -uint8_t nvic_get_active_irq(uint8_t irqn); -void nvic_generate_software_interrupt(uint16_t irqn); -#endif - -void reset_handler(void); -void nmi_handler(void); -void hard_fault_handler(void); -void sv_call_handler(void); -void pend_sv_handler(void); -void sys_tick_handler(void); - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -void mem_manage_handler(void); -void bus_fault_handler(void); -void usage_fault_handler(void); -void debug_monitor_handler(void); -#endif - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/scb.h b/libopencm3/include/libopencm3/cm3/scb.h deleted file mode 100644 index 4b3e4f7..0000000 --- a/libopencm3/include/libopencm3/cm3/scb.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -/** - * @defgroup cm_scb Cortex-M System Control Block - * @ingroup CM3_defines - * - * The System Control Block is a section of the System Control Space. - * Other members of the SCS are, for instance, DWT, ITM, SYSTICKK. - * The exact details of the SCB are defined in the "Architecture Reference - * Manual" for either ARMv7-M or ARMV6-m. - * @{ - */ -#include -#include - -/** @defgroup cm_scb_registers SCB Registers - * @ingroup cm_scb - * @{ - */ - -/** CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/** ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/** VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/** AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/** SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/** CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/** System Handler Priority 8 bits Registers, SHPR1/2/3. - * @note: 12 8bit Registers - * @note: 2 32bit Registers on CM0, requires word access, - * (shpr1 doesn't actually exist) - */ -#if defined(__ARM_ARCH_6M__) -#define SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4)) -#else -#define SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id)) -#endif - -/** SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/** DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/** CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/** HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/** MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/** BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/** AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/** ID_PFR0: Processor Feature Register 0 */ -#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) - -/** ID_PFR1: Processor Feature Register 1 */ -#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) - -/** ID_DFR0: Debug Features Register 0 */ -#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) - -/** ID_AFR0: Auxiliary Features Register 0 */ -#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) - -/** ID_MMFR0: Memory Model Feature Register 0 */ -#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) - -/** ID_MMFR1: Memory Model Feature Register 1 */ -#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) - -/** ID_MMFR2: Memory Model Feature Register 2 */ -#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) - -/** ID_MMFR3: Memory Model Feature Register 3 */ -#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) - -/** ID_ISAR0: Instruction Set Attributes Register 0 */ -#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) - -/** ID_ISAR1: Instruction Set Attributes Register 1 */ -#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) - -/** ID_ISAR2: Instruction Set Attributes Register 2 */ -#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) - -/** ID_ISAR3: Instruction Set Attributes Register 3 */ -#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) - -/** ID_ISAR4: Instruction Set Attributes Register 4 */ -#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) - -/** CPACR: Coprocessor Access Control Register */ -#define SCB_CPACR MMIO32(SCB_BASE + 0x88) - -/** FPCCR: Floating-Point Context Control Register */ -#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) - -/** FPCAR: Floating-Point Context Address Register */ -#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) - -/** FPDSCR: Floating-Point Default Status Control Register */ -#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) - -/** MVFR0: Media and Floating-Point Feature Register 0 */ -#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) - -/** MVFR1: Media and Floating-Point Feature Register 1 */ -#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) -#endif - -/**@}*/ - -/* --- SCB values ---------------------------------------------------------- */ - -/** - * @defgroup cm3_scb_cpuid_values SCB_CPUID Values - * @{ - */ -/** Implementer[31:24]: Implementer code */ -#define SCB_CPUID_IMPLEMENTER_LSB 24 -#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB) -/** Variant[23:20]: Variant number */ -#define SCB_CPUID_VARIANT_LSB 20 -#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB) -/** Constant[19:16] - * Reads as 0xF (ARMv7-M) M3, M4 - * Reads as 0xC (ARMv6-M) M0, M0+ - */ -#define SCB_CPUID_CONSTANT_LSB 16 -#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB) -#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB) -#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB) - -/** PartNo[15:4]: Part number of the processor */ -#define SCB_CPUID_PARTNO_LSB 4 -#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB) -/** Revision[3:0]: Revision number */ -#define SCB_CPUID_REVISION_LSB 0 -#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB) -/**@}*/ - -/** - * @defgroup cm3_scb_icsr_values SCB_ICSR Values - * @{ - */ -/** NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/** PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/** PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/** PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/** PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/** Bit 23: reserved for debug - reads as 0 when not in debug mode */ -#define SCB_ICSR_ISRPREEMPT (1 << 23) -/** ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/** VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB) -/** RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/** VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 -#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB) -/**@}*/ - -/** - * @defgroup cm3_scb_vtor_values SCB_VTOR Values - * @{ - */ - -/* IMPLEMENTATION DEFINED */ - -#if defined(__ARM_ARCH_6M__) - -#define SCB_VTOR_TBLOFF_LSB 7 -#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB) - -#elif defined(CM1) -/* VTOR not defined there */ - -#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -/* inconsistent datasheet - LSB could be 11 */ -/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */ -#define SCB_VTOR_TBLOFF_LSB 9 -#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB) - -#endif -/**@}*/ - - -/** - * @defgroup cm3_scb_aicr_values SCB_AICR Values - * @{ - */ -/** VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB) -#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB) - -/** ENDIANNESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* Bits [14:11]: reserved - must be kept cleared */ -/** PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) -#define SCB_AIRCR_PRIGROUP_SHIFT 8 -/* Bits [7:3]: reserved - must be kept cleared */ -#endif - -/** SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/** VECTCLRACTIVE clears state information for exceptions */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/** VECTRESET cause local system reset */ -#define SCB_AIRCR_VECTRESET (1 << 0) -#endif -/**@}*/ - -/** - * @defgroup cm3_scb_scr_values SCB_SCR Values - * @{ - */ -/* Bits [31:5]: reserved - must be kept cleared */ -/** SEVONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/** SLEEPDEEP implementation defined */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/** SLEEPONEXIT sleep when exiting ISR */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ -/**@}*/ - -/** - * @defgroup cm3_scb_ccr_values SCB_CCR Values - * @{ - */ -/* Bits [31:10]: reserved - must be kept cleared */ -/** STKALIGN set to zero to break things :) */ -#define SCB_CCR_STKALIGN (1 << 9) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/** BFHFNMIGN set to attempt ignoring faults in handlers */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/** DIV_0_TRP set to trap on divide by zero*/ -#define SCB_CCR_DIV_0_TRP (1 << 4) -#endif - -/** UNALIGN_TRP set to trap on unaligned */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* Bit 2: reserved - must be kept cleared */ -/** USERSETMPEND set to allow unprivileged access to STIR */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/** NONBASETHRDENA set to allow non base priority threads */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) -#endif -/**@}*/ - -/* These numbers are designed to be used with the SCB_SHPR() macro */ -/* SCB_SHPR1 */ -#define SCB_SHPR_PRI_4_MEMMANAGE 0 -#define SCB_SHPR_PRI_5_BUSFAULT 1 -#define SCB_SHPR_PRI_6_USAGEFAULT 2 -#define SCB_SHPR_PRI_7_RESERVED 3 -/* SCB_SHPR2 */ -#define SCB_SHPR_PRI_8_RESERVED 4 -#define SCB_SHPR_PRI_9_RESERVED 5 -#define SCB_SHPR_PRI_10_RESERVED 6 -#define SCB_SHPR_PRI_11_SVCALL 7 -/* SCB_SHPR3 */ -#define SCB_SHPR_PRI_12_RESERVED 8 -#define SCB_SHPR_PRI_13_RESERVED 9 -#define SCB_SHPR_PRI_14_PENDSV 10 -#define SCB_SHPR_PRI_15_SYSTICK 11 - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -#endif - -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB_CPACR values ---------------------------------------------------- */ - -/* CPACR CPn: Access privileges values */ -#define SCB_CPACR_NONE 0 /* Access denied */ -#define SCB_CPACR_PRIV 1 /* Privileged access only */ -#define SCB_CPACR_FULL 3 /* Full access */ - -/* CPACR [20:21]: Access privileges for coprocessor 10 */ -#define SCB_CPACR_CP10 (1 << 20) -/* CPACR [22:23]: Access privileges for coprocessor 11 */ -#define SCB_CPACR_CP11 (1 << 22) -#endif - -/* --- SCB functions ------------------------------------------------------- */ - -BEGIN_DECLS - -struct scb_exception_stack_frame { - uint32_t r0; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r12; - uint32_t lr; - uint32_t pc; - uint32_t xpsr; -} __attribute__((packed)); - -#define SCB_GET_EXCEPTION_STACK_FRAME(f) \ - do { \ - asm volatile ("mov %[frameptr], sp" \ - : [frameptr]"=r" (f)); \ - } while (0) - -void scb_reset_system(void) __attribute__((noreturn)); - -/* Those defined only on ARMv7 and above */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -void scb_reset_core(void) __attribute__((noreturn)); -void scb_set_priority_grouping(uint32_t prigroup); -#endif - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/scs.h b/libopencm3/include/libopencm3/cm3/scs.h deleted file mode 100644 index 0af4424..0000000 --- a/libopencm3/include/libopencm3/cm3/scs.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_SCS_H -#define LIBOPENCM3_CM3_SCS_H - -/** - * @defgroup cm_scs Cortex-M System Control Space - * @ingroup CM3_defines - * The System Control Space (SCS) is a memory-mapped 4KB address space that - * provides 32-bit registers for configuration, status reporting and control. - * The SCS registers divide into the following groups: - * - system control and identification - * - the CPUID processor identification space - * - system configuration and status - * - fault reporting - * - a system timer, SysTick - * - a Nested Vectored Interrupt Controller (NVIC) - * - a Protected Memory System Architecture (PMSA) - * - system debug. - * - * Most portions of the SCS are covered by their own header files, eg - * systick.h, dwt.h, scb.h, itm.h, fpb.h - * @{ - */ - -/** @defgroup cm_scs_registers SCS Registers - * @ingroup cm_scs - * @{ - */ - -/** - * Debug Halting Control and Status Register (DHCSR). - * - * Purpose Controls halting debug. - * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when - * the system is running with halting debug enabled is UNPREDICTABLE. - * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running - * when S_HALT is set to 0. - * - When C_DEBUGEN is set to 0, the processor ignores the values of all other - * bits in this register. - * - For more information about the use of DHCSR see Debug stepping on page - * C1-824. - * Configurations Always implemented. - */ -#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) -/** - * Debug Core Register Selector Register (DCRSR). - * - * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core - * registers, special-purpose registers, and Floating-point extension - * registers. A write to DCRSR specifies the register to transfer, whether the - * transfer is a read or a write, and starts the transfer. - * Usage constraints: Only accessible in Debug state. - * Configurations Always implemented. - * - */ -#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) -/** - * Debug Core Register Data Register (DCRDR) - * - * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR - * provides debug access to the ARM core registers, special-purpose registers, - * and Floating-point extension registers. The DCRDR is the data register for - * these accesses. - * - Used on its own, the DCRDR provides a message passing resource between an - * external debugger and a debug agent running on the processor. - * Note: - * The architecture does not define any handshaking mechanism for this use of - * DCRDR. - * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to - * particular transfers using the DCRSR and DCRDR. - * Configurations Always implemented. - * - */ -#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) -/** - * Debug Exception and Monitor Control Register (DEMCR). - * - * Purpose Manages vector catch behavior and DebugMonitor handling when - * debugging. - * Usage constraints: - * - Bits [23:16] provide DebugMonitor exception control. - * - Bits [15:0] provide Debug state, halting debug, control. - * Configurations Always implemented. - * - */ -#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) - -/**@}*/ - -/* Debug Halting Control and Status Register (DHCSR) */ -#define SCS_DHCSR_DBGKEY 0xA05F0000 -#define SCS_DHCSR_C_DEBUGEN 0x00000001 -#define SCS_DHCSR_C_HALT 0x00000002 -#define SCS_DHCSR_C_STEP 0x00000004 -#define SCS_DHCSR_C_MASKINTS 0x00000008 -#define SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define SCS_DHCSR_S_REGRDY 0x00010000 -#define SCS_DHCSR_S_HALT 0x00020000 -#define SCS_DHCSR_S_SLEEP 0x00040000 -#define SCS_DHCSR_S_LOCKUP 0x00080000 -#define SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define SCS_DHCSR_S_RESET_ST 0x02000000 - -/* Debug Core Register Selector Register (DCRSR) */ -#define SCS_DCRSR_REGSEL_MASK 0x0000001F -#define SCS_DCRSR_REGSEL_XPSR 0x00000010 -#define SCS_DCRSR_REGSEL_MSP 0x00000011 -#define SCS_DCRSR_REGSEL_PSP 0x00000012 - -/* Debug Exception and Monitor Control Register (DEMCR) */ -/* Bits 31:25 - Reserved */ -#define SCS_DEMCR_TRCENA (1 << 24) -/* Bits 23:20 - Reserved */ -#define SCS_DEMCR_MON_REQ (1 << 19) -#define SCS_DEMCR_MON_STEP (1 << 18) -#define SCS_DEMCR_VC_MON_PEND (1 << 17) -#define SCS_DEMCR_VC_MON_EN (1 << 16) -/* Bits 15:11 - Reserved */ -#define SCS_DEMCR_VC_HARDERR (1 << 10) -#define SCS_DEMCR_VC_INTERR (1 << 9) -#define SCS_DEMCR_VC_BUSERR (1 << 8) -#define SCS_DEMCR_VC_STATERR (1 << 7) -#define SCS_DEMCR_VC_CHKERR (1 << 6) -#define SCS_DEMCR_VC_NOCPERR (1 << 5) -#define SCS_DEMCR_VC_MMERR (1 << 4) -/* Bits 3:1 - Reserved */ -#define SCS_DEMCR_VC_CORERESET (1 << 0) - -/* CoreSight Lock Status Register for this peripheral */ -#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4) -/* CoreSight Lock Access Register for this peripheral */ -#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0) - - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/cm3/sync.h b/libopencm3/include/libopencm3/cm3/sync.h deleted file mode 100644 index 6937ac6..0000000 --- a/libopencm3/include/libopencm3/cm3/sync.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_SYNC_H -#define LIBOPENCM3_CM3_SYNC_H - -#include "common.h" - -BEGIN_DECLS - -void __dmb(void); - -/* Implements synchronisation primitives as discussed in the ARM document - * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M - * Architecture Reference Manual. -*/ - -/* --- Exclusive load and store instructions ------------------------------- */ - -/* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - -uint32_t __ldrex(volatile uint32_t *addr); -uint32_t __strex(uint32_t val, volatile uint32_t *addr); - -/* --- Convenience functions ----------------------------------------------- */ - -/* Here we implement some simple synchronisation primitives. */ - -typedef uint32_t mutex_t; - -#define MUTEX_UNLOCKED 0 -#define MUTEX_LOCKED 1 - -void mutex_lock(mutex_t *m); -uint32_t mutex_trylock(mutex_t *m); -void mutex_unlock(mutex_t *m); - -#endif - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/cm3/systick.h b/libopencm3/include/libopencm3/cm3/systick.h deleted file mode 100644 index 1563946..0000000 --- a/libopencm3/include/libopencm3/cm3/systick.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/** @defgroup CM3_systick_defines Cortex-M SysTick Defines - * - * @brief libopencm3 Defined Constants and Types for the Cortex SysTick - * - * @ingroup CM3_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2010 Thomas Otto - * - * @date 19 August 2012 - * - * System Control Space (SCS) => System timer register support in the SCS. - * To configure SysTick, load the interval required between SysTick events to - * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in - * the SysTick Control and Status register, is activated on the transition from - * 1 to 0, therefore it activates every n+1 clock ticks. If you require a - * period of 100, write 99 to the SysTick Reload Value register. The SysTick - * Reload Value register supports values between 0x1 and 0x00FFFFFF. - * - * If you want to use SysTick to generate an event at a timed interval, for - * example 1ms, you can use the SysTick Calibration Value Register to scale - * your value for the Reload register. The SysTick Calibration Value Register - * is a read-only register that contains the number of pulses for a period of - * 10ms, in the TENMS field, bits[23:0]. - * - * This register also has a SKEW bit. Bit[30] == 1 indicates that the - * calibration for 10ms in the TENMS section is not exactly 10ms due to clock - * frequency. Bit[31] == 1 indicates that the reference clock is not provided. - * - * LGPL License Terms @ref lgpl_license - */ - -/**@{*/ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/** SysTick Control and Status Register (CSR). - * Controls the system timer and provides status data. - * Usage constraints: There are no usage constraints. - * Configurations Always implemented. - */ -#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00) - -/** SysTick Reload Value Register (RVR). - * Reads or clears the value that will be loaded to the counter. - * Usage constraints: - * - Any write to the register clears the register to zero. - * - The counter does not provide read-modify-write protection. - * - Unsupported bits are read as zero - * Configurations Always implemented. - */ -#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04) - -/** SysTick Current Value Register (CVR). - * Holds the current value of the counter. - * Usage constraints: There are no usage constraints. - * Configurations Always implemented. - */ -#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08) - -/** SysTick Calibration Value Register(Read Only) (CALIB) - * Reads the calibration value and parameters for SysTick. - * Usage constraints: There are no usage constraints. - * Configurations Always implemented. - */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/** @defgroup STK_CSR_VALUES STK_CSR Values - * @{ - */ -/** COUNTFLAG - * Indicates whether the counter has counted to 0 since the last read of this - * register: - * 0 = Timer has not counted to 0 - * 1 = Timer has counted to 0. - */ -#define STK_CSR_COUNTFLAG (1 << 16) - -#define STK_CSR_CLKSOURCE_LSB 2 -/** CLKSOURCE: Clock source selection - * for 0, SysTick uses the IMPLEMENTATION DEFINED external reference clock. - * for 1, SysTick uses the processor clock. - * If no external clock is provided, this bit reads as 1 and ignores writes. - */ -#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB) - -/** @defgroup systick_clksource Clock source selection -@ingroup CM3_systick_defines - -@{*/ -#if defined(__ARM_ARCH_6M__) -#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB) -#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) -#else -#define STK_CSR_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB) -#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) -#endif -/**@}*/ - -/** TICKINT: SysTick exception request enable */ -#define STK_CSR_TICKINT (1 << 1) -/** ENABLE: Counter enable */ -#define STK_CSR_ENABLE (1 << 0) -/**@}*/ - -/** @defgroup STK_RVR_VALUES STK_RVR Values - * @{ - */ -/** RELOAD[23:0]: RELOAD value */ -#define STK_RVR_RELOAD 0x00FFFFFF - -/**@}*/ - - -/** @defgroup STK_RVR_VALUES STK_RVR Values - * @{ - */ -/** CURRENT[23:0]: Current counter value */ -#define STK_CVR_CURRENT 0x00FFFFFF -/**@}*/ - - -/** @defgroup STK_CALIB_VALUES STK_CALIB Values - * @{ - */ -/** NOREF: NOREF flag - * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock - * is implemented: - * 0 = The reference clock is implemented. - * 1 = The reference clock is not implemented. - * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to - * 1 and cannot be cleared to 0. - */ -#define STK_CALIB_NOREF (1 << 31) - -/** SKEW: SKEW flag - * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: - * 0 = 10ms calibration value is exact. - * 1 = 10ms calibration value is inexact, because of the clock frequency - */ -#define STK_CALIB_SKEW (1 << 30) - -/* Bits [29:24] Reserved, must be kept cleared. */ -/** TENMS Calibration value for 10ms. - * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms - * (100Hz) timing, subject to system clock skew errors. If this field is zero, - * the calibration value is not known. - */ -#define STK_CALIB_TENMS 0x00FFFFFF -/**@}*/ - -/* --- Function Prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void systick_set_reload(uint32_t value); -bool systick_set_frequency(uint32_t freq, uint32_t ahb); -uint32_t systick_get_reload(void); -uint32_t systick_get_value(void); -void systick_set_clocksource(uint8_t clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -uint8_t systick_get_countflag(void); -void systick_clear(void); - -uint32_t systick_get_calib(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/cm3/tpiu.h b/libopencm3/include/libopencm3/cm3/tpiu.h deleted file mode 100644 index 7b77af1..0000000 --- a/libopencm3/include/libopencm3/cm3/tpiu.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CM3_TPIU_H -#define LIBOPENCM3_CM3_TPIU_H - -/** - * @defgroup cm_tpiu Cortex-M Trace Port Interface Unit (TPIU) - * @ingroup CM3_defines - * @{ - */ - -/* Those defined only on ARMv7 and above */ -#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) -#error "Trace Port Interface Unit not available in CM0" -#endif - -/* --- TPIU registers ------------------------------------------------------ */ - -/* Supported Synchronous Port Size (TPIU_SSPSR) */ -#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000) - -/* Current Synchronous Port Size (TPIU_CSPSR) */ -#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004) - -/* Asynchronous Clock Prescaler (TPIU_ACPR) */ -#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010) - -/* Selected Pin Protocol (TPIU_SPPR) */ -#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0) - -/* Formatter and Flush Status Register (TPIU_FFSR) */ -#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300) - -/* Formatter and Flush Control Register (TPIU_FFCR) */ -#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304) - -/* (TPIU_DEVID) */ -#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8) - -/* CoreSight Lock Status Register for this peripheral */ -#define TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET) -/* CoreSight Lock Access Register for this peripheral */ -#define TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET) - -/* TODO: PID, CID */ - -/* --- TPIU_ACPR values ---------------------------------------------------- */ - -/* Bits 31:16 - Reserved */ -/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */ - -/* --- TPIU_SPPR values ---------------------------------------------------- */ - -/* Bits 31:2 - Reserved */ -#define TPIU_SPPR_SYNC (0x0) -#define TPIU_SPPR_ASYNC_MANCHESTER (0x1) -#define TPIU_SPPR_ASYNC_NRZ (0x2) - -/* --- TPIU_FFSR values ---------------------------------------------------- */ - -/* Bits 31:4 - Reserved */ -#define TPIU_FFSR_FTNONSTOP (1 << 3) -#define TPIU_FFSR_TCPRESENT (1 << 2) -#define TPIU_FFSR_FTSTOPPED (1 << 1) -#define TPIU_FFSR_FLINPROG (1 << 0) - -/* --- TPIU_FFCR values ---------------------------------------------------- */ - -/* Bits 31:9 - Reserved */ -#define TPIU_FFCR_TRIGIN (1 << 8) -/* Bits 7:2 - Reserved */ -#define TPIU_FFCR_ENFCONT (1 << 1) -/* Bit 0 - Reserved */ - -/* --- TPIU_DEVID values ---------------------------------------------------- */ -/* Bits 31:16 - Reserved */ -/* Bits 15:12 - Implementation defined */ -#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11) -#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10) -/* Bit 9 - RAZ, indicated that trace data and clock are supported */ -#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6) -/* Bits 5:0 - Implementation defined */ - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/cm3/vector.h b/libopencm3/include/libopencm3/cm3/vector.h deleted file mode 100644 index 2afaab4..0000000 --- a/libopencm3/include/libopencm3/cm3/vector.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions for handling vector tables. - * - * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 - * (from the EFM32 documentation at - * http://www.energymicro.com/downloads/datasheets), and was seen analogously - * in other ARM implementations' libopencm3 files. - * - * The structure of the vector table is implemented independently of the system - * vector table starting at memory position 0x0, as it can be relocated to - * other memory locations too. - * - * The exact size of a vector interrupt table depends on the number of - * interrupts IRQ_COUNT, which is defined per family. - */ - -#ifndef LIBOPENCM3_VECTOR_H -#define LIBOPENCM3_VECTOR_H - -#include -#include - -/** Type of an interrupt function. Only used to avoid hard-to-read function - * pointers in the efm32_vector_table_t struct. */ -typedef void (*vector_table_entry_t)(void); - -typedef struct { - unsigned int *initial_sp_value; /**< Initial stack pointer value. */ - vector_table_entry_t reset; - vector_table_entry_t nmi; - vector_table_entry_t hard_fault; - vector_table_entry_t memory_manage_fault; /* not in CM0 */ - vector_table_entry_t bus_fault; /* not in CM0 */ - vector_table_entry_t usage_fault; /* not in CM0 */ - vector_table_entry_t reserved_x001c[4]; - vector_table_entry_t sv_call; - vector_table_entry_t debug_monitor; /* not in CM0 */ - vector_table_entry_t reserved_x0034; - vector_table_entry_t pend_sv; - vector_table_entry_t systick; - vector_table_entry_t irq[NVIC_IRQ_COUNT]; -} vector_table_t; - -/* Common symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; -extern vector_table_t vector_table; - -#endif diff --git a/libopencm3/include/libopencm3/dispatch/nvic.h b/libopencm3/include/libopencm3/dispatch/nvic.h deleted file mode 100644 index b4589dd..0000000 --- a/libopencm3/include/libopencm3/dispatch/nvic.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef LIBOPENCM3_NVIC_H -#error You should not be including this file directly, but -#endif - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32G4) -# include -#elif defined(STM32H7) -# include - -#elif defined(GD32F1X0) -# include - -#elif defined(EFM32TG) -# include -#elif defined(EFM32G) -# include -#elif defined(EFM32LG) -# include -#elif defined(EFM32GG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include - -#elif defined(LPC13XX) -# include -#elif defined(LPC17XX) -# include -#elif defined(LPC43XX_M4) -# include -#elif defined(LPC43XX_M0) -# include - -#elif defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#elif defined(SAM4L) -# include -#elif defined(SAMD) -# include - -#elif defined(LM3S) || defined(LM4F) -/* Yes, we use the same interrupt table for both LM3S and LM4F */ -# include - -#elif defined(MSP432E4) -# include - -#elif defined(VF6XX) -# include - -#elif defined(SWM050) -# include - -#elif defined(PAC55XX) -# include - -#else -# warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0" - -#define NVIC_IRQ_COUNT 0 - -#endif diff --git a/libopencm3/include/libopencm3/docmain.dox b/libopencm3/include/libopencm3/docmain.dox deleted file mode 100644 index 799ebbb..0000000 --- a/libopencm3/include/libopencm3/docmain.dox +++ /dev/null @@ -1,21 +0,0 @@ -/** @mainpage libopencm3 Developer Documentation - -@version 1.0.0 - -@date 7 September 2012 - - * The libopencm3 project (previously known as libopenstm32) aims to create - * a free/libre/open-source (LGPL v3, or later) firmware library for various - * ARM Cortex-M microcontrollers, including ST STM32, Atmel SAM, NXP LPC, - * TI Stellaris/Tiva/MSP432, Silabs (Energy Micro) and others. - * - * @par "" - * - * See the libopencm3 wiki for - * more information. - -LGPL License Terms @ref lgpl_license -*/ - - - diff --git a/libopencm3/include/libopencm3/efm32/acmp.h b/libopencm3/include/libopencm3/efm32/acmp.h deleted file mode 100644 index 471ce29..0000000 --- a/libopencm3/include/libopencm3/efm32/acmp.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/adc.h b/libopencm3/include/libopencm3/efm32/adc.h deleted file mode 100644 index afa5abe..0000000 --- a/libopencm3/include/libopencm3/efm32/adc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/burtc.h b/libopencm3/include/libopencm3/efm32/burtc.h deleted file mode 100644 index 2a2f371..0000000 --- a/libopencm3/include/libopencm3/efm32/burtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/cmu.h b/libopencm3/include/libopencm3/efm32/cmu.h deleted file mode 100644 index d9f51c2..0000000 --- a/libopencm3/include/libopencm3/efm32/cmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/common/acmp_common.h b/libopencm3/include/libopencm3/efm32/common/acmp_common.h deleted file mode 100644 index e47a1ad..0000000 --- a/libopencm3/include/libopencm3/efm32/common/acmp_common.h +++ /dev/null @@ -1,187 +0,0 @@ -/** @addtogroup acmp_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -/**@{*/ - -#include -#include - -#define ACMP_CTRL(base) ((base) + 0x000) -#define ACMP_INPUTSEL(base) ((base) + 0x004) -#define ACMP_STATUS(base) ((base) + 0x008) -#define ACMP_IEN(base) ((base) + 0x00C) -#define ACMP_IF(base) ((base) + 0x010) -#define ACMP_IFS(base) ((base) + 0x014) -#define ACMP_IFC(base) ((base) + 0x018) -#define ACMP_ROUTE(base) ((base) + 0x01C) - -/* ACMP_CTRL */ -#define ACMP_CTRL_FULLBIAS (1 << 31) -#define ACMP_CTRL_HALFBIAS (1 << 30) - -#define ACMP_CTRL_BIASPROG_SHIFT (24) -#define ACMP_CTRL_BIASPROG_MASK (0xF << ACMP_CTRL_BIASPROG_SHIFT) -#define ACMP_CTRL_BIASPROG(v) \ - (((v) << ACMP_CTRL_BIASPROG_SHIFT) & ACMP_CTRL_BIASPROG_MASK) - -#define ACMP_CTRL_IFALL (1 << 17) -#define ACMP_CTRL_IRISE (1 << 16) - -#define ACMP_CTRL_WARMTIME_SHIFT (8) -#define ACMP_CTRL_WARMTIME_MASK (0x7 << ACMP_CTRL_WARMTIME_SHIFT) -#define ACMP_CTRL_WARMTIME(v) \ - (((v) << ACMP_CTRL_WARMTIME_SHIFT) & ACMP_CTRL_WARMTIME_MASK) -#define ACMP_CTRL_WARMTIME_4CYCLES 0 -#define ACMP_CTRL_WARMTIME_8CYCLES 1 -#define ACMP_CTRL_WARMTIME_16CYCLES 2 -#define ACMP_CTRL_WARMTIME_32CYCLES 3 -#define ACMP_CTRL_WARMTIME_64CYCLES 4 -#define ACMP_CTRL_WARMTIME_128CYCLES 5 -#define ACMP_CTRL_WARMTIME_256CYCLES 6 -#define ACMP_CTRL_WARMTIME_512CYCLES 7 - -#define ACMP_CTRL_HYSTSEL_SHIFT (8) -#define ACMP_CTRL_HYSTSEL_MASK (0x7 << ACMP_CTRL_HYSTSEL_SHIFT) -#define ACMP_CTRL_HYSTSEL(v) \ - (((v) << ACMP_CTRL_HYSTSEL_SHIFT) & ACMP_CTRL_HYSTSEL_MASK) -#define ACMP_CTRL_HYSTSEL_HYSTx(x) ACMP_CTRL_HYSTSEL(x) -#define ACMP_CTRL_HYSTSEL_HYST0 0 -#define ACMP_CTRL_HYSTSEL_HYST1 1 -#define ACMP_CTRL_HYSTSEL_HYST2 2 -#define ACMP_CTRL_HYSTSEL_HYST3 3 -#define ACMP_CTRL_HYSTSEL_HYST4 4 -#define ACMP_CTRL_HYSTSEL_HYST5 5 -#define ACMP_CTRL_HYSTSEL_HYST6 6 -#define ACMP_CTRL_HYSTSEL_HYST7 7 - -#define ACMP_CTRL_GPIOINV (1 << 3) -#define ACMP_CTRL_INACTVAL (1 << 2) -#define ACMP_CTRL_MUXEN (1 << 1) -#define ACMP_CTRL_EN (1 << 0) - -/* ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_CSRESSEL_SHIFT (28) -#define ACMP_INPUTSEL_CSRESSEL_MASK (0x3 << ACMP_INPUTSEL_CSRESSEL_SHIFT) -#define ACMP_INPUTSEL_CSRESSEL(v) \ - (((v) << ACMP_INPUTSEL_CSRESSEL_SHIFT) & ACMP_INPUTSEL_CSRESSEL_MASK) -#define ACMP_INPUTSEL_CSRESSEL_RESx(x) ACMP_INPUTSEL_CSRESSEL_RES(x) -#define ACMP_INPUTSEL_CSRESSEL_RES0 ACMP_INPUTSEL_CSRESSEL_RESx(0) -#define ACMP_INPUTSEL_CSRESSEL_RES1 ACMP_INPUTSEL_CSRESSEL_RESx(1) -#define ACMP_INPUTSEL_CSRESSEL_RES2 ACMP_INPUTSEL_CSRESSEL_RESx(2) -#define ACMP_INPUTSEL_CSRESSEL_RES3 ACMP_INPUTSEL_CSRESSEL_RESx(3) - -#define ACMP_INPUTSEL_CSRESEN (1 << 24) -#define ACMP_INPUTSEL_LPREF (1 << 16) - -#define ACMP_INPUTSEL_VDDLEVEL_SHIFT (8) -#define ACMP_INPUTSEL_VDDLEVEL_MASK (0x3F << ACMP_INPUTSEL_VDDLEVEL_SHIFT) -#define ACMP_INPUTSEL_VDDLEVEL(v) \ - (((v) << ACMP_INPUTSEL_VDDLEVEL_SHIFT) & ACMP_INPUTSEL_VDDLEVEL_MASK) - -#define ACMP_INPUTSEL_NEGSEL_SHIFT (8) -#define ACMP_INPUTSEL_NEGSEL_MASK (0x3F << ACMP_INPUTSEL_NEGSEL_SHIFT) -#define ACMP_INPUTSEL_NEGSEL(v) \ - (((v) << ACMP_INPUTSEL_NEGSEL_SHIFT) & ACMP_INPUTSEL_NEGSEL_MASK) -#define ACMP_INPUTSEL_NEGSEL_CHx(x) ACMP_INPUTSEL_NEGSEL(x) -#define ACMP_INPUTSEL_NEGSEL_CH0 0 -#define ACMP_INPUTSEL_NEGSEL_CH1 1 -#define ACMP_INPUTSEL_NEGSEL_CH2 2 -#define ACMP_INPUTSEL_NEGSEL_CH3 3 -#define ACMP_INPUTSEL_NEGSEL_CH4 4 -#define ACMP_INPUTSEL_NEGSEL_CH5 5 -#define ACMP_INPUTSEL_NEGSEL_CH6 6 -#define ACMP_INPUTSEL_NEGSEL_CH7 7 -#define ACMP_INPUTSEL_NEGSEL_1V25 8 -#define ACMP_INPUTSEL_NEGSEL_2V5 9 -#define ACMP_INPUTSEL_NEGSEL_VDD 10 -#define ACMP_INPUTSEL_NEGSEL_CAPSENSE 11 -#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 12 -#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 13 - -#define ACMP_INPUTSEL_POSSEL_SHIFT (0) -#define ACMP_INPUTSEL_POSSEL_MASK (0x7 << ACMP_INPUTSEL_POSSEL_SHIFT) -#define ACMP_INPUTSEL_POSSEL(v) \ - (((v) << ACMP_INPUTSEL_LPOSSELL_SHIFT) & ACMP_INPUTSEL_LPOSSELL_MASK) -#define ACMP_INPUTSEL_POSSEL_CHx(x) ACMP_INPUTSEL_POSSEL(x) -#define ACMP_INPUTSEL_POSSEL_CH0 0 -#define ACMP_INPUTSEL_POSSEL_CH1 1 -#define ACMP_INPUTSEL_POSSEL_CH2 2 -#define ACMP_INPUTSEL_POSSEL_CH3 3 -#define ACMP_INPUTSEL_POSSEL_CH4 4 -#define ACMP_INPUTSEL_POSSEL_CH5 5 -#define ACMP_INPUTSEL_POSSEL_CH6 6 -#define ACMP_INPUTSEL_POSSEL_CH7 7 - -/* ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT (1 << 1) -#define ACMP_STATUS_ACMPACT (1 << 0) - -/* ACMP_IEN */ -#define ACMP_IEN_WARMUP (1 << 1) -#define ACMP_IEN_EDGE (1 << 0) - -/* ACMP_IF */ -#define ACMP_IF_WARMUP (1 << 1) -#define ACMP_IF_EDGE (1 << 0) - -/* ACMP_IFS */ -#define ACMP_IFS_WARMUP (1 << 1) -#define ACMP_IFS_EDGE (1 << 0) - -/* ACMP_IFC */ -#define ACMP_IFC_WARMUP (1 << 1) -#define ACMP_IFC_EDGE (1 << 0) - -/* ACMP_ROUTE */ -#define ACMP_ROUTE_LOCATION_SHIFT (8) -#define ACMP_ROUTE_LOCATION_MASK (0x7 << ACMP_ROUTE_LOCATION_SHIFT) -#define ACMP_ROUTE_LOCATION(v) \ - (((v) << ACMP_ROUTE_LOCATION_SHIFT) & ACMP_ROUTE_LOCATION_MASK) -#define ACMP_ROUTE_LOCATION_LOCx(x) ACMP_ROUTE_LOCATION(x) -#define ACMP_ROUTE_LOCATION_LOC0 ACMP_ROUTE_LOCATIONx(0) -#define ACMP_ROUTE_LOCATION_LOC1 ACMP_ROUTE_LOCATIONx(1) -#define ACMP_ROUTE_LOCATION_LOC2 ACMP_ROUTE_LOCATIONx(2) - -#define ACMP_ROUTE_ACMPPEN (1 << 0) - -#define ACMP0 ACMP0_BASE -#define ACMP0_CTRL ACMP_CTRL(ACMP0) -#define ACMP0_INPUTSEL ACMP_INPUTSEL(ACMP0) -#define ACMP0_STATUS ACMP_STATUS(ACMP0) -#define ACMP0_IEN ACMP_IEN(ACMP0) -#define ACMP0_IF ACMP_IF(ACMP0) -#define ACMP0_IFS ACMP_IFS(ACMP0) -#define ACMP0_IFC ACMP_IFC(ACMP0) -#define ACMP0_ROUTE ACMP_ROUTE(ACMP0) - -#define ACMP1 ACMP1_BASE -#define ACMP1_CTRL ACMP_CTRL(ACMP1) -#define ACMP1_INPUTSEL ACMP_INPUTSEL(ACMP1) -#define ACMP1_STATUS ACMP_STATUS(ACMP1) -#define ACMP1_IEN ACMP_IEN(ACMP1) -#define ACMP1_IF ACMP_IF(ACMP1) -#define ACMP1_IFS ACMP_IFS(ACMP1) -#define ACMP1_IFC ACMP_IFC(ACMP1) -#define ACMP1_ROUTE ACMP_ROUTE(ACMP1) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/adc_common.h b/libopencm3/include/libopencm3/efm32/common/adc_common.h deleted file mode 100644 index 0ce80a4..0000000 --- a/libopencm3/include/libopencm3/efm32/common/adc_common.h +++ /dev/null @@ -1,457 +0,0 @@ -/** @addtogroup adc_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#pragma once - -#include -#include - -#define ADC_CTRL(base) MMIO32((base) + 0x000) -#define ADC_CMD(base) MMIO32((base) + 0x004) -#define ADC_STATUS(base) MMIO32((base) + 0x008) -#define ADC_SINGLECTRL(base) MMIO32((base) + 0x00C) -#define ADC_SCANCTRL(base) MMIO32((base) + 0x010) -#define ADC_IEN(base) MMIO32((base) + 0x014) -#define ADC_IF(base) MMIO32((base) + 0x018) -#define ADC_IFS(base) MMIO32((base) + 0x01C) -#define ADC_IFC(base) MMIO32((base) + 0x020) -#define ADC_SINGLEDATA(base) MMIO32((base) + 0x024) -#define ADC_SCANDATA(base) MMIO32((base) + 0x028) -#define ADC_SINGLEDATAP(base) MMIO32((base) + 0x02C) -#define ADC_SCANDATAP(base) MMIO32((base) + 0x030) -#define ADC_CAL(base) MMIO32((base) + 0x034) -#define ADC_BIASPROG(base) MMIO32((base) + 0x03C) - -/* ADC_CTRL */ -#define ADC_CTRL_OVERSEL_SHIFT (24) -#define ADC_CTRL_OVERSEL_MASK (0xF << ADC_CTRL_OVERSEL_SHIFT) -#define ADC_CTRL_OVERSEL(v) \ - (((v) << ADC_CTRL_OVERSEL_SHIFT) & ADC_CTRL_OVERSEL_MASK) -#define ADC_CTRL_OVERSEL_X2 0 -#define ADC_CTRL_OVERSEL_X4 1 -#define ADC_CTRL_OVERSEL_X8 2 -#define ADC_CTRL_OVERSEL_X16 3 -#define ADC_CTRL_OVERSEL_X32 4 -#define ADC_CTRL_OVERSEL_X64 5 -#define ADC_CTRL_OVERSEL_X128 6 -#define ADC_CTRL_OVERSEL_X256 7 -#define ADC_CTRL_OVERSEL_X512 8 -#define ADC_CTRL_OVERSEL_X1024 9 -#define ADC_CTRL_OVERSEL_X2048 10 -#define ADC_CTRL_OVERSEL_X4096 11 - -#define ADC_CTRL_TIMEBASE_SHIFT (16) -#define ADC_CTRL_TIMEBASE_MASK (0x3F << ADC_CTRL_TIMEBASE_SHIFT) -#define ADC_CTRL_TIMEBASE(v) \ - (((v) << ADC_CTRL_TIMEBASE_SHIFT) & ADC_CTRL_TIMEBASE_MASK) - -#define ADC_CTRL_PRESC_SHIFT (8) -#define ADC_CTRL_PRESC_MASK (0x3F << ADC_CTRL_PRESC_SHIFT) -#define ADC_CTRL_PRESC(v) \ - (((v) << ADC_CTRL_PRESC_SHIFT) & ADC_CTRL_PRESC_MASK) - -#define ADC_CTRL_LPFMODE_SHIFT (4) -#define ADC_CTRL_LPFMODE_MASK (0x3 << ADC_CTRL_LPFMODE_SHIFT) -#define ADC_CTRL_LPFMODE(v) \ - (((v) << ADC_CTRL_LPFMODE_SHIFT) & ADC_CTRL_LPFMODE_MASK) -#define ADC_CTRL_LPFMODE_BYPASS 0 -#define ADC_CTRL_LPFMODE_DECAP 1 -#define ADC_CTRL_LPFMODE_RCFILT 2 - -#define ADC_CTRL_TAILGATE (1 << 3) - -#define ADC_CTRL_WARMUPMODE_SHIFT (0) -#define ADC_CTRL_WARMUPMODE_MASK (0x3 << ADC_CTRL_WARMUPMODE_SHIFT) -#define ADC_CTRL_WARMUPMODE(v) \ - (((v) << ADC_CTRL_WARMUPMODE_SHIFT) & ADC_CTRL_WARMUPMODE_MASK) -#define ADC_CTRL_WARMUPMODE_NORMAL 0 -#define ADC_CTRL_WARMUPMODE_FASTBG 1 -#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 2 -#define ADC_CTRL_WARMUPMODE_KEEPADCWARM 3 - -/* ADC_CMD */ -#define ADC_CMD_SCANSTOP (1 << 3) -#define ADC_CMD_SCANSTART (1 << 2) -#define ADC_CMD_SINGLESTOP (1 << 1) -#define ADC_CMD_SINGLESTART (1 << 0) - -/* ADC_STATUS */ -#define ADC_STATUS_SCANDATASRC_SHIFT (0) -#define ADC_STATUS_SCANDATASRC_MASK (0x7 << ADC_STATUS_SCANDATASRC_SHIFT) -#define ADC_STATUS_SCANDATASRC(v) \ - (((v) << ADC_STATUS_SCANDATASRC_SHIFT) & ADC_STATUS_SCANDATASRC_MASK) - -#define ADC_STATUS_SCANDV (1 << 17) -#define ADC_STATUS_SINGLEDV (1 << 16) -#define ADC_STATUS_WARM (1 << 12) -#define ADC_STATUS_SCANREFWARM (1 << 9) -#define ADC_STATUS_SINGLEREFWARM (1 << 8) -#define ADC_STATUS_SCANACT (1 << 1) -#define ADC_STATUS_SINGLEACT (1 << 0) - -/* ADC_SINGLECTRL */ -#define ADC_SINGLECTRL_PRSSEL_SHIFT (28) -#define ADC_SINGLECTRL_PRSSEL_MASK (0xF << ADC_SINGLECTRL_PRSSEL_SHIFT) -#define ADC_SINGLECTRL_PRSSEL(v) \ - (((v) << ADC_SINGLECTRL_PRSSEL_SHIFT) & ADC_SINGLECTRL_PRSSEL_MASK) -#define ADC_SINGLECTRL_PRSSEL_PRSCHx(x) ADC_SINGLECTRL_PRSSEL(x) -#define ADC_SINGLECTRL_PRSSEL_PRSCH0 0 -#define ADC_SINGLECTRL_PRSSEL_PRSCH1 1 -#define ADC_SINGLECTRL_PRSSEL_PRSCH2 2 -#define ADC_SINGLECTRL_PRSSEL_PRSCH3 3 -#define ADC_SINGLECTRL_PRSSEL_PRSCH4 4 -#define ADC_SINGLECTRL_PRSSEL_PRSCH5 5 -#define ADC_SINGLECTRL_PRSSEL_PRSCH6 6 -#define ADC_SINGLECTRL_PRSSEL_PRSCH7 7 -#define ADC_SINGLECTRL_PRSSEL_PRSCH8 8 -#define ADC_SINGLECTRL_PRSSEL_PRSCH9 9 -#define ADC_SINGLECTRL_PRSSEL_PRSCH10 10 -#define ADC_SINGLECTRL_PRSSEL_PRSCH11 11 - -#define ADC_SINGLECTRL_PRSEN (1 << 24) - -#define ADC_SINGLECTRL_AT_SHIFT (20) -#define ADC_SINGLECTRL_AT_MASK (0xF << ADC_SINGLECTRL_AT_SHIFT) -#define ADC_SINGLECTRL_AT(v) \ - (((v) << ADC_SINGLECTRL_AT_SHIFT) & ADC_SINGLECTRL_AT_MASK) -#define ADC_SINGLECTRL_AT_1CYCLE 0x0 -#define ADC_SINGLECTRL_AT_2CYCLES 0x1 -#define ADC_SINGLECTRL_AT_4CYCLES 0x2 -#define ADC_SINGLECTRL_AT_8CYCLES 0x3 -#define ADC_SINGLECTRL_AT_16CYCLES 0x4 -#define ADC_SINGLECTRL_AT_32CYCLES 0x5 -#define ADC_SINGLECTRL_AT_64CYCLES 0x6 -#define ADC_SINGLECTRL_AT_128CYCLES 0x7 -#define ADC_SINGLECTRL_AT_256CYCLES 0x8 - -#define ADC_SINGLECTRL_REF_SHIFT (16) -#define ADC_SINGLECTRL_REF_MASK (0xF << ADC_SINGLECTRL_REF_SHIFT) -#define ADC_SINGLECTRL_REF(v) \ - (((v) << ADC_SINGLECTRL_REF_SHIFT) & ADC_SINGLECTRL_REF_MASK) -#define ADC_SINGLECTRL_REF_1V25 0 -#define ADC_SINGLECTRL_REF_2V5 1 -#define ADC_SINGLECTRL_REF_VDD 2 -#define ADC_SINGLECTRL_REF_5VDIFF 3 -#define ADC_SINGLECTRL_REF_EXTSINGLE 4 -#define ADC_SINGLECTRL_REF_2XEXTDIFF 5 -#define ADC_SINGLECTRL_REF_2XVDD 6 - -#define ADC_SINGLECTRL_INPUTSEL_SHIFT (8) -#define ADC_SINGLECTRL_INPUTSEL_MASK (0xF << ADC_SINGLECTRL_INPUTSEL_SHIFT) -#define ADC_SINGLECTRL_INPUTSEL(v) \ - (((v) << ADC_SINGLECTRL_INPUTSEL_SHIFT) & ADC_SINGLECTRL_INPUTSEL_MASK) -/* DIFF=0 */ -#define ADC_SINGLECTRL_INPUTSEL_CHx(x) ADC_SINGLECTRL_INPUTSEL(x) -#define ADC_SINGLECTRL_INPUTSEL_CH0 0 -#define ADC_SINGLECTRL_INPUTSEL_CH1 1 -#define ADC_SINGLECTRL_INPUTSEL_CH2 2 -#define ADC_SINGLECTRL_INPUTSEL_CH3 3 -#define ADC_SINGLECTRL_INPUTSEL_CH4 4 -#define ADC_SINGLECTRL_INPUTSEL_CH5 5 -#define ADC_SINGLECTRL_INPUTSEL_CH6 6 -#define ADC_SINGLECTRL_INPUTSEL_CH7 7 -#define ADC_SINGLECTRL_INPUTSEL_TEMP 8 -#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 9 -#define ADC_SINGLECTRL_INPUTSEL_VDD 10 -#define ADC_SINGLECTRL_INPUTSEL_VSS 11 -#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 12 -#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 13 -#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 14 -/* DIFF=1 */ -#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 0 -#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 1 -#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 2 -#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 3 -#define ADC_SINGLECTRL_INPUTSEL_DIFF0 4 - -#define ADC_SINGLECTRL_RES_SHIFT (4) -#define ADC_SINGLECTRL_RES_MASK (0x3 << ADC_SINGLECTRL_RES_SHIFT) -#define ADC_SINGLECTRL_RES(v) \ - (((v) << ADC_SINGLECTRL_RES_SHIFT) & ADC_SINGLECTRL_RES_MASK) -#define ADC_SINGLECTRL_RES_12BIT 0 -#define ADC_SINGLECTRL_RES_8BIT 1 -#define ADC_SINGLECTRL_RES_6BIT 2 -#define ADC_SINGLECTRL_RES_OVS 3 - -#define ADC_SINGLECTRL_ADJ (1 << 2) -#define ADC_SINGLECTRL_DIFF (1 << 1) -#define ADC_SINGLECTRL_REP (1 << 0) - -/* ADC_SCANCTRL */ -#define ADC_SCANCTRL_PRSSEL_SHIFT (28) -#define ADC_SCANCTRL_PRSSEL_MASK (0xF << ADC_SCANCTRL_PRSSEL_SHIFT) -#define ADC_SCANCTRL_PRSSEL(v) \ - (((v) << ADC_SCANCTRL_PRSSEL_SHIFT) & ADC_SCANCTRL_PRSSEL_MASK) -#define ADC_SCANCTRL_PRSSEL_PRSCHx(x) ADC_SCANCTRL_PRSSEL(x) -#define ADC_SCANCTRL_PRSSEL_PRSCH0 0 -#define ADC_SCANCTRL_PRSSEL_PRSCH1 1 -#define ADC_SCANCTRL_PRSSEL_PRSCH2 2 -#define ADC_SCANCTRL_PRSSEL_PRSCH3 3 -#define ADC_SCANCTRL_PRSSEL_PRSCH4 4 -#define ADC_SCANCTRL_PRSSEL_PRSCH5 5 -#define ADC_SCANCTRL_PRSSEL_PRSCH6 6 -#define ADC_SCANCTRL_PRSSEL_PRSCH7 7 -#define ADC_SCANCTRL_PRSSEL_PRSCH8 8 -#define ADC_SCANCTRL_PRSSEL_PRSCH9 9 -#define ADC_SCANCTRL_PRSSEL_PRSCH10 10 -#define ADC_SCANCTRL_PRSSEL_PRSCH11 11 - -#define ADC_SCANCTRL_PRSEN (1 << 24) - -#define ADC_SCANCTRL_AT_SHIFT (20) -#define ADC_SCANCTRL_AT_MASK (0xF << ADC_SCANCTRL_AT_SHIFT) -#define ADC_SCANCTRL_AT(v) \ - (((v) << ADC_SCANCTRL_AT_SHIFT) & ADC_SCANCTRL_AT_MASK) -#define ADC_SCANCTRL_AT_1CYCLE 0 -#define ADC_SCANCTRL_AT_2CYCLES 1 -#define ADC_SCANCTRL_AT_4CYCLES 2 -#define ADC_SCANCTRL_AT_8CYCLES 3 -#define ADC_SCANCTRL_AT_16CYCLES 4 -#define ADC_SCANCTRL_AT_32CYCLES 5 -#define ADC_SCANCTRL_AT_64CYCLES 6 -#define ADC_SCANCTRL_AT_128CYCLES 7 -#define ADC_SCANCTRL_AT_256CYCLES 8 - -#define ADC_SCANCTRL_REF_SHIFT (16) -#define ADC_SCANCTRL_REF_MASK (0xF << ADC_SCANCTRL_REF_SHIFT) -#define ADC_SCANCTRL_REF(v) \ - (((v) << ADC_SCANCTRL_REF_SHIFT) & ADC_SCANCTRL_REF_MASK) -#define ADC_SCANCTRL_REF_1V25 0 -#define ADC_SCANCTRL_REF_2V5 1 -#define ADC_SCANCTRL_REF_VDD 2 -#define ADC_SCANCTRL_REF_5VDIFF 3 -#define ADC_SCANCTRL_REF_EXTSCAN 4 -#define ADC_SCANCTRL_REF_2XEXTDIFF 5 -#define ADC_SCANCTRL_REF_2XVDD 6 - - -#define ADC_SCANCTRL_INPUTSEL_SHIFT (8) -#define ADC_SCANCTRL_INPUTSEL_MASK (0xFF << ADC_SCANCTRL_INPUTSEL_SHIFT) -#define ADC_SCANCTRL_INPUTSEL(v) \ - (((v) << ADC_SCANCTRL_INPUTSEL_SHIFT) & ADC_SCANCTRL_INPUTSEL_MASK) -/* DIFF=0 */ -#define ADC_SCANCTRL_INPUTSEL_CHx(x) ADC_SCANCTRL_INPUTSEL(1 << (x)) -#define ADC_SCANCTRL_INPUTSEL_CH0 ADC_SCANCTRL_INPUTSEL_CHx(0) -#define ADC_SCANCTRL_INPUTSEL_CH1 ADC_SCANCTRL_INPUTSEL_CHx(1) -#define ADC_SCANCTRL_INPUTSEL_CH2 ADC_SCANCTRL_INPUTSEL_CHx(2) -#define ADC_SCANCTRL_INPUTSEL_CH3 ADC_SCANCTRL_INPUTSEL_CHx(3) -#define ADC_SCANCTRL_INPUTSEL_CH4 ADC_SCANCTRL_INPUTSEL_CHx(4) -#define ADC_SCANCTRL_INPUTSEL_CH5 ADC_SCANCTRL_INPUTSEL_CHx(5) -#define ADC_SCANCTRL_INPUTSEL_CH6 ADC_SCANCTRL_INPUTSEL_CHx(6) -#define ADC_SCANCTRL_INPUTSEL_CH7 ADC_SCANCTRL_INPUTSEL_CHx(7) -/* DIFF=1 */ -#define ADC_SCANCTRL_INPUTSEL_CH0CH1 ADC_SCANCTRL_INPUTSEL(1 << 0) -#define ADC_SCANCTRL_INPUTSEL_CH2CH3 ADC_SCANCTRL_INPUTSEL(1 << 1) -#define ADC_SCANCTRL_INPUTSEL_CH4CH5 ADC_SCANCTRL_INPUTSEL(1 << 2) -#define ADC_SCANCTRL_INPUTSEL_CH6CH7 ADC_SCANCTRL_INPUTSEL(1 << 3) - -#define ADC_SCANCTRL_RES_SHIFT (4) -#define ADC_SCANCTRL_RES_MASK (0x3 << ADC_SCANCTRL_RES_SHIFT) -#define ADC_SCANCTRL_RES(v) \ - (((v) << ADC_SCANCTRL_RES_SHIFT) & ADC_SCANCTRL_RES_MASK) -#define ADC_SCANCTRL_RES_12BIT 0 -#define ADC_SCANCTRL_RES_8BIT 1 -#define ADC_SCANCTRL_RES_6BIT 2 -#define ADC_SCANCTRL_RES_OVS 3 - -#define ADC_SCANCTRL_ADJ (1 << 2) -#define ADC_SCANCTRL_DIFF (1 << 1) -#define ADC_SCANCTRL_REP (1 << 0) - -/* ADC_IEN */ -#define ADC_IEN_SCANOF (1 << 9) -#define ADC_IEN_SINGLEOF (1 << 8) -#define ADC_IEN_SCAN (1 << 1) -#define ADC_IEN_SINGLE (1 << 0) - -/* ADC_IF */ -#define ADC_IF_SCANOF (1 << 9) -#define ADC_IF_SINGLEOF (1 << 8) -#define ADC_IF_SCAN (1 << 1) -#define ADC_IF_SINGLE (1 << 0) - -/* ADC_IFS */ -#define ADC_IFS_SCANOF (1 << 9) -#define ADC_IFS_SINGLEOF (1 << 8) -#define ADC_IFS_SCAN (1 << 1) -#define ADC_IFS_SINGLE (1 << 0) - -/* ADC_IFC */ -#define ADC_IFC_SCANOF (1 << 9) -#define ADC_IFC_SINGLEOF (1 << 8) -#define ADC_IFC_SCAN (1 << 1) -#define ADC_IFC_SINGLE (1 << 0) - -/* ADC_CAL */ -#define ADC_CAL_SCANGAIN_SHIFT (24) -#define ADC_CAL_SCANGAIN_MASK (0x7F) - -#define ADC_CAL_SCANOFF_SHIFT (16) -#define ADC_CAL_SCANOFF_MASK (0x7F) - -#define ADC_CAL_SINGLEGAIN_SHIFT (8) -#define ADC_CAL_SINGLEGAIN_MASK (0x7F) - -#define ADC_CAL_SINGLEOFF_SHIFT (0) -#define ADC_CAL_SINGLEOFF_MASK (0x7F) - -/* ADC_BIASPROG */ -#define ADC_BIASPROG_COMPBIAS_SHIFT (8) -#define ADC_BIASPROG_COMPBIAS_MASK (0xF) - -#define ADC_BIASPROG_HALFBIAS (1 << 6) - -#define ADC_BIASPROG_BIASPROG_SHIFT (0) -#define ADC_BIASPROG_BIASPROG_MASK (0xF) - -/* ADC0 */ -#define ADC0 ADC0_BASE -#define ADC0_CTRL ADC_CTRL(ADC0) -#define ADC0_CMD ADC_CMD(ADC0) -#define ADC0_STATUS ADC_STATUS(ADC0) -#define ADC0_SINGLECTRL ADC_SINGLECTRL(ADC0) -#define ADC0_SCANCTRL ADC_SCANCTRL(ADC0) -#define ADC0_IEN ADC_IEN(ADC0) -#define ADC0_IF ADC_IF(ADC0) -#define ADC0_IFS ADC_IFS(ADC0) -#define ADC0_IFC ADC_IFC(ADC0) -#define ADC0_SINGLEDATA ADC_SINGLEDATA(ADC0) -#define ADC0_SCANDATA ADC_SCANDATA(ADC0) -#define ADC0_SINGLEDATAP ADC_SINGLEDATAP(ADC0) -#define ADC0_SCANDATAP ADC_SCANDATAP(ADC0) -#define ADC0_CAL ADC_CAL(ADC0) -#define ADC0_BIASPROG ADC_BIASPROG(ADC0) - -/** @defgroup adc_ch ADC Channel Number -@{*/ -#define ADC_CH0 0 -#define ADC_CH1 1 -#define ADC_CH2 2 -#define ADC_CH3 3 -#define ADC_CH4 4 -#define ADC_CH5 5 -#define ADC_CH6 6 -#define ADC_CH7 7 -#define ADC_CH_TEMP 8 -#define ADC_CH_VDDDIV3 9 -#define ADC_CH_VDD 10 -#define ADC_CH_VSS 11 -#define ADC_CH_VREFDIV2 12 -#define ADC_CH_DAC0OUT0 13 -#define ADC_CH_DAC0OUT1 14 - -#define ADC_CH_CH0CH1 0 -#define ADC_CH_CH2CH3 1 -#define ADC_CH_CH4CH5 2 -#define ADC_CH_CH6CH7 3 -#define ADC_CH_DIFF0 4 -/**@}*/ - -BEGIN_DECLS - -void adc_set_oversampling(uint32_t adc, uint32_t oversamp); -void adc_set_warm_up(uint32_t adc, uint8_t clocks); -void adc_set_clock_prescaler(uint32_t adc, uint8_t factor); -void adc_set_lowpass_filter(uint32_t adc, uint32_t lpfmode); - -void adc_enable_tailgating(uint32_t adc); -void adc_disable_tailgating(uint32_t adc); - -void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode); - -void adc_single_start(uint32_t adc); -void adc_single_stop(uint32_t adc); - -void adc_scan_start(uint32_t adc); -void adc_scan_stop(uint32_t adc); - -/* TODO: ADC_STATUS */ - -void adc_set_single_prs_trigger(uint32_t adc, uint8_t prssel); -void adc_enable_single_prs_trigger(uint32_t adc); -void adc_disable_single_prs_trigger(uint32_t adc); -void adc_set_single_acquisition_cycle(uint32_t adc, uint32_t at); -void adc_set_single_reference(uint32_t adc, uint32_t ref); -void adc_set_single_channel(uint32_t adc, uint8_t ch); -void adc_set_single_resolution(uint32_t adc, uint32_t res); -void adc_set_single_left_aligned(uint32_t adc); -void adc_set_single_right_aligned(uint32_t adc); -void adc_set_single_single_ended(uint32_t adc); -void adc_set_single_differential(uint32_t adc); -void adc_enable_single_repeat_conv(uint32_t adc); -void adc_disable_single_repeat_conv(uint32_t adc); - -void adc_set_scan_prs_trigger(uint32_t adc, uint8_t prssel); -void adc_enable_scan_prs_trigger(uint32_t adc); -void adc_disable_scan_prs_trigger(uint32_t adc); -void adc_set_scan_acquisition_cycle(uint32_t adc, uint32_t at); -void adc_set_scan_reference(uint32_t adc, uint32_t ref); -void adc_set_scan_channel(uint32_t adc, uint8_t length, - uint8_t channel[]); -void adc_set_scan_resolution(uint32_t adc, uint32_t res); -void adc_set_scan_left_aligned(uint32_t adc); -void adc_set_scan_right_aligned(uint32_t adc); -void adc_set_scan_single_ended(uint32_t adc); -void adc_set_scan_differential(uint32_t adc); -void adc_enable_scan_repeat_conv(uint32_t adc); -void adc_disable_scan_repeat_conv(uint32_t adc); - -void adc_enable_single_result_overflow_interrupt(uint32_t adc); -void adc_disable_single_result_overflow_interrupt(uint32_t adc); -void adc_enable_single_conversion_complete_interrupt(uint32_t adc); -void adc_disable_single_conversion_complete_interrupt(uint32_t adc); -void adc_enable_scan_result_overflow_interrupt(uint32_t adc); -void adc_disable_scan_result_overflow_interrupt(uint32_t adc); -void adc_enable_scan_conversion_complete_interrupt(uint32_t adc); -void adc_disable_scan_conversion_complete_interrupt(uint32_t adc); - -bool adc_get_single_result_overflow_flag(uint32_t adc); -bool adc_get_single_conversion_complete_flag(uint32_t adc); -bool adc_get_scan_result_overflow_flag(uint32_t adc); -bool adc_get_scan_conversion_complete_flag(uint32_t adc); - -void adc_set_single_result_overflow_flag(uint32_t adc); -void adc_set_single_conversion_complete_flag(uint32_t adc); -void adc_set_scan_result_overflow_flag(uint32_t adc); -void adc_set_scan_conversion_complete_flag(uint32_t adc); - -void adc_clear_single_result_overflow_flag(uint32_t adc); -void adc_clear_single_conversion_complete_flag(uint32_t adc); -void adc_clear_scan_result_overflow_flag(uint32_t adc); -void adc_clear_scan_conversion_complete_flag(uint32_t adc); - -uint32_t adc_single_data(uint32_t adc); -uint32_t adc_scan_data(uint32_t adc); - -uint32_t adc_single_data_peak(uint32_t adc); -uint32_t adc_scan_data_peak(uint32_t adc); - -void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain); -void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset); - -void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain); -void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/burtc_common.h b/libopencm3/include/libopencm3/efm32/common/burtc_common.h deleted file mode 100644 index e2202a1..0000000 --- a/libopencm3/include/libopencm3/efm32/common/burtc_common.h +++ /dev/null @@ -1,173 +0,0 @@ -/** @addtogroup burtc_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define BURTC_CTRL MMIO32(BURTC_BASE + 0x000) -#define BURTC_LPMODE MMIO32(BURTC_BASE + 0x004) -#define BURTC_CNT MMIO32(BURTC_BASE + 0x008) -#define BURTC_COMP0 MMIO32(BURTC_BASE + 0x00C) -#define BURTC_TIMESTAMP MMIO32(BURTC_BASE + 0x010) -#define BURTC_LFXOFDET MMIO32(BURTC_BASE + 0x014) -#define BURTC_STATUS MMIO32(BURTC_BASE + 0x018) -#define BURTC_CMD MMIO32(BURTC_BASE + 0x01C) -#define BURTC_POWERDOWN MMIO32(BURTC_BASE + 0x020) -#define BURTC_LOCK MMIO32(BURTC_BASE + 0x024) -#define BURTC_IF MMIO32(BURTC_BASE + 0x028) -#define BURTC_IFS MMIO32(BURTC_BASE + 0x02C) -#define BURTC_IFC MMIO32(BURTC_BASE + 0x030) -#define BURTC_IEN MMIO32(BURTC_BASE + 0x034) -#define BURTC_FREEZE MMIO32(BURTC_BASE + 0x038) -#define BURTC_SYNCBUSY MMIO32(BURTC_BASE + 0x03C) - -#define RETx_REG(x) MMIO32(BURTC_BASE + 0x100 + (4 * (x))) -/* [for ease] */ -#define BURTC_RETx(x) RETx_REG(x) - -/* BURTC_CTRL */ -#define BURTC_CTRL_BUMODETSEN (1 << 14) - -#define BURTC_CTRL_CLKSEL_SHIFT (8) -#define BURTC_CTRL_CLKSEL_MASK (0x3 << BURTC_CTRL_CLKSEL_SHIFT) -#define BURTC_CTRL_CLKSEL(v) \ - (((v) << BURTC_CTRL_CLKSEL_SHIFT) & BURTC_CTRL_CLKSEL_MASK) -#define BURTC_CTRL_CLKSEL_NONE 0 -#define BURTC_CTRL_CLKSEL_LFRCO 1 -#define BURTC_CTRL_CLKSEL_LFXO 2 -#define BURTC_CTRL_CLKSEL_ULFRCO 3 - -#define BURTC_CTRL_PRESC_SHIFT (12) -#define BURTC_CTRL_PRESC_MASK (0x7 << BURTC_CTRL_PRESC_SHIFT) -#define BURTC_CTRL_PRESC(v) \ - (((v) << BURTC_CTRL_PRESC_SHIFT) & BURTC_CTRL_PRESC_MASK) -#define BURTC_CTRL_PRESC_DIV1 0 -#define BURTC_CTRL_PRESC_DIV2 1 -#define BURTC_CTRL_PRESC_DIV4 2 -#define BURTC_CTRL_PRESC_DIV8 3 -#define BURTC_CTRL_PRESC_DIV16 4 -#define BURTC_CTRL_PRESC_DIV32 5 -#define BURTC_CTRL_PRESC_DIV64 6 -#define BURTC_CTRL_PRESC_DIV128 7 -#define BURTC_CTRL_PRESC_NODIV BURTC_CTRL_PRESC_DIV1 - -#define BURTC_CTRL_LPCOMPC_SHIFT (5) -#define BURTC_CTRL_LPCOMPC_MASK (0x7 << BURTC_CTRL_LPCOMPC_SHIFT) -#define BURTC_CTRL_LPCOMPC(v) \ - (((v) << BURTC_CTRL_LPCOMPC_SHIFT) & BURTC_CTRL_LPCOMPC_MASK) -#define BURTC_CTRL_LPCOMPC_IGNxLSB(x) BURTC_CTRL_LPCOMPC(x) -#define BURTC_CTRL_LPCOMPC_IGN0LSB 0 -#define BURTC_CTRL_LPCOMPC_IGN1LSB 1 -#define BURTC_CTRL_LPCOMPC_IGN2LSB 2 -#define BURTC_CTRL_LPCOMPC_IGN3LSB 3 -#define BURTC_CTRL_LPCOMPC_IGN4LSB 4 -#define BURTC_CTRL_LPCOMPC_IGN5LSB 5 -#define BURTC_CTRL_LPCOMPC_IGN6LSB 6 -#define BURTC_CTRL_LPCOMPC_IGN7LSB 7 - -#define BURTC_CTRL_COMP0TOP (1 << 4) -#define BURTC_CTRL_RSTEN (1 << 3) -#define BURTC_CTRL_DEBUGRUN (1 << 2) - -#define BURTC_CTRL_MODE_SHIFT (0) -#define BURTC_CTRL_MODE_MASK (0x3 << BURTC_CTRL_MODE_SHIFT) -#define BURTC_CTRL_MODE(v) \ - (((v) << BURTC_CTRL_MODE_SHIFT) & BURTC_CTRL_MODE_MASK) -#define BURTC_CTRL_MODE_DISABLE 0 -#define BURTC_CTRL_MODE_EM2EN 1 -#define BURTC_CTRL_MODE_EM3EN 2 -#define BURTC_CTRL_MODE_EM4EN 3 - -/* BURTC_LPMODE */ -#define BURTC_LPMODE_LPMODE_SHIFT (0) -#define BURTC_LPMODE_LPMODE_MASK (0x3 << BURTC_LPMODE_LPMODE_SHIFT) -#define BURTC_LPMODE_LPMODE(v) \ - (((v) << BURTC_LPMODE_LPMODE_SHIFT) & BURTC_LPMODE_LPMODE_MASK) -#define BURTC_LPMODE_LPMODE_DISABLE 0 -#define BURTC_LPMODE_LPMODE_ENABLE 1 -#define BURTC_LPMODE_LPMODE_BUEN 2 - -/* BURTC_LFXOFDET */ -#define BURTC_LFXOFDET_TOP_SHIFT (4) -#define BURTC_LFXOFDET_TOP_MASK (0xF << BURTC_LFXOFDET_TOP_SHIFT) -#define BURTC_LFXOFDET_TOP(v) \ - (((v) << BURTC_LFXOFDET_TOP_SHIFT) & BURTC_LFXOFDET_TOP_MASK) - -#define BURTC_LFXOFDET_OSC_SHIFT (0) -#define BURTC_LFXOFDET_OSC_MASK (0x3 << BURTC_LFXOFDET_OSC_SHIFT) -#define BURTC_LFXOFDET_OSC(v) \ - (((v) << BURTC_LFXOFDET_OSC_SHIFT) & BURTC_LFXOFDET_OSC_MASK) -#define BURTC_LFXOFDET_OSC_DISABLE 0 -#define BURTC_LFXOFDET_OSC_LFRCO 1 -#define BURTC_LFXOFDET_OSC_ULFRCO 2 - -/* BURTC_STATUS */ -#define BURTC_STATUS_RAMWERR (1 << 2) -#define BURTC_STATUS_BUMODETS (1 << 1) -#define BURTC_STATUS_LPMODEACT (1 << 0) - -/* BURTC_CMD */ -#define BURTC_CMD_CLRSTATUS (1 << 0) - -/* BURTC_POWERDOWN */ -#define BURTC_POWERDOWN_RAM (1 << 0) - -/* BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_SHIFT (0) -#define BURTC_LOCK_LOCKKEY_MASK (0xFFFF << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_UNLOCKED (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_LOCKED (0x0001 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_LOCK (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_UNLOCK (0xAEE8 << BURTC_LOCK_LOCKKEY_SHIFT) - -/* BURTC_IF */ -#define BURTC_IF_LFXOFAIL (1 << 2) -#define BURTC_IF_COMP0 (1 << 1) -#define BURTC_IF_OF (1 << 0) - -/* BURTC_IFS */ -#define BURTC_IFS_LFXOFAIL (1 << 2) -#define BURTC_IFS_COMP0 (1 << 1) -#define BURTC_IFS_OF (1 << 0) - -/* BURTC_IFC */ -#define BURTC_IFC_LFXOFAIL (1 << 2) -#define BURTC_IFC_COMP0 (1 << 1) -#define BURTC_IFC_OF (1 << 0) - -/* BURTC_IEN */ -#define BURTC_IEN_LFXOFAIL (1 << 2) -#define BURTC_IEN_COMP0 (1 << 1) -#define BURTC_IEN_OF (1 << 0) - -/* BURTC_FREEZE */ -#define BURTC_FREEZE_REGFREEZE (1 << 0) - -/* BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP0 (1 << 1) -#define BURTC_SYNCBUSY_LPMODE (1 << 0) - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/efm32/common/cmu_common.h b/libopencm3/include/libopencm3/efm32/common/cmu_common.h deleted file mode 100644 index e200594..0000000 --- a/libopencm3/include/libopencm3/efm32/common/cmu_common.h +++ /dev/null @@ -1,707 +0,0 @@ -/** @addtogroup cmu_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -/**@{*/ - -#include -#include - -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) -#define CMU_CMD MMIO32(CMU_BASE + 0x024) -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) -#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) -#define CMU_IF MMIO32(CMU_BASE + 0x030) -#define CMU_IFS MMIO32(CMU_BASE + 0x034) -#define CMU_IFC MMIO32(CMU_BASE + 0x038) -#define CMU_IEN MMIO32(CMU_BASE + 0x03C) -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) -#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) - -/* CMU_CTRL */ -#define CMU_CTRL_HFLE (1 << 30) -#define CMU_CTRL_DBGCLK (1 << 28) - - -#define CMU_CTRL_CLKOUTSEL1_SHIFT (23) -#define CMU_CTRL_CLKOUTSEL1_MASK (0x7 << CMU_CTRL_CLKOUTSEL1_SHIFT) -#define CMU_CTRL_CLKOUTSEL1(v) \ - (((v) << CMU_CTRL_CLKOUTSEL1_SHIFT) & CMU_CTRL_CLKOUTSEL1_MASK) -#define CMU_CTRL_CLKOUTSEL1_LFRCO 0 -#define CMU_CTRL_CLKOUTSEL1_LFXO 1 -#define CMU_CTRL_CLKOUTSEL1_HFCLK 2 -#define CMU_CTRL_CLKOUTSEL1_LFXOQ 3 -#define CMU_CTRL_CLKOUTSEL1_HFXOQ 4 -#define CMU_CTRL_CLKOUTSEL1_LFRCOQ 5 -#define CMU_CTRL_CLKOUTSEL1_HFRCOQ 6 -#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 7 - -#define CMU_CTRL_CLKOUTSEL0_SHIFT (23) -#define CMU_CTRL_CLKOUTSEL0_MASK (0x7 << CMU_CTRL_CLKOUTSEL0_SHIFT) -#define CMU_CTRL_CLKOUTSEL0(v) \ - (((v) << CMU_CTRL_CLKOUTSEL0_SHIFT) & CMU_CTRL_CLKOUTSEL0_MASK) -#define CMU_CTRL_CLKOUTSEL0_HFRCO 0 -#define CMU_CTRL_CLKOUTSEL0_HFXO 1 -#define CMU_CTRL_CLKOUTSEL0_HFCLK2 2 -#define CMU_CTRL_CLKOUTSEL0_HFCLK4 3 -#define CMU_CTRL_CLKOUTSEL0_HFCLK8 4 -#define CMU_CTRL_CLKOUTSEL0_HFCLK16 5 -#define CMU_CTRL_CLKOUTSEL0_ULFRCO 6 -#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO 7 - -#define CMU_CTRL_LFXOTIMEOUT_SHIFT (18) -#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3 << CMU_CTRL_LFXOTIMEOUT_SHIFT) -#define CMU_CTRL_LFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_LFXOTIMEOUT_SHIFT) & CMU_CTRL_LFXOTIMEOUT_MASK) -#define CMU_CTRL_LFXOTIMEOUT_8CYCLES 0 -#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES 1 -#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES 2 -#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES 3 - -#define CMU_CTRL_LFXOBUFCUR (1 << 17) - -#define CMU_CTRL_HFCLKDIV_SHIFT (14) -#define CMU_CTRL_HFCLKDIV_MASK (0x7 << CMU_CTRL_HFCLKDIV_SHIFT) -#define CMU_CTRL_HFCLKDIV(v) \ - (((v) << CMU_CTRL_HFCLKDIV_SHIFT) & CMU_CTRL_HFCLKDIV_MASK) -#define CMU_CTRL_HFCLKDIV_NODIV 0 -#define CMU_CTRL_HFCLKDIV_DIV2 1 -#define CMU_CTRL_HFCLKDIV_DIV3 2 -#define CMU_CTRL_HFCLKDIV_DIV4 3 -#define CMU_CTRL_HFCLKDIV_DIV5 4 -#define CMU_CTRL_HFCLKDIV_DIV6 5 -#define CMU_CTRL_HFCLKDIV_DIV7 6 -#define CMU_CTRL_HFCLKDIV_DIV8 7 - -#define CMU_CTRL_LFXOBOOST (1 << 13) - -#define CMU_CTRL_LFXOMODE_SHIFT (11) -#define CMU_CTRL_LFXOMODE_MASK (0x3 << CMU_CTRL_LFXOMODE_SHIFT) -#define CMU_CTRL_LFXOMODE(v) \ - (((v) << CMU_CTRL_LFXOMODE_SHIFT) & CMU_CTRL_LFXOMODE_MASK) -#define CMU_CTRL_LFXOMODE_XTAL 0 -#define CMU_CTRL_LFXOMODE_BUFEXTCLK 1 -#define CMU_CTRL_LFXOMODE_DIGEXTCLK 2 - -#define CMU_CTRL_HFXOTIMEOUT_SHIFT (9) -#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3 << CMU_CTRL_HFXOTIMEOUT_SHIFT) -#define CMU_CTRL_HFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_HFXOTIMEOUT_SHIFT) & CMU_CTRL_HFXOTIMEOUT_MASK) -#define CMU_CTRL_HFXOTIMEOUT_8CYCLES 0 -#define CMU_CTRL_HFXOTIMEOUT_256CYCLES 1 -#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES 2 -#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES 3 - -#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) - -#define CMU_CTRL_HFXOBUFCUR_SHIFT (5) -#define CMU_CTRL_HFXOBUFCUR_MASK (0x3 << CMU_CTRL_HFXOBUFCUR_SHIFT) -#define CMU_CTRL_HFXOBUFCUR(v) \ - (((v) << CMU_CTRL_HFXOBUFCUR_SHIFT) & CMU_CTRL_HFXOBUFCUR_MASK) -#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 1 -#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 3 - -#define CMU_CTRL_HFXOBOOST_SHIFT (2) -#define CMU_CTRL_HFXOBOOST_MASK (0x3 << CMU_CTRL_HFXOBOOST_SHIFT) -#define CMU_CTRL_HFXOBOOST(v) \ - (((v) << CMU_CTRL_HFXOBOOST_SHIFT) & CMU_CTRL_HFXOBOOST_MASK) -#define CMU_CTRL_HFXOBOOST_50PCENT 0 -#define CMU_CTRL_HFXOBOOST_70PCENT 1 -#define CMU_CTRL_HFXOBOOST_80PCENT 2 -#define CMU_CTRL_HFXOBOOST_100PCENT 3 - -#define CMU_CTRL_HFXOMODE_SHIFT (0) -#define CMU_CTRL_HFXOMODE_MASK (0x3 << CMU_CTRL_HFXOMODE_SHIFT) -#define CMU_CTRL_HFXOMODE(v) \ - (((v) << CMU_CTRL_HFXOMODE_SHIFT) & CMU_CTRL_HFXOMODE_MASK) -#define CMU_CTRL_HFXOMODE_XTAL 0 -#define CMU_CTRL_HFXOMODE_BUFEXTCLK 1 -#define CMU_CTRL_HFXOMODE_DIGEXTCLK 2 - -/* CMU_HFCORECLKDIV */ -#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (1 << 8) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT (0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_MASK \ - (0xF << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) -#define CMU_HFCORECLKDIV_HFCORECLKDIV(v) \ - (((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \ - CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK \ - CMU_HFCORECLKDIV_HFCORECLKDIV(0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(1) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(2) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(3) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(4) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(5) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(6) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(7) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(8) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(9) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 - -/* CMU_HFPERCLKDIV */ -#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) - -#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT (0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK \ - (0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) -#define CMU_HFPERCLKDIV_HFPERCLKDIV(v) \ - (((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \ - CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK CMU_HFPERCLKDIV_HFPERCLKDIV(0) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2 CMU_HFPERCLKDIV_HFPERCLKDIV(1) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4 CMU_HFPERCLKDIV_HFPERCLKDIV(2) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK8 CMU_HFPERCLKDIV_HFPERCLKDIV(3) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK16 CMU_HFPERCLKDIV_HFPERCLKDIV(4) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK32 CMU_HFPERCLKDIV_HFPERCLKDIV(5) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK64 CMU_HFPERCLKDIV_HFPERCLKDIV(6) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK128 CMU_HFPERCLKDIV_HFPERCLKDIV(7) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK256 CMU_HFPERCLKDIV_HFPERCLKDIV(8) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512 CMU_HFPERCLKDIV_HFPERCLKDIV(9) - -/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */ -#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 - -/* CMU_HFRCOCTRL */ -#define CMU_HFRCOCTRL_SUDELAY_SHIFT (12) -#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1F << CMU_HFRCOCTRL_SUDELAY_SHIFT) -#define CMU_HFRCOCTRL_SUDELAY(v) \ - ((((v) << CMU_HFRCOCTRL_SUDELAY_SHIFT) & CMU_HFRCOCTRL_SUDELAY_MASK)) - -#define CMU_HFRCOCTRL_BAND_SHIFT (8) -#define CMU_HFRCOCTRL_BAND_MASK (0x7 << CMU_HFRCOCTRL_BAND_SHIFT) -#define CMU_HFRCOCTRL_BAND(v) \ - (((v) << CMU_HFRCOCTRL_BAND_SHIFT) & CMU_HFRCOCTRL_BAND_MASK) -#define CMU_HFRCOCTRL_BAND_1MHZ 0 -#define CMU_HFRCOCTRL_BAND_7MHZ 1 -#define CMU_HFRCOCTRL_BAND_11MHZ 2 -#define CMU_HFRCOCTRL_BAND_14MHZ 3 -#define CMU_HFRCOCTRL_BAND_21MHZ 4 -#define CMU_HFRCOCTRL_BAND_28MHZ 5 - -#define CMU_HFRCOCTRL_TUNING_SHIFT (0) -#define CMU_HFRCOCTRL_TUNING_MASK (0xFF << CMU_HFRCOCTRL_TUNING_SHIFT) -#define CMU_HFRCOCTRL_TUNING(v) \ - (((v) << CMU_HFRCOCTRL_TUNING_SHIFT) & CMU_HFRCOCTRL_TUNING_MASK) - -/* CMU_LFRCOCTRL */ -#define CMU_LFRCOCTRL_TUNING_SHIFT (0) -#define CMU_LFRCOCTRL_TUNING_MASK (0xFF << CMU_LFRCOCTRL_TUNING_SHIFT) -#define CMU_LFRCOCTRL_TUNING(v) \ - (((v) << CMU_LFRCOCTRL_TUNING_SHIFT) & CMU_LFRCOCTRL_TUNING_MASK) - -/* CMU_AUXHFRCOCTRL */ -#define CMU_AUXHFRCOCTRL_BAND_SHIFT (8) -#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7 << CMU_AUXHFRCOCTRL_BAND_SHIFT) -#define CMU_AUXHFRCOCTRL_BAND(v) \ - (((v) << CMU_AUXHFRCOCTRL_BAND_SHIFT) & CMU_AUXHFRCOCTRL_BAND_MASK) -#define CMU_AUXHFRCOCTRL_BAND_1MHZ 0 -#define CMU_AUXHFRCOCTRL_BAND_7MHZ 1 -#define CMU_AUXHFRCOCTRL_BAND_11MHZ 2 -#define CMU_AUXHFRCOCTRL_BAND_14MHZ 3 -#define CMU_AUXHFRCOCTRL_BAND_28MHZ 4 -#define CMU_AUXHFRCOCTRL_BAND_21MHZ 5 - -#define CMU_AUXHFRCOCTRL_TUNING_SHIFT (0) -#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xFF << CMU_AUXHFRCOCTRL_TUNING_SHIFT) -#define CMU_AUXHFRCOCTRL_TUNING(v) \ - (((v) << CMU_AUXHFRCOCTRL_TUNING_SHIFT) & CMU_AUXHFRCOCTRL_TUNING_MASK) - -/* CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (1 << 6) - -#define CMU_CALCTRL_DOWNSEL_SHIFT (3) -#define CMU_CALCTRL_DOWNSEL_MASK (0x7 << CMU_CALCTRL_DOWNSEL_SHIFT) -#define CMU_CALCTRL_DOWNSEL(v) \ - (((v) << CMU_CALCTRL_DOWNSEL_SHIFT) & CMU_CALCTRL_DOWNSEL_MASK) -#define CMU_CALCTRL_DOWNSEL_HFCLK 0 -#define CMU_CALCTRL_DOWNSEL_HFXO 1 -#define CMU_CALCTRL_DOWNSEL_LFXO 2 -#define CMU_CALCTRL_DOWNSEL_HFRCO 3 -#define CMU_CALCTRL_DOWNSEL_LFRCO 4 -#define CMU_CALCTRL_DOWNSEL_AUXHFRCO 5 - -#define CMU_CALCTRL_UPSEL_SHIFT (3) -#define CMU_CALCTRL_UPSEL_MASK (0x7 << CMU_CALCTRL_UPSEL_SHIFT) -#define CMU_CALCTRL_UPSEL(v) \ - (((v) << CMU_CALCTRL_UPSEL_SHIFT) & CMU_CALCTRL_UPSEL_MASK) -#define CMU_CALCTRL_UPSEL_HFXO 0 -#define CMU_CALCTRL_UPSEL_LFXO 1 -#define CMU_CALCTRL_UPSEL_HFRCO 2 -#define CMU_CALCTRL_UPSEL_LFRCO 3 -#define CMU_CALCTRL_UPSEL_AUXHFRCO 4 - -/* CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_SHIFT (0) -#define CMU_CALCNT_CALCNT_MASK (0xFFFFF << CMU_CALCNT_CALCNT_SHIFT) -#define CMU_CALCNT_CALCNT(v) \ - (((v) << CMU_CALCNT_CALCNT_SHIFT) & CMU_CALCNT_CALCNT_MASK) - -/* CMU_OSCENCMD */ -#define CMU_OSCENCMD_LFXODIS (1 << 9) -#define CMU_OSCENCMD_LFXOEN (1 << 8) -#define CMU_OSCENCMD_LFRCODIS (1 << 7) -#define CMU_OSCENCMD_LFRCOEN (1 << 6) -#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) -#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) -#define CMU_OSCENCMD_HFXODIS (1 << 3) -#define CMU_OSCENCMD_HFXOEN (1 << 2) -#define CMU_OSCENCMD_HFRCODIS (1 << 1) -#define CMU_OSCENCMD_HFRCOEN (1 << 0) - -/* CMU_CMD */ -#define CMU_CMD_USBCCLKSEL_SHIFT (5) -#define CMU_CMD_USBCCLKSEL_MASK (0x3 << CMU_CMD_USBCCLKSEL_SHIFT) -#define CMU_CMD_USBCCLKSEL(v) \ - (((v) << CMU_CMD_USBCCLKSEL_SHIFT) & CMU_CMD_USBCCLKSEL_MASK) -#define CMU_CMD_USBCCLKSEL_HFCLKNODIV 1 -#define CMU_CMD_USBCCLKSEL_LFXO 2 -#define CMU_CMD_USBCCLKSEL_LFRCO 3 - -#define CMU_CMD_CALSTOP (1 << 4) -#define CMU_CMD_CALSTART (1 << 3) - -#define CMU_CMD_HFCLKSEL_SHIFT (0) -#define CMU_CMD_HFCLKSEL_MASK (0x7 << CMU_CMD_HFCLKSEL_SHIFT) -#define CMU_CMD_HFCLKSEL(v) \ - (((v) << CMU_CMD_HFCLKSEL_SHIFT) & CMU_CMD_HFCLKSEL_MASK) -#define CMU_CMD_HFCLKSEL_HFRCO 1 -#define CMU_CMD_HFCLKSEL_HFXO 2 -#define CMU_CMD_HFCLKSEL_LFRCO 3 -#define CMU_CMD_HFCLKSEL_LFXO 4 - -/* CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE (1 << 20) -#define CMU_LFCLKSEL_LFAE (1 << 16) - -#define CMU_LFCLKSEL_LFB_SHIFT (2) -#define CMU_LFCLKSEL_LFB_MASK (0x3 << CMU_LFCLKSEL_LFB_MASK) -#define CMU_LFCLKSEL_LFB(v) \ - (((v) << CMU_LFCLKSEL_LFB_MASK) & CMU_LFCLKSEL_LFB_MASK) - -#define CMU_LFCLKSEL_LFA_SHIFT (0) -#define CMU_LFCLKSEL_LFA_MASK (0x3 << CMU_LFCLKSEL_LFA_MASK) -#define CMU_LFCLKSEL_LFA(v) \ - (((v) << CMU_LFCLKSEL_LFA_MASK) & CMU_LFCLKSEL_LFA_MASK) - -/* CMU_STATUS */ -#define CMU_STATUS_USBCLFRCOSEL (1 << 17) -#define CMU_STATUS_USBCLFXOSEL (1 << 16) -#define CMU_STATUS_USBCHFCLKSEL (1 << 15) -#define CMU_STATUS_CALBSY (1 << 14) -#define CMU_STATUS_LFXOSEL (1 << 13) -#define CMU_STATUS_LFRCOSEL (1 << 12) -#define CMU_STATUS_HFXOSEL (1 << 11) -#define CMU_STATUS_HFRCOSEL (1 << 10) -#define CMU_STATUS_LFXORDY (1 << 9) -#define CMU_STATUS_LFXOENS (1 << 8) -#define CMU_STATUS_LFRCORDY (1 << 7) -#define CMU_STATUS_LFRCOENS (1 << 6) -#define CMU_STATUS_AUXHFRCORDY (1 << 5) -#define CMU_STATUS_AUXHFRCOENS (1 << 4) -#define CMU_STATUS_HFXORDY (1 << 3) -#define CMU_STATUS_HFXOENS (1 << 2) -#define CMU_STATUS_HFRCORDY (1 << 1) -#define CMU_STATUS_HFRCOENS (1 << 0) - -/* CMU_IF */ -#define CMU_IF_USBCHFCLKSEL (1 << 7) -#define CMU_IF_CALOF (1 << 6) -#define CMU_IF_CALRDY (1 << 5) -#define CMU_IF_AUXHFRCORDY (1 << 4) -#define CMU_IF_LFXORDY (1 << 3) -#define CMU_IF_LFRCORDY (1 << 2) -#define CMU_IF_HFXORDY (1 << 1) -#define CMU_IF_HFRCORDY (1 << 0) - -/* CMU_IFS */ -#define CMU_IFS_USBCHFCLKSEL (1 << 7) -#define CMU_IFS_CALOF (1 << 6) -#define CMU_IFS_CALRDY (1 << 5) -#define CMU_IFS_AUXHFRCORDY (1 << 4) -#define CMU_IFS_LFXORDY (1 << 3) -#define CMU_IFS_LFRCORDY (1 << 2) -#define CMU_IFS_HFXORDY (1 << 1) -#define CMU_IFS_HFRCORDY (1 << 0) - -/* CMU_IFC */ -#define CMU_IFC_USBCHFCLKSEL (1 << 7) -#define CMU_IFC_CALOF (1 << 6) -#define CMU_IFC_CALRDY (1 << 5) -#define CMU_IFC_AUXHFRCORDY (1 << 4) -#define CMU_IFC_LFXORDY (1 << 3) -#define CMU_IFC_LFRCORDY (1 << 2) -#define CMU_IFC_HFXORDY (1 << 1) -#define CMU_IFC_HFRCORDY (1 << 0) - -/* CMU_IEN */ -#define CMU_IEN_USBCHFCLKSEL (1 << 7) -#define CMU_IEN_CALOF (1 << 6) -#define CMU_IEN_CALRDY (1 << 5) -#define CMU_IEN_AUXHFRCORDY (1 << 4) -#define CMU_IEN_LFXORDY (1 << 3) -#define CMU_IEN_LFRCORDY (1 << 2) -#define CMU_IEN_HFXORDY (1 << 1) -#define CMU_IEN_HFRCORDY (1 << 0) - -/* CMU_HFCORECLKEN0 */ -#define CMU_HFCORECLKEN0_EBI (1 << 5) -#define CMU_HFCORECLKEN0_LE (1 << 4) -#define CMU_HFCORECLKEN0_USB (1 << 3) -#define CMU_HFCORECLKEN0_USBC (1 << 2) -#define CMU_HFCORECLKEN0_AES (1 << 1) -#define CMU_HFCORECLKEN0_DMA (1 << 0) - -/* CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_DAC0 (1 << 17) -#define CMU_HFPERCLKEN0_ADC0 (1 << 16) -#define CMU_HFPERCLKEN0_PRS (1 << 15) -#define CMU_HFPERCLKEN0_VCMP (1 << 14) -#define CMU_HFPERCLKEN0_GPIO (1 << 13) -#define CMU_HFPERCLKEN0_I2C1 (1 << 12) -#define CMU_HFPERCLKEN0_I2C0 (1 << 11) -#define CMU_HFPERCLKEN0_ACMP1 (1 << 10) -#define CMU_HFPERCLKEN0_ACMP0 (1 << 9) -#define CMU_HFPERCLKEN0_TIMER3 (1 << 8) -#define CMU_HFPERCLKEN0_TIMER2 (1 << 7) -#define CMU_HFPERCLKEN0_TIMER1 (1 << 6) -#define CMU_HFPERCLKEN0_TIMER0 (1 << 5) -#define CMU_HFPERCLKEN0_UART1 (1 << 4) -#define CMU_HFPERCLKEN0_UART0 (1 << 3) -#define CMU_HFPERCLKEN0_USART2 (1 << 2) -#define CMU_HFPERCLKEN0_USART1 (1 << 1) -#define CMU_HFPERCLKEN0_USART0 (1 << 0) - -/* CMU_SYNCBUSY */ -#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) -#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) -#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) -#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) - -/* CMU_FREEZE */ -#define CMU_FREEZE_REGFREEZE (1 << 0) - -/* CMU_LFACLKEN0 */ -#define CMU_LFACLKEN0_LCD (1 << 3) -#define CMU_LFACLKEN0_LETIMER0 (1 << 2) -#define CMU_LFACLKEN0_RTC (1 << 1) -#define CMU_LFACLKEN0_LESENSE (1 << 0) - -/* CMU_LFBCLKEN0 */ -#define CMU_LFBCLKEN0_LEUART1 (1 << 1) -#define CMU_LFBCLKEN0_LEUART0 (1 << 0) - -/* CMU_LFAPRESC0 */ -#define CMU_LFAPRESC0_LCD_SHIFT (12) -#define CMU_LFAPRESC0_LCD_MASK (0x3 << CMU_LFAPRESC0_LCD_SHIFT) -#define CMU_LFAPRESC0_LCD(v) \ - (((v) << CMU_LFAPRESC0_LCD_SHIFT) & CMU_LFAPRESC0_LCD_MASK) -#define CMU_LFAPRESC0_LCD_DIV16 0 -#define CMU_LFAPRESC0_LCD_DIV32 1 -#define CMU_LFAPRESC0_LCD_DIV64 2 -#define CMU_LFAPRESC0_LCD_DIV128 3 - -#define CMU_LFAPRESC0_LETIMER0_SHIFT (8) -#define CMU_LFAPRESC0_LETIMER0_MASK (0xF << CMU_LFAPRESC0_LETIMER0_SHIFT) -#define CMU_LFAPRESC0_LETIMER0(v) \ - (((v) << CMU_LFAPRESC0_LETIMER0_SHIFT) & CMU_LFAPRESC0_LETIMER0_MASK) -#define CMU_LFAPRESC0_LETIMER0_DIV1 0 -#define CMU_LFAPRESC0_LETIMER0_DIV2 1 -#define CMU_LFAPRESC0_LETIMER0_DIV4 2 -#define CMU_LFAPRESC0_LETIMER0_DIV8 3 -#define CMU_LFAPRESC0_LETIMER0_DIV16 4 -#define CMU_LFAPRESC0_LETIMER0_DIV32 5 -#define CMU_LFAPRESC0_LETIMER0_DIV64 6 -#define CMU_LFAPRESC0_LETIMER0_DIV128 7 -#define CMU_LFAPRESC0_LETIMER0_DIV256 8 -#define CMU_LFAPRESC0_LETIMER0_DIV512 9 -#define CMU_LFAPRESC0_LETIMER0_DIV1024 10 -#define CMU_LFAPRESC0_LETIMER0_DIV2048 11 -#define CMU_LFAPRESC0_LETIMER0_DIV4096 12 -#define CMU_LFAPRESC0_LETIMER0_DIV8192 13 -#define CMU_LFAPRESC0_LETIMER0_DIV16384 14 -#define CMU_LFAPRESC0_LETIMER0_DIV32768 15 -#define CMU_LFAPRESC0_LETIMER0_NODIV CMU_LFAPRESC0_LETIMER0_DIV1 - -#define CMU_LFAPRESC0_RTC_SHIFT (4) -#define CMU_LFAPRESC0_RTC_MASK (0xF << CMU_LFAPRESC0_RTC_SHIFT) -#define CMU_LFAPRESC0_RTC(v) \ - (((v) << CMU_LFAPRESC0_RTC_SHIFT) & CMU_LFAPRESC0_RTC_MASK) -#define CMU_LFAPRESC0_RTC_DIV1 0 -#define CMU_LFAPRESC0_RTC_DIV2 1 -#define CMU_LFAPRESC0_RTC_DIV4 2 -#define CMU_LFAPRESC0_RTC_DIV8 3 -#define CMU_LFAPRESC0_RTC_DIV16 4 -#define CMU_LFAPRESC0_RTC_DIV32 5 -#define CMU_LFAPRESC0_RTC_DIV64 6 -#define CMU_LFAPRESC0_RTC_DIV128 7 -#define CMU_LFAPRESC0_RTC_DIV256 8 -#define CMU_LFAPRESC0_RTC_DIV512 9 -#define CMU_LFAPRESC0_RTC_DIV1024 10 -#define CMU_LFAPRESC0_RTC_DIV2048 11 -#define CMU_LFAPRESC0_RTC_DIV4096 12 -#define CMU_LFAPRESC0_RTC_DIV8192 13 -#define CMU_LFAPRESC0_RTC_DIV16384 14 -#define CMU_LFAPRESC0_RTC_DIV32768 15 -#define CMU_LFAPRESC0_RTC_NODIV CMU_LFAPRESC0_RTC_DIV1 - -#define CMU_LFAPRESC0_LESENSE_SHIFT (12) -#define CMU_LFAPRESC0_LESENSE_MASK (0x3 << CMU_LFAPRESC0_LESENSE_SHIFT) -#define CMU_LFAPRESC0_LESENSE(v) \ - (((v) << CMU_LFAPRESC0_LESENSE_SHIFT) & CMU_LFAPRESC0_LESENSE_MASK) -#define CMU_LFAPRESC0_LESENSE_DIV1 0 -#define CMU_LFAPRESC0_LESENSE_DIV2 1 -#define CMU_LFAPRESC0_LESENSE_DIV4 2 -#define CMU_LFAPRESC0_LESENSE_DIV8 3 -#define CMU_LFAPRESC0_LESENSE_NODIV CMU_LFAPRESC0_LESENSE_DIV1 - -/* CMU_LFBPRESC0 */ -#define CMU_LFBPRESC0_LEUART1_SHIFT (4) -#define CMU_LFBPRESC0_LEUART1_MASK (0x3 << CMU_LFBPRESC0_LEUART1_SHIFT) -#define CMU_LFBPRESC0_LEUART1(v) \ - (((v) << CMU_LFBPRESC0_LEUART1_SHIFT) & CMU_LFBPRESC0_LEUART1_MASK) -#define CMU_LFBPRESC0_LEUART1_DIV1 0 -#define CMU_LFBPRESC0_LEUART1_DIV2 1 -#define CMU_LFBPRESC0_LEUART1_DIV4 2 -#define CMU_LFBPRESC0_LEUART1_DIV8 3 -#define CMU_LFBPRESC0_LEUART1_NODIV CMU_LFBPRESC0_LEUART1_DIV1 - -#define CMU_LFBPRESC0_LEUART0_SHIFT (0) -#define CMU_LFBPRESC0_LEUART0_MASK (0x3 << CMU_LFBPRESC0_LEUART0_SHIFT) -#define CMU_LFBPRESC0_LEUART0(v) \ - (((v) << CMU_LFBPRESC0_LEUART0_SHIFT) & CMU_LFBPRESC0_LEUART0_MASK) -#define CMU_LFBPRESC0_LEUART0_DIV1 0 -#define CMU_LFBPRESC0_LEUART0_DIV2 1 -#define CMU_LFBPRESC0_LEUART0_DIV4 2 -#define CMU_LFBPRESC0_LEUART0_DIV8 3 -#define CMU_LFBPRESC0_LEUART0_NODIV CMU_LFBPRESC0_LEUART0_DIV1 - -/* CMU_PCNTCTRL */ -#define CMU_PCNTCTRL_PCNT2CLKSE (1 << 5) -#define CMU_PCNTCTRL_PCNT2CLKEN (1 << 4) -#define CMU_PCNTCTRL_PCNT1CLKSEL (1 << 3) -#define CMU_PCNTCTRL_PCNT1CLKEN (1 << 2) -#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) -#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) - -/* CMU_LCDCTRL */ -#define CMU_LCDCTRL_VBFDIV_SHIFT (4) -#define CMU_LCDCTRL_VBFDIV_MASK (0xF << CMU_LCDCTRL_VBFDIV_SHIFT) -#define CMU_LCDCTRL_VBFDIV(v) \ - (((v) << CMU_LCDCTRL_VBFDIV_SHIFT) & CMU_LCDCTRL_VBFDIV_MASK) -#define CMU_LCDCTRL_VBFDIV_DIV1 0 -#define CMU_LCDCTRL_VBFDIV_DIV2 1 -#define CMU_LCDCTRL_VBFDIV_DIV4 2 -#define CMU_LCDCTRL_VBFDIV_DIV8 3 -#define CMU_LCDCTRL_VBFDIV_DIV16 4 -#define CMU_LCDCTRL_VBFDIV_DIV32 5 -#define CMU_LCDCTRL_VBFDIV_DIV64 6 -#define CMU_LCDCTRL_VBFDIV_DIV128 7 -#define CMU_LCDCTRL_VBFDIV_NODIV CMU_LCDCTRL_VBFDIV_DIV1 - -#define CMU_LCDCTRL_VBOOSTEN (1 << 3) - -#define CMU_LCDCTRL_FDIV_SHIFT (0) -#define CMU_LCDCTRL_FDIV_MASK (0x3 << CMU_LCDCTRL_FDIV_SHIFT) -#define CMU_LCDCTRL_FDIV(v) \ - (((v) & CMU_LCDCTRL_FDIV_MASK) << CMU_LCDCTRL_FDIV_SHIFT) - -/* CMU_ROUTE */ -#define CMU_ROUTE_LOCATION_SHIFT (2) -#define CMU_ROUTE_LOCATION_MASK (0x7 << CMU_ROUTE_LOCATION_SHIFT) -#define CMU_ROUTE_LOCATION_LOCx(i) \ - (((i) << CMU_ROUTE_LOCATION_SHIFT) & CMU_ROUTE_LOCATION_MASK) -#define CMU_ROUTE_LOCATION_LOC0 0 -#define CMU_ROUTE_LOCATION_LOC1 1 -#define CMU_ROUTE_LOCATION_LOC2 2 - -#define CMU_ROUTE_CLKOUT1PEN (1 << 1) -#define CMU_ROUTE_CLKOUT0PEN (1 << 0) - -/* CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_SHIFT (0) -#define CMU_LOCK_LOCKKEY_MASK (0xFFFF << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCKED (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCKED (0x0001 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCK (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCK (0x580E << CMU_LOCK_LOCKKEY_SHIFT) - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum cmu_periph_clken { - /* CMU_PCNTCTRL */ - CMU_PCNT2 = _REG_BIT(0x078, 4), - CMU_PCNT1 = _REG_BIT(0x078, 2), - CMU_PCNT0 = _REG_BIT(0x078, 0), - - /* CMU_LFBCLKEN0 */ - CMU_LEUART1 = _REG_BIT(0x060, 1), - CMU_LEUART0 = _REG_BIT(0x060, 0), - - /* CMU_LFACLKEN0 */ - CMU_LCD = _REG_BIT(0x058, 3), - CMU_LETIMER0 = _REG_BIT(0x058, 2), - CMU_RTC = _REG_BIT(0x058, 1), - CMU_LESENSE = _REG_BIT(0x058, 0), - - /* CMU_HFPERCLKEN0 */ - CMU_DAC0 = _REG_BIT(0x044, 17), - CMU_ADC0 = _REG_BIT(0x044, 16), - CMU_PRS = _REG_BIT(0x044, 15), - CMU_VCMP = _REG_BIT(0x044, 14), - CMU_GPIO = _REG_BIT(0x044, 13), - CMU_I2C1 = _REG_BIT(0x044, 12), - CMU_I2C0 = _REG_BIT(0x044, 11), - CMU_ACMP1 = _REG_BIT(0x044, 10), - CMU_ACMP0 = _REG_BIT(0x044, 9), - CMU_TIMER3 = _REG_BIT(0x044, 8), - CMU_TIMER2 = _REG_BIT(0x044, 7), - CMU_TIMER1 = _REG_BIT(0x044, 6), - CMU_TIMER0 = _REG_BIT(0x044, 5), - CMU_UART1 = _REG_BIT(0x044, 4), - CMU_UART0 = _REG_BIT(0x044, 3), - CMU_USART2 = _REG_BIT(0x044, 2), - CMU_USART1 = _REG_BIT(0x044, 1), - CMU_USART0 = _REG_BIT(0x044, 0), - - /* CMU_HFCORECLKEN0 */ - CMU_EBI = _REG_BIT(0x040, 5), - CMU_LE = _REG_BIT(0x040, 4), - CMU_USB = _REG_BIT(0x040, 3), - CMU_USBC = _REG_BIT(0x040, 2), - CMU_AES = _REG_BIT(0x040, 1), - CMU_DMA = _REG_BIT(0x040, 0) -}; - -enum cmu_osc { - HFRCO, /**< Internal, 1 - 28Mhz */ - LFRCO, /**< Internal, 32.768kHz */ - ULFRCO, /**< Internal, 1Khz */ - HFXO, /**< External, 4-48Mhz */ - LFXO, /**< External, 32.768kHz */ - AUXHFRCO, /**< Internal, 1-28Mhz */ -}; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void cmu_enable_lock(void); -void cmu_disable_lock(void); -bool cmu_get_lock_flag(void); - -void cmu_periph_clock_enable(enum cmu_periph_clken periph); -void cmu_periph_clock_disable(enum cmu_periph_clken periph); - -/* TODO: CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, - * CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_CALCTRL, CMU_CALCNT */ - -void cmu_osc_on(enum cmu_osc osc); -void cmu_osc_off(enum cmu_osc osc); - -/* TODO: CMU_CMD, CMU_LFCLKSEL */ - -/* TODO: portions of CMU_STATUS */ -bool cmu_osc_ready_flag(enum cmu_osc osc); -void cmu_wait_for_osc_ready(enum cmu_osc osc); -void cmu_set_hfclk_source(enum cmu_osc osc); -void cmu_set_usbclk_source(enum cmu_osc osc); -enum cmu_osc cmu_get_hfclk_source(void); - -/* TODO: CMU_IF, CMU_IFS, CMU_IFC, CMU_IEN */ - -/* TODO: CMU_SYNCBUSY, CMU_FREEZE, CMU_LFACLKEN0 */ - -/* TODO: CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_PCNTCTRL, CMU_LCDCTRL, CMU_ROUTE */ - -void cmu_clock_setup_in_hfxo_out_48mhz(void); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/dac_common.h b/libopencm3/include/libopencm3/efm32/common/dac_common.h deleted file mode 100644 index d77bd75..0000000 --- a/libopencm3/include/libopencm3/efm32/common/dac_common.h +++ /dev/null @@ -1,514 +0,0 @@ -/** @addtogroup dac_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include -#include - -/**@{*/ - -#define DAC_CTRL(base) MMIO32((base) + 0x00) -#define DAC_STATUS(base) MMIO32((base) + 0x04) -#define DAC_CHx_CTRL(base, x) MMIO32((base) + 0x08 + (0x04 * (x))) -#define DAC_CH0CTRL(base) DAC_CHx_CTRL(base, 0) -#define DAC_CH1CTRL(base) DAC_CHx_CTRL(base, 1) -#define DAC_IEN(base) MMIO32((base) + 0x010) -#define DAC_IF(base) MMIO32((base) + 0x014) -#define DAC_IFS(base) MMIO32((base) + 0x018) -#define DAC_IFC(base) MMIO32((base) + 0x01C) -#define DAC_CH0DATA(base) MMIO32((base) + 0x020) -#define DAC_CH1DATA(base) MMIO32((base) + 0x024) -#define DAC_COMBDATA(base) MMIO32((base) + 0x028) -#define DAC_CAL(base) MMIO32((base) + 0x02C) -#define DAC_BIASPROG(base) MMIO32((base) + 0x030) -#define DAC_OPACTRL(base) MMIO32((base) + 0x054) -#define DAC_OPAOFFSET(base) MMIO32((base) + 0x058) -#define DAC_OPA0MUX(base) MMIO32((base) + 0x05C) -#define DAC_OPA1MUX(base) MMIO32((base) + 0x060) -#define DAC_OPA2MUX(base) MMIO32((base) + 0x064) - -/* DAC_CTRL */ -#define DAC_CTRL_REFRSEL_SHIFT (20) -#define DAC_CTRL_REFRSEL_MASK (0x3 << DAC_CTRL_REFRSEL_SHIFT) -#define DAC_CTRL_REFRSEL(v) \ - (((v) << DAC_CTRL_REFRSEL_SHIFT) & DAC_CTRL_REFRSEL_MASK) -#define DAC_CTRL_REFRSEL_8CYCLES 0 -#define DAC_CTRL_REFRSEL_16CYCLES 1 -#define DAC_CTRL_REFRSEL_32CYCLES 2 -#define DAC_CTRL_REFRSEL_64CYCLES 3 - -#define DAC_CTRL_PRESC_SHIFT (16) -#define DAC_CTRL_PRESC_MASK (0x7 << DAC_CTRL_PRESC_SHIFT) -#define DAC_CTRL_PRESC(v) \ - (((v) << DAC_CTRL_PRESC_SHIFT) & DAC_CTRL_PRESC_MASK) -#define DAC_CTRL_PRESC_DIV1 0 -#define DAC_CTRL_PRESC_DIV2 1 -#define DAC_CTRL_PRESC_DIV4 2 -#define DAC_CTRL_PRESC_DIV8 3 -#define DAC_CTRL_PRESC_DIV16 4 -#define DAC_CTRL_PRESC_DIV32 5 -#define DAC_CTRL_PRESC_DIV64 6 -#define DAC_CTRL_PRESC_DIV128 7 -#define DAC_CTRL_PRESC_NODIV DAC_CTRL_PRESC_DIV1 - -#define DAC_CTRL_REFSEL_SHIFT (8) -#define DAC_CTRL_REFSEL_MASK (0x3 << DAC_CTRL_REFSEL_SHIFT) -#define DAC_CTRL_REFSEL(v) \ - (((v) << DAC_CTRL_REFSEL_SHIFT) & DAC_CTRL_REFSEL_MASK) -#define DAC_CTRL_REFSEL_1V25 0 -#define DAC_CTRL_REFSEL_2V5 1 -#define DAC_CTRL_REFSEL_VDD 2 - -#define DAC_CTRL_CH0PRESCRST (1 << 7) -#define DAC_CTRL_OUTENPRS (1 << 6) - -#define DAC_CTRL_OUTMODE_SHIFT (4) -#define DAC_CTRL_OUTMODE_MASK (0x3 << DAC_CTRL_OUTMODE_SHIFT) -#define DAC_CTRL_OUTMODE(v) \ - (((v) << DAC_CTRL_OUTMODE_SHIFT) & DAC_CTRL_OUTMODE_MASK) -#define DAC_CTRL_OUTMODE_DISABLE 0 -#define DAC_CTRL_OUTMODE_PIN 1 -#define DAC_CTRL_OUTMODE_ADC 2 -#define DAC_CTRL_OUTMODE_PINADC 3 - -#define DAC_CTRL_CONVMODE_SHIFT (2) -#define DAC_CTRL_CONVMODE_MASK (0x3 << DAC_CTRL_CONVMODE_SHIFT) -#define DAC_CTRL_CONVMODE(v) \ - (((v) << DAC_CTRL_CONVMODE_SHIFT) & DAC_CTRL_CONVMODE_MASK) -#define DAC_CTRL_CONVMODE_CONTINUOUS 0 -#define DAC_CTRL_CONVMODE_SAMPLEHOLD 1 -#define DAC_CTRL_CONVMODE_SAMPLEOFF 2 - -#define DAC_CTRL_SINMODE (1 << 1) -#define DAC_CTRL_DIFF (1 << 0) - -/* DAC_STATUS */ -#define DAC_STATUS_CH1DV (1 << 1) -#define DAC_STATUS_CH0DV (1 << 0) - -/* DAC_CH_CTRL */ -#define DAC_CH_CTRL_PRSSEL_SHIFT (4) -#define DAC_CH_CTRL_PRSSEL_MASK (0xF << DAC_CH_CTRL_PRSSEL_SHIFT) -#define DAC_CH_CTRL_PRSSEL(v) \ - (((v) << DAC_CH_CTRL_PRSSEL_SHIFT) & DAC_CH_CTRL_PRSSEL_MASK) -#define DAC_CH_CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL(x) -#define DAC_CH_CTRL_PRSSEL_PRSCH0 0 -#define DAC_CH_CTRL_PRSSEL_PRSCH1 1 -#define DAC_CH_CTRL_PRSSEL_PRSCH2 2 -#define DAC_CH_CTRL_PRSSEL_PRSCH3 3 -#define DAC_CH_CTRL_PRSSEL_PRSCH4 4 -#define DAC_CH_CTRL_PRSSEL_PRSCH5 5 -#define DAC_CH_CTRL_PRSSEL_PRSCH6 6 -#define DAC_CH_CTRL_PRSSEL_PRSCH7 7 -#define DAC_CH_CTRL_PRSSEL_PRSCH8 8 -#define DAC_CH_CTRL_PRSSEL_PRSCH9 9 -#define DAC_CH_CTRL_PRSSEL_PRSCH10 10 -#define DAC_CH_CTRL_PRSSEL_PRSCH11 11 - -#define DAC_CH_CTRL_PRSEN (1 << 2) -#define DAC_CH_CTRL_REFREN (1 << 1) -#define DAC_CH_CTRL_EN (1 << 0) - -/* DAC_CH0CTRL */ -#define DAC_CH0CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT -#define DAC_CH0CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK -#define DAC_CH0CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) -#define DAC_CH0CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) -#define DAC_CH0CTRL_PRSSEL_PRSCH0 DAC_CH0CTRL_PRSSEL_PRSCH0 -#define DAC_CH0CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 -#define DAC_CH0CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 -#define DAC_CH0CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 -#define DAC_CH0CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 -#define DAC_CH0CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 -#define DAC_CH0CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 -#define DAC_CH0CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 -#define DAC_CH0CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 -#define DAC_CH0CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 -#define DAC_CH0CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 -#define DAC_CH0CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 - -#define DAC_CH0CTRL_PRSEN DAC_CH_CTRL_PRSEN -#define DAC_CH0CTRL_REFREN DAC_CH_CTRL_REFREN -#define DAC_CH0CTRL_EN DAC_CH_CTRL_EN - -/* DAC_CH1CTRL */ -#define DAC_CH1CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT -#define DAC_CH1CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK -#define DAC_CH1CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) -#define DAC_CH1CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) -#define DAC_CH1CTRL_PRSSEL_PRSCH0 DAC_CH_CTRL_PRSSEL_PRSCH0 -#define DAC_CH1CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 -#define DAC_CH1CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 -#define DAC_CH1CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 -#define DAC_CH1CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 -#define DAC_CH1CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 -#define DAC_CH1CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 -#define DAC_CH1CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 -#define DAC_CH1CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 -#define DAC_CH1CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 -#define DAC_CH1CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 -#define DAC_CH1CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 - -#define DAC_CH1CTRL_PRSEN DAC_CH_CTRL_PRSEN -#define DAC_CH1CTRL_REFREN DAC_CH_CTRL_REFREN -#define DAC_CH1CTRL_EN DAC_CH_CTRL_EN - -/* DAC_IEN */ -#define DAC_IEN_CH1UF (5 << 0) -#define DAC_IEN_CH0UF (4 << 0) -#define DAC_IEN_CH1 (1 << 1) -#define DAC_IEN_CH0 (1 << 0) - -/* DAC_IF */ -#define DAC_IF_CH1UF (5 << 0) -#define DAC_IF_CH0UF (4 << 0) -#define DAC_IF_CH1 (1 << 1) -#define DAC_IF_CH0 (1 << 0) - -/* DAC_IFS */ -#define DAC_IFS_CH1UF (5 << 0) -#define DAC_IFS_CH0UF (4 << 0) -#define DAC_IFS_CH1 (1 << 1) -#define DAC_IFS_CH0 (1 << 0) - -/* DAC_IFC */ -#define DAC_IFC_CH1UF (5 << 0) -#define DAC_IFC_CH0UF (4 << 0) -#define DAC_IFC_CH1 (1 << 1) -#define DAC_IFC_CH0 (1 << 0) - -/* DAC_CAL */ -#define DAC_CAL_GAIN_SHIFT (16) -#define DAC_CAL_GAIN_MASK (0x7F << DAC_CAL_GAIN_SHIFT) -#define DAC_CAL_GAIN(v) \ - (((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK) - -#define DAC_CAL_CH1OFFSET_SHIFT (8) -#define DAC_CAL_CH1OFFSET_MASK (0x3F << DAC_CAL_CH1OFFSET_SHIFT) -#define DAC_CAL_CH1OFFSET(v) \ - (((v) << DAC_CAL_CH1OFFSET_SHIFT) & DAC_CAL_CH1OFFSET_MASK) - -#define DAC_CAL_CH0OFFSET_SHIFT (0) -#define DAC_CAL_CH0OFFSET_MASK (0x3F << DAC_CAL_CH0OFFSET_SHIFT) -#define DAC_CAL_CH0OFFSET(v) \ - (((v) << DAC_CAL_CH0OFFSET_SHIFT) & DAC_CAL_CH0OFFSET_MASK) - -/* DAC_BIASPROG */ -#define DAC_BIASPROG_OPA2HALFBIAS (1 << 14) - -#define DAC_BIASPROG_OPA2BIASPROG_SHIFT (8) -#define DAC_BIASPROG_OPA2BIASPROG_MASK (0xF << DAC_BIASPROG_OPA2BIASPROG_SHIFT) -#define DAC_BIASPROG_OPA2BIASPROG(v) \ - ((((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \ - DAC_BIASPROG_OPA2BIASPROG_MASK) - -#define DAC_BIASPROG_HALFBIAS (1 << 6) - -#define DAC_BIASPROG_BIASPROG_SHIFT (0) -#define DAC_BIASPROG_BIASPROG_MASK (0xF << DAC_BIASPROG_BIASPROG_SHIFT) -#define DAC_BIASPROG_BIASPROG(v) \ - ((((v) << DAC_BIASPROG_BIASPROG_SHIFT)) & DAC_BIASPROG_BIASPROG_MASK) - -/* DAC_OPACTRL */ -#define DAC_OPACTRL_OPA2SHORT (1 << 24) -#define DAC_OPACTRL_OPA1SHORT (1 << 23) -#define DAC_OPACTRL_OPA0SHORT (1 << 22) - -#define DAC_OPACTRL_OPA2LPFDIS_SHIFT (16) -#define DAC_OPACTRL_OPA2LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA2LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA2LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA2LPFDIS_SHIFT) & DAC_OPACTRL_OPA2LPFDIS_MASK) -#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0b01 -#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0b10 - -#define DAC_OPACTRL_OPA1LPFDIS_SHIFT (14) -#define DAC_OPACTRL_OPA1LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA1LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA1LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA1LPFDIS_SHIFT) & DAC_OPACTRL_OPA1LPFDIS_MASK) -#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0b01 -#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0b10 - -#define DAC_OPACTRL_OPA0LPFDIS_SHIFT (14) -#define DAC_OPACTRL_OPA0LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA0LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA0LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA0LPFDIS_SHIFT) & DAC_OPACTRL_OPA0LPFDIS_MASK) -#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0b01 -#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0b10 - -#define DAC_OPACTRL_OPA2HCMDIS (1 << 8) -#define DAC_OPACTRL_OPA1HCMDIS (1 << 7) -#define DAC_OPACTRL_OPA0HCMDIS (1 << 6) - -#define DAC_OPACTRL_OPA2EN (1 << 2) -#define DAC_OPACTRL_OPA1EN (1 << 1) -#define DAC_OPACTRL_OPA0EN (1 << 0) - -/* DAC_OPA0MUX */ -#define DAC_OPA0MUX_RESSEL_SHIFT (28) -#define DAC_OPA0MUX_RESSEL_MASK (0x7 << DAC_OPA0MUX_RESSEL_SHIFT) -#define DAC_OPA0MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK) -#define DAC_OPA0MUX_RESSEL_RESSEL_RESx(x) DAC_OPA0MUX_RESSEL_RESSEL(x) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES0 DAC_OPA0MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES1 DAC_OPA0MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES2 DAC_OPA0MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES3 DAC_OPA0MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES4 DAC_OPA0MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES5 DAC_OPA0MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES6 DAC_OPA0MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES7 DAC_OPA0MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA0MUX_NEXTOUT (1 << 26) - -#define DAC_OPA0MUX_OUTMODE_SHIFT (22) -#define DAC_OPA0MUX_OUTMODE_MASK (0x3 << DAC_OPA0MUX_OUTMODE_SHIFT) -#define DAC_OPA0MUX_OUTMODE(v) \ - (((v) << DAC_OPA0MUX_OUTMODE_SHIFT) & DAC_OPA0MUX_OUTMODE_MASK) -#define DAC_OPA0MUX_OUTMODE_DISABLE 0 -#define DAC_OPA0MUX_OUTMODE_MAIN 1 -#define DAC_OPA0MUX_OUTMODE_ALT 2 -#define DAC_OPA0MUX_OUTMODE_ALL 3 - -#define DAC_OPA0MUX_OUTPEN_SHIFT (18) -#define DAC_OPA0MUX_OUTPEN_MASK (0x1F << DAC_OPA0MUX_OUTPEN_SHIFT) -#define DAC_OPA0MUX_OUTPEN(v) \ - (((v) << DAC_OPA0MUX_OUTPEN_SHIFT) & DAC_OPA0MUX_OUTPEN_MASK) -#define DAC_OPA0MUX_OUTPEN_OUT0 DAC_OPA0MUX_OUTPEN(1 << 0) -#define DAC_OPA0MUX_OUTPEN_OUT1 DAC_OPA0MUX_OUTPEN(1 << 1) -#define DAC_OPA0MUX_OUTPEN_OUT2 DAC_OPA0MUX_OUTPEN(1 << 2) -#define DAC_OPA0MUX_OUTPEN_OUT3 DAC_OPA0MUX_OUTPEN(1 << 3) -#define DAC_OPA0MUX_OUTPEN_OUT4 DAC_OPA0MUX_OUTPEN(1 << 4) - -#define DAC_OPA0MUX_NPEN (1 << 13) -#define DAC_OPA0MUX_PPEN (1 << 12) - -#define DAC_OPA0MUX_RESINMUX_SHIFT (8) -#define DAC_OPA0MUX_RESINMUX_MASK (0x7 << DAC_OPA0MUX_RESINMUX_SHIFT) -#define DAC_OPA0MUX_RESINMUX(v) \ - (((v) << DAC_OPA0MUX_RESINMUX_SHIFT) & DAC_OPA0MUX_RESINMUX_MASK) -#define DAC_OPA0MUX_RESINMUX_DISABLE 0 -#define DAC_OPA0MUX_RESINMUX_OPA0INP 1 -#define DAC_OPA0MUX_RESINMUX_NEGPAD 2 -#define DAC_OPA0MUX_RESINMUX_POSPAD 3 -#define DAC_OPA0MUX_RESINMUX_VSS 4 - -#define DAC_OPA0MUX_NEGSEL_SHIFT (4) -#define DAC_OPA0MUX_NEGSEL_MASK (0x3 << DAC_OPA0MUX_NEGSEL_SHIFT) -#define DAC_OPA0MUX_NEGSEL(v) \ - (((v) << DAC_OPA0MUX_NEGSEL_SHIFT) & DAC_OPA0MUX_NEGSEL_MASK) -#define DAC_OPA0MUX_NEGSEL_DISABLE 0 -#define DAC_OPA0MUX_NEGSEL_UG 1 -#define DAC_OPA0MUX_NEGSEL_OPATAP 2 -#define DAC_OPA0MUX_NEGSEL_NEGPAD 3 - -#define DAC_OPA0MUX_POSSEL_SHIFT (0) -#define DAC_OPA0MUX_POSSEL_MASK (0x7 << DAC_OPA0MUX_POSSEL_SHIFT) -#define DAC_OPA0MUX_POSSEL(v) \ - (((v) << DAC_OPA0MUX_POSSEL_SHIFT) & DAC_OPA0MUX_POSSEL_MASK) -#define DAC_OPA0MUX_POSSEL_DISABLE 0 -#define DAC_OPA0MUX_POSSEL_DAC 1 -#define DAC_OPA0MUX_POSSEL_POSPAD 2 -#define DAC_OPA0MUX_POSSEL_OPA0INP 3 -#define DAC_OPA0MUX_POSSEL_OPATAP 4 - -/* DAC_OPA1MUX */ -#define DAC_OPA1MUX_RESSEL_SHIFT (28) -#define DAC_OPA1MUX_RESSEL_MASK (0x7 << DAC_OPA1MUX_RESSEL_SHIFT) -#define DAC_OPA1MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK) -#define DAC_OPA1MUX_RESSEL_RESSEL_RESx(x) DAC_OPA1MUX_RESSEL_RESSEL(x) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES0 DAC_OPA1MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES1 DAC_OPA1MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES2 DAC_OPA1MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES3 DAC_OPA1MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES4 DAC_OPA1MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES5 DAC_OPA1MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES6 DAC_OPA1MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES7 DAC_OPA1MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA1MUX_NEXTOUT (1 << 26) - -#define DAC_OPA1MUX_OUTMODE_SHIFT (22) -#define DAC_OPA1MUX_OUTMODE_MASK (0x3 << DAC_OPA1MUX_OUTMODE_SHIFT) -#define DAC_OPA1MUX_OUTMODE(v) \ - (((v) << DAC_OPA1MUX_OUTMODE_SHIFT) & DAC_OPA1MUX_OUTMODE_MASK) -#define DAC_OPA1MUX_OUTMODE_DISABLE 0 -#define DAC_OPA1MUX_OUTMODE_MAIN 1 -#define DAC_OPA1MUX_OUTMODE_ALT 2 -#define DAC_OPA1MUX_OUTMODE_ALL 3 - -#define DAC_OPA1MUX_OUTPEN_SHIFT (18) -#define DAC_OPA1MUX_OUTPEN_MASK (0x1F << DAC_OPA1MUX_OUTPEN_SHIFT) -#define DAC_OPA1MUX_OUTPEN(v) \ - (((v) << DAC_OPA1MUX_OUTPEN_SHIFT) & DAC_OPA1MUX_OUTPEN_MASK) -#define DAC_OPA1MUX_OUTPEN_OUT0 DAC_OPA1MUX_OUTPEN(1 << 0) -#define DAC_OPA1MUX_OUTPEN_OUT1 DAC_OPA1MUX_OUTPEN(1 << 1) -#define DAC_OPA1MUX_OUTPEN_OUT2 DAC_OPA1MUX_OUTPEN(1 << 2) -#define DAC_OPA1MUX_OUTPEN_OUT3 DAC_OPA1MUX_OUTPEN(1 << 3) -#define DAC_OPA1MUX_OUTPEN_OUT4 DAC_OPA1MUX_OUTPEN(1 << 4) - -#define DAC_OPA1MUX_NPEN (1 << 13) -#define DAC_OPA1MUX_PPEN (1 << 12) - -#define DAC_OPA1MUX_RESINMUX_SHIFT (8) -#define DAC_OPA1MUX_RESINMUX_MASK (0x7 << DAC_OPA1MUX_RESINMUX_SHIFT) -#define DAC_OPA1MUX_RESINMUX(v) \ - (((v) << DAC_OPA1MUX_RESINMUX_SHIFT) & DAC_OPA1MUX_RESINMUX_MASK) -#define DAC_OPA1MUX_RESINMUX_DISABLE 0 -#define DAC_OPA1MUX_RESINMUX_OPA0INP 1 -#define DAC_OPA1MUX_RESINMUX_NEGPAD 2 -#define DAC_OPA1MUX_RESINMUX_POSPAD 3 -#define DAC_OPA1MUX_RESINMUX_VSS 4 - -#define DAC_OPA1MUX_NEGSEL_SHIFT (4) -#define DAC_OPA1MUX_NEGSEL_MASK (0x3 << DAC_OPA1MUX_NEGSEL_SHIFT) -#define DAC_OPA1MUX_NEGSEL(v) \ - (((v) << DAC_OPA1MUX_NEGSEL_SHIFT) & DAC_OPA1MUX_NEGSEL_MASK) -#define DAC_OPA1MUX_NEGSEL_DISABLE 0 -#define DAC_OPA1MUX_NEGSEL_UG 1 -#define DAC_OPA1MUX_NEGSEL_OPATAP 2 -#define DAC_OPA1MUX_NEGSEL_NEGPAD 3 - -#define DAC_OPA1MUX_POSSEL_SHIFT (0) -#define DAC_OPA1MUX_POSSEL_MASK (0x7 << DAC_OPA1MUX_POSSEL_SHIFT) -#define DAC_OPA1MUX_POSSEL(v) \ - (((v) << DAC_OPA1MUX_POSSEL_SHIFT) & DAC_OPA1MUX_POSSEL_MASK) -#define DAC_OPA1MUX_POSSEL_DISABLE 0 -#define DAC_OPA1MUX_POSSEL_DAC 1 -#define DAC_OPA1MUX_POSSEL_POSPAD 2 -#define DAC_OPA1MUX_POSSEL_OPA0INP 3 -#define DAC_OPA1MUX_POSSEL_OPATAP 4 - - -/* DAC_OPA2MUX */ -#define DAC_OPA2MUX_RESSEL_SHIFT (28) -#define DAC_OPA2MUX_RESSEL_MASK (0x7 << DAC_OPA2MUX_RESSEL_SHIFT) -#define DAC_OPA2MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK) -#define DAC_OPA2MUX_RESSEL_RESSEL_RESx(x) DAC_OPA2MUX_RESSEL_RESSEL(x) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES0 DAC_OPA2MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES1 DAC_OPA2MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES2 DAC_OPA2MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES3 DAC_OPA2MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES4 DAC_OPA2MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES5 DAC_OPA2MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES6 DAC_OPA2MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES7 DAC_OPA2MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA2MUX_NEXTOUT (1 << 26) - -#define DAC_OPA2MUX_OUTMODE (1 << 22) - -#define DAC_OPA2MUX_OUTPEN_SHIFT (14) -#define DAC_OPA2MUX_OUTPEN_MASK (0x3 << DAC_OPA2MUX_OUTPEN_SHIFT) -#define DAC_OPA2MUX_OUTPEN(v) \ - (((v) << DAC_OPA2MUX_OUTPEN_SHIFT) & DAC_OPA2MUX_OUTPEN_MASK) -#define DAC_OPA2MUX_OUTPEN_OUT0 0 -#define DAC_OPA2MUX_OUTPEN_OUT1 1 - -#define DAC_OPA2MUX_NPEN (1 << 13) -#define DAC_OPA2MUX_PPEN (1 << 12) - -#define DAC_OPA2MUX_RESINMUX_SHIFT (8) -#define DAC_OPA2MUX_RESINMUX_MASK (0x7 << DAC_OPA2MUX_RESINMUX_SHIFT) -#define DAC_OPA2MUX_RESINMUX(v) \ - (((v) << DAC_OPA2MUX_RESINMUX_SHIFT) & DAC_OPA2MUX_RESINMUX_MASK) -#define DAC_OPA2MUX_RESINMUX_DISABLE 0 -#define DAC_OPA2MUX_RESINMUX_OPA1INP 1 -#define DAC_OPA2MUX_RESINMUX_NEGPAD 2 -#define DAC_OPA2MUX_RESINMUX_POSPAD 3 -#define DAC_OPA2MUX_RESINMUX_VSS 4 - -#define DAC_OPA2MUX_NEGSEL_SHIFT (4) -#define DAC_OPA2MUX_NEGSEL_MASK (0x3 << DAC_OPA2MUX_NEGSEL_SHIFT) -#define DAC_OPA2MUX_NEGSEL(v) \ - (((v) << DAC_OPA2MUX_NEGSEL_SHIFT) & DAC_OPA2MUX_NEGSEL_MASK) -#define DAC_OPA2MUX_NEGSEL_DISABLE 0 -#define DAC_OPA2MUX_NEGSEL_UG 1 -#define DAC_OPA2MUX_NEGSEL_OPATAP 2 -#define DAC_OPA2MUX_NEGSEL_NEGPAD 3 - -#define DAC_OPA2MUX_POSSEL_SHIFT (0) -#define DAC_OPA2MUX_POSSEL_MASK (0x7 << DAC_OPA2MUX_POSSEL_SHIFT) -#define DAC_OPA2MUX_POSSEL(v) \ - (((v) << DAC_OPA2MUX_POSSEL_SHIFT) & DAC_OPA2MUX_POSSEL_MASK) -#define DAC_OPA2MUX_POSSEL_DISABLE 0 -#define DAC_OPA2MUX_POSSEL_DAC 1 -#define DAC_OPA2MUX_POSSEL_POSPAD 2 -#define DAC_OPA2MUX_POSSEL_OPA1INP 3 -#define DAC_OPA2MUX_POSSEL_OPATAP 4 - -/* DAC0 */ -#define DAC0 DAC0_BASE -#define DAC0_CTRL DAC_CTRL(DAC0) -#define DAC0_STATUS DAC_STATUS(DAC0) -#define DAC0_CH0CTRL DAC_CH0CTRL(DAC0) -#define DAC0_CH1CTRL DAC_CH1CTRL(DAC0) -#define DAC0_IEN DAC_IEN(DAC0) -#define DAC0_IF DAC_IF(DAC0) -#define DAC0_IFS DAC_IFS(DAC0) -#define DAC0_IFC DAC_IFC(DAC0) -#define DAC0_CH0DATA DAC_CH0DATA(DAC0) -#define DAC0_CH1DATA DAC_CH1DATA(DAC0) -#define DAC0_COMBDATA DAC_COMBDATA(DAC0) -#define DAC0_CAL DAC_CAL(DAC0) -#define DAC0_BIASPROG DAC_BIASPROG(DAC0) -#define DAC0_OPACTRL DAC_OPACTRL(DAC0) -#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) -#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) -#define DAC0_OPA1MUX DAC_OPA1MUX(DAC0) -#define DAC0_OPA2MUX DAC_OPA2MUX(DAC0) - -/** @defgroup dac_ch DAC Channel Number -@ingroup dac_defines - -@{*/ -enum dac_ch { - DAC_CH0 = 0, - DAC_CH1 -}; -/**@}*/ - -BEGIN_DECLS - -void dac_set_refresh_cycle(uint32_t dac_base, uint32_t refrsel); -void dac_set_clock_prescaler(uint32_t dac_base, uint32_t presc); -void dac_set_reference(uint32_t dac_base, uint32_t refsel); -void dac_set_out_mode(uint32_t dac_base, uint32_t outmode); -void dac_set_conversion_mode(uint32_t dac_base, uint32_t convmode); -void dac_enable_sine(uint32_t dac_base); -void dac_disable_sine(uint32_t dac_base); - -void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan, - enum prs_ch prs_chan); -void dac_enable_prs_trigger(uint32_t dac_base, enum dac_ch ch); -void dac_disable_prs_trigger(uint32_t dac_base, enum dac_ch ch); -void dac_enable_auto_refresh(uint32_t dac_base, enum dac_ch ch); -void dac_disable_auto_refresh(uint32_t dac_base, enum dac_ch ch); - -void dac_enable_channel(uint32_t dac_base, enum dac_ch ch); -void dac_disable_channel(uint32_t dac_base, enum dac_ch ch); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/dma_common.h b/libopencm3/include/libopencm3/efm32/common/dma_common.h deleted file mode 100644 index d274979..0000000 --- a/libopencm3/include/libopencm3/efm32/common/dma_common.h +++ /dev/null @@ -1,914 +0,0 @@ -/** @addtogroup dma_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -/* - * As per the datasheet, it is an PL230 (licenced from ARM) - * note: but only implement 12 channel (PL230 can have upto 32 channels) - * - * in-future: we can move this to a common peripherial directory - * that is idependent of core and as well as uC. - * something like device tree in Linux kernel - * - * note: DMA_STATUS contain the number of PL230 channel are implemented - */ - -#define DMA DMA_BASE - -#define DMA_STATUS MMIO32(DMA_BASE + 0x000) -#define DMA_CONFIG MMIO32(DMA_BASE + 0x004) -#define DMA_CTRLBASE MMIO32(DMA_BASE + 0x008) -#define DMA_ALTCTRLBASE MMIO32(DMA_BASE + 0x00C) - -#define DMA_CHWAITSTATUS MMIO32(DMA_BASE + 0x010) -#define DMA_CHSWREQ MMIO32(DMA_BASE + 0x014) -#define DMA_CHUSEBURSTS MMIO32(DMA_BASE + 0x018) -#define DMA_CHUSEBURSTC MMIO32(DMA_BASE + 0x01C) -#define DMA_CHREQMASKS MMIO32(DMA_BASE + 0x020) -#define DMA_CHREQMASKC MMIO32(DMA_BASE + 0x024) -#define DMA_CHENS MMIO32(DMA_BASE + 0x028) -#define DMA_CHENC MMIO32(DMA_BASE + 0x02C) -#define DMA_CHALTS MMIO32(DMA_BASE + 0x030) -#define DMA_CHALTC MMIO32(DMA_BASE + 0x034) -#define DMA_CHPRIS MMIO32(DMA_BASE + 0x038) -#define DMA_CHPRIC MMIO32(DMA_BASE + 0x03C) -#define DMA_ERRORC MMIO32(DMA_BASE + 0x04C) -#define DMA_CHREQSTATUS MMIO32(DMA_BASE + 0xE10) -#define DMA_CHSREQSTATUS MMIO32(DMA_BASE + 0xE18) -#define DMA_IF MMIO32(DMA_BASE + 0x1000) -#define DMA_IFS MMIO32(DMA_BASE + 0x1004) -#define DMA_IFC MMIO32(DMA_BASE + 0x1008) -#define DMA_IEN MMIO32(DMA_BASE + 0x100C) -#define DMA_CTRL MMIO32(DMA_BASE + 0x1010) -#define DMA_RDS MMIO32(DMA_BASE + 0x1014) - -#define DMA_LOOPx(i) MMIO32(DMA_BASE + 0x1020 + ((i) * 0x4)) -#define DMA_LOOP0 DMA_LOOPx(0) -#define DMA_LOOP1 DMA_LOOPx(1) - -#define DMA_RECTx(i) MMIO32(DMA_BASE + 0x1060 + ((i) * 0x4)) -#define DMA_RECT0 DMA_RECT(0) - -#define DMA_CHx_CTRL(i) MMIO32(DMA_BASE + 0x1100 + ((i) * 0x4)) -#define DMA_CH0_CTRL DMA_CHx_CTRL(0) -#define DMA_CH1_CTRL DMA_CHx_CTRL(1) -#define DMA_CH2_CTRL DMA_CHx_CTRL(2) -#define DMA_CH3_CTRL DMA_CHx_CTRL(3) -#define DMA_CH4_CTRL DMA_CHx_CTRL(4) -#define DMA_CH5_CTRL DMA_CHx_CTRL(5) -#define DMA_CH6_CTRL DMA_CHx_CTRL(6) -#define DMA_CH7_CTRL DMA_CHx_CTRL(7) -#define DMA_CH8_CTRL DMA_CHx_CTRL(8) -#define DMA_CH9_CTRL DMA_CHx_CTRL(9) -#define DMA_CH10_CTRL DMA_CHx_CTRL(10) -#define DMA_CH11_CTRL DMA_CHx_CTRL(11) - -/* DMA_STATUS */ -#define DMA_STATUS_CHNUM_SHIFT (16) -#define DMA_STATUS_CHNUM_MASK (0x1F << DMA_STATUS_CHNUM_SHIFT) - -#define DMA_STATUS_STATE_SHIFT (4) -#define DMA_STATUS_STATE_MASK (0xF << DMA_STATUS_STATE_SHIFT) -#define DMA_STATUS_STATE(v) \ - (((v) << DMA_STATUS_STATE_SHIFT) & DMA_STATUS_STATE_MASK) -#define DMA_STATUS_STATE_IDLE 0 -#define DMA_STATUS_STATE_RDCHCTRLDATA 1 -#define DMA_STATUS_STATE_RDSRCENDPTR 2 -#define DMA_STATUS_STATE_RDDSTENDPTR 3 -#define DMA_STATUS_STATE_RDSRCDATA 4 -#define DMA_STATUS_STATE_WRDSTDATA 5 -#define DMA_STATUS_STATE_WAITREQCLR 6 -#define DMA_STATUS_STATE_WRCHCTRLDATA 7 -#define DMA_STATUS_STATE_STALLED 8 -#define DMA_STATUS_STATE_DONE 9 -#define DMA_STATUS_STATE_PERSCATTRANS 10 - -#define DMA_STATUS_EN (1 << 0) - -/* DMA_CONFIG */ -#define DMA_CONFIG_CHPROT (1 << 5) -#define DMA_CONFIG_EN (1 << 0) - -/* DMA_CHWAITSTATUS */ -#define DMA_CHWAITSTATUS_CHxWAITSTATUS(i) (1 << (i)) -#define DMA_CHWAITSTATUS_CH11WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(11) -#define DMA_CHWAITSTATUS_CH10WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(10) -#define DMA_CHWAITSTATUS_CH9WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(9) -#define DMA_CHWAITSTATUS_CH8WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(8) -#define DMA_CHWAITSTATUS_CH7WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(7) -#define DMA_CHWAITSTATUS_CH6WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(6) -#define DMA_CHWAITSTATUS_CH5WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(5) -#define DMA_CHWAITSTATUS_CH4WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(4) -#define DMA_CHWAITSTATUS_CH3WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(3) -#define DMA_CHWAITSTATUS_CH2WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(2) -#define DMA_CHWAITSTATUS_CH1WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(1) -#define DMA_CHWAITSTATUS_CH0WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(0) - -/* DMA_CHSWREQ */ -#define DMA_CHSWREQ_CHxSWREQ(i) (1 << (i)) -#define DMA_CHSWREQ_CH11SWREQ DMA_CHSWREQ_CHxSWREQ(11) -#define DMA_CHSWREQ_CH10SWREQ DMA_CHSWREQ_CHxSWREQ(10) -#define DMA_CHSWREQ_CH9SWREQ DMA_CHSWREQ_CHxSWREQ(9) -#define DMA_CHSWREQ_CH8SWREQ DMA_CHSWREQ_CHxSWREQ(8) -#define DMA_CHSWREQ_CH7SWREQ DMA_CHSWREQ_CHxSWREQ(7) -#define DMA_CHSWREQ_CH6SWREQ DMA_CHSWREQ_CHxSWREQ(6) -#define DMA_CHSWREQ_CH5SWREQ DMA_CHSWREQ_CHxSWREQ(5) -#define DMA_CHSWREQ_CH4SWREQ DMA_CHSWREQ_CHxSWREQ(4) -#define DMA_CHSWREQ_CH3SWREQ DMA_CHSWREQ_CHxSWREQ(3) -#define DMA_CHSWREQ_CH2SWREQ DMA_CHSWREQ_CHxSWREQ(2) -#define DMA_CHSWREQ_CH1SWREQ DMA_CHSWREQ_CHxSWREQ(1) -#define DMA_CHSWREQ_CH0SWREQ DMA_CHSWREQ_CHxSWREQ(0) - -/* DMA_CHUSEBURSTS */ -#define DMA_CHUSEBURSTS_CHxSUSEBURSTS(i) (1 << (i)) -#define DMA_CHUSEBURSTS_CH11SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(11) -#define DMA_CHUSEBURSTS_CH10SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(10) -#define DMA_CHUSEBURSTS_CH9SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(9) -#define DMA_CHUSEBURSTS_CH8SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(8) -#define DMA_CHUSEBURSTS_CH7SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(7) -#define DMA_CHUSEBURSTS_CH6SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(6) -#define DMA_CHUSEBURSTS_CH5SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(5) -#define DMA_CHUSEBURSTS_CH4SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(4) -#define DMA_CHUSEBURSTS_CH3SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(3) -#define DMA_CHUSEBURSTS_CH2SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(2) -#define DMA_CHUSEBURSTS_CH1SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(1) -#define DMA_CHUSEBURSTS_CH0SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(0) - -/* DMA_CHUSEBURSTC */ -#define DMA_CHUSEBURSTC_CHxSUSEBURSTC(i) (1 << (i)) -#define DMA_CHUSEBURSTC_CH11SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(11) -#define DMA_CHUSEBURSTC_CH10SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(10) -#define DMA_CHUSEBURSTC_CH9SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(9) -#define DMA_CHUSEBURSTC_CH8SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(8) -#define DMA_CHUSEBURSTC_CH7SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(7) -#define DMA_CHUSEBURSTC_CH6SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(6) -#define DMA_CHUSEBURSTC_CH5SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(5) -#define DMA_CHUSEBURSTC_CH4SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(4) -#define DMA_CHUSEBURSTC_CH3SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(3) -#define DMA_CHUSEBURSTC_CH2SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(2) -#define DMA_CHUSEBURSTC_CH1SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(1) -#define DMA_CHUSEBURSTC_CH0SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(0) - -/* DMA_CHREQMASKS */ -#define DMA_CHREQMASKS_CHxSREQMASKS(i) (1 << (i)) -#define DMA_CHREQMASKS_CH11SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(11) -#define DMA_CHREQMASKS_CH10SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(10) -#define DMA_CHREQMASKS_CH9SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(9) -#define DMA_CHREQMASKS_CH8SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(8) -#define DMA_CHREQMASKS_CH7SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(7) -#define DMA_CHREQMASKS_CH6SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(6) -#define DMA_CHREQMASKS_CH5SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(5) -#define DMA_CHREQMASKS_CH4SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(4) -#define DMA_CHREQMASKS_CH3SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(3) -#define DMA_CHREQMASKS_CH2SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(2) -#define DMA_CHREQMASKS_CH1SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(1) -#define DMA_CHREQMASKS_CH0SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(0) - -/* DMA_CHREQMASKC */ -#define DMA_CHREQMASKC_CHxSREQMASKC(i) (1 << (i)) -#define DMA_CHREQMASKC_CH11SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(11) -#define DMA_CHREQMASKC_CH10SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(10) -#define DMA_CHREQMASKC_CH9SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(9) -#define DMA_CHREQMASKC_CH8SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(8) -#define DMA_CHREQMASKC_CH7SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(7) -#define DMA_CHREQMASKC_CH6SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(6) -#define DMA_CHREQMASKC_CH5SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(5) -#define DMA_CHREQMASKC_CH4SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(4) -#define DMA_CHREQMASKC_CH3SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(3) -#define DMA_CHREQMASKC_CH2SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(2) -#define DMA_CHREQMASKC_CH1SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(1) -#define DMA_CHREQMASKC_CH0SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(0) - -/* DMA_CHENS */ -#define DMA_CHENS_CHxSENS(i) (1 << (i)) -#define DMA_CHENS_CH11SENS DMA_CHENS_CHxSENS(11) -#define DMA_CHENS_CH10SENS DMA_CHENS_CHxSENS(10) -#define DMA_CHENS_CH9SENS DMA_CHENS_CHxSENS(9) -#define DMA_CHENS_CH8SENS DMA_CHENS_CHxSENS(8) -#define DMA_CHENS_CH7SENS DMA_CHENS_CHxSENS(7) -#define DMA_CHENS_CH6SENS DMA_CHENS_CHxSENS(6) -#define DMA_CHENS_CH5SENS DMA_CHENS_CHxSENS(5) -#define DMA_CHENS_CH4SENS DMA_CHENS_CHxSENS(4) -#define DMA_CHENS_CH3SENS DMA_CHENS_CHxSENS(3) -#define DMA_CHENS_CH2SENS DMA_CHENS_CHxSENS(2) -#define DMA_CHENS_CH1SENS DMA_CHENS_CHxSENS(1) -#define DMA_CHENS_CH0SENS DMA_CHENS_CHxSENS(0) - -/* DMA_CHENC */ -#define DMA_CHENC_CHxSENC(i) (1 << (i)) -#define DMA_CHENC_CH11SENC DMA_CHENC_CHxSENC(11) -#define DMA_CHENC_CH10SENC DMA_CHENC_CHxSENC(10) -#define DMA_CHENC_CH9SENC DMA_CHENC_CHxSENC(9) -#define DMA_CHENC_CH8SENC DMA_CHENC_CHxSENC(8) -#define DMA_CHENC_CH7SENC DMA_CHENC_CHxSENC(7) -#define DMA_CHENC_CH6SENC DMA_CHENC_CHxSENC(6) -#define DMA_CHENC_CH5SENC DMA_CHENC_CHxSENC(5) -#define DMA_CHENC_CH4SENC DMA_CHENC_CHxSENC(4) -#define DMA_CHENC_CH3SENC DMA_CHENC_CHxSENC(3) -#define DMA_CHENC_CH2SENC DMA_CHENC_CHxSENC(2) -#define DMA_CHENC_CH1SENC DMA_CHENC_CHxSENC(1) -#define DMA_CHENC_CH0SENC DMA_CHENC_CHxSENC(0) - -/* DMA_CHALTS */ -#define DMA_CHALTS_CHxSALTS(i) (1 << (i)) -#define DMA_CHALTS_CH11SALTS DMA_CHALTS_CHxSALTS(11) -#define DMA_CHALTS_CH10SALTS DMA_CHALTS_CHxSALTS(10) -#define DMA_CHALTS_CH9SALTS DMA_CHALTS_CHxSALTS(9) -#define DMA_CHALTS_CH8SALTS DMA_CHALTS_CHxSALTS(8) -#define DMA_CHALTS_CH7SALTS DMA_CHALTS_CHxSALTS(7) -#define DMA_CHALTS_CH6SALTS DMA_CHALTS_CHxSALTS(6) -#define DMA_CHALTS_CH5SALTS DMA_CHALTS_CHxSALTS(5) -#define DMA_CHALTS_CH4SALTS DMA_CHALTS_CHxSALTS(4) -#define DMA_CHALTS_CH3SALTS DMA_CHALTS_CHxSALTS(3) -#define DMA_CHALTS_CH2SALTS DMA_CHALTS_CHxSALTS(2) -#define DMA_CHALTS_CH1SALTS DMA_CHALTS_CHxSALTS(1) -#define DMA_CHALTS_CH0SALTS DMA_CHALTS_CHxSALTS(0) - -/* DMA_CHALTC */ -#define DMA_CHALTC_CHxSALTC(i) (1 << (i)) -#define DMA_CHALTC_CH11SALTC DMA_CHALTC_CHxSALTC(11) -#define DMA_CHALTC_CH10SALTC DMA_CHALTC_CHxSALTC(10) -#define DMA_CHALTC_CH9SALTC DMA_CHALTC_CHxSALTC(9) -#define DMA_CHALTC_CH8SALTC DMA_CHALTC_CHxSALTC(8) -#define DMA_CHALTC_CH7SALTC DMA_CHALTC_CHxSALTC(7) -#define DMA_CHALTC_CH6SALTC DMA_CHALTC_CHxSALTC(6) -#define DMA_CHALTC_CH5SALTC DMA_CHALTC_CHxSALTC(5) -#define DMA_CHALTC_CH4SALTC DMA_CHALTC_CHxSALTC(4) -#define DMA_CHALTC_CH3SALTC DMA_CHALTC_CHxSALTC(3) -#define DMA_CHALTC_CH2SALTC DMA_CHALTC_CHxSALTC(2) -#define DMA_CHALTC_CH1SALTC DMA_CHALTC_CHxSALTC(1) -#define DMA_CHALTC_CH0SALTC DMA_CHALTC_CHxSALTC(0) - -/* DMA_CHPRIS */ -#define DMA_CHPRIS_CHxSPRIC(i) (1 << (i)) -#define DMA_CHPRIS_CH11SPRIC DMA_CHPRIS_CHxSPRIC(11) -#define DMA_CHPRIS_CH10SPRIC DMA_CHPRIS_CHxSPRIC(10) -#define DMA_CHPRIS_CH9SPRIC DMA_CHPRIS_CHxSPRIC(9) -#define DMA_CHPRIS_CH8SPRIC DMA_CHPRIS_CHxSPRIC(8) -#define DMA_CHPRIS_CH7SPRIC DMA_CHPRIS_CHxSPRIC(7) -#define DMA_CHPRIS_CH6SPRIC DMA_CHPRIS_CHxSPRIC(6) -#define DMA_CHPRIS_CH5SPRIC DMA_CHPRIS_CHxSPRIC(5) -#define DMA_CHPRIS_CH4SPRIC DMA_CHPRIS_CHxSPRIC(4) -#define DMA_CHPRIS_CH3SPRIC DMA_CHPRIS_CHxSPRIC(3) -#define DMA_CHPRIS_CH2SPRIC DMA_CHPRIS_CHxSPRIC(2) -#define DMA_CHPRIS_CH1SPRIC DMA_CHPRIS_CHxSPRIC(1) -#define DMA_CHPRIS_CH0SPRIC DMA_CHPRIS_CHxSPRIC(0) - -/* DMA_CHPRIC */ -#define DMA_CHPRIC_CHxSPRIC(i) (1 << (i)) -#define DMA_CHPRIC_CH11SPRIC DMA_CHPRIC_CHxSPRIC(11) -#define DMA_CHPRIC_CH10SPRIC DMA_CHPRIC_CHxSPRIC(10) -#define DMA_CHPRIC_CH9SPRIC DMA_CHPRIC_CHxSPRIC(9) -#define DMA_CHPRIC_CH8SPRIC DMA_CHPRIC_CHxSPRIC(8) -#define DMA_CHPRIC_CH7SPRIC DMA_CHPRIC_CHxSPRIC(7) -#define DMA_CHPRIC_CH6SPRIC DMA_CHPRIC_CHxSPRIC(6) -#define DMA_CHPRIC_CH5SPRIC DMA_CHPRIC_CHxSPRIC(5) -#define DMA_CHPRIC_CH4SPRIC DMA_CHPRIC_CHxSPRIC(4) -#define DMA_CHPRIC_CH3SPRIC DMA_CHPRIC_CHxSPRIC(3) -#define DMA_CHPRIC_CH2SPRIC DMA_CHPRIC_CHxSPRIC(2) -#define DMA_CHPRIC_CH1SPRIC DMA_CHPRIC_CHxSPRIC(1) -#define DMA_CHPRIC_CH0SPRIC DMA_CHPRIC_CHxSPRIC(0) - -/* DMA_ERRORC */ -#define DMA_ERRORC_ERRORC (1 << 0) - -/* DMA_CHREQSTATUS */ -#define DMA_CHREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) -#define DMA_CHREQSTATUS_CH11SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(11) -#define DMA_CHREQSTATUS_CH10SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(10) -#define DMA_CHREQSTATUS_CH9SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(9) -#define DMA_CHREQSTATUS_CH8SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(8) -#define DMA_CHREQSTATUS_CH7SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(7) -#define DMA_CHREQSTATUS_CH6SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(6) -#define DMA_CHREQSTATUS_CH5SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(5) -#define DMA_CHREQSTATUS_CH4SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(4) -#define DMA_CHREQSTATUS_CH3SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(3) -#define DMA_CHREQSTATUS_CH2SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(2) -#define DMA_CHREQSTATUS_CH1SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(1) -#define DMA_CHREQSTATUS_CH0SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(0) - -/* DMA_CHSREQSTATUS */ -#define DMA_CHSREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) -#define DMA_CHSREQSTATUS_CH11SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(11) -#define DMA_CHSREQSTATUS_CH10SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(10) -#define DMA_CHSREQSTATUS_CH9SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(9) -#define DMA_CHSREQSTATUS_CH8SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(8) -#define DMA_CHSREQSTATUS_CH7SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(7) -#define DMA_CHSREQSTATUS_CH6SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(6) -#define DMA_CHSREQSTATUS_CH5SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(5) -#define DMA_CHSREQSTATUS_CH4SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(4) -#define DMA_CHSREQSTATUS_CH3SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(3) -#define DMA_CHSREQSTATUS_CH2SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(2) -#define DMA_CHSREQSTATUS_CH1SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(1) -#define DMA_CHSREQSTATUS_CH0SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(0) - -/* DMA_IF */ -#define DMA_IF_ERR (1UL << 31) -#define DMA_IF_CHxDONE(x) (1 << (x)) -#define DMA_IF_CH11DONE DMA_IF_CHxDONE(11) -#define DMA_IF_CH10DONE DMA_IF_CHxDONE(10) -#define DMA_IF_CH9DONE DMA_IF_CHxDONE(9) -#define DMA_IF_CH8DONE DMA_IF_CHxDONE(8) -#define DMA_IF_CH7DONE DMA_IF_CHxDONE(7) -#define DMA_IF_CH6DONE DMA_IF_CHxDONE(6) -#define DMA_IF_CH5DONE DMA_IF_CHxDONE(5) -#define DMA_IF_CH4DONE DMA_IF_CHxDONE(4) -#define DMA_IF_CH3DONE DMA_IF_CHxDONE(3) -#define DMA_IF_CH2DONE DMA_IF_CHxDONE(2) -#define DMA_IF_CH1DONE DMA_IF_CHxDONE(1) -#define DMA_IF_CH0DONE DMA_IF_CHxDONE(0) - - -/* DMA_IFS */ -#define DMA_IFS_ERR (1 << 31) -#define DMA_IFS_CHxDONE(x) (1 << (x)) -#define DMA_IFS_CH11DONE DMA_IFS_CHxDONE(11) -#define DMA_IFS_CH10DONE DMA_IFS_CHxDONE(10) -#define DMA_IFS_CH9DONE DMA_IFS_CHxDONE(9) -#define DMA_IFS_CH8DONE DMA_IFS_CHxDONE(8) -#define DMA_IFS_CH7DONE DMA_IFS_CHxDONE(7) -#define DMA_IFS_CH6DONE DMA_IFS_CHxDONE(6) -#define DMA_IFS_CH5DONE DMA_IFS_CHxDONE(5) -#define DMA_IFS_CH4DONE DMA_IFS_CHxDONE(4) -#define DMA_IFS_CH3DONE DMA_IFS_CHxDONE(3) -#define DMA_IFS_CH2DONE DMA_IFS_CHxDONE(2) -#define DMA_IFS_CH1DONE DMA_IFS_CHxDONE(1) -#define DMA_IFS_CH0DONE DMA_IFS_CHxDONE(0) - -/* DMA_IFC */ -#define DMA_IFC_ERR (1 << 31) -#define DMA_IFC_CHxDONE(x) (1 << (x)) -#define DMA_IFC_CH11DONE DMA_IFC_CHxDONE(11) -#define DMA_IFC_CH10DONE DMA_IFC_CHxDONE(10) -#define DMA_IFC_CH9DONE DMA_IFC_CHxDONE(9) -#define DMA_IFC_CH8DONE DMA_IFC_CHxDONE(8) -#define DMA_IFC_CH7DONE DMA_IFC_CHxDONE(7) -#define DMA_IFC_CH6DONE DMA_IFC_CHxDONE(6) -#define DMA_IFC_CH5DONE DMA_IFC_CHxDONE(5) -#define DMA_IFC_CH4DONE DMA_IFC_CHxDONE(4) -#define DMA_IFC_CH3DONE DMA_IFC_CHxDONE(3) -#define DMA_IFC_CH2DONE DMA_IFC_CHxDONE(2) -#define DMA_IFC_CH1DONE DMA_IFC_CHxDONE(1) -#define DMA_IFC_CH0DONE DMA_IFC_CHxDONE(0) - -/* DMA_IEN */ -#define DMA_IEN_ERR (1 << 31) -#define DMA_IEN_CHxDONE(x) (1 << (x)) -#define DMA_IEN_CH11DONE DMA_IEN_CHxDONE(11) -#define DMA_IEN_CH10DONE DMA_IEN_CHxDONE(10) -#define DMA_IEN_CH9DONE DMA_IEN_CHxDONE(9) -#define DMA_IEN_CH8DONE DMA_IEN_CHxDONE(8) -#define DMA_IEN_CH7DONE DMA_IEN_CHxDONE(7) -#define DMA_IEN_CH6DONE DMA_IEN_CHxDONE(6) -#define DMA_IEN_CH5DONE DMA_IEN_CHxDONE(5) -#define DMA_IEN_CH4DONE DMA_IEN_CHxDONE(4) -#define DMA_IEN_CH3DONE DMA_IEN_CHxDONE(3) -#define DMA_IEN_CH2DONE DMA_IEN_CHxDONE(2) -#define DMA_IEN_CH1DONE DMA_IEN_CHxDONE(1) -#define DMA_IEN_CH0DONE DMA_IEN_CHxDONE(0) - -/* DMA_CTRL */ -#define DMA_CTRL_PRDU (1 << 1) -#define DMA_CTRL_DESCRECT (1 << 0) - -/* DMA_RDS */ -#define DMA_RDS_RDSCHx(i) (1 << (i)) -#define DMA_RDS_RDSCH11 DMA_RDS_RDSCHx(11) -#define DMA_RDS_RDSCH10 DMA_RDS_RDSCHx(10) -#define DMA_RDS_RDSCH9 DMA_RDS_RDSCHx(9) -#define DMA_RDS_RDSCH8 DMA_RDS_RDSCHx(8) -#define DMA_RDS_RDSCH7 DMA_RDS_RDSCHx(7) -#define DMA_RDS_RDSCH6 DMA_RDS_RDSCHx(6) -#define DMA_RDS_RDSCH5 DMA_RDS_RDSCHx(5) -#define DMA_RDS_RDSCH4 DMA_RDS_RDSCHx(4) -#define DMA_RDS_RDSCH3 DMA_RDS_RDSCHx(3) -#define DMA_RDS_RDSCH2 DMA_RDS_RDSCHx(2) -#define DMA_RDS_RDSCH1 DMA_RDS_RDSCHx(1) -#define DMA_RDS_RDSCH0 DMA_RDS_RDSCHx(0) - -/* DMA_LOOP */ -#define DMA_LOOP_EN (1 << 16) -#define DMA_LOOP_WIDTH_SHIFT (0) -#define DMA_LOOP_WIDTH_MASK (0x3FF << DMA_LOOP_WIDTH_SHIFT) -#define DMA_LOOP_WIDTH(v) \ - (((v) << DMA_LOOP_WIDTH_SHIFT) & DMA_LOOP_WIDTH_MASK) - -/* DMA_RECT */ -#define DMA_RECT_DSTSTRIDE_SHIFT (21) -#define DMA_RECT_DSTSTRIDE_MASK (0x7FF << DMA_RECT_DSTSTRIDE_SHIFT) -#define DMA_RECT_DSTSTRIDE(v) \ - (((v) << DMA_RECT_DSTSTRIDE_SHIFT) & DMA_RECT_DSTSTRIDE_MASK) - -#define DMA_RECT_SRCSTRIDE_SHIFT (10) -#define DMA_RECT_SRCSTRIDE_MASK (0x7FF << DMA_RECT_SRCSTRIDE_SHIFT) -#define DMA_RECT_SRCSTRIDE(v) \ - (((v) << DMA_RECT_SRCSTRIDE_SHIFT) & DMA_RECT_SRCSTRIDE_MASK) - -#define DMA_RECT_HEIGHT_SHIFT (0) -#define DMA_RECT_HEIGHT_MASK (0x3FF << DMA_RECT_HEIGHT_SHIFT) -#define DMA_RECT_HEIGHT(v) \ - (((v) << DMA_RECT_HEIGHT_SHIFT) & DMA_RECT_HEIGHT_MASK) - -/* DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_SHIFT (16) -#define DMA_CH_CTRL_SOURCESEL_MASK (0x3F << DMA_CH_CTRL_SOURCESEL_SHIFT) -#define DMA_CH_CTRL_SOURCESEL(v) \ - (((v) << DMA_CH_CTRL_SOURCESEL_SHIFT) & DMA_CH_CTRL_SOURCESEL_MASK) -#define DMA_CH_CTRL_SOURCESEL_NONE 0b000000 -#define DMA_CH_CTRL_SOURCESEL_ADC0 0b001000 -#define DMA_CH_CTRL_SOURCESEL_DAC0 0b001010 -#define DMA_CH_CTRL_SOURCESEL_USART0 0b001100 -#define DMA_CH_CTRL_SOURCESEL_USART1 0b001101 -#define DMA_CH_CTRL_SOURCESEL_USART2 0b001110 -#define DMA_CH_CTRL_SOURCESEL_LEUART0 0b010000 -#define DMA_CH_CTRL_SOURCESEL_LEUART1 0b010001 -#define DMA_CH_CTRL_SOURCESEL_I2C0 0b010100 -#define DMA_CH_CTRL_SOURCESEL_I2C1 0b010101 -#define DMA_CH_CTRL_SOURCESEL_TIMER0 0b011000 -#define DMA_CH_CTRL_SOURCESEL_TIMER1 0b011001 -#define DMA_CH_CTRL_SOURCESEL_TIMER2 0b011010 -#define DMA_CH_CTRL_SOURCESEL_TIMER3 0b011011 -#define DMA_CH_CTRL_SOURCESEL_UART0 0b101100 -#define DMA_CH_CTRL_SOURCESEL_UART1 0b101101 -#define DMA_CH_CTRL_SOURCESEL_MSC 0b110000 -#define DMA_CH_CTRL_SOURCESEL_AES 0b110001 -#define DMA_CH_CTRL_SOURCESEL_LESENSE 0b110010 -#define DMA_CH_CTRL_SOURCESEL_EBI 0b110011 - -#define DMA_CH_CTRL_SIGSEL_SHIFT (0) -#define DMA_CH_CTRL_SIGSEL_MASK (0xF << DMA_CH_CTRL_SIGSEL_SHIFT) -#define DMA_CH_CTRL_SIGSEL(v) \ - (((v) << DMA_CH_CTRL_SIGSEL_SHIFT) & DMA_CH_CTRL_SIGSEL_MASK) - -#define DMA_CH_CTRL_SIGSEL_OFF 0 -#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0 -#define DMA_CH_CTRL_SIGSEL_ADC0SCAN 1 -#define DMA_CH_CTRL_SIGSEL_DAC0CH0 0 -#define DMA_CH_CTRL_SIGSEL_DAC0CH1 1 -#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_USART0TXBL 1 -#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_USART1TXBL 1 -#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 3 -#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 4 -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_USART2TXBL 1 -#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 3 -#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 4 -#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL 1 -#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL 1 -#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_I2C0TXBL 1 -#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_I2C1TXBL 1 -#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0 -#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 1 -#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 2 -#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 3 -#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0 -#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 1 -#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 2 -#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 3 -#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0 -#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 1 -#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 2 -#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 3 -#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0 -#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 1 -#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 2 -#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 3 -#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_UART0TXBL 1 -#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_UART1TXBL 1 -#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_MSCWDATA 0 -#define DMA_CH_CTRL_SIGSEL_AESDATAWR 0 -#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR 1 -#define DMA_CH_CTRL_SIGSEL_AESDATARD 2 -#define DMA_CH_CTRL_SIGSEL_AESKEYWR 3 -#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0 -#define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0 -#define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 1 -#define DMA_CH_CTRL_SIGSEL_EBIPXLFULL 2 -#define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 3 - -/* generic of above */ -#define DMA_CH_CTRL_SIGSEL_ADC_SINGLE 0 -#define DMA_CH_CTRL_SIGSEL_ADC_SCAN 1 -#define DMA_CH_CTRL_SIGSEL_DAC_CHx(x) DMA_CH_CTRL_SIGSEL(x) -#define DMA_CH_CTRL_SIGSEL_DAC_CH0 0 -#define DMA_CH_CTRL_SIGSEL_DAC_CH1 1 -#define DMA_CH_CTRL_SIGSEL_USART_RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_USART_TXBL 1 -#define DMA_CH_CTRL_SIGSEL_USART_TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_USART_RXDATAVRIGHT 3 -#define DMA_CH_CTRL_SIGSEL_USART_TXBLRIGHT 4 -#define DMA_CH_CTRL_SIGSEL_LEUART_RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_LEUART_TXBL 1 -#define DMA_CH_CTRL_SIGSEL_LEUART_TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_I2C_TXBL 1 -#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_I2C_TXBL 1 -#define DMA_CH_CTRL_SIGSEL_TIMER_UFOF 0 -#define DMA_CH_CTRL_SIGSEL_TIMER_CCx(x) DMA_CH_CTRL_SIGSEL((x) + 1) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC0 DMA_CH_CTRL_SIGSEL_TIMER_CCx(0) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC1 DMA_CH_CTRL_SIGSEL_TIMER_CCx(1) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC2 DMA_CH_CTRL_SIGSEL_TIMER_CCx(3) -#define DMA_CH_CTRL_SIGSEL_UART_RXDATAV 0 -#define DMA_CH_CTRL_SIGSEL_UART_TXBL 1 -#define DMA_CH_CTRL_SIGSEL_UART_TXEMPTY 2 -#define DMA_CH_CTRL_SIGSEL_MSC_WDATA 0 -#define DMA_CH_CTRL_SIGSEL_AES_DATA_WR 0 -#define DMA_CH_CTRL_SIGSEL_AES_XOR_DATA_WR 1 -#define DMA_CH_CTRL_SIGSEL_AES_DATA_RD 2 -#define DMA_CH_CTRL_SIGSEL_AES_KEY_WR 3 -#define DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV 0 -#define DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x) DMA_CH_CTRL_SIGSEL(x) -#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY \ - 0 -#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY \ - 1 -#define DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL 2 -#define DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY 3 - -/** - * Application needs to allocate (DMA_DESC_CH_SIZE * N) byte - * where N is the number of first N channels to use. - * and this allocated memory needs to be assigned to DMA using - * dma_set_desc_address(). - * - * if the application code needs alternate descriptor facility also. - * it needs to allocate the required memory (usually equal to the one above) - * and assign the memory using dma_set_alternate_desc_address() - * - * rest of the work will be transparently managed by convience functions. - * - * all the memory above should be aligned to 256bit - * (ie LSB 8bits of array address should be 0) - * use gcc's __attribute__((aligned(256))) - */ -#define DMA_DESC_CH_SIZE (0x4 * 0x4) -#define DMA_DESC_CHx_BASE(base, x) \ - ((base) + ((x) * DMA_DESC_CH_SIZE)) -#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00) -#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04) -#define DMA_DESC_CHx_CFG(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08) -#define DMA_DESC_CHx_USER_DATA(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C) - -/* DMA_DESC_CH_CFG */ -#define DMA_DESC_CH_CFG_DEST_INC_SHIFT (30) -#define DMA_DESC_CH_CFG_DEST_INC_MASK \ - (0x3 << DMA_DESC_CH_CFG_DEST_INC_SHIFT) -#define DMA_DESC_CH_CFG_DEST_INC(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_INC_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_INC_MASK) -#define DMA_DESC_CH_CFG_DEST_INC_BYTE DMA_DESC_CH_CFG_DEST_INC(0) -#define DMA_DESC_CH_CFG_DEST_INC_HALFWORD DMA_DESC_CH_CFG_DEST_INC(1) -#define DMA_DESC_CH_CFG_DEST_INC_WORD DMA_DESC_CH_CFG_DEST_INC(2) -#define DMA_DESC_CH_CFG_DEST_INC_NOINC DMA_DESC_CH_CFG_DEST_INC(3) - -#define DMA_DESC_CH_CFG_DEST_SIZE_SHIFT (28) -#define DMA_DESC_CH_CFG_DEST_SIZE_MASK \ - (0x3 << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) -#define DMA_DESC_CH_CFG_DEST_SIZE(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_SIZE_MASK) -#define DMA_DESC_CH_CFG_DEST_SIZE_BYTE DMA_DESC_CH_CFG_DEST_SIZE(0) -#define DMA_DESC_CH_CFG_DEST_SIZE_HALFWORD DMA_DESC_CH_CFG_DEST_SIZE(1) -#define DMA_DESC_CH_CFG_DEST_SIZE_WORD DMA_DESC_CH_CFG_DEST_SIZE(2) -#define DMA_DESC_CH_CFG_DEST_SIZE_NOINC DMA_DESC_CH_CFG_DEST_SIZE(3) - -#define DMA_DESC_CH_CFG_SRC_INC_SHIFT (26) -#define DMA_DESC_CH_CFG_SRC_INC_MASK \ - (0x3 << DMA_DESC_CH_CFG_SRC_INC_SHIFT) -#define DMA_DESC_CH_CFG_SRC_INC(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_INC_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_INC_MASK) -#define DMA_DESC_CH_CFG_SRC_INC_BYTE DMA_DESC_CH_CFG_SRC_INC(0) -#define DMA_DESC_CH_CFG_SRC_INC_HALFWORD DMA_DESC_CH_CFG_SRC_INC(1) -#define DMA_DESC_CH_CFG_SRC_INC_WORD DMA_DESC_CH_CFG_SRC_INC(2) -#define DMA_DESC_CH_CFG_SRC_INC_NOINC DMA_DESC_CH_CFG_SRC_INC(3) - -#define DMA_DESC_CH_CFG_SRC_SIZE_SHIFT (24) -#define DMA_DESC_CH_CFG_SRC_SIZE_MASK \ - (0x3 << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) -#define DMA_DESC_CH_CFG_SRC_SIZE(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_SIZE_MASK) -#define DMA_DESC_CH_CFG_SRC_SIZE_BYTE DMA_DESC_CH_CFG_SRC_SIZE(0) -#define DMA_DESC_CH_CFG_SRC_SIZE_HALFWORD DMA_DESC_CH_CFG_SRC_SIZE(1) -#define DMA_DESC_CH_CFG_SRC_SIZE_WORD DMA_DESC_CH_CFG_SRC_SIZE(2) -#define DMA_DESC_CH_CFG_SRC_SIZE_NOINC DMA_DESC_CH_CFG_SRC_SIZE(3) - -#define DMA_DESC_CH_CFG_R_POWER_SHIFT (14) -#define DMA_DESC_CH_CFG_R_POWER_MASK \ - (0xF << DMA_DESC_CH_CFG_R_POWER_SHIFT) -#define DMA_DESC_CH_CFG_R_POWER(v) \ - (((v) << DMA_DESC_CH_CFG_R_POWER_SHIFT) & \ - DMA_DESC_CH_CFG_R_POWER_MASK) - -#define DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT (0) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_CYCLE_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_CYCLE_CTRL_MASK) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_INVALD \ - DMA_DESC_CH_CFG_CYCLE_CTRL(0) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_BASIC \ - DMA_DESC_CH_CFG_CYCLE_CTRL(1) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_AUTOREQUEST \ - DMA_DESC_CH_CFG_CYCLE_CTRL(2) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PINGPONG \ - DMA_DESC_CH_CFG_CYCLE_CTRL(3) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_PRIM \ - DMA_DESC_CH_CFG_CYCLE_CTRL(4) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_ALT \ - DMA_DESC_CH_CFG_CYCLE_CTRL(5) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_PRIM \ - DMA_DESC_CH_CFG_CYCLE_CTRL(6) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_ALT \ - DMA_DESC_CH_CFG_CYCLE_CTRL(7) - -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT (21) -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK) - -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT (18) -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) - -#define DMA_DESC_CH_CFG_N_MINUS_1_SHIFT (4) -#define DMA_DESC_CH_CFG_N_MINUS_1_MASK \ - (0x3FF << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) -#define DMA_DESC_CH_CFG_N_MINUS_1(v) \ - (((v) << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) & \ - DMA_DESC_CH_CFG_N_MINUS_1_MASK) - -#define DMA_DESC_CH_CFG_NEXT_USEBURST (1 << 3) - -/* DMA Channel Descriptor in structure style */ -struct dma_chan_desc { - uint32_t src_data_end_ptr; - uint32_t dst_data_end_ptr; - uint32_t cfg; - uint32_t user_data; -} __attribute__((packed)); - -/** @defgroup dma_ch DMA Channel Number -@ingroup dma_defines - -@{*/ -enum dma_ch { - DMA_CH0 = 0, - DMA_CH1, - DMA_CH2, - DMA_CH3, - DMA_CH4, - DMA_CH5, - DMA_CH6, - DMA_CH7, - DMA_CH8, - DMA_CH9, - DMA_CH10, - DMA_CH11 -}; -/**@}*/ - -/* API version for {src, dest} * {size, inc} */ -enum dma_mem { - DMA_MEM_BYTE = 0, - DMA_MEM_HALF_WORD, - DMA_MEM_WORD, - DMA_MEM_NONE -}; - -/* API version of DMA_DESC_CH_CFG_CYCLE_CTRL_* */ -enum dma_mode { - DMA_MODE_INVALID = 0, - DMA_MODE_BASIC, - DMA_MODE_AUTO_REQUEST, - DMA_MODE_PING_PONG, - DMA_MODE_MEM_SCAT_GATH_PRIM, - DMA_MODE_MEM_SCAT_GATH_ALT, - DMA_MODE_PERIPH_SCAT_GATH_PRIM, - DMA_MODE_PERIPH_SCAT_GATH_ALT, -}; - -/* API version of DMA_DESC_CH_CFG_R_POWER() */ -enum dma_r_power { - DMA_R_POWER_1 = 0, - DMA_R_POWER_2, - DMA_R_POWER_4, - DMA_R_POWER_8, - DMA_R_POWER_16, - DMA_R_POWER_32, - DMA_R_POWER_64, - DMA_R_POWER_128, - DMA_R_POWER_256, - DMA_R_POWER_512, - DMA_R_POWER_1024 -}; - -BEGIN_DECLS - -void dma_enable(void); -void dma_disable(void); - -bool dma_get_wait_on_request_flag(enum dma_ch ch); - -/*bool dma_get_wait_flag(enum dma_ch ch);*/ - -void dma_enable_with_unprivileged_access(void); -void dma_enable_with_privileged_access(void); - -void dma_set_desc_address(uint32_t desc_base); - -void dma_generate_software_request(enum dma_ch ch); - -void dma_enable_burst_only(enum dma_ch ch); -void dma_enable_single_and_burst(enum dma_ch ch); - -void dma_enable_periph_request(enum dma_ch ch); -void dma_disable_periph_request(enum dma_ch ch); - -void dma_enable_channel(enum dma_ch ch); -void dma_disable_channel(enum dma_ch ch); - -void dma_disable_alternate_structure(enum dma_ch ch); -void dma_enable_alternate_structure(enum dma_ch ch); - -void dma_enable_priority(enum dma_ch ch); -void dma_disable_priority(enum dma_ch ch); - -bool dma_get_bus_error_flag(void); -void dma_clear_bus_error_flag(void); - -bool dma_get_request_flag(enum dma_ch ch); - -/*bool dma_get_single_request_flag(enum dma_ch ch);*/ - -bool dma_get_bus_error_interrupt_flag(void); -bool dma_get_done_interrupt_flag(enum dma_ch ch); - -void dma_set_bus_error_interrupt_flag(void); -void dma_set_done_interrupt_flag(enum dma_ch ch); - -void dma_clear_bus_error_interrupt_flag(void); -void dma_clear_done_interrupt_flag(enum dma_ch ch); - -void dma_enable_bus_error_interrupt(void); -void dma_disable_bus_error_interrupt(void); -void dma_enable_done_interrupt(enum dma_ch ch); -void dma_disable_done_interrupt(enum dma_ch ch); - -/* TODO: DMA_CTRL, DMA_RDS, DMA_LOOP0, DMA_LOOP1, DMA_RECT0 */ - -void dma_set_source(enum dma_ch ch, uint32_t source); -void dma_set_signal(enum dma_ch ch, uint32_t signal); - -void dma_channel_reset(enum dma_ch ch); - -void dma_set_loop_count(enum dma_ch ch, uint16_t count); -void dma_enable_loop(enum dma_ch ch); -void dma_disable_loop(enum dma_ch ch); - -/* descriptor convient function. (prefix "dma_desc_") */ -void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, - enum dma_mem size); -void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, - enum dma_mem inc); -void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, - enum dma_mem size); -void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, - enum dma_mem inc); - -void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, - enum dma_r_power r_power); - -void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch); -void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch); - -void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count); - -void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, - uint32_t user_data); -uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch); - -void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, - uint32_t src); -void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, - uint32_t dest); - -void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode); - -/* based on descriptor convient, macro are passing - * {DMA_CTRLBASE, CTRL_ALTCTRLBASE} as per naming */ -#define dma_set_dest_size(ch, size) \ - dma_desc_set_dest_size(DMA_CTRLBASE, ch, size) -#define dma_set_dest_inc(ch, inc) \ - dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc) -#define dma_set_src_size(ch, size) \ - dma_desc_set_src_size(DMA_CTRLBASE, ch, size) -#define dma_set_src_inc(ch, inc) \ - dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc) - -#define dma_set_alt_dest_size(ch, size) \ - dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size) -#define dma_set_alt_dest_inc(ch, inc) \ - dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc) -#define dma_set_alt_src_size(ch, size) \ - dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size) -#define dma_set_alt_src_inc(ch, inc) \ - dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc) - -#define dma_set_r_power(ch, r_power) \ - dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power) -#define dma_set_alt_r_power(ch, r_power) \ - dma_desc_set_r_power(DMA_ALTCTRLBASE, ch, r_power) - -#define dma_enable_next_useburst(ch) \ - dma_desc_enable_next_useburst(DMA_CTRLBASE, ch) -#define dma_disable_next_useburst(ch) \ - dma_desc_disable_next_useburst(DMA_CTRLBASE, ch) -#define dma_enable_alt_next_useburst(ch) \ - dma_desc_enable_alt_next_useburst(DMA_CTRLBASE, ch) -#define dma_disable_alt_next_useburst(ch) \ - dma_desc_disable_alt_next_useburst(DMA_CTRLBASE, ch) - -#define dma_set_count(ch, count) \ - dma_desc_set_count(DMA_CTRLBASE, ch, count) -#define dma_set_alt_count(ch, count) \ - dma_desc_set_count(DMA_ALTCTRLBASE, ch, count) - -#define dma_set_user_data(ch, user_data) \ - dma_desc_set_user_data(DMA_CTRLBASE, ch, user_data) -#define dma_set_alt_user_data(ch, user_data) \ - dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data) - -#define dma_get_user_data(ch) \ - dma_desc_get_user_data(DMA_CTRLBASE, ch) -#define dma_get_alt_user_data(ch) \ - dma_desc_get_user_data(DMA_ALTCTRLBASE, ch) - -#define dma_set_src_address(ch, src) \ - dma_desc_set_src_address(DMA_CTRLBASE, ch, src) -#define dma_set_alt_src_address(ch, src) \ - dma_desc_set_src_address(DMA_ALTCTRLBASE, ch, src) -#define dma_set_dest_address(ch, dest) \ - dma_desc_set_dest_address(DMA_CTRLBASE, ch, dest) -#define dma_set_alt_dest_address(ch, dest) \ - dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest) - -#define dma_set_mode(ch, mode) \ - dma_desc_set_mode(DMA_CTRLBASE, ch, mode) -#define dma_set_alt_mode(ch, mode) \ - dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode) - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/emu_common.h b/libopencm3/include/libopencm3/efm32/common/emu_common.h deleted file mode 100644 index f33020b..0000000 --- a/libopencm3/include/libopencm3/efm32/common/emu_common.h +++ /dev/null @@ -1,191 +0,0 @@ -/** @addtogroup emu_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define EMU_CTRL MMIO32(EMU_BASE + 0x000) -#define EMU_LOCK MMIO32(EMU_BASE + 0x008) -#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) -#define EMU_EM4CONF MMIO32(EMU_BASE + 0x02C) -#define EMU_BUCTRL MMIO32(EMU_BASE + 0x030) -#define EMU_PWRCONF MMIO32(EMU_BASE + 0x034) -#define EMU_BUINACT MMIO32(EMU_BASE + 0x038) -#define EMU_BUACT MMIO32(EMU_BASE + 0x03C) -#define EMU_STATUS MMIO32(EMU_BASE + 0x040) -#define EMU_ROUTE MMIO32(EMU_BASE + 0x044) -#define EMU_IF MMIO32(EMU_BASE + 0x048) -#define EMU_IFS MMIO32(EMU_BASE + 0x04C) -#define EMU_IFC MMIO32(EMU_BASE + 0x050) -#define EMU_IEN MMIO32(EMU_BASE + 0x054) -#define EMU_BUBODBUVINCAL MMIO32(EMU_BASE + 0x058) -#define EMU_BUBODUNREGCAL MMIO32(EMU_BASE + 0x05C) - -/* EMU_CTRL */ -#define EMU_CTRL_EM4CTRL_SHIFT (2) -#define EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT) -#define EMU_CTLR_EM4CTRL(v) \ - (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK) - -#define EMU_CTRL_EM2BLOCK (1 << 1) -#define EMU_CTRL_EMVREG (1 << 0) - -/* EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_MASK (0xFFFF) -#define EMU_LOCK_LOCKKEY_LOCK (0) -#define EMU_LOCK_LOCKKEY_UNLOCK (0xADE8) - -/* EMU_AUXCTRL */ -#define EMU_AUXCTRL_HRCCLR (1 << 0) - -/* EMU_EM4CONF */ -#define EMU_EM4CONF_LOCKCONF (1 << 16) -#define EMU_EM4CONF_BUBODRSTDIS (1 << 4) - -#define EMU_EM4CONF_OSC_SHIFT (2) -#define EMU_EM4CONF_OSC_MASK (0x3 << EMU_EM4CONF_OSC_SHIFT) -#define EMU_EM4CONF_OSC(v) \ - (((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK) -#define EMU_EM4CONF_OSC_ULFRCO 0 -#define EMU_EM4CONF_OSC_LFRCO 1 -#define EMU_EM4CONF_OSC_LFXO 2 - -#define EMU_EM4CONF_BURTCWU (1 << 1) -#define EMU_EM4CONF_VREGEN (1 << 0) - -/* EMU_BUCTRL */ -#define EMU_BUCTRL_PROBE_SHIFT (5) -#define EMU_BUCTRL_PROBE_MASK (0x3 << EMU_BUCTRL_PROBE_SHIFT) -#define EMU_BUCTRL_PROBE(v) \ - (((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK) -#define EMU_BUCTRL_PROBE_DISABLE 0 -#define EMU_BUCTRL_PROBE_VDDDREG 1 -#define EMU_BUCTRL_PROBE_BUIN 2 -#define EMU_BUCTRL_PROBE_BUOUT 3 - -#define EMU_BUCTRL_BUMODEBODEN (1 << 3) -#define EMU_BUCTRL_BODCAL (1 << 2) -#define EMU_BUCTRL_STATEN (1 << 1) -#define EMU_BUCTRL_EN (1 << 0) - -/* EMU_PWRCONF */ -#define EMU_PWRCONF_PWRRES_SHIFT (3) -#define EMU_PWRCONF_PWRRES_MASK (0x3 << EMU_PWRCONF_PWRRES_SHIFT) -#define EMU_PWRCONF_PWRRES(v) \ - (((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK) -#define EMU_PWRCONF_PWRRES_DISABLE 0 -#define EMU_PWRCONF_PWRRES_VDDDREG 1 -#define EMU_PWRCONF_PWRRES_BUIN 2 -#define EMU_PWRCONF_PWRRES_BUOUT 3 - -#define EMU_PWRCONF_VOUTSTRONG (1 << 2) -#define EMU_PWRCONF_VOUTMED (1 << 1) -#define EMU_PWRCONF_VOUTWEAK (1 << 0) - -/* EMU_BUINACT */ -#define EMU_BUINACT_PWRCON_SHIFT (5) -#define EMU_BUINACT_PWRCON_MASK (0x3 << EMU_BUINACT_PWRCON_SHIFT) -#define EMU_BUINACT_PWRCON(v) \ - (((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK) -#define EMU_BUINACT_PWRCON_NONE 0 -#define EMU_BUINACT_PWRCON_BUMAIN 1 -#define EMU_BUINACT_PWRCON_MAINBU 2 -#define EMU_BUINACT_PWRCON_NODIODE 3 - -#define EMU_BUINACT_BUENRANGE_SHIFT (3) -#define EMU_BUINACT_BUENRANGE_MASK (0x3 << EMU_BUINACT_BUENRANGE_SHIFT) -#define EMU_BUINACT_BUENRANGE(v) \ - (((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK) - -#define EMU_BUINACT_BUENTHRES_SHIFT (0) -#define EMU_BUINACT_BUENTHRES_MASK (0x7 << EMU_BUINACT_BUENTHRES_SHIFT) -#define EMU_BUINACT_BUENTHRES(v) \ - (((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK) - -/* EMU_BUACT */ -#define EMU_BUACT_PWRCON_SHIFT (5) -#define EMU_BUACT_PWRCON_MASK (0x3 << EMU_BUACT_PWRCON_SHIFT) -#define EMU_BUACT_PWRCON(v) \ - (((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK) -#define EMU_BUACT_PWRCON_NONE 0 -#define EMU_BUACT_PWRCON_BUMAIN 1 -#define EMU_BUACT_PWRCON_MAINBU 2 -#define EMU_BUACT_PWRCON_NODIODE 3 - -#define EMU_BUACT_BUEXRANGE_SHIFT (3) -#define EMU_BUACT_BUEXRANGE_MASK (0x3 << EMU_BUACT_BUEXRANGE_SHIFT) -#define EMU_BUACT_BUEXRANGE(v) \ - (((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK) - -#define EMU_BUACT_BUEXTHRES_SHIFT (0) -#define EMU_BUACT_BUEXTHRES_MASK (0x7 << EMU_BUACT_BUEXTHRES_SHIFT) -#define EMU_BUACT_BUEXTHRES(v) \ - (((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK) - -/* EMU_STATUS */ -#define EMU_STATUS_BURDY (1 << 0) - -/* EMU_ROUTE */ -#define EMU_ROUTE_BUVINPEN (1 << 0) - -/* EMU_IF */ -#define EMU_IF_BURDY (1 << 0) - -/* EMU_IFS */ -#define EMU_IFS_BURDY (1 << 0) - -/* EMU_IFC */ -#define EMU_IFC_BURDY (1 << 0) - -/* EMU_IEN */ -#define EMU_IEN_BURDY (1 << 0) - -/* EMU_BUBODBUVINCAL */ -#define EMU_BUBODBUVINCAL_RANGE_SHIFT (3) -#define EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT) -#define EMU_BUBODBUVINCAL_RANGE(v) \ - (((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \ - EMU_BUBODBUVINCAL_RANGE_MASK) - -#define EMU_BUBODBUVINCAL_THRES_SHIFT (0) -#define EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT) -#define EMU_BUBODBUVINCAL_THRES(v) \ - (((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \ - EMU_BUBODBUVINCAL_THRES_MASK) - -/* EMU_BUBODUNREGCAL */ -#define EMU_BUBODUNREGCAL_RANGE_SHIFT (3) -#define EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT) -#define EMU_BUBODUNREGCAL_RANGE(v) \ - (((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \ - EMU_BUBODUNREGCAL_RANGE_MASK) - -#define EMU_BUBODUNREGCAL_THRES_SHIFT (0) -#define EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT) -#define EMU_BUBODUNREGCAL_THRES(v) \ - (((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \ - EMU_BUBODUNREGCAL_THRES_MASK) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/gpio_common.h b/libopencm3/include/libopencm3/efm32/common/gpio_common.h deleted file mode 100644 index 5099b99..0000000 --- a/libopencm3/include/libopencm3/efm32/common/gpio_common.h +++ /dev/null @@ -1,332 +0,0 @@ -/** @addtogroup gpio_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define GPIO_P(i) (GPIO_BASE + (0x24 * (i))) -#define GPIO_PA GPIO_P(0) -#define GPIO_PB GPIO_P(1) -#define GPIO_PC GPIO_P(2) -#define GPIO_PD GPIO_P(3) -#define GPIO_PE GPIO_P(4) -#define GPIO_PF GPIO_P(5) - -#define GPIO_P_CTRL(port) MMIO32((port) + 0x00) -#define GPIO_PA_CTRL GPIO_P_CTRL(GPIO_PA) -#define GPIO_PB_CTRL GPIO_P_CTRL(GPIO_PB) -#define GPIO_PC_CTRL GPIO_P_CTRL(GPIO_PC) -#define GPIO_PD_CTRL GPIO_P_CTRL(GPIO_PD) -#define GPIO_PE_CTRL GPIO_P_CTRL(GPIO_PE) -#define GPIO_PF_CTRL GPIO_P_CTRL(GPIO_PF) - -#define GPIO_P_CTRL_DRIVEMODE_SHIFT (0) -#define GPIO_P_CTRL_DRIVEMODE_MASK (0x03 << GPIO_P_CTRL_DRIVEMODE_SHIFT) -#define GPIO_P_CTRL_DRIVEMODE(v) \ - (((v) << GPIO_P_CTRL_DRIVEMODE_SHIFT) & GPIO_P_CTRL_DRIVEMODE_MASK) -#define GPIO_P_CTRL_DRIVEMODE_STANDARD 0 -#define GPIO_P_CTRL_DRIVEMODE_LOWEST 1 -#define GPIO_P_CTRL_DRIVEMODE_HIGH 2 -#define GPIO_P_CTRL_DRIVEMODE_LOW 3 - -/* NOTE: GPIO_MODE and GPIO_MODE_MASK is generic. - * it is used with both GPIO_Px_MODEL and GPIO_Px_MODEH */ -#define GPIO_P_MODE_MODEx_MASK(x) (0x0F << (((x) & 0x7) * 4)) -/* for mode: use GPIO_MODE_* */ -#define GPIO_P_MODE_MODEx(x, mode) \ - (((mode) << (((x) & 0x7) * 4)) & GPIO_P_MODE_MODEx_MASK(x)) - -#define GPIO_P_MODEL(port) MMIO32((port) + 0x04) -#define GPIO_PA_MODEL GPIO_P_MODEL(GPIO_PA) -#define GPIO_PB_MODEL GPIO_P_MODEL(GPIO_PB) -#define GPIO_PC_MODEL GPIO_P_MODEL(GPIO_PC) -#define GPIO_PD_MODEL GPIO_P_MODEL(GPIO_PD) -#define GPIO_PE_MODEL GPIO_P_MODEL(GPIO_PE) - -#define GPIO_P_MODEL_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK(x) -#define GPIO_P_MODEL_MODEx(x, mode) GPIO_P_MODE_MODEx(x, mode) - -#define GPIO_P_MODEL_MODE0_MASK GPIO_P_MODEL_MODEx_MASK(0) -#define GPIO_P_MODEL_MODE0(mode) GPIO_P_MODEL_MODEx(0, mode) - -#define GPIO_P_MODEL_MODE1_MASK GPIO_P_MODEL_MODEx_MASK(1) -#define GPIO_P_MODEL_MODE1(mode) GPIO_P_MODEL_MODEx(1, mode) - -#define GPIO_P_MODEL_MODE2_MASK GPIO_P_MODEL_MODEx_MASK(2) -#define GPIO_P_MODEL_MODE2(mode) GPIO_P_MODEL_MODEx(2, mode) - -#define GPIO_P_MODEL_MODE3_MASK GPIO_P_MODEL_MODEx_MASK(3) -#define GPIO_P_MODEL_MODE3(mode) GPIO_P_MODEL_MODEx(3, mode) - -#define GPIO_P_MODEL_MODE4_MASK GPIO_P_MODEL_MODEx_MASK(4) -#define GPIO_P_MODEL_MODE4(mode) GPIO_P_MODEL_MODEx(4, mode) - -#define GPIO_P_MODEL_MODE5_MASK GPIO_P_MODEL_MODEx_MASK(5) -#define GPIO_P_MODEL_MODE5(mode) GPIO_P_MODEL_MODEx(5, mode) - -#define GPIO_P_MODEL_MODE6_MASK GPIO_P_MODEL_MODEx_MASK(6) -#define GPIO_P_MODEL_MODE6(mode) GPIO_P_MODEL_MODEx(6, mode) - -#define GPIO_P_MODEL_MODE7_MASK GPIO_P_MODEL_MODEx_MASK(7) -#define GPIO_P_MODEL_MODE7(mode) GPIO_P_MODEL_MODEx(7, mode) - -#define GPIO_P_MODEH(port) MMIO32((port) + 0x08) -#define GPIO_PA_MODEH GPIO_P_MODEH(GPIO_PA) -#define GPIO_PB_MODEH GPIO_P_MODEH(GPIO_PB) -#define GPIO_PC_MODEH GPIO_P_MODEH(GPIO_PC) -#define GPIO_PD_MODEH GPIO_P_MODEH(GPIO_PD) -#define GPIO_PE_MODEH GPIO_P_MODEH(GPIO_PE) - -/* note: (x - 8) is because for MODEH, MODE8 refers to offset 0 */ -#define GPIO_P_MODEH_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK((x) - 8) -#define GPIO_P_MODEH_MODEx(x, mode) GPIO_P_MODE_MODEx((x) - 8, mode) - -#define GPIO_P_MODEH_MODE8_MASK GPIO_P_MODEH_MODEx_MASK(8) -#define GPIO_P_MODEH_MODE8(mode) GPIO_P_MODEH_MODEx(8, mode) - -#define GPIO_P_MODEH_MODE9_MASK GPIO_P_MODEH_MODEx_MASK(9) -#define GPIO_P_MODEH_MODE9(mode) GPIO_P_MODEH_MODEx(9, mode) - -#define GPIO_P_MODEH_MODE10_MASK GPIO_P_MODEH_MODEx_MASK(10) -#define GPIO_P_MODEH_MODE10(mode) GPIO_P_MODEH_MODEx(10, mode) - -#define GPIO_P_MODEH_MODE11_MASK GPIO_P_MODEH_MODEx_MASK(11) -#define GPIO_P_MODEH_MODE11(mode) GPIO_P_MODEH_MODEx(11, mode) - -#define GPIO_P_MODEH_MODE12_MASK GPIO_P_MODEH_MODEx_MASK(12) -#define GPIO_P_MODEH_MODE12(mode) GPIO_P_MODEH_MODEx(12, mode) - -#define GPIO_P_MODEH_MODE13_MASK GPIO_P_MODEH_MODEx_MASK(13) -#define GPIO_P_MODEH_MODE13(mode) GPIO_P_MODEH_MODEx(13, mode) - -#define GPIO_P_MODEH_MODE14_MASK GPIO_P_MODEH_MODEx_MASK(14) -#define GPIO_P_MODEH_MODE14(mode) GPIO_P_MODEH_MODEx(14, mode) - -#define GPIO_P_MODEH_MODE15_MASK GPIO_P_MODEH_MODEx_MASK(15) -#define GPIO_P_MODEH_MODE15(mode) GPIO_P_MODEH_MODEx(15, mode) - -#define GPIO_P_DOUT(port) MMIO32((port) + 0x0C) -#define GPIO_PA_DOUT GPIO_P_DOUT(GPIO_PA) -#define GPIO_PB_DOUT GPIO_P_DOUT(GPIO_PB) -#define GPIO_PC_DOUT GPIO_P_DOUT(GPIO_PC) -#define GPIO_PD_DOUT GPIO_P_DOUT(GPIO_PD) -#define GPIO_PE_DOUT GPIO_P_DOUT(GPIO_PE) - -#define GPIO_P_DOUTSET(port) MMIO32((port) + 0x10) -#define GPIO_PA_DOUTSET GPIO_P_DOUTSET(GPIO_PA) -#define GPIO_PB_DOUTSET GPIO_P_DOUTSET(GPIO_PB) -#define GPIO_PC_DOUTSET GPIO_P_DOUTSET(GPIO_PC) -#define GPIO_PD_DOUTSET GPIO_P_DOUTSET(GPIO_PD) -#define GPIO_PE_DOUTSET GPIO_P_DOUTSET(GPIO_PE) - -#define GPIO_P_DOUTCLR(port) MMIO32((port) + 0x14) -#define GPIO_PA_DOUTCLR GPIO_P_DOUTCLR(GPIO_PA) -#define GPIO_PB_DOUTCLR GPIO_P_DOUTCLR(GPIO_PB) -#define GPIO_PC_DOUTCLR GPIO_P_DOUTCLR(GPIO_PC) -#define GPIO_PD_DOUTCLR GPIO_P_DOUTCLR(GPIO_PD) -#define GPIO_PE_DOUTCLR GPIO_P_DOUTCLR(GPIO_PE) - -#define GPIO_P_DOUTTGL(port) MMIO32((port) + 0x18) -#define GPIO_PA_DOUTTGL GPIO_P_DOUTTGL(GPIO_PA) -#define GPIO_PB_DOUTTGL GPIO_P_DOUTTGL(GPIO_PB) -#define GPIO_PC_DOUTTGL GPIO_P_DOUTTGL(GPIO_PC) -#define GPIO_PD_DOUTTGL GPIO_P_DOUTTGL(GPIO_PD) -#define GPIO_PE_DOUTTGL GPIO_P_DOUTTGL(GPIO_PE) - -#define GPIO_P_DIN(port) MMIO32((port) + 0x1C) -#define GPIO_PA_DIN GPIO_P_DIN(GPIO_PA) -#define GPIO_PB_DIN GPIO_P_DIN(GPIO_PB) -#define GPIO_PC_DIN GPIO_P_DIN(GPIO_PC) -#define GPIO_PD_DIN GPIO_P_DIN(GPIO_PD) -#define GPIO_PE_DIN GPIO_P_DIN(GPIO_PE) - -#define GPIO_P_PINLOCKN(port) MMIO32((port) + 0x20) -#define GPIO_PA_PINLOCKN GPIO_P_PINLOCKN(GPIO_PA) -#define GPIO_PB_PINLOCKN GPIO_P_PINLOCKN(GPIO_PB) -#define GPIO_PC_PINLOCKN GPIO_P_PINLOCKN(GPIO_PC) -#define GPIO_PD_PINLOCKN GPIO_P_PINLOCKN(GPIO_PD) -#define GPIO_PE_PINLOCKN GPIO_P_PINLOCKN(GPIO_PE) - -#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) -#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) -#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) -#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) -#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) -#define GPIO_IF MMIO32(GPIO_BASE + 0x114) -#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) -#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) -#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) -#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) -#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) -#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) -#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) -#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) -#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) -#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) - -/* mask is performed so that can be used with L and H */ -#define GPIO_EXTIPSEL_MASK(n) (0x7 << ((n) & 0xF)) -#define GPIO_EXTIPSEL_PORTMASK(n, v) ((v) << ((n) & 0xF)) -#define GPIO_EXTIPSEL_PORTA 0x0 -#define GPIO_EXTIPSEL_PORTB 0x1 -#define GPIO_EXTIPSEL_PORTC 0x2 -#define GPIO_EXTIPSEL_PORTD 0x3 -#define GPIO_EXTIPSEL_PORTE 0x4 -#define GPIO_EXTIPSEL_PORTF 0x5 - -#define GPIO_ROUTE_SWCLKPEN (1 << 0) -#define GPIO_ROUTE_SWDIOPEN (1 << 1) -#define GPIO_ROUTE_SWOPEN (1 << 3) - -#define GPIO_ROUTE_SWLOCATION_SHIFT (8) -#define GPIO_ROUTE_SWLOCATION_MASK (0x3 << GPIO_ROUTE_SWLOCATION_SHIFT) -#define GPIO_ROUTE_SWLOCATION(v) \ - (((v) << GPIO_ROUTE_SWLOCATION_SHIFT) & GPIO_ROUTE_SWLOCATION_MASK) - -#define GPIO_ROUTE_TCLKPEN (1 << 12) -#define GPIO_ROUTE_TD0PEN (1 << 13) -#define GPIO_ROUTE_TD1PEN (1 << 14) -#define GPIO_ROUTE_TD2PEN (1 << 15) -#define GPIO_ROUTE_TD3PEN (1 << 16) - -#define GPIO_ROUTE_ETMLOCATION_SHIFT (24) -#define GPIO_ROUTE_ETMLOCATION_MASK (0x3 << GPIO_ROUTE_ETMLOCATION_SHIFT) -#define GPIO_ROUTE_ETMLOCATION(v) \ - (((v) << GPIO_ROUTE_ETMLOCATION_SHIFT) & GPIO_ROUTE_ETMLOCATION_MASK) -#define GPIO_ROUTE_ETMLOCATION_LOCx(x) GPIO_ROUTE_ETMLOCATION(x) -#define GPIO_ROUTE_ETMLOCATION_LOC0 0 -#define GPIO_ROUTE_ETMLOCATION_LOC1 1 -#define GPIO_ROUTE_ETMLOCATION_LOC2 2 -#define GPIO_ROUTE_ETMLOCATION_LOC3 3 - -#define GPIO_INSENSE_INT (1 << 0) -#define GPIO_INSENSE_PRS (1 << 1) - -#define GPIO_LOCK_LOCKKEY_SHIFT (0) -#define GPIO_LOCK_LOCKKEY_MASK (0xFFFF << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_UNLOCKED (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_LOCKED (0x0001 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_LOCK (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_UNLOCK (0xA534 << GPIO_LOCK_LOCKKEY_SHIFT) - -#define GPIO_CTRL_EM4RET (1 << 0) - -#define GPIO_CMD_EM4WUCLR (1 << 0) - -#define GPIO_EM4WUEN_EM4WUEN_A0 (1 << 0) -#define GPIO_EM4WUEN_EM4WUEN_A6 (1 << 1) -#define GPIO_EM4WUEN_EM4WUEN_C9 (1 << 2) -#define GPIO_EM4WUEN_EM4WUEN_F1 (1 << 3) -#define GPIO_EM4WUEN_EM4WUEN_F2 (1 << 4) -#define GPIO_EM4WUEN_EM4WUEN_E13 (1 << 5) - -#define GPIO_EM4WUPOL_EM4WUPOL_A0 (1 << 0) -#define GPIO_EM4WUPOL_EM4WUPOL_A6 (1 << 1) -#define GPIO_EM4WUPOL_EM4WUPOL_C9 (1 << 2) -#define GPIO_EM4WUPOL_EM4WUPOL_F1 (1 << 3) -#define GPIO_EM4WUPOL_EM4WUPOL_F2 (1 << 4) -#define GPIO_EM4WUPOL_EM4WUPOL_E13 (1 << 5) - -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL (0xFFFF) - -/* These are the acceptable mode values. - * (+ readable counterparts) - * do not confuse GPIO_MODE_* for GPIO_P_MODE_MODEx. - */ -enum gpio_mode { - GPIO_MODE_DISABLE = 0, - GPIO_MODE_INPUT, - GPIO_MODE_INPUT_PULL, - GPIO_MODE_INPUT_PULL_FILTER, - GPIO_MODE_PUSH_PULL, - GPIO_MODE_PUSH_PULL_DRIVE, - GPIO_MODE_WIRED_OR, - GPIO_MODE_WIRED_OR_PULL_DOWN, - GPIO_MODE_WIRED_AND, - GPIO_MODE_WIRED_AND_FILTER, - GPIO_MODE_WIRED_AND_PULLUP, - GPIO_MODE_WIRED_AND_PULLUP_FILTER, - GPIO_MODE_WIRED_AND_DRIVE, - GPIO_MODE_WIRED_AND_DRIVE_FILTER, - GPIO_MODE_WIRED_AND_DRIVE_PULLUP, - GPIO_MODE_WIRED_AND_DRIVE_PULLUP_FILTER -}; - -/* for readability. */ -enum gpio_drive_strength { - GPIO_STRENGTH_STANDARD = 0, - GPIO_STRENGTH_LOWEST, - GPIO_STRENGTH_HIGH, - GPIO_STRENGTH_LOW -}; - -/* for readability */ -#define GPIOA GPIO_PA -#define GPIOB GPIO_PB -#define GPIOC GPIO_PC -#define GPIOD GPIO_PD -#define GPIOE GPIO_PE -#define GPIOF GPIO_PF - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void gpio_enable_lock(void); -void gpio_disable_lock(void); -bool gpio_get_lock_flag(void); - -void gpio_set_drive_strength(uint32_t gpio_port, - enum gpio_drive_strength driver_stength); -void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios); - -void gpio_set(uint32_t gpio_port, uint16_t gpios); -void gpio_clear(uint32_t gpio_port, uint16_t gpios); -uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios); -void gpio_toggle(uint32_t gpio_port, uint16_t gpios); -uint16_t gpio_port_read(uint32_t gpio_port); -void gpio_port_write(uint32_t gpio_port, uint16_t data); - -void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/gpio_common_hglg.h b/libopencm3/include/libopencm3/efm32/common/gpio_common_hglg.h deleted file mode 100644 index 5574490..0000000 --- a/libopencm3/include/libopencm3/efm32/common/gpio_common_hglg.h +++ /dev/null @@ -1,332 +0,0 @@ -/** @addtogroup gpio_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define GPIO_P(i) (GPIO_BASE + (0x24 * (i))) -#define GPIO_PA GPIO_P(0) -#define GPIO_PB GPIO_P(1) -#define GPIO_PC GPIO_P(2) -#define GPIO_PD GPIO_P(3) -#define GPIO_PE GPIO_P(4) -#define GPIO_PF GPIO_P(5) - -#define GPIO_P_CTRL(port) MMIO32((port) + 0x00) -#define GPIO_PA_CTRL GPIO_P_CTRL(GPIO_PA) -#define GPIO_PB_CTRL GPIO_P_CTRL(GPIO_PB) -#define GPIO_PC_CTRL GPIO_P_CTRL(GPIO_PC) -#define GPIO_PD_CTRL GPIO_P_CTRL(GPIO_PD) -#define GPIO_PE_CTRL GPIO_P_CTRL(GPIO_PE) -#define GPIO_PF_CTRL GPIO_P_CTRL(GPIO_PF) - -#define GPIO_P_CTRL_DRIVEMODE_SHIFT (0) -#define GPIO_P_CTRL_DRIVEMODE_MASK (0x03 << GPIO_P_CTRL_DRIVEMODE_SHIFT) -#define GPIO_P_CTRL_DRIVEMODE(v) \ - (((v) << GPIO_P_CTRL_DRIVEMODE_SHIFT) & GPIO_P_CTRL_DRIVEMODE_MASK) -#define GPIO_P_CTRL_DRIVEMODE_STANDARD GPIO_P_CTRL_DRIVEMODE(0) -#define GPIO_P_CTRL_DRIVEMODE_LOWEST GPIO_P_CTRL_DRIVEMODE(1) -#define GPIO_P_CTRL_DRIVEMODE_HIGH GPIO_P_CTRL_DRIVEMODE(2) -#define GPIO_P_CTRL_DRIVEMODE_LOW GPIO_P_CTRL_DRIVEMODE(3) - -/* NOTE: GPIO_MODE and GPIO_MODE_MASK is generic. - * it is used with both GPIO_Px_MODEL and GPIO_Px_MODEH */ -#define GPIO_P_MODE_MODEx_MASK(x) (0x0F << (((x) & 0x7) * 4)) -/* for mode: use GPIO_MODE_* */ -#define GPIO_P_MODE_MODEx(x, mode) \ - (((mode) << (((x) & 0x7) * 4)) & GPIO_P_MODE_MODEx_MASK(x)) - -#define GPIO_P_MODEL(port) MMIO32((port) + 0x04) -#define GPIO_PA_MODEL GPIO_P_MODEL(GPIO_PA) -#define GPIO_PB_MODEL GPIO_P_MODEL(GPIO_PB) -#define GPIO_PC_MODEL GPIO_P_MODEL(GPIO_PC) -#define GPIO_PD_MODEL GPIO_P_MODEL(GPIO_PD) -#define GPIO_PE_MODEL GPIO_P_MODEL(GPIO_PE) - -#define GPIO_P_MODEL_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK(x) -#define GPIO_P_MODEL_MODEx(x, mode) GPIO_P_MODE_MODEx(x, mode) - -#define GPIO_P_MODEL_MODE0_MASK GPIO_P_MODEL_MODEx_MASK(0) -#define GPIO_P_MODEL_MODE0(mode) GPIO_P_MODEL_MODEx(0, mode) - -#define GPIO_P_MODEL_MODE1_MASK GPIO_P_MODEL_MODEx_MASK(1) -#define GPIO_P_MODEL_MODE1(mode) GPIO_P_MODEL_MODEx(1, mode) - -#define GPIO_P_MODEL_MODE2_MASK GPIO_P_MODEL_MODEx_MASK(2) -#define GPIO_P_MODEL_MODE2(mode) GPIO_P_MODEL_MODEx(2, mode) - -#define GPIO_P_MODEL_MODE3_MASK GPIO_P_MODEL_MODEx_MASK(3) -#define GPIO_P_MODEL_MODE3(mode) GPIO_P_MODEL_MODEx(3, mode) - -#define GPIO_P_MODEL_MODE4_MASK GPIO_P_MODEL_MODEx_MASK(4) -#define GPIO_P_MODEL_MODE4(mode) GPIO_P_MODEL_MODEx(4, mode) - -#define GPIO_P_MODEL_MODE5_MASK GPIO_P_MODEL_MODEx_MASK(5) -#define GPIO_P_MODEL_MODE5(mode) GPIO_P_MODEL_MODEx(5, mode) - -#define GPIO_P_MODEL_MODE6_MASK GPIO_P_MODEL_MODEx_MASK(6) -#define GPIO_P_MODEL_MODE6(mode) GPIO_P_MODEL_MODEx(6, mode) - -#define GPIO_P_MODEL_MODE7_MASK GPIO_P_MODEL_MODEx_MASK(7) -#define GPIO_P_MODEL_MODE7(mode) GPIO_P_MODEL_MODEx(7, mode) - -#define GPIO_P_MODEH(port) MMIO32((port) + 0x08) -#define GPIO_PA_MODEH GPIO_P_MODEH(GPIO_PA) -#define GPIO_PB_MODEH GPIO_P_MODEH(GPIO_PB) -#define GPIO_PC_MODEH GPIO_P_MODEH(GPIO_PC) -#define GPIO_PD_MODEH GPIO_P_MODEH(GPIO_PD) -#define GPIO_PE_MODEH GPIO_P_MODEH(GPIO_PE) - -/* note: (x - 8) is because for MODEH, MODE8 refers to offset 0 */ -#define GPIO_P_MODEH_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK((x) - 8) -#define GPIO_P_MODEH_MODEx(x, mode) GPIO_P_MODE_MODEx((x) - 8, mode) - -#define GPIO_P_MODEH_MODE8_MASK GPIO_P_MODEH_MODEx_MASK(8) -#define GPIO_P_MODEH_MODE8(mode) GPIO_P_MODEH_MODEx(8, mode) - -#define GPIO_P_MODEH_MODE9_MASK GPIO_P_MODEH_MODEx_MASK(9) -#define GPIO_P_MODEH_MODE9(mode) GPIO_P_MODEH_MODEx(9, mode) - -#define GPIO_P_MODEH_MODE10_MASK GPIO_P_MODEH_MODEx_MASK(10) -#define GPIO_P_MODEH_MODE10(mode) GPIO_P_MODEH_MODEx(10, mode) - -#define GPIO_P_MODEH_MODE11_MASK GPIO_P_MODEH_MODEx_MASK(11) -#define GPIO_P_MODEH_MODE11(mode) GPIO_P_MODEH_MODEx(11, mode) - -#define GPIO_P_MODEH_MODE12_MASK GPIO_P_MODEH_MODEx_MASK(12) -#define GPIO_P_MODEH_MODE12(mode) GPIO_P_MODEH_MODEx(12, mode) - -#define GPIO_P_MODEH_MODE13_MASK GPIO_P_MODEH_MODEx_MASK(13) -#define GPIO_P_MODEH_MODE13(mode) GPIO_P_MODEH_MODEx(13, mode) - -#define GPIO_P_MODEH_MODE14_MASK GPIO_P_MODEH_MODEx_MASK(14) -#define GPIO_P_MODEH_MODE14(mode) GPIO_P_MODEH_MODEx(14, mode) - -#define GPIO_P_MODEH_MODE15_MASK GPIO_P_MODEH_MODEx_MASK(15) -#define GPIO_P_MODEH_MODE15(mode) GPIO_P_MODEH_MODEx(15, mode) - -#define GPIO_P_DOUT(port) MMIO32((port) + 0x0C) -#define GPIO_PA_DOUT GPIO_P_DOUT(GPIO_PA) -#define GPIO_PB_DOUT GPIO_P_DOUT(GPIO_PB) -#define GPIO_PC_DOUT GPIO_P_DOUT(GPIO_PC) -#define GPIO_PD_DOUT GPIO_P_DOUT(GPIO_PD) -#define GPIO_PE_DOUT GPIO_P_DOUT(GPIO_PE) - -#define GPIO_P_DOUTSET(port) MMIO32((port) + 0x10) -#define GPIO_PA_DOUTSET GPIO_P_DOUTSET(GPIO_PA) -#define GPIO_PB_DOUTSET GPIO_P_DOUTSET(GPIO_PB) -#define GPIO_PC_DOUTSET GPIO_P_DOUTSET(GPIO_PC) -#define GPIO_PD_DOUTSET GPIO_P_DOUTSET(GPIO_PD) -#define GPIO_PE_DOUTSET GPIO_P_DOUTSET(GPIO_PE) - -#define GPIO_P_DOUTCLR(port) MMIO32((port) + 0x14) -#define GPIO_PA_DOUTCLR GPIO_P_DOUTCLR(GPIO_PA) -#define GPIO_PB_DOUTCLR GPIO_P_DOUTCLR(GPIO_PB) -#define GPIO_PC_DOUTCLR GPIO_P_DOUTCLR(GPIO_PC) -#define GPIO_PD_DOUTCLR GPIO_P_DOUTCLR(GPIO_PD) -#define GPIO_PE_DOUTCLR GPIO_P_DOUTCLR(GPIO_PE) - -#define GPIO_P_DOUTTGL(port) MMIO32((port) + 0x18) -#define GPIO_PA_DOUTTGL GPIO_P_DOUTTGL(GPIO_PA) -#define GPIO_PB_DOUTTGL GPIO_P_DOUTTGL(GPIO_PB) -#define GPIO_PC_DOUTTGL GPIO_P_DOUTTGL(GPIO_PC) -#define GPIO_PD_DOUTTGL GPIO_P_DOUTTGL(GPIO_PD) -#define GPIO_PE_DOUTTGL GPIO_P_DOUTTGL(GPIO_PE) - -#define GPIO_P_DIN(port) MMIO32((port) + 0x1C) -#define GPIO_PA_DIN GPIO_P_DIN(GPIO_PA) -#define GPIO_PB_DIN GPIO_P_DIN(GPIO_PB) -#define GPIO_PC_DIN GPIO_P_DIN(GPIO_PC) -#define GPIO_PD_DIN GPIO_P_DIN(GPIO_PD) -#define GPIO_PE_DIN GPIO_P_DIN(GPIO_PE) - -#define GPIO_P_PINLOCKN(port) MMIO32((port) + 0x20) -#define GPIO_PA_PINLOCKN GPIO_P_PINLOCKN(GPIO_PA) -#define GPIO_PB_PINLOCKN GPIO_P_PINLOCKN(GPIO_PB) -#define GPIO_PC_PINLOCKN GPIO_P_PINLOCKN(GPIO_PC) -#define GPIO_PD_PINLOCKN GPIO_P_PINLOCKN(GPIO_PD) -#define GPIO_PE_PINLOCKN GPIO_P_PINLOCKN(GPIO_PE) - -#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) -#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) -#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) -#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) -#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) -#define GPIO_IF MMIO32(GPIO_BASE + 0x114) -#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) -#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) -#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) -#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) -#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) -#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) -#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) -#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) -#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) -#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) - -/* mask is performed so that can be used with L and H */ -#define GPIO_EXTIPSEL_MASK(n) (0x7 << ((n) & 0xF)) -#define GPIO_EXTIPSEL_PORTMASK(n, v) ((v) << ((n) & 0xF)) -#define GPIO_EXTIPSEL_PORTA 0x0 -#define GPIO_EXTIPSEL_PORTB 0x1 -#define GPIO_EXTIPSEL_PORTC 0x2 -#define GPIO_EXTIPSEL_PORTD 0x3 -#define GPIO_EXTIPSEL_PORTE 0x4 -#define GPIO_EXTIPSEL_PORTF 0x5 - -#define GPIO_ROUTE_SWCLKPEN (1 << 0) -#define GPIO_ROUTE_SWDIOPEN (1 << 1) -#define GPIO_ROUTE_SWOPEN (1 << 3) - -#define GPIO_ROUTE_SWLOCATION_SHIFT (8) -#define GPIO_ROUTE_SWLOCATION_MASK (0x3 << GPIO_ROUTE_SWLOCATION_SHIFT) -#define GPIO_ROUTE_SWLOCATION(v) \ - (((v) << GPIO_ROUTE_SWLOCATION_SHIFT) & GPIO_ROUTE_SWLOCATION_MASK) - -#define GPIO_ROUTE_TCLKPEN (1 << 12) -#define GPIO_ROUTE_TD0PEN (1 << 13) -#define GPIO_ROUTE_TD1PEN (1 << 14) -#define GPIO_ROUTE_TD2PEN (1 << 15) -#define GPIO_ROUTE_TD3PEN (1 << 16) - -#define GPIO_ROUTE_ETMLOCATION_SHIFT (24) -#define GPIO_ROUTE_ETMLOCATION_MASK (0x3 << GPIO_ROUTE_ETMLOCATION_SHIFT) -#define GPIO_ROUTE_ETMLOCATION(v) \ - (((v) << GPIO_ROUTE_ETMLOCATION_SHIFT) & GPIO_ROUTE_ETMLOCATION_MASK) -#define GPIO_ROUTE_ETMLOCATION_LOCx(x) GPIO_ROUTE_ETMLOCATION(x) -#define GPIO_ROUTE_ETMLOCATION_LOC0 GPIO_ROUTE_ETMLOCATION_LOCx(0) -#define GPIO_ROUTE_ETMLOCATION_LOC1 GPIO_ROUTE_ETMLOCATION_LOCx(1) -#define GPIO_ROUTE_ETMLOCATION_LOC2 GPIO_ROUTE_ETMLOCATION_LOCx(2) -#define GPIO_ROUTE_ETMLOCATION_LOC3 GPIO_ROUTE_ETMLOCATION_LOCx(3) - -#define GPIO_INSENSE_INT (1 << 0) -#define GPIO_INSENSE_PRS (1 << 1) - -#define GPIO_LOCK_LOCKKEY_SHIFT (0) -#define GPIO_LOCK_LOCKKEY_MASK (0xFFFF << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_UNLOCKED (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_LOCKED (0x0001 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_LOCK (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) -#define GPIO_LOCK_LOCKKEY_UNLOCK (0xA534 << GPIO_LOCK_LOCKKEY_SHIFT) - -#define GPIO_CTRL_EM4RET (1 << 0) - -#define GPIO_CMD_EM4WUCLR (1 << 0) - -#define GPIO_EM4WUEN_EM4WUEN_A0 (1 << 0) -#define GPIO_EM4WUEN_EM4WUEN_A6 (1 << 1) -#define GPIO_EM4WUEN_EM4WUEN_C9 (1 << 2) -#define GPIO_EM4WUEN_EM4WUEN_F1 (1 << 3) -#define GPIO_EM4WUEN_EM4WUEN_F2 (1 << 4) -#define GPIO_EM4WUEN_EM4WUEN_E13 (1 << 5) - -#define GPIO_EM4WUPOL_EM4WUPOL_A0 (1 << 0) -#define GPIO_EM4WUPOL_EM4WUPOL_A6 (1 << 1) -#define GPIO_EM4WUPOL_EM4WUPOL_C9 (1 << 2) -#define GPIO_EM4WUPOL_EM4WUPOL_F1 (1 << 3) -#define GPIO_EM4WUPOL_EM4WUPOL_F2 (1 << 4) -#define GPIO_EM4WUPOL_EM4WUPOL_E13 (1 << 5) - -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL (0xFFFF) - -/* These are the acceptable mode values. - * (+ readable counterparts) - * do not confuse GPIO_MODE_* for GPIO_P_MODE_MODEx. - */ -enum gpio_mode { - GPIO_MODE_DISABLE = 0, - GPIO_MODE_INPUT, - GPIO_MODE_INPUT_PULL, - GPIO_MODE_INPUT_PULL_FILTER, - GPIO_MODE_PUSH_PULL, - GPIO_MODE_PUSH_PULL_DRIVE, - GPIO_MODE_WIRED_OR, - GPIO_MODE_WIRED_OR_PULL_DOWN, - GPIO_MODE_WIRED_AND, - GPIO_MODE_WIRED_AND_FILTER, - GPIO_MODE_WIRED_AND_PULLUP, - GPIO_MODE_WIRED_AND_PULLUP_FILTER, - GPIO_MODE_WIRED_AND_DRIVE, - GPIO_MODE_WIRED_AND_DRIVE_FILTER, - GPIO_MODE_WIRED_AND_DRIVE_PULLUP, - GPIO_MODE_WIRED_AND_DRIVE_PULLUP_FILTER -}; - -/* for readability. */ -enum gpio_drive_strength { - GPIO_STRENGTH_STANDARD = 0, - GPIO_STRENGTH_LOWEST, - GPIO_STRENGTH_HIGH, - GPIO_STRENGTH_LOW -}; - -/* for readability */ -#define GPIOA GPIO_PA -#define GPIOB GPIO_PB -#define GPIOC GPIO_PC -#define GPIOD GPIO_PD -#define GPIOE GPIO_PE -#define GPIOF GPIO_PF - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void gpio_enable_lock(void); -void gpio_disable_lock(void); -bool gpio_get_lock_flag(void); - -void gpio_set_drive_strength(uint32_t gpio_port, - enum gpio_drive_strength driver_stength); -void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios); - -void gpio_set(uint32_t gpio_port, uint16_t gpios); -void gpio_clear(uint32_t gpio_port, uint16_t gpios); -uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios); -void gpio_toggle(uint32_t gpio_port, uint16_t gpios); -uint16_t gpio_port_read(uint32_t gpio_port); -void gpio_port_write(uint32_t gpio_port, uint16_t data); - -void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/i2c_common.h b/libopencm3/include/libopencm3/efm32/common/i2c_common.h deleted file mode 100644 index c9a53fe..0000000 --- a/libopencm3/include/libopencm3/efm32/common/i2c_common.h +++ /dev/null @@ -1,271 +0,0 @@ -/** @addtogroup i2c_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define I2C_CTRL(base) MMIO32((base) + 0x000) -#define I2C_CMD(base) MMIO32((base) + 0x004) -#define I2C_STATE(base) MMIO32((base) + 0x008) -#define I2C_STATUS(base) MMIO32((base) + 0x00C) -#define I2C_CLKDIV(base) MMIO32((base) + 0x010) -#define I2C_SADDR(base) MMIO32((base) + 0x014) -#define I2C_SADDRMASK(base) MMIO32((base) + 0x018) -#define I2C_RXDATA(base) MMIO32((base) + 0x01C) -#define I2C_RXDATAP(base) MMIO32((base) + 0x020) -#define I2C_TXDATA(base) MMIO32((base) + 0x024) -#define I2C_IF(base) MMIO32((base) + 0x028) -#define I2C_IFS(base) MMIO32((base) + 0x02C) -#define I2C_IFC(base) MMIO32((base) + 0x030) -#define I2C_IEN(base) MMIO32((base) + 0x034) -#define I2C_ROUTE(base) MMIO32((base) + 0x038) - -/* I2C_CTRL */ -#define I2C_CTRL_CLTO_SHIFT (16) -#define I2C_CTRL_CLTO_MASK (0x7 << I2C_CTRL_CLTO_SHIFT) -#define I2C_CTRL_CLTO(v) \ - (((v) << I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK) -#define I2C_CTRL_CLTO_OFF 0 -#define I2C_CTRL_CLTO_40PCC 1 -#define I2C_CTRL_CLTO_80PCC 2 -#define I2C_CTRL_CLTO_160PCC 3 -#define I2C_CTRL_CLTO_320PPC 4 -#define I2C_CTRL_CLTO_1024PPC 5 - -#define I2C_CTRL_GIBITO (1 << 15) - -#define I2C_CTRL_BTO_SHIFT (12) -#define I2C_CTRL_BTO_MASK (0x3 << I2C_CTRL_BTO_SHIFT) -#define I2C_CTRL_BTO(v) \ - (((v) << I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK) -#define I2C_CTRL_BTO_OFF 0 -#define I2C_CTRL_BTO_40PCC 1 -#define I2C_CTRL_BTO_80PCC 2 -#define I2C_CTRL_BTO_160PCC 3 - -#define I2C_CTRL_CLHR_SHIFT (12) -#define I2C_CTRL_CLHR_MASK (0x3 << I2C_CTRL_CLHR_SHIFT) -#define I2C_CTRL_CLHR(v) \ - (((v) << I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK) -#define I2C_CTRL_CLHR_STANDARD 0 -#define I2C_CTRL_CLHR_ASYMMETRIC 1 -#define I2C_CTRL_CLHR_FAST 2 - -#define I2C_CTRL_GCAMEN (1 << 6) -#define I2C_CTRL_ARBDIS (1 << 5) -#define I2C_CTRL_AUTOSN (1 << 4) -#define I2C_CTRL_AUTOSE (1 << 3) -#define I2C_CTRL_AUTOACK (1 << 2) -#define I2C_CTRL_SLAVE (1 << 1) -#define I2C_CTRL_EN (1 << 0) - -/* I2C_CMD */ -#define I2C_CMD_CLEARPC (1 << 7) -#define I2C_CMD_CLEARTX (1 << 6) -#define I2C_CMD_ABORT (1 << 5) -#define I2C_CMD_CONT (1 << 4) -#define I2C_CMD_NACK (1 << 3) -#define I2C_CMD_ACK (1 << 2) -#define I2C_CMD_STOP (1 << 1) -#define I2C_CMD_START (1 << 0) - -/* I2C_STATE */ -#define I2C_STATE_STATE_SHIFT (5) -#define I2C_STATE_STATE_MASK (0x7 << I2C_STATE_STATE_SHIFT) -#define I2C_STATE_STATE(v) \ - (((v) << I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK) -#define I2C_STATE_STATE_IDLE 0 -#define I2C_STATE_STATE_WAIT 1 -#define I2C_STATE_STATE_START 2 -#define I2C_STATE_STATE_ADDR 3 -#define I2C_STATE_STATE_ADDRACK 4 -#define I2C_STATE_STATE_DATA 5 -#define I2C_STATE_STATE_DATAACK 6 - -#define I2C_STATE_BUSHOLD (1 << 4) -#define I2C_STATE_NACKED (1 << 3) -#define I2C_STATE_TRANSMITTER (1 << 2) -#define I2C_STATE_MASTER (1 << 1) -#define I2C_STATE_BUSY (1 << 0) - -/* I2C_STATUS */ -#define I2C_STATUS_RXDATAV (1 << 8) -#define I2C_STATUS_TXBL (1 << 7) -#define I2C_STATUS_TXC (1 << 6) -#define I2C_STATUS_PABORT (1 << 5) -#define I2C_STATUS_PCONT (1 << 4) -#define I2C_STATUS_PNACK (1 << 3) -#define I2C_STATUS_PACK (1 << 2) -#define I2C_STATUS_PSTOP (1 << 1) -#define I2C_STATUS_PSTART (1 << 0) - -/* I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_SHIFT (0) -#define I2C_CLKDIV_DIV_MASK (0xFF << I2C_CLKDIV_DIV_SHIFT) -#define I2C_CLKDIV_DIV(v) \ - (((v) << I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK) - -/* I2C_SADDR */ -#define I2C_SADDR_ADDR_SHIFT (0) -#define I2C_SADDR_ADDR_MASK (0xFF << I2C_SADDR_ADDR_SHIFT) -#define I2C_SADDR_ADDR(v) \ - (((v) << I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK) - -/* I2C_SADDRMASK */ -#define I2C_SADDRMASK_MASK_SHIFT (0) -#define I2C_SADDRMASK_MASK_MASK (0xFF << I2C_SADDRMASK_MASK_SHIFT) -#define I2C_SADDRMASK_MASK(v) \ - (((v) << I2C_SADDRMASK_MASK_SHIFT) & I2C_SADDRMASK_MASK_MASK) - -/* I2C_IF */ -#define I2C_IF_SSTOP (1 << 16) -#define I2C_IF_CLTO (1 << 15) -#define I2C_IF_BITO (1 << 14) -#define I2C_IF_RXUF (1 << 13) -#define I2C_IF_TXOF (1 << 12) -#define I2C_IF_BUSHOLD (1 << 11) -#define I2C_IF_BUSERR (1 << 10) -#define I2C_IF_ARBLOST (1 << 9) -#define I2C_IF_MSTOP (1 << 8) -#define I2C_IF_NACK (1 << 7) -#define I2C_IF_ACK (1 << 6) -#define I2C_IF_RXDATAV (1 << 5) -#define I2C_IF_TXBL (1 << 4) -#define I2C_IF_TXC (1 << 3) -#define I2C_IF_ADDR (1 << 2) -#define I2C_IF_RSTART (1 << 1) -#define I2C_IF_START (1 << 0) - -/* I2C_IFS */ -#define I2C_IFS_SSTOP (1 << 16) -#define I2C_IFS_CLTO (1 << 15) -#define I2C_IFS_BITO (1 << 14) -#define I2C_IFS_RXUF (1 << 13) -#define I2C_IFS_TXOF (1 << 12) -#define I2C_IFS_BUSHOLD (1 << 11) -#define I2C_IFS_BUSERR (1 << 10) -#define I2C_IFS_ARBLOST (1 << 9) -#define I2C_IFS_MSTOP (1 << 8) -#define I2C_IFS_NACK (1 << 7) -#define I2C_IFS_ACK (1 << 6) -#define I2C_IFS_RXDATAV (1 << 5) -#define I2C_IFS_TXBL (1 << 4) -#define I2C_IFS_TXC (1 << 3) -#define I2C_IFS_ADDR (1 << 2) -#define I2C_IFS_RSTART (1 << 1) -#define I2C_IFS_START (1 << 0) - -/* I2C_IFC */ -#define I2C_IFC_SSTOP (1 << 16) -#define I2C_IFC_CLTO (1 << 15) -#define I2C_IFC_BITO (1 << 14) -#define I2C_IFC_RXUF (1 << 13) -#define I2C_IFC_TXOF (1 << 12) -#define I2C_IFC_BUSHOLD (1 << 11) -#define I2C_IFC_BUSERR (1 << 10) -#define I2C_IFC_ARBLOST (1 << 9) -#define I2C_IFC_MSTOP (1 << 8) -#define I2C_IFC_NACK (1 << 7) -#define I2C_IFC_ACK (1 << 6) -#define I2C_IFC_RXDATAV (1 << 5) -#define I2C_IFC_TXBL (1 << 4) -#define I2C_IFC_TXC (1 << 3) -#define I2C_IFC_ADDR (1 << 2) -#define I2C_IFC_RSTART (1 << 1) -#define I2C_IFC_START (1 << 0) - -/* I2C_IEN */ -#define I2C_IEN_SSTOP (1 << 16) -#define I2C_IEN_CLTO (1 << 15) -#define I2C_IEN_BITO (1 << 14) -#define I2C_IEN_RXUF (1 << 13) -#define I2C_IEN_TXOF (1 << 12) -#define I2C_IEN_BUSHOLD (1 << 11) -#define I2C_IEN_BUSERR (1 << 10) -#define I2C_IEN_ARBLOST (1 << 9) -#define I2C_IEN_MSTOP (1 << 8) -#define I2C_IEN_NACK (1 << 7) -#define I2C_IEN_ACK (1 << 6) -#define I2C_IEN_RXDATAV (1 << 5) -#define I2C_IEN_TXBL (1 << 4) -#define I2C_IEN_TXC (1 << 3) -#define I2C_IEN_ADDR (1 << 2) -#define I2C_IEN_RSTART (1 << 1) -#define I2C_IEN_START (1 << 0) - -/* I2C_ROUTE */ -#define I2C_ROUTE_LOCATION_SHIFT (8) -#define I2C_ROUTE_LOCATION_MASK (0x7 << I2C_ROUTE_LOCATION_SHIFT) -#define I2C_ROUTE_LOCATION(v) \ - (((v) << I2C_ROUTE_LOCATION_SHIFT) & I2C_ROUTE_LOCATION_MASK) -#define I2C_ROUTE_LOCATION_LOCx(x) I2C_ROUTE_LOCATION(x) -#define I2C_ROUTE_LOCATION_LOC0 0 -#define I2C_ROUTE_LOCATION_LOC1 1 -#define I2C_ROUTE_LOCATION_LOC2 2 -#define I2C_ROUTE_LOCATION_LOC3 3 -#define I2C_ROUTE_LOCATION_LOC4 4 -#define I2C_ROUTE_LOCATION_LOC5 5 -#define I2C_ROUTE_LOCATION_LOC6 6 - -#define I2C_ROUTE_SCLPEN (1 << 1) -#define I2C_ROUTE_SDAPEN (1 << 0) - -/* I2C0 */ -#define I2C0 I2C0_BASE -#define I2C0_CTRL I2C_CTRL(I2C0) -#define I2C0_CMD I2C_CMD(I2C0) -#define I2C0_STATE I2C_STATE(I2C0) -#define I2C0_STATUS I2C_STATUS(I2C0) -#define I2C0_CLKDIV I2C_CLKDIV(I2C0) -#define I2C0_SADDR I2C_SADDR(I2C0) -#define I2C0_SADDRMASK I2C_SADDRMASK(I2C0) -#define I2C0_RXDATA I2C_RXDATA(I2C0) -#define I2C0_RXDATAP I2C_RXDATAP(I2C0) -#define I2C0_TXDATA I2C_TXDATA(I2C0) -#define I2C0_IF I2C_IF(I2C0) -#define I2C0_IFS I2C_IFS(I2C0) -#define I2C0_IFC I2C_IFC(I2C0) -#define I2C0_IEN I2C_IEN(I2C0) -#define I2C0_ROUTE I2C_ROUTE(I2C0) - -/* I2C1 */ -#define I2C1 I2C1_BASE -#define I2C1_CTRL I2C_CTRL(I2C1) -#define I2C1_CMD I2C_CMD(I2C1) -#define I2C1_STATE I2C_STATE(I2C1) -#define I2C1_STATUS I2C_STATUS(I2C1) -#define I2C1_CLKDIV I2C_CLKDIV(I2C1) -#define I2C1_SADDR I2C_SADDR(I2C1) -#define I2C1_SADDRMASK I2C_SADDRMASK(I2C1) -#define I2C1_RXDATA I2C_RXDATA(I2C1) -#define I2C1_RXDATAP I2C_RXDATAP(I2C1) -#define I2C1_TXDATA I2C_TXDATA(I2C1) -#define I2C1_IF I2C_IF(I2C1) -#define I2C1_IFS I2C_IFS(I2C1) -#define I2C1_IFC I2C_IFC(I2C1) -#define I2C1_IEN I2C_IEN(I2C1) -#define I2C1_ROUTE I2C_ROUTE(I2C1) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/letimer_common.h b/libopencm3/include/libopencm3/efm32/common/letimer_common.h deleted file mode 100644 index a782673..0000000 --- a/libopencm3/include/libopencm3/efm32/common/letimer_common.h +++ /dev/null @@ -1,167 +0,0 @@ -/** @addtogroup letimer_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define LETIMER_CTRL(base) ((base) + 0x000) -#define LETIMER_CMD(base) ((base) + 0x004) -#define LETIMER_STATUS(base) ((base) + 0x008) -#define LETIMER_CNT(base) ((base) + 0x00C) -#define LETIMER_COMP0(base) ((base) + 0x010) -#define LETIMER_COMP1(base) ((base) + 0x014) -#define LETIMER_REP0(base) ((base) + 0x018) -#define LETIMER_REP1(base) ((base) + 0x01C) -#define LETIMER_IF(base) ((base) + 0x020) -#define LETIMER_IFS(base) ((base) + 0x024) -#define LETIMER_IFC(base) ((base) + 0x028) -#define LETIMER_IEN(base) ((base) + 0x02C) -#define LETIMER_FREEZE(base) ((base) + 0x030) -#define LETIMER_SYNCBUSY(base) ((base) + 0x034) -#define LETIMER_ROUTE(base) ((base) + 0x040) - -/* LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUG (1 << 12) -#define LETIMER_CTRL_RTCC1TEN (1 << 11) -#define LETIMER_CTRL_RTCC0TEN (1 << 10) -#define LETIMER_CTRL_COMP0TOP (1 << 9) -#define LETIMER_CTRL_BUFTOP (1 << 8) -#define LETIMER_CTRL_OPOL1 (1 << 7) -#define LETIMER_CTRL_OPOL0 (1 << 6) - -#define LETIMER_CTRL_UFOA1_SHIFT (4) -#define LETIMER_CTRL_UFOA1_MASK (0x3 << LETIMER_CTRL_UFOA1_SHIFT) -#define LETIMER_CTRL_UFOA1(v) \ - (((v) << LETIMER_CTRL_UFOA1_SHIFT) & LETIMER_CTRL_UFOA1_MASK) -#define LETIMER_CTRL_UFOA1_NONE 0 -#define LETIMER_CTRL_UFOA1_TOGGLE 1 -#define LETIMER_CTRL_UFOA1_PULSE 2 -#define LETIMER_CTRL_UFOA1_PWM 3 - -#define LETIMER_CTRL_UFOA0_SHIFT (2) -#define LETIMER_CTRL_UFOA0_MASK (0x3 << LETIMER_CTRL_UFOA0_SHIFT) -#define LETIMER_CTRL_UFOA0(v) \ - (((v) << LETIMER_CTRL_UFOA0_SHIFT) & LETIMER_CTRL_UFOA0_MASK) -#define LETIMER_CTRL_UFOA0_NONE 0 -#define LETIMER_CTRL_UFOA0_TOGGLE 1 -#define LETIMER_CTRL_UFOA0_PULSE 2 -#define LETIMER_CTRL_UFOA0_PWM 3 - -#define LETIMER_CTRL_REPMODE_SHIFT (2) -#define LETIMER_CTRL_REPMODE_MASK (0x3 << LETIMER_CTRL_REPMODE_SHIFT) -#define LETIMER_CTRL_REPMODE(v) \ - (((v) << LETIMER_CTRL_REPMODE_SHIFT) & LETIMER_CTRL_REPMODE_MASK) -#define LETIMER_CTRL_REPMODE_FREE 0 -#define LETIMER_CTRL_REPMODE_ONESHOT 1 -#define LETIMER_CTRL_REPMODE_BUFFERED 2 -#define LETIMER_CTRL_REPMODE_DOUBLE 3 -#define LETIMER_CTRL_REPMODE_ONE_SHOT LETIMER_CTRL_REPMODE_ONESHOT - -/* LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (1 << 4) -#define LETIMER_CMD_CTO0 (1 << 3) -#define LETIMER_CMD_CLEAR (1 << 2) -#define LETIMER_CMD_STOP (1 << 1) -#define LETIMER_CMD_START (1 << 0) - -/* LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (1 << 0) - -/* LETIMER_IF */ -#define LETIMER_IF_REP1 (1 << 4) -#define LETIMER_IF_REP0 (1 << 3) -#define LETIMER_IF_UF (1 << 2) -#define LETIMER_IF_COMP1 (1 << 1) -#define LETIMER_IF_COMP0 (1 << 0) - -/* LETIMER_IFS */ -#define LETIMER_IFS_REP1 (1 << 4) -#define LETIMER_IFS_REP0 (1 << 3) -#define LETIMER_IFS_UF (1 << 2) -#define LETIMER_IFS_COMP1 (1 << 1) -#define LETIMER_IFS_COMP0 (1 << 0) - -/* LETIMER_IFC */ -#define LETIMER_IFC_REP1 (1 << 4) -#define LETIMER_IFC_REP0 (1 << 3) -#define LETIMER_IFC_UF (1 << 2) -#define LETIMER_IFC_COMP1 (1 << 1) -#define LETIMER_IFC_COMP0 (1 << 0) - -/* LETIMER_IFE */ -#define LETIMER_IFE_REP1 (1 << 4) -#define LETIMER_IFE_REP0 (1 << 3) -#define LETIMER_IFE_UF (1 << 2) -#define LETIMER_IFE_COMP1 (1 << 1) -#define LETIMER_IFE_COMP0 (1 << 0) - -/* LETIMER_FREEZE */ -#define LETIMER_FREEZE_REGFREEZE (1 << 0) - -/* LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (1 << 5) -#define LETIMER_SYNCBUSY_REP0 (1 << 4) -#define LETIMER_SYNCBUSY_COMP1 (1 << 3) -#define LETIMER_SYNCBUSY_COMP0 (1 << 2) -#define LETIMER_SYNCBUSY_CMD (1 << 1) -#define LETIMER_SYNCBUSY_CTRL (1 << 0) - -/* LETIMER_ROUTE */ -#define LETIMER_ROUTE_LOCATION_SHIFT (8) -#define LETIMER_ROUTE_LOCATION_MASK (0x7 << LETIMER_ROUTE_LOCATION_SHIFT) -#define LETIMER_ROUTE_LOCATION(v) \ - (((v) << LETIMER_ROUTE_LOCATION_SHIFT) & LETIMER_ROUTE_LOCATION_MASK) -#define LETIMER_ROUTE_LOCATION_LOCx(x) LETIMER_ROUTE_LOCATION(x) -#define LETIMER_ROUTE_LOCATION_LOC0 0 -#define LETIMER_ROUTE_LOCATION_LOC1 1 -#define LETIMER_ROUTE_LOCATION_LOC2 2 -#define LETIMER_ROUTE_LOCATION_LOC3 3 -#define LETIMER_ROUTE_LOCATION_LOC4 4 -#define LETIMER_ROUTE_LOCATION_LOC5 5 -#define LETIMER_ROUTE_LOCATION_LOC6 6 -#define LETIMER_ROUTE_LOCATION_LOC7 7 - -#define LETIMER_ROUTE_OUT1PEN (1 << 1) -#define LETIMER_ROUTE_OUT0PEN (1 << 0) - -/* LETIMER0 */ -#define LETIMER0 LETIMER0_BASE -#define LETIMER0_CTRL LETIMER_CTRL(LETIMER0) -#define LETIMER0_CMD LETIMER_CMD(LETIMER0) -#define LETIMER0_STATUS LETIMER_STATUS(LETIMER0) -#define LETIMER0_CNT LETIMER_CNT(LETIMER0) -#define LETIMER0_COMP0 LETIMER_COMP0(LETIMER0) -#define LETIMER0_COMP1 LETIMER_COMP1(LETIMER0) -#define LETIMER0_REP0 LETIMER_REP0(LETIMER0) -#define LETIMER0_REP1 LETIMER_REP1(LETIMER0) -#define LETIMER0_IF LETIMER_IF(LETIMER0) -#define LETIMER0_IFS LETIMER_IFS(LETIMER0) -#define LETIMER0_IFC LETIMER_IFC(LETIMER0) -#define LETIMER0_IEN LETIMER_IEN(LETIMER0) -#define LETIMER0_FREEZE LETIMER_FREEZE(LETIMER0) -#define LETIMER0_SYNCBUSY LETIMER_SYNCBUSY(LETIMER0) -#define LETIMER0_ROUTE LETIMER_ROUTE(LETIMER0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/msc_common.h b/libopencm3/include/libopencm3/efm32/common/msc_common.h deleted file mode 100644 index 34932c6..0000000 --- a/libopencm3/include/libopencm3/efm32/common/msc_common.h +++ /dev/null @@ -1,156 +0,0 @@ -/** @addtogroup msc_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define MSC_CTRL MMIO32(MSC_BASE + 0x000) -#define MSC_READCTRL MMIO32(MSC_BASE + 0x004) -#define MSC_WRITECTRL MMIO32(MSC_BASE + 0x008) -#define MSC_WRITECMD MMIO32(MSC_BASE + 0x00C) -#define MSC_ADDRB MMIO32(MSC_BASE + 0x010) -#define MSC_WDATA MMIO32(MSC_BASE + 0x018) -#define MSC_STATUS MMIO32(MSC_BASE + 0x01C) -#define MSC_IF MMIO32(MSC_BASE + 0x02C) -#define MSC_IFS MMIO32(MSC_BASE + 0x030) -#define MSC_IFC MMIO32(MSC_BASE + 0x034) -#define MSC_IEN MMIO32(MSC_BASE + 0x038) -#define MSC_LOCK MMIO32(MSC_BASE + 0x03C) -#define MSC_CMD MMIO32(MSC_BASE + 0x040) -#define MSC_CACHEHITS MMIO32(MSC_BASE + 0x044) -#define MSC_CACHEMISSES MMIO32(MSC_BASE + 0x048) -#define MSC_TIMEBASE MMIO32(MSC_BASE + 0x050) -#define MSC_MASSLOCK MMIO32(MSC_BASE + 0x054) - -/* MSC_CTRL */ -#define MSC_CTRL_BUSFAULT (1 << 0) - -/* MSC_READCTRL */ -#define MSC_READCTRL_BUSSTRATEGY_SHIFT (16) -#define MSC_READCTRL_BUSSTRATEGY_MASK \ - (0x3 << MSC_READCTRL_BUSSTRATEGY_SHIFT) -#define MSC_READCTRL_BUSSTRATEGY(v) \ - (((v) << MSC_READCTRL_BUSSTRATEGY_SHIFT) & \ - MSC_READCTRL_BUSSTRATEGY_MASK) - -#define MSC_READCTRL_BUSSTRATEGY_CPU MSC_READCTRL_BUSSTRATEGY(0) -#define MSC_READCTRL_BUSSTRATEGY_DMA MSC_READCTRL_BUSSTRATEGY(1) -#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 MSC_READCTRL_BUSSTRATEGY(2) -#define MSC_READCTRL_BUSSTRATEGY_NONE MSC_READCTRL_BUSSTRATEGY(3) - -#define MSC_READCTRL_RAMCEN (1 << 7) -#define MSC_READCTRL_EBICDIS (1 << 6) -#define MSC_READCTRL_ICCDIS (1 << 5) -#define MSC_READCTRL_AIDIS (1 << 4) -#define MSC_READCTRL_IFCDIS (1 << 3) - -#define MSC_READCTRL_MODE_SHIFT (0) -#define MSC_READCTRL_MODE_MASK (0x7 << MSC_READCTRL_MODE_SHIFT) -#define MSC_READCTRL_MODE(v) \ - (((v) << MSC_READCTRL_MODE_SHIFT) & MSC_READCTRL_MODE_MASK) -#define MSC_READCTRL_MODE_WS0 0 -#define MSC_READCTRL_MODE_WS1 1 -#define MSC_READCTRL_MODE_WS0SCBTP 2 -#define MSC_READCTRL_MODE_WS1SCBTP 3 -#define MSC_READCTRL_MODE_WS2 4 -#define MSC_READCTRL_MODE_WS2SCBTP 5 - -/* MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT (1 << 1) -#define MSC_WRITECTRL_WREN (1 << 0) - -/* MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA (1 << 12) -#define MSC_WRITECMD_ERASEMAIN0 (1 << 8) -#define MSC_WRITECMD_ERASEABORT (1 << 5) -#define MSC_WRITECMD_WRITETRIG (1 << 4) -#define MSC_WRITECMD_WRITEONCE (1 << 3) -#define MSC_WRITECMD_WRITEEND (1 << 2) -#define MSC_WRITECMD_ERASEPAGE (1 << 1) -#define MSC_WRITECMD_LADDRIM (1 << 0) - -/* MSC_STATUS */ -#define MSC_STATUS_PCRUNNING (1 << 6) -#define MSC_STATUS_ERASEABORTED (1 << 5) -#define MSC_STATUS_WORDTIMEOUT (1 << 4) -#define MSC_STATUS_WDATAREADY (1 << 3) -#define MSC_STATUS_INVADDR (1 << 2) -#define MSC_STATUS_LOCKED (1 << 1) -#define MSC_STATUS_BUSY (1 << 0) - -/* MSC_IF */ -#define MSC_IF_CMOF (1 << 3) -#define MSC_IF_CHOF (1 << 2) -#define MSC_IF_WRITE (1 << 1) -#define MSC_IF_ERASE (1 << 0) - -/* MSC_IFS */ -#define MSC_IFS_CMOF (1 << 3) -#define MSC_IFS_CHOF (1 << 2) -#define MSC_IFS_WRITE (1 << 1) -#define MSC_IFS_ERASE (1 << 0) - -/* MSC_IFC */ -#define MSC_IFC_CMOF (1 << 3) -#define MSC_IFC_CHOF (1 << 2) -#define MSC_IFC_WRITE (1 << 1) -#define MSC_IFC_ERASE (1 << 0) - -/* MSC_*IEN */ -#define MSC_IEN_CMOF (1 << 3) -#define MSC_IEN_CHOF (1 << 2) -#define MSC_IEN_WRITE (1 << 1) -#define MSC_IEN_ERASE (1 << 0) - -/* MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_SHIFT (0) -#define MSC_LOCK_LOCKKEY(v) ((v) << MSC_LOCK_LOCKKEY_SHIFT) -#define MSC_LOCK_LOCKKEY_UNLOCKED MSC_LOCK_LOCKKEY(0) -#define MSC_LOCK_LOCKKEY_LOCKED MSC_LOCK_LOCKKEY(1) -#define MSC_LOCK_LOCKKEY_LOCK MSC_LOCK_LOCKKEY(0) -#define MSC_LOCK_LOCKKEY_UNLOCK MSC_LOCK_LOCKKEY(0x1B71) - -/* MSC_CMD */ -#define MSC_CMD_STOPPC (1 << 2) -#define MSC_CMD_STARTPC (1 << 1) -#define MSC_CMD_INVCACHE (1 << 0) - -/* MSC_TIMEBASE */ -#define MSC_TIMEBASE_PERIOD (1 << 16) - -#define MSC_TIMEBASE_BASE_SHIFT (0) -#define MSC_TIMEBASE_BASE_MASK (0x3F << MSC_TIMEBASE_BASE_SHIFT) -#define MSC_TIMEBASE_BASE(v) \ - (((v) << MSC_TIMEBASE_BASE_SHIFT) & MSC_TIMEBASE_BASE_MASK) - -/* MSC_MASSLOCK */ -#define MSC_MASSLOCK_LOCKKEY_SHIFT (0) -#define MSC_MASSLOCK_LOCKKEY(v) ((v) << MSC_MASSLOCK_LOCKKEY_SHIFT) -#define MSC_MASSLOCK_LOCKKEY_UNLOCKED MSC_MASSLOCK_LOCKKEY(0) -#define MSC_MASSLOCK_LOCKKEY_LOCKED MSC_MASSLOCK_LOCKKEY(1) -#define MSC_MASSLOCK_LOCKKEY_LOCK MSC_MASSLOCK_LOCKKEY(0) -#define MSC_MASSLOCK_LOCKKEY_UNLOCK MSC_MASSLOCK_LOCKKEY(0x631A) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/opamp_common.h b/libopencm3/include/libopencm3/efm32/common/opamp_common.h deleted file mode 100644 index 2982909..0000000 --- a/libopencm3/include/libopencm3/efm32/common/opamp_common.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* OpAmp register are in dac.h */ -#include diff --git a/libopencm3/include/libopencm3/efm32/common/prs_common.h b/libopencm3/include/libopencm3/efm32/common/prs_common.h deleted file mode 100644 index fa8bad1..0000000 --- a/libopencm3/include/libopencm3/efm32/common/prs_common.h +++ /dev/null @@ -1,365 +0,0 @@ -/** @addtogroup prs_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define PRS_SWPULSE MMIO32(PRS_BASE + 0x000) -#define PRS_SWLEVEL MMIO32(PRS_BASE + 0x004) -#define PRS_ROUTE MMIO32(PRS_BASE + 0x008) -#define PRS_CHx_CTRL(x) MMIO32(PRS_BASE + 0x010 + (0x004 * (x))) -#define PRS_CH0_CTRL PRS_CHx_CTRL(0) -#define PRS_CH1_CTRL PRS_CHx_CTRL(1) -#define PRS_CH2_CTRL PRS_CHx_CTRL(2) -#define PRS_CH3_CTRL PRS_CHx_CTRL(3) -#define PRS_CH4_CTRL PRS_CHx_CTRL(4) -#define PRS_CH5_CTRL PRS_CHx_CTRL(5) -#define PRS_CH6_CTRL PRS_CHx_CTRL(6) -#define PRS_CH7_CTRL PRS_CHx_CTRL(71) -#define PRS_CH8_CTRL PRS_CHx_CTRL(8) -#define PRS_CH9_CTRL PRS_CHx_CTRL(9) -#define PRS_CH10_CTRL PRS_CHx_CTRL(10) -#define PRS_CH11_CTRL PRS_CHx_CTRL(11) - -/* PRS_SWPULSE */ -#define PRS_SWPULSE_CHxPULSE(x) (1 << (x)) -#define PRS_SWPULSE_CH0PULSE PRS_SWPULSE_CHxPULSE(0) -#define PRS_SWPULSE_CH1PULSE PRS_SWPULSE_CHxPULSE(1) -#define PRS_SWPULSE_CH2PULSE PRS_SWPULSE_CHxPULSE(2) -#define PRS_SWPULSE_CH3PULSE PRS_SWPULSE_CHxPULSE(3) -#define PRS_SWPULSE_CH4PULSE PRS_SWPULSE_CHxPULSE(4) -#define PRS_SWPULSE_CH5PULSE PRS_SWPULSE_CHxPULSE(5) -#define PRS_SWPULSE_CH6PULSE PRS_SWPULSE_CHxPULSE(6) -#define PRS_SWPULSE_CH7PULSE PRS_SWPULSE_CHxPULSE(7) -#define PRS_SWPULSE_CH8PULSE PRS_SWPULSE_CHxPULSE(8) -#define PRS_SWPULSE_CH9PULSE PRS_SWPULSE_CHxPULSE(9) -#define PRS_SWPULSE_CH10PULSE PRS_SWPULSE_CHxPULSE(10) -#define PRS_SWPULSE_CH11PULSE PRS_SWPULSE_CHxPULSE(11) - -/* PRS_SWLEVEL */ -#define PRS_SWLEVEL_CHxLEVEL(x) (1 << (x)) -#define PRS_SWLEVEL_CH0LEVEL PRS_SWLEVEL_CHxLEVEL(0) -#define PRS_SWLEVEL_CH1LEVEL PRS_SWLEVEL_CHxLEVEL(1) -#define PRS_SWLEVEL_CH2LEVEL PRS_SWLEVEL_CHxLEVEL(2) -#define PRS_SWLEVEL_CH3LEVEL PRS_SWLEVEL_CHxLEVEL(3) -#define PRS_SWLEVEL_CH4LEVEL PRS_SWLEVEL_CHxLEVEL(4) -#define PRS_SWLEVEL_CH5LEVEL PRS_SWLEVEL_CHxLEVEL(5) -#define PRS_SWLEVEL_CH6LEVEL PRS_SWLEVEL_CHxLEVEL(6) -#define PRS_SWLEVEL_CH7LEVEL PRS_SWLEVEL_CHxLEVEL(7) -#define PRS_SWLEVEL_CH8LEVEL PRS_SWLEVEL_CHxLEVEL(8) -#define PRS_SWLEVEL_CH9LEVEL PRS_SWLEVEL_CHxLEVEL(9) -#define PRS_SWLEVEL_CH10LEVEL PRS_SWLEVEL_CHxLEVEL(10) -#define PRS_SWLEVEL_CH11LEVEL PRS_SWLEVEL_CHxLEVEL(11) - -/* PRS_ROUTE */ -#define PRS_ROUTE_LOCATION_SHIFT (8) -#define PRS_ROUTE_LOCATION_MASK (0x7 << PRS_ROUTE_LOCATION_SHIFT) -#define PRS_ROUTE_LOCATION(v) \ - (((v) << PRS_ROUTE_LOCATION_SHIFT) & PRS_ROUTE_LOCATION_MASK) -#define PRS_ROUTE_LOCATION_LOCx(x) PRS_ROUTE_LOCATION(x) -#define PRS_ROUTE_LOCATION_LOC0 0 -#define PRS_ROUTE_LOCATION_LOC1 1 - -#define PRS_ROUTE_CHxPEN(x) (1 << (x)) -#define PRS_ROUTE_CH3PEN PRS_ROUTE_CHxPEN(3) -#define PRS_ROUTE_CH2PEN PRS_ROUTE_CHxPEN(2) -#define PRS_ROUTE_CH1PEN PRS_ROUTE_CHxPEN(1) -#define PRS_ROUTE_CH0PEN PRS_ROUTE_CHxPEN(0) - -/* PRS_CHx_CTRL */ -#define PRS_CH_CTRL_ASYNC (1 << 28) - -#define PRS_CH_CTRL_EDSEL_SHIFT (24) -#define PRS_CH_CTRL_EDSEL_MASK (0x3 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_OFF (0 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_POSEDGE (1 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_NEGEDGE (2 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_BOTHEDGES (3 << PRS_CH_CTRL_EDSEL_SHIFT) - -#define PRS_CH_CTRL_SOURCESEL_SHIFT (16) -#define PRS_CH_CTRL_SOURCESEL_MASK (0x3F << PRS_CH_CTRL_SOURCESEL_SHIFT) -#define PRS_CH_CTRL_SOURCESEL(v) \ - (((v) << PRS_CH_CTRL_SOURCESEL_SHIFT) & PRS_CH_CTRL_SOURCESEL_MASK) -#define PRS_CH_CTRL_SOURCESEL_NONE 0b000000 -#define PRS_CH_CTRL_SOURCESEL_VCMP 0b000001 -#define PRS_CH_CTRL_SOURCESEL_ACMP0 0b000010 -#define PRS_CH_CTRL_SOURCESEL_ACMP1 0b000011 -#define PRS_CH_CTRL_SOURCESEL_DAC0 0b000110 -#define PRS_CH_CTRL_SOURCESEL_ADC0 0b001000 -#define PRS_CH_CTRL_SOURCESEL_USART0 0b010000 -#define PRS_CH_CTRL_SOURCESEL_USART1 0b010001 -#define PRS_CH_CTRL_SOURCESEL_USART2 0b010010 -#define PRS_CH_CTRL_SOURCESEL_TIMER0 0b011100 -#define PRS_CH_CTRL_SOURCESEL_TIMER1 0b011101 -#define PRS_CH_CTRL_SOURCESEL_TIMER2 0b011110 -#define PRS_CH_CTRL_SOURCESEL_TIMER3 0b011111 -#define PRS_CH_CTRL_SOURCESEL_USB 0b100100 -#define PRS_CH_CTRL_SOURCESEL_RTC 0b101000 -#define PRS_CH_CTRL_SOURCESEL_UART0 0b101001 -#define PRS_CH_CTRL_SOURCESEL_UART1 0b101010 -#define PRS_CH_CTRL_SOURCESEL_GPIOL 0b110000 -#define PRS_CH_CTRL_SOURCESEL_GPIOH 0b110001 -#define PRS_CH_CTRL_SOURCESEL_LETIMER0 0b110100 -#define PRS_CH_CTRL_SOURCESEL_BURTC 0b110111 -#define PRS_CH_CTRL_SOURCESEL_LESENSEL 0b111001 -#define PRS_CH_CTRL_SOURCESEL_LESENSEH 0b111010 -#define PRS_CH_CTRL_SOURCESEL_LESENSED 0b111011 - -#define PRS_CH_CTRL_SIGSEL_SHIFT (0) -#define PRS_CH_CTRL_SIGSEL_MASK (0x7 << PRS_CH_CTRL_SIGSEL_SHIFT) -#define PRS_CH_CTRL_SIGSEL(v) \ - (((v) << PRS_CH_CTRL_SIGSEL_SHIFT) & PRS_CH_CTRL_SIGSEL_MASK) -#define PRS_CH_CTRL_SIGSEL_OFF 0 -#define PRS_CH_CTRL_SIGSEL_VCMPOUT 0 -#define PRS_CH_CTRL_SIGSEL_ACMP0OUT 0 -#define PRS_CH_CTRL_SIGSEL_ACMP1OUT 0 -#define PRS_CH_CTRL_SIGSEL_DAC0CH0 0 -#define PRS_CH_CTRL_SIGSEL_DAC0CH1 1 -#define PRS_CH_CTRL_SIGSEL_ADCSINGLE 0 -#define PRS_CH_CTRL_SIGSEL_ADCSCAN 1 -#define PRS_CH_CTRL_SIGSEL_USART0IRTX 0 -#define PRS_CH_CTRL_SIGSEL_USART0TXC 1 -#define PRS_CH_CTRL_SIGSEL_USART0RXDATA 2 -#define PRS_CH_CTRL_SIGSEL_USART1TXC 1 -#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_USART2TXC 1 -#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_TIMER0UF 0 -#define PRS_CH_CTRL_SIGSEL_TIMER0OF 1 -#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 2 -#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 3 -#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 4 -#define PRS_CH_CTRL_SIGSEL_TIMER1UF 0 -#define PRS_CH_CTRL_SIGSEL_TIMER1OF 1 -#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 2 -#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 3 -#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 4 -#define PRS_CH_CTRL_SIGSEL_TIMER2UF 0 -#define PRS_CH_CTRL_SIGSEL_TIMER2OF 1 -#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 2 -#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 3 -#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 4 -#define PRS_CH_CTRL_SIGSEL_TIMER3UF 0 -#define PRS_CH_CTRL_SIGSEL_TIMER3OF 1 -#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 2 -#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 3 -#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 4 -#define PRS_CH_CTRL_SIGSEL_USBSOF 0 -#define PRS_CH_CTRL_SIGSEL_USBSOFSR 1 -#define PRS_CH_CTRL_SIGSEL_RTCOF 0 -#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 1 -#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 2 -#define PRS_CH_CTRL_SIGSEL_UART0TXC 1 -#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_UART1TXC 1 -#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 0 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 1 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 2 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 3 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 4 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 5 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 6 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 7 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 0 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 1 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 2 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 3 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 4 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 5 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 6 -#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 7 -#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0 -#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 1 -#define PRS_CH_CTRL_SIGSEL_BURTCOF 0 -#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 1 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 1 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 2 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 3 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 4 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 5 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 6 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 7 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 1 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 2 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 3 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 4 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 5 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 6 -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 7 -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0 -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 1 -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 2 - -/* generic of above */ -#define PRS_CH_CTRL_SIGSEL_VCMP_OUT 0 -#define PRS_CH_CTRL_SIGSEL_ACMP_OUT 0 -#define PRS_CH_CTRL_SIGSEL_DAC_CHx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_DAC_CH0 0 -#define PRS_CH_CTRL_SIGSEL_DAC_CH1 1 -#define PRS_CH_CTRL_SIGSEL_ADC_SINGLE 0 -#define PRS_CH_CTRL_SIGSEL_ADC_SCAN 1 -#define PRS_CH_CTRL_SIGSEL_USART_IRTX 0 -#define PRS_CH_CTRL_SIGSEL_USART_TXC 1 -#define PRS_CH_CTRL_SIGSEL_USART_RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_TIMER_UF 0 -#define PRS_CH_CTRL_SIGSEL_TIMER_OF 1 -#define PRS_CH_CTRL_SIGSEL_TIMER_CCx(x) PRS_CH_CTRL_SIGSEL((x) + 2) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC0 PRS_CH_CTRL_SIGSEL_TIMER_CCx(0) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC1 PRS_CH_CTRL_SIGSEL_TIMER_CCx(1) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC2 PRS_CH_CTRL_SIGSEL_TIMER_CCx(2) -#define PRS_CH_CTRL_SIGSEL_USB_SOF 0 -#define PRS_CH_CTRL_SIGSEL_USB_SOFSR 1 -#define PRS_CH_CTRL_SIGSEL_RTC_OF 0 -#define PRS_CH_CTRL_SIGSEL_RTC_COMPx(x) PRS_CH_CTRL_SIGSEL((x) + 1) -#define PRS_CH_CTRL_SIGSEL_RTC_COMP0 PRS_CH_CTRL_SIGSEL_RTC_COMPx(0) -#define PRS_CH_CTRL_SIGSEL_RTC_COMP1 PRS_CH_CTRL_SIGSEL_RTC_COMPx(1) -#define PRS_CH_CTRL_SIGSEL_UART_TXC 1 -#define PRS_CH_CTRL_SIGSEL_UART_RXDATAV 2 -#define PRS_CH_CTRL_SIGSEL_GPIOL_PINx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0 \ - 0 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1 \ - 1 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2 \ - 2 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3 \ - 3 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4 \ - 4 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5 \ - 5 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6 \ - 6 -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7 \ - 7 -#define PRS_CH_CTRL_SIGSEL_GPIOH_PINx(x) PRS_CH_CTRL_SIGSEL((x) - 8) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15) -#define PRS_CH_CTRL_SIGSEL_LETIMER_CHx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0 \ - 0 -#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1 \ - 1 -#define PRS_CH_CTRL_SIGSEL_BURTC_OF 0 -#define PRS_CH_CTRL_SIGSEL_BURTC_COMP0 1 -#define PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0 \ - 0 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1 \ - 1 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2 \ - 2 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3 \ - 3 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4 \ - 4 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5 \ - 5 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6 \ - 6 -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7 \ - 7 -#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x) \ - PRS_CH_CTRL_SIGSEL((x) - 8) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15) -#define PRS_CH_CTRL_SIGSEL_LESENSED_DECx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0 \ - 0 -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1 \ - 1 -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2 \ - 2 - -/** @defgroup prs_ch PRS Channel Number -@ingroup prs_defines - -@{*/ -enum prs_ch { - PRS_CH0 = 0, - PRS_CH1, - PRS_CH2, - PRS_CH3, - PRS_CH4, - PRS_CH5, - PRS_CH6, - PRS_CH7, - PRS_CH8, - PRS_CH9, - PRS_CH10, - PRS_CH11 -}; -/**@}*/ - -BEGIN_DECLS - -void prs_enable_gpio_output(enum prs_ch ch); -void prs_disable_gpio_output(enum prs_ch ch); -void prs_set_output_loc(uint32_t loc); - -void prs_software_pulse(enum prs_ch ch); -void prs_software_level_high(enum prs_ch ch); -void prs_software_level_low(enum prs_ch ch); - -void prs_enable_async(enum prs_ch ch); -void prs_disable_async(enum prs_ch ch); -void prs_set_edge(enum prs_ch ch, uint32_t edge); -void prs_set_source(enum prs_ch ch, uint32_t source); -void prs_set_signal(enum prs_ch ch, uint32_t sig); - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/rmu_common.h b/libopencm3/include/libopencm3/efm32/common/rmu_common.h deleted file mode 100644 index 96723bb..0000000 --- a/libopencm3/include/libopencm3/efm32/common/rmu_common.h +++ /dev/null @@ -1,58 +0,0 @@ -/** @addtogroup rmu_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define RMU_CTRL MMIO32(RMU_BASE + 0x00) -#define RMU_RSTCAUSE MMIO32(RMU_BASE + 0x04) -#define RMU_CMD MMIO32(RMU_BASE + 0x08) - -/* RMU_CTRL */ -#define RMU_CTRL_BURSTEN (1 << 1) -#define RMU_CTRL_LOCKUPRDIS (1 << 0) - -/* RMU_RSTCAUSE */ -#define RMU_RSTCAUSE_BUMODERST (1 << 15) -#define RMU_RSTCAUSE_BUBODREG (1 << 14) -#define RMU_RSTCAUSE_BUBODUNREG (1 << 13) -#define RMU_RSTCAUSE_BUBODBUVIN (1 << 12) -#define RMU_RSTCAUSE_BUBODVDDDREG (1 << 11) -#define RMU_RSTCAUSE_BODAVDD1 (1 << 10) -#define RMU_RSTCAUSE_BODAVDD0 (1 << 9) -#define RMU_RSTCAUSE_EM4WURST (1 << 8) -#define RMU_RSTCAUSE_EM4RST (1 << 7) -#define RMU_RSTCAUSE_SYSREQRST (1 << 6) -#define RMU_RSTCAUSE_LOCKUPRST (1 << 5) -#define RMU_RSTCAUSE_WDOGRST (1 << 4) -#define RMU_RSTCAUSE_EXTRST (1 << 3) -#define RMU_RSTCAUSE_BODREGRST (1 << 2) -#define RMU_RSTCAUSE_BODUNREGRST (1 << 1) -#define RMU_RSTCAUSE_PORST (1 << 0) - -/* RMU_CMD */ -#define RMU_CMD_RCCLR (1 << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/rtc_common.h b/libopencm3/include/libopencm3/efm32/common/rtc_common.h deleted file mode 100644 index c7eea3e..0000000 --- a/libopencm3/include/libopencm3/efm32/common/rtc_common.h +++ /dev/null @@ -1,73 +0,0 @@ -/** @addtogroup rtc_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define RTC_CTRL (RTC_BASE + 0x000) -#define RTC_CNT (RTC_BASE + 0x004) -#define RTC_COMP0 (RTC_BASE + 0x008) -#define RTC_COMP1 (RTC_BASE + 0x00C) -#define RTC_IF (RTC_BASE + 0x010) -#define RTC_IFS (RTC_BASE + 0x014) -#define RTC_IFC (RTC_BASE + 0x018) -#define RTC_IEN (RTC_BASE + 0x01C) -#define RTC_FREEZE (RTC_BASE + 0x020) -#define RTC_SYNCBUSY (RTC_BASE + 0x024) - -/* RTC_CTRL */ -#define RTC_CTRL_COMP0TOP (1 << 2) -#define RTC_CTRL_DEBUGRUN (1 << 1) -#define RTC_CTRL_EN (1 << 0) - -/* RTC_IF */ -#define RTC_IF_COMP1 (1 << 2) -#define RTC_IF_COMP0 (1 << 1) -#define RTC_IF_OF (1 << 0) - -/* RTC_IFS */ -#define RTC_IFS_COMP1 (1 << 2) -#define RTC_IFS_COMP0 (1 << 1) -#define RTC_IFS_OF (1 << 0) - -/* RTC_IFC */ -#define RTC_IFC_COMP1 (1 << 2) -#define RTC_IFC_COMP0 (1 << 1) -#define RTC_IFC_OF (1 << 0) - -/* RTC_IFE */ -#define RTC_IFE_COMP1 (1 << 2) -#define RTC_IFE_COMP0 (1 << 1) -#define RTC_IFE_OF (1 << 0) - -/* RTC_FREEZE */ -#define RTC_FREEZE_REGFREEZE (1 << 0) - -/* RTC_SYNCBUSY */ -#define RTC_SYNCBUSY_COMP1 (1 << 2) -#define RTC_SYNCBUSY_COMP0 (1 << 1) -#define RTC_SYNCBUSY_CTRL (1 << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/timer_common.h b/libopencm3/include/libopencm3/efm32/common/timer_common.h deleted file mode 100644 index a89d2e3..0000000 --- a/libopencm3/include/libopencm3/efm32/common/timer_common.h +++ /dev/null @@ -1,612 +0,0 @@ -/** @addtogroup timer_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define TIMER_CTRL(base) MMIO32((base) + 0x000) -#define TIMER_CMD(base) MMIO32((base) + 0x004) -#define TIMER_STATUS(base) MMIO32((base) + 0x008) -#define TIMER_IEN(base) MMIO32((base) + 0x00C) -#define TIMER_IF(base) MMIO32((base) + 0x010) -#define TIMER_IFS(base) MMIO32((base) + 0x014) -#define TIMER_IFC(base) MMIO32((base) + 0x018) -#define TIMER_TOP(base) MMIO32((base) + 0x01C) -#define TIMER_TOPB(base) MMIO32((base) + 0x020) -#define TIMER_CNT(base) MMIO32((base) + 0x024) -#define TIMER_ROUTE(base) MMIO32((base) + 0x028) - -#define TIMER_CCx_CTRL(base, x) MMIO32((base) + 0x030 + (0x10 * (x))) -#define TIMER_CCx_CCV(base, x) MMIO32((base) + 0x034 + (0x10 * (x))) -#define TIMER_CCx_CCVP(base, x) MMIO32((base) + 0x038 + (0x10 * (x))) -#define TIMER_CCx_CCVB(base, x) MMIO32((base) + 0x03C + (0x10 * (x))) - -#define TIMER_CC0_CTRL(base) TIMER_CCx_CTRL(base, 0) -#define TIMER_CC0_CCV(base) TIMER_CCx_CCV(base, 0) -#define TIMER_CC0_CCVP(base) TIMER_CCx_CCVP(base, 0) -#define TIMER_CC0_CCVB(base) TIMER_CCx_CCVB(base, 0) - -#define TIMER_CC1_CTRL(base) TIMER_CCx_CTRL(base, 1) -#define TIMER_CC1_CCV(base) TIMER_CCx_CCV(base, 1) -#define TIMER_CC1_CCVP(base) TIMER_CCx_CCVP(base, 1) -#define TIMER_CC1_CCVB(base) TIMER_CCx_CCVB(base, 1) - -#define TIMER_CC2_CTRL(base) TIMER_CCx_CTRL(base, 2) -#define TIMER_CC2_CCV(base) TIMER_CCx_CCV(base, 2) -#define TIMER_CC2_CCVP(base) TIMER_CCx_CCVP(base, 2) -#define TIMER_CC2_CCVB(base) TIMER_CCx_CCVB(base, 2) - -#define TIMER_DTCTRL(base) MMIO32((base) + 0x070) -#define TIMER_DTTIME(base) MMIO32((base) + 0x074) -#define TIMER_DTFC(base) MMIO32((base) + 0x078) -#define TIMER_DTOGEN(base) MMIO32((base) + 0x07C) -#define TIMER_DTFAULT(base) MMIO32((base) + 0x080) -#define TIMER_DTFAULTC(base) MMIO32((base) + 0x084) -#define TIMER_DTLOCK(base) MMIO32((base) + 0x088) - -/* TIMER_CTRL */ -#define TIMER_CTRL_RSSCOIST (1 << 29) -#define TIMER_CTRL_ATI (1 << 28) - -#define TIMER_CTRL_PRESC_SHIFT (24) -#define TIMER_CTRL_PRESC_MASK (0xF << TIMER_CTRL_PRESC_SHIFT) -#define TIMER_CTRL_PRESC(v) \ - (((v) << TIMER_CTRL_PRESC_SHIFT) & TIMER_CTRL_PRESC_MASK) -#define TIMER_CTRL_PRESC_DIV1 0 -#define TIMER_CTRL_PRESC_DIV2 1 -#define TIMER_CTRL_PRESC_DIV4 2 -#define TIMER_CTRL_PRESC_DIV8 3 -#define TIMER_CTRL_PRESC_DIV16 4 -#define TIMER_CTRL_PRESC_DIV32 5 -#define TIMER_CTRL_PRESC_DIV64 6 -#define TIMER_CTRL_PRESC_DIV128 7 -#define TIMER_CTRL_PRESC_DIV256 8 -#define TIMER_CTRL_PRESC_DIV512 9 -#define TIMER_CTRL_PRESC_DIV1024 10 -#define TIMER_CTRL_PRESC_NODIV TIMER_CTRL_PRESC_DIV1 - -#define TIMER_CTRL_CLKSEL_SHIFT (16) -#define TIMER_CTRL_CLKSEL_MASK (0x3 << TIMER_CTRL_CLKSEL_SHIFT) -#define TIMER_CTRL_CLKSEL(v) \ - (((v) << TIMER_CTRL_CLKSEL_SHIFT) & TIMER_CTRL_CLKSEL_MASK) -#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0 -#define TIMER_CTRL_CLKSEL_CC1 1 -#define TIMER_CTRL_CLKSEL_TIMEROUF 2 - -#define TIMER_CTRL_X2CNT (1 << 13) - -#define TIMER_CTRL_FALLA_SHIFT (10) -#define TIMER_CTRL_FALLA_MASK (0x3 << TIMER_CTRL_FALLA_SHIFT) -#define TIMER_CTRL_FALLA(v) \ - (((v) << TIMER_CTRL_FALLA_SHIFT) & TIMER_CTRL_FALLA_MASK) -#define TIMER_CTRL_FALLA_NONE 0 -#define TIMER_CTRL_FALLA_START 1 -#define TIMER_CTRL_FALLA_STOP 2 -#define TIMER_CTRL_FALLA_RELOADSTART 3 - -#define TIMER_CTRL_RISEA_SHIFT (8) -#define TIMER_CTRL_RISEA_MASK (0x3 << TIMER_CTRL_RISEA_SHIFT) -#define TIMER_CTRL_RISEA(v) \ - (((v) << TIMER_CTRL_RISEA_SHIFT) & TIMER_CTRL_RISEA_MASK) -#define TIMER_CTRL_RISEA_NONE 0 -#define TIMER_CTRL_RISEA_START 1 -#define TIMER_CTRL_RISEA_STOP 2 -#define TIMER_CTRL_RISEA_RELOADSTART 3 - -/* TIMER_CTRL_DMACLRACT bit is strangely documented. - * set this bit, - * in case you are doing one DMA transfer on every timer trigger event. - * if this bit is not set, strange behaviour is seen. -*/ - -#define TIMER_CTRL_DMACLRACT (1 << 7) -#define TIMER_CTRL_DEBUGRUN (1 << 6) -#define TIMER_CTRL_QDM (1 << 5) -#define TIMER_CTRL_OSMEN (1 << 4) -#define TIMER_CTRL_SYNC (1 << 3) - -#define TIMER_CTRL_MODE_SHIFT (0) -#define TIMER_CTRL_MODE_MASK (0x3 << TIMER_CTRL_MODE_SHIFT) -#define TIMER_CTRL_MODE(v) \ - (((v) << TIMER_CTRL_MODE_SHIFT) & TIMER_CTRL_MODE_MASK) -#define TIMER_CTRL_MODE_UP 0 -#define TIMER_CTRL_MODE_DOWN 1 -#define TIMER_CTRL_MODE_UPDOWN 2 -#define TIMER_CTRL_MODE_QDEC 3 - -/* TIMER_CMD */ -#define TIMER_CMD_STOP (1 << 1) -#define TIMER_CMD_START (1 << 0) - -/* TIMER_STATUS */ -#define TIMER_STATUS_CCPOLx(x) (1 << ((x) + 24)) -#define TIMER_STATUS_CCPOL2 TIMER_STATUS_CCPOLx(2) -#define TIMER_STATUS_CCPOL1 TIMER_STATUS_CCPOLx(1) -#define TIMER_STATUS_CCPOL0 TIMER_STATUS_CCPOLx(0) - -#define TIMER_STATUS_ICVx(x) (1 << ((x) + 16)) -#define TIMER_STATUS_ICV2 TIMER_STATUS_ICVx(2) -#define TIMER_STATUS_ICV1 TIMER_STATUS_ICVx(1) -#define TIMER_STATUS_ICV0 TIMER_STATUS_ICVx(0) - -#define TIMER_STATUS_CCVBVx(x) (1 << ((x) + 8)) -#define TIMER_STATUS_CCVBV2 TIMER_STATUS_CCVBVx(2) -#define TIMER_STATUS_CCVBV1 TIMER_STATUS_CCVBVx(1) -#define TIMER_STATUS_CCVBV0 TIMER_STATUS_CCVBVx(0) - -#define TIMER_STATUS_TOPBV (1 << 2) -#define TIMER_STATUS_DIR (1 << 1) -#define TIMER_STATUS_RUNNING (1 << 0) - -/* TIMER_IEN */ -#define TIMER_IEN_ICBOFx(x) (1 << ((x) + 8)) -#define TIMER_IEN_ICBOF0 TIMER_IEN_ICBOFx(0) -#define TIMER_IEN_ICBOF1 TIMER_IEN_ICBOFx(1) -#define TIMER_IEN_ICBOF2 TIMER_IEN_ICBOFx(2) - -#define TIMER_IEN_CCx(x) (1 << ((x) + 4)) -#define TIMER_IEN_CC0 TIMER_IEN_CCx(0) -#define TIMER_IEN_CC1 TIMER_IEN_CCx(1) -#define TIMER_IEN_CC2 TIMER_IEN_CCx(2) - -#define TIMER_IEN_UF (1 << 1) -#define TIMER_IEN_OF (1 << 0) - - -/* TIMER_IF */ -#define TIMER_IF_ICBOFx(x) (1 << ((x) + 8)) -#define TIMER_IF_ICBOF0 TIMER_IF_ICBOFx(0) -#define TIMER_IF_ICBOF1 TIMER_IF_ICBOFx(1) -#define TIMER_IF_ICBOF2 TIMER_IF_ICBOFx(2) - -#define TIMER_IF_CCx(x) (1 << ((x) + 4)) -#define TIMER_IF_CC0 TIMER_IF_CCx(0) -#define TIMER_IF_CC1 TIMER_IF_CCx(1) -#define TIMER_IF_CC2 TIMER_IF_CCx(2) - -#define TIMER_IF_UF (1 << 1) -#define TIMER_IF_OF (1 << 0) - -/* TIMER_IFS */ -#define TIMER_IFS_ICBOFx(x) (1 << ((x) + 8)) -#define TIMER_IFS_ICBOF0 TIMER_IFS_ICBOFx(0) -#define TIMER_IFS_ICBOF1 TIMER_IFS_ICBOFx(1) -#define TIMER_IFS_ICBOF2 TIMER_IFS_ICBOFx(2) - -#define TIMER_IFS_CCx(x) (1 << ((x) + 4)) -#define TIMER_IFS_CC0 TIMER_IFS_CCx(0) -#define TIMER_IFS_CC1 TIMER_IFS_CCx(1) -#define TIMER_IFS_CC2 TIMER_IFS_CCx(2) - -#define TIMER_IFS_UF (1 << 1) -#define TIMER_IFS_OF (1 << 0) - - -/* TIMER_IFC */ -#define TIMER_IFC_ICBOFx(x) (1 << ((x) + 8)) -#define TIMER_IFC_ICBOF0 TIMER_IFC_ICBOFx(0) -#define TIMER_IFC_ICBOF1 TIMER_IFC_ICBOFx(1) -#define TIMER_IFC_ICBOF2 TIMER_IFC_ICBOFx(2) - -#define TIMER_IFC_CCx(x) (1 << ((x) + 4)) -#define TIMER_IFC_CC0 TIMER_IFC_CCx(0) -#define TIMER_IFC_CC1 TIMER_IFC_CCx(1) -#define TIMER_IFC_CC2 TIMER_IFC_CCx(2) - -#define TIMER_IFC_UF (1 << 1) -#define TIMER_IFC_OF (1 << 0) - -/* TIMER_ROUTE */ -#define TIMER_ROUTE_LOCATION_SHIFT (16) -#define TIMER_ROUTE_LOCATION_MASK (0x7 << TIMER_ROUTE_LOCATION_SHIFT) -#define TIMER_ROUTE_LOCATION(v) \ - (((v) << TIMER_ROUTE_LOCATION_SHIFT) & TIMER_ROUTE_LOCATION_MASK) -#define TIMER_ROUTE_LOCATION_LOCx(x) TIMER_ROUTE_LOCATION(x) -#define TIMER_ROUTE_LOCATION_LOC0 0 -#define TIMER_ROUTE_LOCATION_LOC1 1 -#define TIMER_ROUTE_LOCATION_LOC2 2 -#define TIMER_ROUTE_LOCATION_LOC3 3 -#define TIMER_ROUTE_LOCATION_LOC4 4 -#define TIMER_ROUTE_LOCATION_LOC5 5 - -#define TIMER_ROUTE_CDTIxPEN(x) (1 << (8 + (x))) -#define TIMER_ROUTE_CDTI0PEN TIMER_ROUTE_CDTIxPEN(0) -#define TIMER_ROUTE_CDTI1PEN TIMER_ROUTE_CDTIxPEN(1) -#define TIMER_ROUTE_CDTI2PEN TIMER_ROUTE_CDTIxPEN(2) - -#define TIMER_ROUTE_CCxPEN(x) (1 << (0 + (x))) -#define TIMER_ROUTE_CC0PEN TIMER_ROUTE_CCxPEN(0) -#define TIMER_ROUTE_CC1PEN TIMER_ROUTE_CCxPEN(1) -#define TIMER_ROUTE_CC2PEN TIMER_ROUTE_CCxPEN(2) - -/* TIMER_CCx_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_SHIFT (26) -#define TIMER_CC_CTRL_ICEVCTRL_MASK (0x3 << TIMER_CC_CTRL_ICEVCTRL_SHIFT) -#define TIMER_CC_CTRL_ICEVCTRL(v) \ - (((v) << TIMER_CC_CTRL_ICEVCTRL_SHIFT) & TIMER_CC_CTRL_ICEVCTRL_MASK) -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0 -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 1 -#define TIMER_CC_CTRL_ICEVCTRL_RISING 2 -#define TIMER_CC_CTRL_ICEVCTRL_FALLING 3 - -#define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE \ - TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE -#define TIMER_CC_CTRL_ICEVCTRL_EVERY_SECOND_EDGE \ - TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE - -#define TIMER_CC_CTRL_ICEDGE_SHIFT (24) -#define TIMER_CC_CTRL_ICEDGE_MASK (0x3 << TIMER_CC_CTRL_ICEDGE_SHIFT) -#define TIMER_CC_CTRL_ICEDGE(v) \ - (((v) << TIMER_CC_CTRL_ICEDGE_SHIFT) & TIMER_CC_CTRL_ICEDGE_MASK) -#define TIMER_CC_CTRL_ICEDGE_RISING 0 -#define TIMER_CC_CTRL_ICEDGE_FALLING 1 -#define TIMER_CC_CTRL_ICEDGE_BOTH 2 -#define TIMER_CC_CTRL_ICEDGE_NONE 3 - -#define TIMER_CC_CTRL_FILT (1 << 21) -#define TIMER_CC_CTRL_INSEL (1 << 21) - - -#define TIMER_CC_CTRL_PRSSEL_SHIFT (16) -#define TIMER_CC_CTRL_PRSSEL_MASK (0xF << TIMER_CC_CTRL_PRSSEL_SHIFT) -#define TIMER_CC_CTRL_PRSSEL(v) \ - (((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK) -#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x) TIMER_CC_CTRL_PRSSEL(x) -#define TIMER_CC_CTRL_PRSSEL_PRSCH0 0 -#define TIMER_CC_CTRL_PRSSEL_PRSCH1 1 -#define TIMER_CC_CTRL_PRSSEL_PRSCH2 2 -#define TIMER_CC_CTRL_PRSSEL_PRSCH3 3 -#define TIMER_CC_CTRL_PRSSEL_PRSCH4 4 -#define TIMER_CC_CTRL_PRSSEL_PRSCH5 5 -#define TIMER_CC_CTRL_PRSSEL_PRSCH6 6 -#define TIMER_CC_CTRL_PRSSEL_PRSCH7 7 -#define TIMER_CC_CTRL_PRSSEL_PRSCH8 8 -#define TIMER_CC_CTRL_PRSSEL_PRSCH9 9 -#define TIMER_CC_CTRL_PRSSEL_PRSCH10 10 -#define TIMER_CC_CTRL_PRSSEL_PRSCH11 11 - -#define TIMER_CC_CTRL_CUFOA_SHIFT (12) -#define TIMER_CC_CTRL_CUFOA_MASK (0x3 << TIMER_CC_CTRL_CUFOA_SHIFT) -#define TIMER_CC_CTRL_CUFOA(v) \ - (((v) << TIMER_CC_CTRL_CUFOA_SHIFT) & TIMER_CC_CTRL_CUFOA_MASK) -#define TIMER_CC_CTRL_CUFOA_NONE 0 -#define TIMER_CC_CTRL_CUFOA_TOGGLE 1 -#define TIMER_CC_CTRL_CUFOA_CLEAR 2 -#define TIMER_CC_CTRL_CUFOA_SET 3 - -#define TIMER_CC_CTRL_COFOA_SHIFT (10) -#define TIMER_CC_CTRL_COFOA_MASK (0x3 << TIMER_CC_CTRL_COFOA_SHIFT) -#define TIMER_CC_CTRL_COFOA(v) \ - (((v) << TIMER_CC_CTRL_COFOA_SHIFT) & TIMER_CC_CTRL_COFOA_MASK) -#define TIMER_CC_CTRL_COFOA_NONE 0 -#define TIMER_CC_CTRL_COFOA_TOGGLE 1 -#define TIMER_CC_CTRL_COFOA_CLEAR 2 -#define TIMER_CC_CTRL_COFOA_SET 3 - -#define TIMER_CC_CTRL_CMOA_SHIFT (8) -#define TIMER_CC_CTRL_CMOA_MASK (0x3 << TIMER_CC_CTRL_CMOA_SHIFT) -#define TIMER_CC_CTRL_CMOA(v) \ - (((v) << TIMER_CC_CTRL_CMOA_SHIFT) & TIMER_CC_CTRL_CMOA_MASK) -#define TIMER_CC_CTRL_CMOA_NONE 0 -#define TIMER_CC_CTRL_CMOA_TOGGLE 1 -#define TIMER_CC_CTRL_CMOA_CLEAR 2 -#define TIMER_CC_CTRL_CMOA_SET 3 - -#define TIMER_CC_CTRL_COIST (1 << 4) -#define TIMER_CC_CTRL_OUTINV (1 << 2) - -#define TIMER_CC_CTRL_MODE_SHIFT (0) -#define TIMER_CC_CTRL_MODE_MASK (0x3 << TIMER_CC_CTRL_MODE_SHIFT) -#define TIMER_CC_CTRL_MODE(v) \ - (((v) << TIMER_CC_CTRL_MODE_SHIFT) & TIMER_CC_CTRL_MODE_MASK) -#define TIMER_CC_CTRL_MODE_OFF 0 -#define TIMER_CC_CTRL_MODE_INPUTCAPTURE 1 -#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 2 -#define TIMER_CC_CTRL_MODE_PWM 3 - -#define TIMER_CC_CTRL_MODE_INPUT_CAPTURE \ - TIMER_CC_CTRL_MODE_INPUTCAPTURE -#define TIMER_CC_CTRL_MODE_OUTPUT_CAPTURE \ - TIMER_CC_CTRL_MODE_OUTPUTCAPTURE - -/* TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTPRSEN (1 << 24) - -#define TIMER_DTCTRL_DTPRSSEL_SHIFT (4) -#define TIMER_DTCTRL_DTPRSSEL_MASK (0xF << TIMER_DTCTRL_DTPRSSEL_SHIFT) -#define TIMER_DTCTRL_DTPRSSEL(v) \ - (((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK) -#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x) TIMER_DTCTRL_DTPRSSEL(x) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 0 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 1 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 2 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 3 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 4 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 5 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 6 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 7 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 8 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 9 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 10 -#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 11 - -#define TIMER_DTCTRL_DTCINV (1 << 3) -#define TIMER_DTCTRL_DTIPOL (1 << 2) -#define TIMER_DTCTRL_DTDAS (1 << 1) -#define TIMER_DTCTRL_DTEN (1 << 0) - -/* TIMER_DTTIME */ -#define TIMER_DTTIME_DTFALLT_SHIFT (16) -#define TIMER_DTTIME_DTFALLT_MASK (0x3F << TIMER_DTTIME_DTFALLT_SHIFT) -#define TIMER_DTTIME_DTFALLT(v) \ - (((v) << TIMER_DTTIME_DTFALLT_SHIFT) & TIMER_DTTIME_DTFALLT_MASK) - -#define TIMER_DTTIME_DTRISET_SHIFT (8) -#define TIMER_DTTIME_DTRISET_MASK (0x3F << TIMER_DTTIME_DTRISET_SHIFT) -#define TIMER_DTTIME_DTRISET(v) \ - (((v) << TIMER_DTTIME_DTRISET_SHIFT) & TIMER_DTTIME_DTRISET_MASK) - - -#define TIMER_DTTIME_DTPRESC_SHIFT (0) -#define TIMER_DTTIME_DTPRESC_MASK (0xF << TIMER_DTTIME_DTPRESC_SHIFT) -#define TIMER_DTTIME_DTPRESC(v) \ - (((v) << TIMER_DTTIME_DTPRESC_SHIFT) & TIMER_DTTIME_DTPRESC_MASK) -#define TIMER_DTTIME_DTPRESC_DIV1 0 -#define TIMER_DTTIME_DTPRESC_DIV2 1 -#define TIMER_DTTIME_DTPRESC_DIV4 2 -#define TIMER_DTTIME_DTPRESC_DIV8 3 -#define TIMER_DTTIME_DTPRESC_DIV16 4 -#define TIMER_DTTIME_DTPRESC_DIV32 5 -#define TIMER_DTTIME_DTPRESC_DIV64 6 -#define TIMER_DTTIME_DTPRESC_DIV128 7 -#define TIMER_DTTIME_DTPRESC_DIV256 8 -#define TIMER_DTTIME_DTPRESC_DIV512 8 -#define TIMER_DTTIME_DTPRESC_DIV1024 10 -#define TIMER_DTTIME_DTPRESC_NODIV TIMER_DTTIME_DTPRESC_DIV1 - -/* TIMER_DTFC */ -#define TIMER_DTFC_DTLOCKUPFEN (1 << 27) -#define TIMER_DTFC_DTDBGFEN (1 << 26) -#define TIMER_DTFC_DTPRS1FEN (1 << 25) -#define TIMER_DTFC_DTPRS0FEN (1 << 24) - -#define TIMER_DTFC_DTFA_SHIFT (16) -#define TIMER_DTFC_DTFA_MASK (0x3 << TIMER_DTFC_DTFA_SHIFT) -#define TIMER_DTFC_DTFA(v) \ - (((v) << TIMER_DTFC_DTFA_SHIFT) & TIMER_DTFC_DTFA_MASK) -#define TIMER_DTFC_DTFA_NONE 0 -#define TIMER_DTFC_DTFA_INACTIVE 1 -#define TIMER_DTFC_DTFA_CLEAR 2 -#define TIMER_DTFC_DTFA_TRISTATE 3 - -#define TIMER_DTFC_DTPRS1FSEL_SHIFT (8) -#define TIMER_DTFC_DTPRS1FSEL_MASK (0x3 << TIMER_DTFC_DTPRS1FSEL_SHIFT) -#define TIMER_DTFC_DTPRS1FSEL(v) \ - (((v) << TIMER_DTFC_DTPRS1FSEL_SHIFT) & TIMER_DTFC_DTPRS1FSEL_MASK) -#define TIMER_DTFC_DTPRS1FSEL_PRSCHx(x) TIMER_DTFC_DTPRS1FSEL(x) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 0 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 1 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 2 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 3 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 4 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 5 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 6 -#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 7 - -#define TIMER_DTFC_DTPRS0FSEL_SHIFT (8) -#define TIMER_DTFC_DTPRS0FSEL_MASK (0x3 << TIMER_DTFC_DTPRS0FSEL_SHIFT) -#define TIMER_DTFC_DTPRS0FSEL(v) \ - (((v) << TIMER_DTFC_DTPRS0FSEL_SHIFT) & TIMER_DTFC_DTPRS0FSEL_MASK) -#define TIMER_DTFC_DTPRS0FSEL_PRSCHx(x) TIMER_DTFC_DTPRS0FSEL(x) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 0 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 1 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 2 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 3 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 4 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 5 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 6 -#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 7 - -/* TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN (1 << 5) -#define TIMER_DTOGEN_DTOGCDTI1EN (1 << 4) -#define TIMER_DTOGEN_DTOGCDTI0EN (1 << 3) -#define TIMER_DTOGEN_DTOGCC2EN (1 << 2) -#define TIMER_DTOGEN_DTOGCC1EN (1 << 1) -#define TIMER_DTOGEN_DTOGCC0EN (1 << 0) - -/* TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF (1 << 3) -#define TIMER_DTFAULT_DTDBGF (1 << 2) -#define TIMER_DTFAULT_DTPRS1F (1 << 1) -#define TIMER_DTFAULT_DTPRS0F (1 << 0) - -/* TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_TLOCKUPFC (1 << 3) -#define TIMER_DTFAULTC_DTDBGFC (1 << 2) -#define TIMER_DTFAULTC_DTPRS1FC (1 << 1) -#define TIMER_DTFAULTC_DTPRS0FC (1 << 0) - -/* TIMER_DTLOCK */ -#define TIMER_DTLOCK_LOCKKEY_SHIFT (0) -#define TIMER_DTLOCK_LOCKKEY_MASK (0xFFFF << TIMER_DTLOCK_LOCKKEY_SHIFT) -#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT) -#define TIMER_DTLOCK_LOCKKEY_LOCKED (0x0001 << TIMER_DTLOCK_LOCKKEY_SHIFT) -#define TIMER_DTLOCK_LOCKKEY_LOCK (0x0000 << TIMER_DTLOCK_LOCKKEY_SHIFT) -#define TIMER_DTLOCK_LOCKKEY_UNLOCK (0xCE80 << TIMER_DTLOCK_LOCKKEY_SHIFT) - -/* TIMER0 */ -#define TIMER0 TIMER0_BASE -#define TIMER0_CTRL TIMER_CTRL(TIMER0) -#define TIMER0_CMD TIMER_CMD(TIMER0) -#define TIMER0_STATUS TIMER_STATUS(TIMER0) -#define TIMER0_IEN TIMER_IEN(TIMER0) -#define TIMER0_IF TIMER_IF(TIMER0) -#define TIMER0_IFS TIMER_IFS(TIMER0) -#define TIMER0_IFC TIMER_IFC(TIMER0) -#define TIMER0_TOP TIMER_TOP(TIMER0) -#define TIMER0_TOPB TIMER_TOPB(TIMER0) -#define TIMER0_CNT TIMER_CNT(TIMER0) -#define TIMER0_ROUTE TIMER_ROUTE(TIMER0) - -#define TIMER0_CC0_CTRL TIMER_CC0_CTRL(TIMER0) -#define TIMER0_CC0_CCV TIMER_CC0_CCV(TIMER0) -#define TIMER0_CC0_CCVP TIMER_CC0_CCVP(TIMER0) -#define TIMER0_CC0_CCVB TIMER_CC0_CCVB(TIMER0) - -#define TIMER0_CC1_CTRL TIMER_CC1_CTRL(TIMER0) -#define TIMER0_CC1_CCV TIMER_CC1_CCV(TIMER0) -#define TIMER0_CC1_CCVP TIMER_CC1_CCVP(TIMER0) -#define TIMER0_CC1_CCVB TIMER_CC1_CCVB(TIMER0) - -#define TIMER0_CC2_CTRL TIMER_CC2_CTRL(TIMER0) -#define TIMER0_CC2_CCV TIMER_CC2_CCV(TIMER0) -#define TIMER0_CC2_CCVP TIMER_CC2_CCVP(TIMER0) -#define TIMER0_CC2_CCVB TIMER_CC2_CCVB(TIMER0) - -#define TIMER0_DTCTRL TIMER_DTCTRL(TIMER0) -#define TIMER0_DTTIME TIMER_DTTIME(TIMER0) -#define TIMER0_DTFC TIMER_DTFC(TIMER0) -#define TIMER0_DTOGEN TIMER_DTOGEN(TIMER0) -#define TIMER0_DTFAULT TIMER_DTFAULT(TIMER0) -#define TIMER0_DTFAULTC TIMER_DTFAULTC(TIMER0) -#define TIMER0_DTLOCK TIMER_DTLOCK(TIMER0) - -/* TIMER1 */ -#define TIMER1 TIMER1_BASE -#define TIMER1_CTRL TIMER_CTRL(TIMER1) -#define TIMER1_CMD TIMER_CMD(TIMER1) -#define TIMER1_STATUS TIMER_STATUS(TIMER1) -#define TIMER1_IEN TIMER_IEN(TIMER1) -#define TIMER1_IF TIMER_IF(TIMER1) -#define TIMER1_IFS TIMER_IFS(TIMER1) -#define TIMER1_IFC TIMER_IFC(TIMER1) -#define TIMER1_TOP TIMER_TOP(TIMER1) -#define TIMER1_TOPB TIMER_TOPB(TIMER1) -#define TIMER1_CNT TIMER_CNT(TIMER1) -#define TIMER1_ROUTE TIMER_ROUTE(TIMER1) - -#define TIMER1_CC0_CTRL TIMER_CC0_CTRL(TIMER1) -#define TIMER1_CC0_CCV TIMER_CC0_CCV(TIMER1) -#define TIMER1_CC0_CCVP TIMER_CC0_CCVP(TIMER1) -#define TIMER1_CC0_CCVB TIMER_CC0_CCVB(TIMER1) - -#define TIMER1_CC1_CTRL TIMER_CC1_CTRL(TIMER1) -#define TIMER1_CC1_CCV TIMER_CC1_CCV(TIMER1) -#define TIMER1_CC1_CCVP TIMER_CC1_CCVP(TIMER1) -#define TIMER1_CC1_CCVB TIMER_CC1_CCVB(TIMER1) - -#define TIMER1_CC2_CTRL TIMER_CC2_CTRL(TIMER1) -#define TIMER1_CC2_CCV TIMER_CC2_CCV(TIMER1) -#define TIMER1_CC2_CCVP TIMER_CC2_CCVP(TIMER1) -#define TIMER1_CC2_CCVB TIMER_CC2_CCVB(TIMER1) - -/* TIMER2 */ -#define TIMER2 TIMER2_BASE -#define TIMER2_CTRL TIMER_CTRL(TIMER2) -#define TIMER2_CMD TIMER_CMD(TIMER2) -#define TIMER2_STATUS TIMER_STATUS(TIMER2) -#define TIMER2_IEN TIMER_IEN(TIMER2) -#define TIMER2_IF TIMER_IF(TIMER2) -#define TIMER2_IFS TIMER_IFS(TIMER2) -#define TIMER2_IFC TIMER_IFC(TIMER2) -#define TIMER2_TOP TIMER_TOP(TIMER2) -#define TIMER2_TOPB TIMER_TOPB(TIMER2) -#define TIMER2_CNT TIMER_CNT(TIMER2) -#define TIMER2_ROUTE TIMER_ROUTE(TIMER2) - -#define TIMER2_CC0_CTRL TIMER_CC0_CTRL(TIMER2) -#define TIMER2_CC0_CCV TIMER_CC0_CCV(TIMER2) -#define TIMER2_CC0_CCVP TIMER_CC0_CCVP(TIMER2) -#define TIMER2_CC0_CCVB TIMER_CC0_CCVB(TIMER2) - -#define TIMER2_CC1_CTRL TIMER_CC1_CTRL(TIMER2) -#define TIMER2_CC1_CCV TIMER_CC1_CCV(TIMER2) -#define TIMER2_CC1_CCVP TIMER_CC1_CCVP(TIMER2) -#define TIMER2_CC1_CCVB TIMER_CC1_CCVB(TIMER2) - -#define TIMER2_CC2_CTRL TIMER_CC2_CTRL(TIMER2) -#define TIMER2_CC2_CCV TIMER_CC2_CCV(TIMER2) -#define TIMER2_CC2_CCVP TIMER_CC2_CCVP(TIMER2) -#define TIMER2_CC2_CCVB TIMER_CC2_CCVB(TIMER2) - -/* TIMER3 */ -#define TIMER3 TIMER3_BASE -#define TIMER3_CTRL TIMER_CTRL(TIMER3) -#define TIMER3_CMD TIMER_CMD(TIMER3) -#define TIMER3_STATUS TIMER_STATUS(TIMER3) -#define TIMER3_IEN TIMER_IEN(TIMER3) -#define TIMER3_IF TIMER_IF(TIMER3) -#define TIMER3_IFS TIMER_IFS(TIMER3) -#define TIMER3_IFC TIMER_IFC(TIMER3) -#define TIMER3_TOP TIMER_TOP(TIMER3) -#define TIMER3_TOPB TIMER_TOPB(TIMER3) -#define TIMER3_CNT TIMER_CNT(TIMER3) -#define TIMER3_ROUTE TIMER_ROUTE(TIMER3) - -#define TIMER3_CC0_CTRL TIMER_CC0_CTRL(TIMER3) -#define TIMER3_CC0_CCV TIMER_CC0_CCV(TIMER3) -#define TIMER3_CC0_CCVP TIMER_CC0_CCVP(TIMER3) -#define TIMER3_CC0_CCVB TIMER_CC0_CCVB(TIMER3) - -#define TIMER3_CC1_CTRL TIMER_CC1_CTRL(TIMER3) -#define TIMER3_CC1_CCV TIMER_CC1_CCV(TIMER3) -#define TIMER3_CC1_CCVP TIMER_CC1_CCVP(TIMER3) -#define TIMER3_CC1_CCVB TIMER_CC1_CCVB(TIMER3) - -#define TIMER3_CC2_CTRL TIMER_CC2_CTRL(TIMER3) -#define TIMER3_CC2_CCV TIMER_CC2_CCV(TIMER3) -#define TIMER3_CC2_CCVP TIMER_CC2_CCVP(TIMER3) -#define TIMER3_CC2_CCVB TIMER_CC2_CCVB(TIMER3) - -/** @defgroup timer_ch Timer Channel Number -@ingroup timer_defines - -@{*/ -enum tim_ch { - TIM_CH0 = 0, - TIM_CH1, - TIM_CH2 -}; -/**@}*/ - -BEGIN_DECLS - -void timer_start(uint32_t timer); -void timer_stop(uint32_t timer); - -void timer_set_clock_prescaler(uint32_t timer, uint32_t prescaler); - -void timer_set_top(uint32_t timer, uint32_t top); - -/* TODO: interrupt {enable, disable, read-flags} */ - -/* TODO: for channel (output value, input value) - * enable channel - * set location, set output mode */ - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/uart_common.h b/libopencm3/include/libopencm3/efm32/common/uart_common.h deleted file mode 100644 index 58b65aa..0000000 --- a/libopencm3/include/libopencm3/efm32/common/uart_common.h +++ /dev/null @@ -1,104 +0,0 @@ -/** @addtogroup uart_defines - * - * @brief UART registers are mostly equivalent to USART registers. - * - * USART and UART registers are equivalent except [in UART registers]: - * - * * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA - * (Synchronous operation not available) - * * USART_STATUS: MASTEREN (Synchronous operation not available) - * * USART_CTRL: MSBF (transmission LSB first only) - * * USART_CTRL: AUTOCS (chip-select not available) - * * USART_CTRL: SCMODE (SmartCard mode not available) - * * USART_FRAME: DATABITS (limited framesize. 8-9 databits only) - * * USART_IRCTRL: IREN (IrDA not available) - * (except DATABITS, all the above are 0) - * - * full text: (p495, "d0183_Rev1.10" EFM32LG-RM) - * - "18.3 Functional Description", - * - "18.4 Register Description" - * - "18.5 Register Map" - * - * use USART macro's to manipulate UART registers. - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -/* UART0 */ -#define UART0 UART0_BASE -#define UART0_CTRL USART_CTRL(UART0) -#define UART0_FRAME USART_FRAME(UART0) -#define UART0_TRIGCTRL USART_TRIGCTRL(UART0) -#define UART0_CMD USART_CMD(UART0) -#define UART0_STATUS USART_STATUS(UART0) -#define UART0_CLKDIV USART_CLKDIV(UART0) -#define UART0_RXDATAX USART_RXDATAX(UART0) -#define UART0_RXDATA USART_RXDATA(UART0) -#define UART0_RXDOUBLEX USART_RXDOUBLEX(UART0) -#define UART0_RXDOUBLE USART_RXDOUBLE(UART0) -#define UART0_RXDATAXP USART_RXDATAXP(UART0) -#define UART0_RXDOUBLEXP USART_RXDOUBLEXP(UART0) -#define UART0_TXDATAX USART_TXDATAX(UART0) -#define UART0_TXDATA USART_TXDATA(UART0) -#define UART0_TXDOUBLEX USART_TXDOUBLEX(UART0) -#define UART0_TXDOUBLE USART_TXDOUBLE(UART0) -#define UART0_IF USART_IF(UART0) -#define UART0_IFS USART_IFS(UART0) -#define UART0_IFC USART_IFC(UART0) -#define UART0_IEN USART_IEN(UART0) -#define UART0_IRCTRL USART_IRCTRL(UART0) -#define UART0_ROUTE USART_ROUTE(UART0) -#define UART0_INPUT USART_INPUT(UART0) -#define UART0_I2SCTRL USART_I2SCTRL(UART0) - -/* UART1 */ -#define UART1 UART1_BASE -#define UART1_CTRL USART_CTRL(UART1) -#define UART1_FRAME USART_FRAME(UART1) -#define UART1_TRIGCTRL USART_TRIGCTRL(UART1) -#define UART1_CMD USART_CMD(UART1) -#define UART1_STATUS USART_STATUS(UART1) -#define UART1_CLKDIV USART_CLKDIV(UART1) -#define UART1_RXDATAX USART_RXDATAX(UART1) -#define UART1_RXDATA USART_RXDATA(UART1) -#define UART1_RXDOUBLEX USART_RXDOUBLEX(UART1) -#define UART1_RXDOUBLE USART_RXDOUBLE(UART1) -#define UART1_RXDATAXP USART_RXDATAXP(UART1) -#define UART1_RXDOUBLEXP USART_RXDOUBLEXP(UART1) -#define UART1_TXDATAX USART_TXDATAX(UART1) -#define UART1_TXDATA USART_TXDATA(UART1) -#define UART1_TXDOUBLEX USART_TXDOUBLEX(UART1) -#define UART1_TXDOUBLE USART_TXDOUBLE(UART1) -#define UART1_IF USART_IF(UART1) -#define UART1_IFS USART_IFS(UART1) -#define UART1_IFC USART_IFC(UART1) -#define UART1_IEN USART_IEN(UART1) -#define UART1_IRCTRL USART_IRCTRL(UART1) -#define UART1_ROUTE USART_ROUTE(UART1) -#define UART1_INPUT USART_INPUT(UART1) -#define UART1_I2SCTRL USART_I2SCTRL(UART1) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/usart_common.h b/libopencm3/include/libopencm3/efm32/common/usart_common.h deleted file mode 100644 index 84f8800..0000000 --- a/libopencm3/include/libopencm3/efm32/common/usart_common.h +++ /dev/null @@ -1,514 +0,0 @@ -/** @addtogroup usart_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define USART_CTRL(base) MMIO32((base) + 0x000) -#define USART_FRAME(base) MMIO32((base) + 0x004) -#define USART_TRIGCTRL(base) MMIO32((base) + 0x008) -#define USART_CMD(base) MMIO32((base) + 0x00C) -#define USART_STATUS(base) MMIO32((base) + 0x010) -#define USART_CLKDIV(base) MMIO32((base) + 0x014) -#define USART_RXDATAX(base) MMIO32((base) + 0x018) -#define USART_RXDATA(base) MMIO32((base) + 0x01C) -#define USART_RXDOUBLEX(base) MMIO32((base) + 0x020) -#define USART_RXDOUBLE(base) MMIO32((base) + 0x024) -#define USART_RXDATAXP(base) MMIO32((base) + 0x028) -#define USART_RXDOUBLEXP(base) MMIO32((base) + 0x02C) -#define USART_TXDATAX(base) MMIO32((base) + 0x030) -#define USART_TXDATA(base) MMIO32((base) + 0x034) -#define USART_TXDOUBLEX(base) MMIO32((base) + 0x038) -#define USART_TXDOUBLE(base) MMIO32((base) + 0x03C) -#define USART_IF(base) MMIO32((base) + 0x040) -#define USART_IFS(base) MMIO32((base) + 0x044) -#define USART_IFC(base) MMIO32((base) + 0x048) -#define USART_IEN(base) MMIO32((base) + 0x04C) -#define USART_IRCTRL(base) MMIO32((base) + 0x050) -#define USART_ROUTE(base) MMIO32((base) + 0x054) -#define USART_INPUT(base) MMIO32((base) + 0x058) -#define USART_I2SCTRL(base) MMIO32((base) + 0x05C) - -/* USART_CTRL */ -#define USART_CTRL_SMSDELAY (1 << 31) -#define USART_CTRL_MVDIS (1 << 30) -#define USART_CTRL_AUTOTX (1 << 29) -#define USART_CTRL_BYTESWAP (1 << 28) - -#define USART_CTRL_TXDELAY_SHIFT (26) -#define USART_CTRL_TXDELAY_MASK (0x3 << USART_CTRL_TXDELAY_SHIFT) -#define USART_CTRL_TXDELAY(v) \ - (((v) << USART_CTRL_TXDELAY_SHIFT) & USART_CTRL_TXDELAY_MASK) -#define USART_CTRL_TXDELAY_NONE 0 -#define USART_CTRL_TXDELAY_SINGLE 1 -#define USART_CTRL_TXDELAY_DOUBLE 2 -#define USART_CTRL_TXDELAY_TRIPLE 3 - -#define USART_CTRL_SSSEARLY (1 << 25) -#define USART_CTRL_ERRSTX (1 << 24) -#define USART_CTRL_ERRSRX (1 << 23) -#define USART_CTRL_ERRSDMA (1 << 22) -#define USART_CTRL_BIT8DV (1 << 21) -#define USART_CTRL_SKIPPERRF (1 << 20) -#define USART_CTRL_SCRETRANS (1 << 19) -#define USART_CTRL_SCMODE (1 << 18) -#define USART_CTRL_AUTOTRI (1 << 17) -#define USART_CTRL_AUTOCS (1 << 16) -#define USART_CTRL_CSINV (1 << 15) -#define USART_CTRL_TXINV (1 << 14) -#define USART_CTRL_RXINV (1 << 13) -#define USART_CTRL_TXBIL (1 << 12) -#define USART_CTRL_CSMA (1 << 11) -#define USART_CTRL_MSBF (1 << 10) -#define USART_CTRL_CLKPHA (1 << 9) -#define USART_CTRL_CLKPOL (1 << 8) - -#define USART_CTRL_OVS_SHIFT (5) -#define USART_CTRL_OVS_MASK (0x3 << USART_CTRL_OVS_SHIFT) -#define USART_CTRL_OVS(v) \ - (((v) << USART_CTRL_OVS_SHIFT) & USART_CTRL_OVS_MASK) -#define USART_CTRL_OVS_X16 0 -#define USART_CTRL_OVS_X8 1 -#define USART_CTRL_OVS_X6 2 -#define USART_CTRL_OVS_X4 3 - -#define USART_CTRL_MPAB (1 << 4) -#define USART_CTRL_MPM (1 << 3) -#define USART_CTRL_CCEN (1 << 2) -#define USART_CTRL_LOOPBK (1 << 1) -#define USART_CTRL_SYNC (1 << 0) - -/* USART_FRAME */ - -#define USART_FRAME_STOPBITS_SHIFT (12) -#define USART_FRAME_STOPBITS_MASK (0x3 << USART_FRAME_STOPBITS_SHIFT) -#define USART_FRAME_STOPBITS(v) \ - (((v) << USART_FRAME_STOPBITS_SHIFT) & USART_FRAME_STOPBITS_MASK) -#define USART_FRAME_STOPBITS_HALF 0 -#define USART_FRAME_STOPBITS_ONE 1 -#define USART_FRAME_STOPBITS_ONEANDAHALF 2 -#define USART_FRAME_STOPBITS_ONE_AND_A_HALF \ - USART_FRAME_STOPBITS_ONEANDAHALF -#define USART_FRAME_STOPBITS_TWO 3 - -#define USART_FRAME_PARITY_SHIFT (8) -#define USART_FRAME_PARITY_MASK (0x3 << USART_FRAME_PARITY_SHIFT) -#define USART_FRAME_PARITY(v) \ - (((v) << USART_FRAME_PARITY_SHIFT) & USART_FRAME_PARITY_MASK) -#define USART_FRAME_PARITY_NONE 0 -#define USART_FRAME_PARITY_EVEN 2 -#define USART_FRAME_PARITY_ODD 3 - -#define USART_FRAME_DATABITS_SHIFT (0) -#define USART_FRAME_DATABITS_MASK (0xF << USART_FRAME_DATABITS_SHIFT) -#define USART_FRAME_DATABITS(v) \ - (((v) << USART_FRAME_DATABITS_SHIFT) & USART_FRAME_DATABITS_MASK) -#define USART_FRAME_DATABITS_FOUR 1 -#define USART_FRAME_DATABITS_FIVE 2 -#define USART_FRAME_DATABITS_SIX 3 -#define USART_FRAME_DATABITS_SEVEN 4 -#define USART_FRAME_DATABITS_EIGHT 5 -#define USART_FRAME_DATABITS_NINE 6 -#define USART_FRAME_DATABITS_TEN 7 -#define USART_FRAME_DATABITS_ELEVEN 8 -#define USART_FRAME_DATABITS_TWELVE 9 -#define USART_FRAME_DATABITS_THIRTEEN 10 -#define USART_FRAME_DATABITS_FOURTEEN 11 -#define USART_FRAME_DATABITS_FIFTEEN 12 -#define USART_FRAME_DATABITS_SIXTEEN 13 - -/* USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (1 << 6) -#define USART_TRIGCTRL_TXTEN (1 << 5) -#define USART_TRIGCTRL_RXTEN (1 << 4) - -#define USART_TRIGCTRL_TSEL_SHIFT (8) -#define USART_TRIGCTRL_TSEL_MASK (0x3 << USART_TRIGCTRL_TSEL_SHIFT) -#define USART_TRIGCTRL_TSEL_PRSCHx(v) \ - (((v) << USART_TRIGCTRL_TSEL_SHIFT) & USART_TRIGCTRL_TSEL_MASK) -#define USART_TRIGCTRL_TSEL_PRSCH0 0 -#define USART_TRIGCTRL_TSEL_PRSCH1 1 -#define USART_TRIGCTRL_TSEL_PRSCH2 2 -#define USART_TRIGCTRL_TSEL_PRSCH3 3 -#define USART_TRIGCTRL_TSEL_PRSCH4 4 -#define USART_TRIGCTRL_TSEL_PRSCH5 5 -#define USART_TRIGCTRL_TSEL_PRSCH6 6 -#define USART_TRIGCTRL_TSEL_PRSCH7 7 - -/* USART_CMD */ -#define USART_CMD_CLEARRX (1 << 11) -#define USART_CMD_CLEARTX (1 << 10) -#define USART_CMD_TXTRIDIS (1 << 9) -#define USART_CMD_TXTRIEN (1 << 8) -#define USART_CMD_RXBLOCKDIS (1 << 7) -#define USART_CMD_RXBLOCKEN (1 << 6) -#define USART_CMD_MASTERDIS (1 << 5) -#define USART_CMD_MASTEREN (1 << 4) -#define USART_CMD_TXDIS (1 << 3) -#define USART_CMD_TXEN (1 << 2) -#define USART_CMD_RXDIS (1 << 1) -#define USART_CMD_RXEN (1 << 0) - -/* USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (1 << 12) -#define USART_STATUS_RXDATAVRIGHT (1 << 11) -#define USART_STATUS_TXBSRIGHT (1 << 10) -#define USART_STATUS_TXBDRIGHT (1 << 9) -#define USART_STATUS_RXFULL (1 << 8) -#define USART_STATUS_RXDATAV (1 << 7) -#define USART_STATUS_TXBL (1 << 6) -#define USART_STATUS_TXC (1 << 5) -#define USART_STATUS_TXTRI (1 << 4) -#define USART_STATUS_RXBLOCK (1 << 3) -#define USART_STATUS_MASTER (1 << 2) -#define USART_STATUS_TXENS (1 << 1) -#define USART_STATUS_RXENS (1 << 0) - -/* USART_CLKDIV */ -#define USART_CLKDIV_DIV_SHIFT (6) -#define USART_CLKDIV_DIV_MASK (0x7FFF << USART_CLKDIV_DIV_SHIFT) -#define USART_CLKDIV_DIV(v) \ - (((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK) - -/* USART_RXDATAX */ -#define USART_RXDATAX_FERR (1 << 15) -#define USART_RXDATAX_PERR (1 << 14) - -#define USART_RXDATAX_RXDATA_SHIFT (0) -#define USART_RXDATAX_RXDATA_MASK (0x1FF << USART_RXDATAX_RXDATA_SHIFT) - -/* USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (1 << 31) -#define USART_RXDOUBLEX_PERR1 (1 << 30) - -#define USART_RXDOUBLEX_RXDATA1_SHIFT (16) -#define USART_RXDOUBLEX_RXDATA1_MASK \ - (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) - -#define USART_RXDOUBLEX_FERR0 (1 << 15) -#define USART_RXDOUBLEX_PERR0 (1 << 14) - -#define USART_RXDOUBLEX_RXDATA0_SHIFT (0) -#define USART_RXDOUBLEX_RXDATA0_MASK \ - (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) - -/* USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA1_SHIFT (8) -#define USART_RXDOUBLE_RXDATA1_MASK (0xFF << USART_RXDOUBLE_RXDATA1_SHIFT) - -#define USART_RXDOUBLE_RXDATA0_SHIFT (0) -#define USART_RXDOUBLE_RXDATA0_MASK (0xFF << USART_RXDOUBLE_RXDATA0_SHIFT) - -/* USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP (1 << 15) -#define USART_RXDATAXP_PERRP (1 << 14) - -#define USART_RXDATAXP_RXDATAP_SHIFT (0) -#define USART_RXDATAXP_RXDATAP_MASK (0x1FF << USART_RXDATAXP_RXDATAP_SHIFT) - -/* USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERR1 (1 << 31) -#define USART_RXDOUBLEXP_PERR1 (1 << 30) - -#define USART_RXDOUBLEXP_RXDATA1_SHIFT (16) -#define USART_RXDOUBLEXP_RXDATA1_MASK \ - (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) - -#define USART_RXDOUBLEXP_FERR0 (1 << 15) -#define USART_RXDOUBLEXP_PERR0 (1 << 14) - -#define USART_RXDOUBLEXP_RXDATA0_SHIFT (0) -#define USART_RXDOUBLEXP_RXDATA0_MASK \ - (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) - -/* USART_TXDATAX */ -#define USART_TXDATAX_RXENAT (1 << 15) -#define USART_TXDATAX_TXDISAT (1 << 14) -#define USART_TXDATAX_TXBREAK (1 << 13) -#define USART_TXDATAX_TXTRIAT (1 << 12) -#define USART_TXDATAX_UBRXAT (1 << 11) - -#define USART_TXDATAX_TXDATAX_SHIFT (0) -#define USART_TXDATAX_TXDATAX_MASK (0x1FF << USART_TXDATAX_TXDATAX_SHIFT) - -/* USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (1 << 31) -#define USART_TXDOUBLEX_TXDISAT1 (1 << 30) -#define USART_TXDOUBLEX_TXBREAK1 (1 << 29) -#define USART_TXDOUBLEX_TXTRIAT1 (1 << 28) -#define USART_TXDOUBLEX_UBRXAT1 (1 << 27) - -#define USART_TXDOUBLEX_TXDATA1_SHIFT (16) -#define USART_TXDOUBLEX_TXDATA1_MASK \ - (0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT) - -#define USART_TXDOUBLEX_RXENAT0 (1 << 15) -#define USART_TXDOUBLEX_TXDISAT0 (1 << 14) -#define USART_TXDOUBLEX_TXBREAK0 (1 << 13) -#define USART_TXDOUBLEX_TXTRIAT0 (1 << 12) -#define USART_TXDOUBLEX_UBRXAT0 (1 << 11) - -#define USART_TXDOUBLEX_TXDATA0_SHIFT (0) -#define USART_TXDOUBLEX_TXDATA0_MASK \ - (0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT) - -/* USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA1_SHIFT (8) -#define USART_TXDOUBLE_TXDATA1_MASK (0xFF << USART_TXDOUBLE_TXDATA1_SHIFT) - -#define USART_TXDOUBLE_TXDATA0_SHIFT (0) -#define USART_TXDOUBLE_TXDATA0_MASK (0xFF << USART_TXDOUBLE_TXDATA0_SHIFT) - -/* USART_IF */ -#define USART_IF_CCF (1 << 12) -#define USART_IF_SSM (1 << 11) -#define USART_IF_MPAF (1 << 10) -#define USART_IF_FERR (1 << 9) -#define USART_IF_PERR (1 << 8) -#define USART_IF_TXUF (1 << 7) -#define USART_IF_TXOF (1 << 6) -#define USART_IF_RXUF (1 << 5) -#define USART_IF_RXOF (1 << 4) -#define USART_IF_RXFULL (1 << 3) -#define USART_IF_RXDATAV (1 << 2) -#define USART_IF_TXBL (1 << 1) -#define USART_IF_TXC (1 << 0) - -/* USART_IFS */ -#define USART_IFS_CCF (1 << 12) -#define USART_IFS_SSM (1 << 11) -#define USART_IFS_MPAF (1 << 10) -#define USART_IFS_FERR (1 << 9) -#define USART_IFS_PERR (1 << 8) -#define USART_IFS_TXUF (1 << 7) -#define USART_IFS_TXOF (1 << 6) -#define USART_IFS_RXUF (1 << 5) -#define USART_IFS_RXOF (1 << 4) -#define USART_IFS_RXFULL (1 << 3) -#define USART_IFS_RXDATAV (1 << 2) -#define USART_IFS_TXBL (1 << 1) -#define USART_IFS_TXC (1 << 0) - -/* USART_IFC */ -#define USART_IFC_CCF (1 << 12) -#define USART_IFC_SSM (1 << 11) -#define USART_IFC_MPAF (1 << 10) -#define USART_IFC_FERR (1 << 9) -#define USART_IFC_PERR (1 << 8) -#define USART_IFC_TXUF (1 << 7) -#define USART_IFC_TXOF (1 << 6) -#define USART_IFC_RXUF (1 << 5) -#define USART_IFC_RXOF (1 << 4) -#define USART_IFC_RXFULL (1 << 3) -#define USART_IFC_RXDATAV (1 << 2) -#define USART_IFC_TXBL (1 << 1) -#define USART_IFC_TXC (1 << 0) - -/* USART_IEN */ -#define USART_IEN_CCF (1 << 12) -#define USART_IEN_SSM (1 << 11) -#define USART_IEN_MPAF (1 << 10) -#define USART_IEN_FERR (1 << 9) -#define USART_IEN_PERR (1 << 8) -#define USART_IEN_TXUF (1 << 7) -#define USART_IEN_TXOF (1 << 6) -#define USART_IEN_RXUF (1 << 5) -#define USART_IEN_RXOF (1 << 4) -#define USART_IEN_RXFULL (1 << 3) -#define USART_IEN_RXDATAV (1 << 2) -#define USART_IEN_TXBL (1 << 1) -#define USART_IEN_TXC (1 << 0) - -/* USART_IRCTRL */ -#define USART_IRCTRL_IRPRSEN (1 << 7) - -#define USART_IRCTRL_IRPRSSEL_SHIFT (4) -#define USART_IRCTRL_IRPRSSEL_MASK (0x7 << USART_IRCTRL_IRPRSSEL_SHIFT) -#define USART_IRCTRL_IRPRSSEL(v) \ - (((v) << USART_IRCTRL_IRPRSSEL_SHIFT) & USART_IRCTRL_IRPRSSEL_MASK) -#define USART_IRCTRL_IRPRSSEL_PRSCHx(x) USART_IRCTRL_IRPRSSEL(x) -#define USART_IRCTRL_IRPRSSEL_PRSCH0 0 -#define USART_IRCTRL_IRPRSSEL_PRSCH1 1 -#define USART_IRCTRL_IRPRSSEL_PRSCH2 2 -#define USART_IRCTRL_IRPRSSEL_PRSCH3 3 -#define USART_IRCTRL_IRPRSSEL_PRSCH4 4 -#define USART_IRCTRL_IRPRSSEL_PRSCH5 5 -#define USART_IRCTRL_IRPRSSEL_PRSCH6 6 -#define USART_IRCTRL_IRPRSSEL_PRSCH7 7 - -#define USART_IRCTRL_IRFILT (1 << 3) - -#define USART_IRCTRL_IRPW_SHIFT (1) -#define USART_IRCTRL_IRPW_MASK (0x3 << USART_IRCTRL_IRPW_SHIFT) -#define USART_IRCTRL_IRPW(v) \ - (((v) << USART_IRCTRL_IRPW_SHIFT) & USART_IRCTRL_IRPW_MASK) -#define USART_IRCTRL_IRPW_ONE 0 -#define USART_IRCTRL_IRPW_TWO 1 -#define USART_IRCTRL_IRPW_THREE 2 -#define USART_IRCTRL_IRPW_FOUR 3 - -#define USART_IRCTRL_IREN (1 << 0) - -/* USART_ROUTE */ -#define USART_ROUTE_LOCATION_SHIFT (8) -#define USART_ROUTE_LOCATION_MASK (0x7 << USART_ROUTE_LOCATION_SHIFT) -#define USART_ROUTE_LOCATION(v) \ - (((v) << USART_ROUTE_LOCATION_SHIFT) & USART_ROUTE_LOCATION_MASK) -#define USART_ROUTE_LOCATION_LOCx(x) USART_ROUTE_LOCATION(x) -#define USART_ROUTE_LOCATION_LOC0 0 -#define USART_ROUTE_LOCATION_LOC1 1 -#define USART_ROUTE_LOCATION_LOC2 2 -#define USART_ROUTE_LOCATION_LOC3 3 -#define USART_ROUTE_LOCATION_LOC4 4 -#define USART_ROUTE_LOCATION_LOC5 5 - -#define USART_ROUTE_CLKPEN (1 << 3) -#define USART_ROUTE_CSPEN (1 << 2) -#define USART_ROUTE_TXPEN (1 << 1) -#define USART_ROUTE_RXPEN (1 << 0) - -/* USART_INPUT */ -#define USART_INPUT_RXPRS (1 << 4) - -#define USART_INPUT_RXPRSSEL_SHIFT (0) -#define USART_INPUT_RXPRSSEL_MASK (0xF << USART_INPUT_RXPRSSEL_SHIFT) -#define USART_INPUT_RXPRSSEL(v) \ - (((v) << USART_INPUT_RXPRSSEL_SHIFT) & USART_INPUT_RXPRSSEL_MASK) -#define USART_INPUT_RXPRSSEL_PRSCHx(x) USART_INPUT_RXPRSSEL(x) -#define USART_INPUT_RXPRSSEL_PRSCH0 0 -#define USART_INPUT_RXPRSSEL_PRSCH1 1 -#define USART_INPUT_RXPRSSEL_PRSCH2 2 -#define USART_INPUT_RXPRSSEL_PRSCH3 3 -#define USART_INPUT_RXPRSSEL_PRSCH4 4 -#define USART_INPUT_RXPRSSEL_PRSCH5 5 -#define USART_INPUT_RXPRSSEL_PRSCH6 6 -#define USART_INPUT_RXPRSSEL_PRSCH7 7 -#define USART_INPUT_RXPRSSEL_PRSCH8 8 -#define USART_INPUT_RXPRSSEL_PRSCH9 9 -#define USART_INPUT_RXPRSSEL_PRSCH10 10 -#define USART_INPUT_RXPRSSEL_PRSCH11 11 - -/* USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_SHIFT (8) -#define USART_I2SCTRL_FORMAT_MASK (0x7 << USART_I2SCTRL_FORMAT_SHIFT) -#define USART_I2SCTRL_FORMAT(v) \ - (((v) << USART_I2SCTRL_FORMAT_SHIFT) & USART_I2SCTRL_FORMAT_MASK) -#define USART_I2SCTRL_FORMAT_W32D32 0 -#define USART_I2SCTRL_FORMAT_W32D24M 1 -#define USART_I2SCTRL_FORMAT_W32D24 2 -#define USART_I2SCTRL_FORMAT_W32D16 3 -#define USART_I2SCTRL_FORMAT_W32D8 4 -#define USART_I2SCTRL_FORMAT_W16D16 5 -#define USART_I2SCTRL_FORMAT_W16D8 6 -#define USART_I2SCTRL_FORMAT_W8D8 7 - -#define USART_I2SCTRL_DELAY (1 << 4) -#define USART_I2SCTRL_DMASPLIT (1 << 3) -#define USART_I2SCTRL_JUSTIFY (1 << 2) -#define USART_I2SCTRL_MONO (1 << 1) -#define USART_I2SCTRL_EN (1 << 0) - -/* USART0 */ -#define USART0 USART0_BASE -#define USART0_CTRL USART_CTRL(USART0) -#define USART0_FRAME USART_FRAME(USART0) -#define USART0_TRIGCTRL USART_TRIGCTRL(USART0) -#define USART0_CMD USART_CMD(USART0) -#define USART0_STATUS USART_STATUS(USART0) -#define USART0_CLKDIV USART_CLKDIV(USART0) -#define USART0_RXDATAX USART_RXDATAX(USART0) -#define USART0_RXDATA USART_RXDATA(USART0) -#define USART0_RXDOUBLEX USART_RXDOUBLEX(USART0) -#define USART0_RXDOUBLE USART_RXDOUBLE(USART0) -#define USART0_RXDATAXP USART_RXDATAXP(USART0) -#define USART0_RXDOUBLEXP USART_RXDOUBLEXP(USART0) -#define USART0_TXDATAX USART_TXDATAX(USART0) -#define USART0_TXDATA USART_TXDATA(USART0) -#define USART0_TXDOUBLEX USART_TXDOUBLEX(USART0) -#define USART0_TXDOUBLE USART_TXDOUBLE(USART0) -#define USART0_IF USART_IF(USART0) -#define USART0_IFS USART_IFS(USART0) -#define USART0_IFC USART_IFC(USART0) -#define USART0_IEN USART_IEN(USART0) -#define USART0_IRCTRL USART_IRCTRL(USART0) -#define USART0_ROUTE USART_ROUTE(USART0) -#define USART0_INPUT USART_INPUT(USART0) -#define USART0_I2SCTRL USART_I2SCTRL(USART0) - -/* USART1 */ -#define USART1 USART1_BASE -#define USART1_CTRL USART_CTRL(USART1) -#define USART1_FRAME USART_FRAME(USART1) -#define USART1_TRIGCTRL USART_TRIGCTRL(USART1) -#define USART1_CMD USART_CMD(USART1) -#define USART1_STATUS USART_STATUS(USART1) -#define USART1_CLKDIV USART_CLKDIV(USART1) -#define USART1_RXDATAX USART_RXDATAX(USART1) -#define USART1_RXDATA USART_RXDATA(USART1) -#define USART1_RXDOUBLEX USART_RXDOUBLEX(USART1) -#define USART1_RXDOUBLE USART_RXDOUBLE(USART1) -#define USART1_RXDATAXP USART_RXDATAXP(USART1) -#define USART1_RXDOUBLEXP USART_RXDOUBLEXP(USART1) -#define USART1_TXDATAX USART_TXDATAX(USART1) -#define USART1_TXDATA USART_TXDATA(USART1) -#define USART1_TXDOUBLEX USART_TXDOUBLEX(USART1) -#define USART1_TXDOUBLE USART_TXDOUBLE(USART1) -#define USART1_IF USART_IF(USART1) -#define USART1_IFS USART_IFS(USART1) -#define USART1_IFC USART_IFC(USART1) -#define USART1_IEN USART_IEN(USART1) -#define USART1_IRCTRL USART_IRCTRL(USART1) -#define USART1_ROUTE USART_ROUTE(USART1) -#define USART1_INPUT USART_INPUT(USART1) -#define USART1_I2SCTRL USART_I2SCTRL(USART1) - -/* USART2 */ -#define USART2 USART2_BASE -#define USART2_CTRL USART_CTRL(USART2) -#define USART2_FRAME USART_FRAME(USART2) -#define USART2_TRIGCTRL USART_TRIGCTRL(USART2) -#define USART2_CMD USART_CMD(USART2) -#define USART2_STATUS USART_STATUS(USART2) -#define USART2_CLKDIV USART_CLKDIV(USART2) -#define USART2_RXDATAX USART_RXDATAX(USART2) -#define USART2_RXDATA USART_RXDATA(USART2) -#define USART2_RXDOUBLEX USART_RXDOUBLEX(USART2) -#define USART2_RXDOUBLE USART_RXDOUBLE(USART2) -#define USART2_RXDATAXP USART_RXDATAXP(USART2) -#define USART2_RXDOUBLEXP USART_RXDOUBLEXP(USART2) -#define USART2_TXDATAX USART_TXDATAX(USART2) -#define USART2_TXDATA USART_TXDATA(USART2) -#define USART2_TXDOUBLEX USART_TXDOUBLEX(USART2) -#define USART2_TXDOUBLE USART_TXDOUBLE(USART2) -#define USART2_IF USART_IF(USART2) -#define USART2_IFS USART_IFS(USART2) -#define USART2_IFC USART_IFC(USART2) -#define USART2_IEN USART_IEN(USART2) -#define USART2_IRCTRL USART_IRCTRL(USART2) -#define USART2_ROUTE USART_ROUTE(USART2) -#define USART2_INPUT USART_INPUT(USART2) -#define USART2_I2SCTRL USART_I2SCTRL(USART2) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/usb_common.h b/libopencm3/include/libopencm3/efm32/common/usb_common.h deleted file mode 100644 index e4e8e16..0000000 --- a/libopencm3/include/libopencm3/efm32/common/usb_common.h +++ /dev/null @@ -1,371 +0,0 @@ -/** @addtogroup usb_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define USB_CTRL MMIO32(USB_BASE + 0x000) -#define USB_STATUS MMIO32(USB_BASE + 0x004) -#define USB_IF MMIO32(USB_BASE + 0x008) -#define USB_IFS MMIO32(USB_BASE + 0x00C) -#define USB_IFC MMIO32(USB_BASE + 0x010) -#define USB_IEN MMIO32(USB_BASE + 0x014) -#define USB_ROUTE MMIO32(USB_BASE + 0x018) - -/* USB_CTRL */ -#define USB_CTRL_DMPUAP (1 << 1) - -/* USB_ROUTE */ -#define USB_ROUTE_DMPUPEN (1 << 2) -#define USB_ROUTE_VBUSENPEN (1 << 1) -#define USB_ROUTE_PHYPEN (1 << 0) - -/* Core Global Control and Status Registers */ -#define USB_OTG_BASE (USB_BASE + 0x3C000) -#define USB_GOTGCTL MMIO32(USB_OTG_BASE + 0x000) -#define USB_GOTGINT MMIO32(USB_OTG_BASE + 0x004) -#define USB_GAHBCFG MMIO32(USB_OTG_BASE + 0x008) -#define USB_GUSBCFG MMIO32(USB_OTG_BASE + 0x00C) -#define USB_GRSTCTL MMIO32(USB_OTG_BASE + 0x010) -#define USB_GINTSTS MMIO32(USB_OTG_BASE + 0x014) -#define USB_GINTMSK MMIO32(USB_OTG_BASE + 0x018) -#define USB_GRXSTSR MMIO32(USB_OTG_BASE + 0x01C) -#define USB_GRXSTSP MMIO32(USB_OTG_BASE + 0x020) -#define USB_GRXFSIZ MMIO32(USB_OTG_BASE + 0x024) -#define USB_GNPTXFSIZ MMIO32(USB_OTG_BASE + 0x028) -#define USB_GNPTXSTS MMIO32(USB_OTG_BASE + 0x02C) -#define USB_GDFIFOCFG MMIO32(USB_OTG_BASE + 0x05C) -#define USB_HPTXFSIZ MMIO32(USB_OTG_BASE + 0x100) -#define USB_DIEPTXF(x) \ - MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1))) - -/* Host-mode Control and Status Registers */ -#define USB_HCFG MMIO32(USB_OTG_BASE + 0x400) -#define USB_HFIR MMIO32(USB_OTG_BASE + 0x404) -#define USB_HFNUM MMIO32(USB_OTG_BASE + 0x408) -#define USB_HPTXSTS MMIO32(USB_OTG_BASE + 0x410) -#define USB_HAINT MMIO32(USB_OTG_BASE + 0x414) -#define USB_HAINTMSK MMIO32(USB_OTG_BASE + 0x418) -#define USB_HPRT MMIO32(USB_OTG_BASE + 0x440) -#define USB_HCx_CHAR(x) \ - MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20)) -#define USB_HCx_INT(x) \ - MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20)) -#define USB_HCx_INTMSK(x) \ - MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20)) -#define USB_HCx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20)) -#define USB_HCx_DMAADDR(x) \ - MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20)) - -/* Device-mode Control and Status Registers */ -#define USB_DCFG MMIO32(USB_OTG_BASE + 0x800) -#define USB_DCTL MMIO32(USB_OTG_BASE + 0x804) -#define USB_DSTS MMIO32(USB_OTG_BASE + 0x808) -#define USB_DIEPMSK MMIO32(USB_OTG_BASE + 0x810) -#define USB_DOEPMSK MMIO32(USB_OTG_BASE + 0x814) -#define USB_DAINT MMIO32(USB_OTG_BASE + 0x818) -#define USB_DAINTMSK MMIO32(USB_OTG_BASE + 0x81C) -#define USB_DVBUSDIS MMIO32(USB_OTG_BASE + 0x828) -#define USB_DVBUSPULSE MMIO32(USB_OTG_BASE + 0x82C) -#define USB_DIEPEMPMSK MMIO32(USB_OTG_BASE + 0x834) - -#define USB_DIEPx_CTL(x) \ - MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20)) -#define USB_DIEPx_INT(x) \ - MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20)) -#define USB_DIEPx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20)) -#define USB_DIEP0CTL USB_DIEPx_CTL(0) -#define USB_DIEP0TSIZ USB_DIEPx_TSIZ(0) -#define USB_DIEP0INT USB_DIEPx_INT(0) - -#define USB_DOEPx_CTL(x) \ - MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20)) -#define USB_DOEPx_INT(x) \ - MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20)) -#define USB_DOEPx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20)) -#define USB_DOEP0CTL USB_DOEPx_CTL(0) -#define USB_DOEP0TSIZ USB_DOEPx_TSIZ(0) -#define USB_DOEP0INT USB_DOEPx_INT(0) - -/* Power and clock gating control and status register */ -#define USB_PCGCCTL MMIO32(USB_OTG_BASE + 0xE00) - -/* Data FIFO */ -#define USB_FIFOxD(x) \ - (&MMIO32(USB_OTG_BASE + (((x) + 1) << 12))) - -/* Global CSRs */ -/* USB control registers (OTG_HS_GOTGCTL) */ -#define USB_GOTGCTL_BSVLD (1 << 19) -#define USB_GOTGCTL_ASVLD (1 << 18) -#define USB_GOTGCTL_DBCT (1 << 17) -#define USB_GOTGCTL_CIDSTS (1 << 16) -#define USB_GOTGCTL_DHNPEN (1 << 11) -#define USB_GOTGCTL_HSHNPEN (1 << 10) -#define USB_GOTGCTL_HNPRQ (1 << 9) -#define USB_GOTGCTL_HNGSCS (1 << 8) -#define USB_GOTGCTL_SRQ (1 << 1) -#define USB_GOTGCTL_SRQSCS (1 << 0) - -/* AHB configuration register (USB_GAHBCFG) */ -#define USB_GAHBCFG_GLBLINTRMSK 0x0001 -#define USB_GAHBCFG_TXFELVL 0x0080 -#define USB_GAHBCFG_PTXFELVL 0x0100 - -/* USB configuration register (USB_GUSBCFG) */ -#define USB_GUSBCFG_TOCAL 0x00000003 -#define USB_GUSBCFG_SRPCAP 0x00000100 -#define USB_GUSBCFG_HNPCAP 0x00000200 -#define USB_GUSBCFG_TRDT_MASK (0xf << 10) -#define USB_GUSBCFG_TRDT_16BIT (0x5 << 10) -#define USB_GUSBCFG_TRDT_8BIT (0x9 << 10) -#define USB_GUSBCFG_NPTXRWEN 0x00004000 -#define USB_GUSBCFG_FHMOD 0x20000000 -#define USB_GUSBCFG_FDMOD 0x40000000 -#define USB_GUSBCFG_CTXPKT 0x80000000 -#define USB_GUSBCFG_PHYSEL (1 << 7) - -/* reset register (USB_GRSTCTL) */ -#define USB_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define USB_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define USB_GRSTCTL_TXFFLSH (1 << 5) -#define USB_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define USB_GRSTCTL_FCRST (1 << 2) -#define USB_GRSTCTL_HSRST (1 << 1) -#define USB_GRSTCTL_CSRST (1 << 0) - -/* interrupt status register (USB_GINTSTS) */ -#define USB_GINTSTS_WKUPINT (1 << 31) -#define USB_GINTSTS_SRQINT (1 << 30) -#define USB_GINTSTS_DISCINT (1 << 29) -#define USB_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define USB_GINTSTS_PTXFE (1 << 26) -#define USB_GINTSTS_HCINT (1 << 25) -#define USB_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define USB_GINTSTS_IPXFR (1 << 21) -#define USB_GINTSTS_INCOMPISOOUT (1 << 21) -#define USB_GINTSTS_IISOIXFR (1 << 20) -#define USB_GINTSTS_OEPINT (1 << 19) -#define USB_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define USB_GINTSTS_EOPF (1 << 15) -#define USB_GINTSTS_ISOODRP (1 << 14) -#define USB_GINTSTS_ENUMDNE (1 << 13) -#define USB_GINTSTS_USBRST (1 << 12) -#define USB_GINTSTS_USBSUSP (1 << 11) -#define USB_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define USB_GINTSTS_GONAKEFF (1 << 7) -#define USB_GINTSTS_GINAKEFF (1 << 6) -#define USB_GINTSTS_NPTXFE (1 << 5) -#define USB_GINTSTS_RXFLVL (1 << 4) -#define USB_GINTSTS_SOF (1 << 3) -#define USB_GINTSTS_OTGINT (1 << 2) -#define USB_GINTSTS_MMIS (1 << 1) -#define USB_GINTSTS_CMOD (1 << 0) - -/* interrupt mask register (USB_GINTMSK) */ -#define USB_GINTMSK_MMISM 0x00000002 -#define USB_GINTMSK_OTGINT 0x00000004 -#define USB_GINTMSK_SOFM 0x00000008 -#define USB_GINTMSK_RXFLVLM 0x00000010 -#define USB_GINTMSK_NPTXFEM 0x00000020 -#define USB_GINTMSK_GINAKEFFM 0x00000040 -#define USB_GINTMSK_GONAKEFFM 0x00000080 -#define USB_GINTMSK_ESUSPM 0x00000400 -#define USB_GINTMSK_USBSUSPM 0x00000800 -#define USB_GINTMSK_USBRST 0x00001000 -#define USB_GINTMSK_ENUMDNEM 0x00002000 -#define USB_GINTMSK_ISOODRPM 0x00004000 -#define USB_GINTMSK_EOPFM 0x00008000 -#define USB_GINTMSK_EPMISM 0x00020000 -#define USB_GINTMSK_IEPINT 0x00040000 -#define USB_GINTMSK_OEPINT 0x00080000 -#define USB_GINTMSK_IISOIXFRM 0x00100000 -#define USB_GINTMSK_IISOOXFRM 0x00200000 -#define USB_GINTMSK_IPXFRM 0x00200000 -#define USB_GINTMSK_PRTIM 0x01000000 -#define USB_GINTMSK_HCIM 0x02000000 -#define USB_GINTMSK_PTXFEM 0x04000000 -#define USB_GINTMSK_CIDSCHGM 0x10000000 -#define USB_GINTMSK_DISCINT 0x20000000 -#define USB_GINTMSK_SRQIM 0x40000000 -#define USB_GINTMSK_WUIM 0x80000000 - -/* Receive Status Pop Register (USB_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define USB_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define USB_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define USB_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define USB_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define USB_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define USB_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define USB_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define USB_GRXSTSP_DPID_MASK (0x3 << 15) -#define USB_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define USB_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define USB_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define USB_GRXSTSP_DPID_MDATA (0x3 << 15) -#define USB_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define USB_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* general core configuration register (USB_GCCFG) */ -/* Bits 31:22 - Reserved */ -#define USB_GCCFG_NOVBUSSENS (1 << 21) -#define USB_GCCFG_SOFOUTEN (1 << 20) -#define USB_GCCFG_VBUSBSEN (1 << 19) -#define USB_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define USB_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - - -/* Device-mode CSRs */ -/* device control register (USB_DCTL) */ -/* Bits 31:12 - Reserved */ -#define USB_DCTL_POPRGDNE (1 << 11) -#define USB_DCTL_CGONAK (1 << 10) -#define USB_DCTL_SGONAK (1 << 9) -#define USB_DCTL_SGINAK (1 << 8) -#define USB_DCTL_TCTL_MASK (7 << 4) -#define USB_DCTL_GONSTS (1 << 3) -#define USB_DCTL_GINSTS (1 << 2) -#define USB_DCTL_SDIS (1 << 1) -#define USB_DCTL_RWUSIG (1 << 0) - -/* device configuration register (USB_DCFG) */ -#define USB_DCFG_DSPD 0x0003 -#define USB_DCFG_NZLSOHSK 0x0004 -#define USB_DCFG_DAD 0x07F0 -#define USB_DCFG_PFIVL 0x1800 - -/* Device IN Endpoint Common Interrupt Mask Register (USB_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define USB_DIEPMSK_BIM (1 << 9) -#define USB_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define USB_DIEPMSK_INEPNEM (1 << 6) -#define USB_DIEPMSK_INEPNMM (1 << 5) -#define USB_DIEPMSK_ITTXFEMSK (1 << 4) -#define USB_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DIEPMSK_EPDM (1 << 1) -#define USB_DIEPMSK_XFRCM (1 << 0) - -/* Device OUT Endpoint Common Interrupt Mask Register (USB_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define USB_DOEPMSK_BOIM (1 << 9) -#define USB_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define USB_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DOEPMSK_OTEPDM (1 << 4) -#define USB_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DOEPMSK_EPDM (1 << 1) -#define USB_DOEPMSK_XFRCM (1 << 0) - -/* Device Control IN Endpoint 0 Control Register (USB_DIEP0CTL) */ -#define USB_DIEP0CTL_EPENA (1 << 31) -#define USB_DIEP0CTL_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define USB_DIEP0CTL_SD0PID (1 << 28) -#define USB_DIEP0CTL_SNAK (1 << 27) -#define USB_DIEP0CTL_CNAK (1 << 26) -#define USB_DIEP0CTL_TXFNUM_MASK (0xf << 22) -#define USB_DIEP0CTL_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define USB_DIEP0CTL_EPTYP_MASK (0x3 << 18) -#define USB_DIEP0CTL_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define USB_DIEP0CTL_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define USB_DIEP0CTL_MPSIZ_MASK (0x3 << 0) -#define USB_DIEP0CTL_MPSIZ_64 (0x0 << 0) -#define USB_DIEP0CTL_MPSIZ_32 (0x1 << 0) -#define USB_DIEP0CTL_MPSIZ_16 (0x2 << 0) -#define USB_DIEP0CTL_MPSIZ_8 (0x3 << 0) - -/* Device Control OUT Endpoint 0 Control Register (USB_DOEP0CTL) */ -#define USB_DOEP0CTL_EPENA (1 << 31) -#define USB_DOEP0CTL_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define USB_DOEP0CTL_SD0PID (1 << 28) -#define USB_DOEP0CTL_SNAK (1 << 27) -#define USB_DOEP0CTL_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define USB_DOEP0CTL_STALL (1 << 21) -#define USB_DOEP0CTL_SNPM (1 << 20) -#define USB_DOEP0CTL_EPTYP_MASK (0x3 << 18) -#define USB_DOEP0CTL_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define USB_DOEP0CTL_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define USB_DOEP0CTL_MPSIZ_MASK (0x3 << 0) -#define USB_DOEP0CTL_MPSIZ_64 (0x0 << 0) -#define USB_DOEP0CTL_MPSIZ_32 (0x1 << 0) -#define USB_DOEP0CTL_MPSIZ_16 (0x2 << 0) -#define USB_DOEP0CTL_MPSIZ_8 (0x3 << 0) - -/* Device IN Endpoint Interrupt Register (USB_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define USB_DIEP_INT_TXFE (1 << 7) -#define USB_DIEP_INT_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DIEP_INT_ITTXFE (1 << 4) -#define USB_DIEP_INT_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DIEP_INT_EPDISD (1 << 1) -#define USB_DIEP_INT_XFRC (1 << 0) - -/* Device IN Endpoint Interrupt Register (USB_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define USB_DOEP_INT_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DOEP_INT_OTEPDIS (1 << 4) -#define USB_DOEP_INT_SETUP (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DOEP_INT_EPDISD (1 << 1) -#define USB_DOEP_INT_XFRC (1 << 0) - -/* Device OUT Endpoint 0 Transfer Size Register (USB_DOEP0TSIZ) */ -/* Bit 31 - Reserved */ -#define USB_DIEP0TSIZ_STUPCNT_1 (0x1 << 29) -#define USB_DIEP0TSIZ_STUPCNT_2 (0x2 << 29) -#define USB_DIEP0TSIZ_STUPCNT_3 (0x3 << 29) -#define USB_DIEP0TSIZ_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define USB_DIEP0TSIZ_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define USB_DIEP0TSIZ_XFRSIZ_MASK (0x7f << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/wdog_common.h b/libopencm3/include/libopencm3/efm32/common/wdog_common.h deleted file mode 100644 index 1168d12..0000000 --- a/libopencm3/include/libopencm3/efm32/common/wdog_common.h +++ /dev/null @@ -1,78 +0,0 @@ -/** @addtogroup wdog_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define WDOG_CTRL MMIO32(WDOG_BASE + 0x000) -#define WDOG_CMD MMIO32(WDOG_BASE + 0x004) -#define WDOG_SYNCBUSY MMIO32(WDOG_BASE + 0x008) - -/* WDOG_CTRL */ -#define WDOG_CTRL_CLKSEL_SHIFT (12) -#define WDOG_CTRL_CLKSEL_MASK (0x3 << WDOG_CTRL_CLKSEL_SHIFT) -#define WDOG_CTRL_CLKSEL(v) \ - (((v) << WDOG_CTRL_CLKSEL_SHIFT) & WDOG_CTRL_CLKSEL_MASK) -#define WDOG_CTRL_CLKSEL_ULFRCO 0 -#define WDOG_CTRL_CLKSEL_LFRCO 1 -#define WDOG_CTRL_CLKSEL_LFXO 2 - -#define WDOG_CTRL_PERSEL_SHIFT (8) -#define WDOG_CTRL_PERSEL_MASK (0xF << WDOG_CTRL_PERSEL_SHIFT) -#define WDOG_CTRL_PERSEL(v) \ - (((v) << WDOG_CTRL_PERSEL_SHIFT) & WDOG_CTRL_PERSEL_MASK) -#define WDOG_CTRL_PERSEL_9CYCLES 0 -#define WDOG_CTRL_PERSEL_17CYCLES 1 -#define WDOG_CTRL_PERSEL_33CYCLES 2 -#define WDOG_CTRL_PERSEL_65CYCLES 3 -#define WDOG_CTRL_PERSEL_129CYCLES 4 -#define WDOG_CTRL_PERSEL_257CYCLES 5 -#define WDOG_CTRL_PERSEL_513CYCLES 6 -#define WDOG_CTRL_PERSEL_1KCYCLES 7 -#define WDOG_CTRL_PERSEL_2KCYCLES 8 -#define WDOG_CTRL_PERSEL_4KCYCLES 9 -#define WDOG_CTRL_PERSEL_8KCYCLES 10 -#define WDOG_CTRL_PERSEL_16KCYCLES 11 -#define WDOG_CTRL_PERSEL_32KCYCLES 12 -#define WDOG_CTRL_PERSEL_64KCYCLES 13 -#define WDOG_CTRL_PERSEL_128KCYCLES 14 -#define WDOG_CTRL_PERSEL_256KCYCLES 15 - -#define WDOG_CTRL_SWOSCBLOCK (1 << 6) -#define WDOG_CTRL_EM4BLOCK (1 << 5) -#define WDOG_CTRL_LOCK (1 << 4) -#define WDOG_CTRL_EM3RUN (1 << 3) -#define WDOG_CTRL_EM2RUN (1 << 2) -#define WDOG_CTRL_DEBUGRUN (1 << 1) -#define WDOG_CTRL_EN (1 << 0) - -/* WDOG_CMD */ -#define WDOG_CMD_CLEAR (1 << 0) - -/* WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (1 << 1) -#define WDOG_SYNCBUSY_CTRL (1 << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/common/wdog_common_hglg.h b/libopencm3/include/libopencm3/efm32/common/wdog_common_hglg.h deleted file mode 100644 index 700c48b..0000000 --- a/libopencm3/include/libopencm3/efm32/common/wdog_common_hglg.h +++ /dev/null @@ -1,78 +0,0 @@ -/** @addtogroup wdog_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define WDOG_CTRL MMIO32(WDOG_BASE + 0x000) -#define WDOG_CMD MMIO32(WDOG_BASE + 0x004) -#define WDOG_SYNCBUSY MMIO32(WDOG_BASE + 0x008) - -/* WDOG_CTRL */ -#define WDOG_CTRL_CLKSEL_SHIFT (12) -#define WDOG_CTRL_CLKSEL_MASK (0x3 << WDOG_CTRL_CLKSEL_SHIFT) -#define WDOG_CTRL_CLKSEL(v) \ - (((v) << WDOG_CTRL_CLKSEL_SHIFT) & WDOG_CTRL_CLKSEL_MASK) -#define WDOG_CTRL_CLKSEL_ULFRCO WDOG_CTRL_CLKSEL(0) -#define WDOG_CTRL_CLKSEL_LFRCO WDOG_CTRL_CLKSEL(1) -#define WDOG_CTRL_CLKSEL_LFXO WDOG_CTRL_CLKSEL(2) - -#define WDOG_CTRL_PERSEL_SHIFT (8) -#define WDOG_CTRL_PERSEL_MASK (0xF << WDOG_CTRL_PERSEL_SHIFT) -#define WDOG_CTRL_PERSEL(v) \ - (((v) << WDOG_CTRL_PERSEL_SHIFT) & WDOG_CTRL_PERSEL_MASK) -#define WDOG_CTRL_PERSEL_9CYCLES WDOG_CTRL_PERSEL(0) -#define WDOG_CTRL_PERSEL_17CYCLES WDOG_CTRL_PERSEL(1) -#define WDOG_CTRL_PERSEL_33CYCLES WDOG_CTRL_PERSEL(2) -#define WDOG_CTRL_PERSEL_65CYCLES WDOG_CTRL_PERSEL(3) -#define WDOG_CTRL_PERSEL_129CYCLES WDOG_CTRL_PERSEL(4) -#define WDOG_CTRL_PERSEL_257CYCLES WDOG_CTRL_PERSEL(5) -#define WDOG_CTRL_PERSEL_513CYCLES WDOG_CTRL_PERSEL(6) -#define WDOG_CTRL_PERSEL_1KCYCLES WDOG_CTRL_PERSEL(7) -#define WDOG_CTRL_PERSEL_2KCYCLES WDOG_CTRL_PERSEL(8) -#define WDOG_CTRL_PERSEL_4KCYCLES WDOG_CTRL_PERSEL(9) -#define WDOG_CTRL_PERSEL_8KCYCLES WDOG_CTRL_PERSEL(10) -#define WDOG_CTRL_PERSEL_16KCYCLES WDOG_CTRL_PERSEL(11) -#define WDOG_CTRL_PERSEL_32KCYCLES WDOG_CTRL_PERSEL(12) -#define WDOG_CTRL_PERSEL_64KCYCLES WDOG_CTRL_PERSEL(13) -#define WDOG_CTRL_PERSEL_128KCYCLES WDOG_CTRL_PERSEL(14) -#define WDOG_CTRL_PERSEL_256KCYCLES WDOG_CTRL_PERSEL(15) - -#define WDOG_CTRL_SWOSCBLOCK (1 << 6) -#define WDOG_CTRL_EM4BLOCK (1 << 5) -#define WDOG_CTRL_LOCK (1 << 4) -#define WDOG_CTRL_EM3RUN (1 << 3) -#define WDOG_CTRL_EM2RUN (1 << 2) -#define WDOG_CTRL_DEBUGRUN (1 << 1) -#define WDOG_CTRL_EN (1 << 0) - -/* WDOG_CMD */ -#define WDOG_CMD_CLEAR (1 << 0) - -/* WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (1 << 1) -#define WDOG_SYNCBUSY_CTRL (1 << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/dac.h b/libopencm3/include/libopencm3/efm32/dac.h deleted file mode 100644 index 8cc5b13..0000000 --- a/libopencm3/include/libopencm3/efm32/dac.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/dma.h b/libopencm3/include/libopencm3/efm32/dma.h deleted file mode 100644 index dac20e7..0000000 --- a/libopencm3/include/libopencm3/efm32/dma.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/emu.h b/libopencm3/include/libopencm3/efm32/emu.h deleted file mode 100644 index 266c6de..0000000 --- a/libopencm3/include/libopencm3/efm32/emu.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/acmp.h b/libopencm3/include/libopencm3/efm32/ezr32wg/acmp.h deleted file mode 100644 index 668eca5..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/acmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup acmp_defines ACMP Defines - * - * @brief Defined Constants and Types for the Analog Comparator module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/adc.h b/libopencm3/include/libopencm3/efm32/ezr32wg/adc.h deleted file mode 100644 index 1626931..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/adc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the EZR32WG Analog to Digital - * Converter - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/burtc.h b/libopencm3/include/libopencm3/efm32/ezr32wg/burtc.h deleted file mode 100644 index 3f5c55a..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/burtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup burtc_defines BURTC Defines - * - * @brief Defined Constants and Types for the Backup RTC - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/cmu.h b/libopencm3/include/libopencm3/efm32/ezr32wg/cmu.h deleted file mode 100644 index dd29340..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/cmu.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @defgroup cmu_defines CMU Defines - * - * @brief Defined Constants and Types for the EZR32WG Clock Management Unit - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -/**@{*/ - -/* EZR32WG refers to USART0 as USART0RF - * because it is connected to the radio MCU. - */ - -#define CMU_HFPERCLKEN0_USARTRF0 CMU_HFPERCLKEN0_USART0 -#define CMU_USARTRF0 CMU_USART0 - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/dac.h b/libopencm3/include/libopencm3/efm32/ezr32wg/dac.h deleted file mode 100644 index 8624e63..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/dac.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dac_defines DAC Defines - * - * @brief Defined Constants and Types for the D/A Converter module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/dma.h b/libopencm3/include/libopencm3/efm32/ezr32wg/dma.h deleted file mode 100644 index 4697186..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/dma.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @brief Defined Constants and Types for the DMA module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h b/libopencm3/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h deleted file mode 100644 index 8907593..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @page libopencm3 EZR32 Wonder Gecko - -@version 1.0.0 - -@date 14 January 2016 - -API documentation for Silicon Laboratories EZR32 Wonder Gecko Cortex M4 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EZR32WG EZR32 WonderGecko -Libraries for Silicon Laboratories EZR32 Wonder Gecko series. - -@version 1.0.0 - -@date 14 January 2016 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EZR32WG_defines EZR32 Wonder Gecko Defines - -@brief Defined Constants and Types for the Silicon Laboratories EZR32 -Wonder Gecko series - -@version 1.0.0 - -@date 12 January 2016 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/emu.h b/libopencm3/include/libopencm3/efm32/ezr32wg/emu.h deleted file mode 100644 index d0e532c..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/emu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup emu_defines EMU Defines - * - * @brief Defined Constants and Types for the Energy Management Unit - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/gpio.h b/libopencm3/include/libopencm3/efm32/ezr32wg/gpio.h deleted file mode 100644 index 8332c85..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the EZR32WG GPIO module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/i2c.h b/libopencm3/include/libopencm3/efm32/ezr32wg/i2c.h deleted file mode 100644 index 50ea556..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/i2c.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the I²C module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/irq.json b/libopencm3/include/libopencm3/efm32/ezr32wg/irq.json deleted file mode 100644 index 35ccb79..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/irq.json +++ /dev/null @@ -1,47 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0334_ezr32wg_reference_manual.pdf table 5.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "usb", - "acmp01", - "adc0", - "dac0", - "i2c0", - "i2c1", - "gpio_odd", - "timer1", - "timer2", - "timer3", - "usart1_rx", - "usart1_tx", - "lesense", - "usart2_rx", - "usart2_tx", - "uart0_rx", - "uart0_tx", - "uart1_rx", - "uart1_tx", - "leuart0", - "leuart1", - "letimer0", - "pcnt0", - "pcnt1", - "pcnt2", - "rtc", - "burtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes", - "ebi", - "emu" - ], - "partname_humanreadable": "EZR32 Wonder Gecko series", - "partname_doxygen": "EZR32WG", - "includeguard": "LIBOPENCM3_EZR32WG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/letimer.h b/libopencm3/include/libopencm3/efm32/ezr32wg/letimer.h deleted file mode 100644 index dc8d4fd..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/letimer.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup letimer_defines LETIMER Defines - * - * @brief Defined Constants and Types for the Low Energy Timer - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/memorymap.h b/libopencm3/include/libopencm3/efm32/ezr32wg/memorymap.h deleted file mode 100644 index 89536ca..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/memorymap.h +++ /dev/null @@ -1,121 +0,0 @@ - /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EZR32WG_MEMORYMAP_H -#define LIBOPENCM3_EZR32WG_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) - -/* Device information */ -#define DI_BASE (0x0FE08000U) - -/* all names are "DI_" + */ -#define DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020) -#define DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028) -#define DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030) -#define DI_ADC0_CAL MMIO32(DI_BASE + 0x040) -#define DI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048) -#define DI_DAC0_CAL MMIO32(DI_BASE + 0x050) -#define DI_DAC0_BIASPROG MMIO32(DI_BASE + 0x058) -#define DI_ACMP0_CTRL MMIO32(DI_BASE + 0x060) -#define DI_ACMP1_CTRL MMIO32(DI_BASE + 0x068) -#define DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x078) -#define DI_DAC0_OPACTRL MMIO32(DI_BASE + 0x0A0) -#define DI_DAC0_OPAOFFSET MMIO32(DI_BASE + 0x0A8) -#define DI_EMU_BUINACT MMIO32(DI_BASE + 0x0B0) -#define DI_EMU_BUACT MMIO32(DI_BASE + 0x0B8) -#define DI_EMU_BUBODBUVINCAL MMIO32(DI_BASE + 0x0C0) -#define DI_EMU_BUBODUNREGCAL MMIO32(DI_BASE + 0x0C8) -#define DI_MCM_REV_MIN MMIO8(DI_BASE + 0x1AA) -#define DI_MCM_REV_MAJ MMIO8(DI_BASE + 0x1AB) -#define DI_RADIO_REV_MIN MMIO8(DI_BASE + 0x1AC) -#define DI_RADIO_REV_MAJ MMIO8(DI_BASE + 0x1AD) -#define DI_RADIO_OPN MMIO8(DI_BASE + 0x1AE) -#define DI_DI_CRC MMIO16(DI_BASE + 0x1B0) -#define DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2) -#define DI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4) -#define DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6) -#define DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8) -#define DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA) -#define DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC) -#define DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE) -#define DI_DAC0_CAL_1V25 MMIO32(DI_BASE + 0x1C8) -#define DI_DAC0_CAL_2V5 MMIO32(DI_BASE + 0x1CC) -#define DI_DAC0_CAL_VDD MMIO32(DI_BASE + 0x1D0) -#define DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4) -#define DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5) -#define DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6) -#define DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7) -#define DI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8) -#define DI_AUXHFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1D9) -#define DI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC) -#define DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD) -#define DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE) -#define DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF) -#define DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0) -#define DI_HFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1E1) -#define DI_MEM_INFO_PAGE_SIZE MMIO8(DI_BASE + 0x1E7) -#define DI_RADIO_ID MMIO16(DI_BASE + 0x1EE) -#define DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0) -#define DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4) -#define DI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8) -#define DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA) -#define DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC) -#define DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE) -#define DI_PROD_REV MMIO8(DI_BASE + 0x1FF) - -#define AES_BASE (PERIPH_BASE + 0xE0000) -#define RMU_BASE (PERIPH_BASE + 0xCA000) -#define CMU_BASE (PERIPH_BASE + 0xC8000) -#define EMU_BASE (PERIPH_BASE + 0xC6000) -#define USB_BASE (PERIPH_BASE + 0xC4000) -#define DMA_BASE (PERIPH_BASE + 0xC2000) -#define MSC_BASE (PERIPH_BASE + 0xC0000) -#define LESENSE_BASE (PERIPH_BASE + 0x8C000) -#define WDOG_BASE (PERIPH_BASE + 0x88000) -#define PCNT2_BASE (PERIPH_BASE + 0x86800) -#define PCNT1_BASE (PERIPH_BASE + 0x86400) -#define PCNT0_BASE (PERIPH_BASE + 0x86000) -#define LEUART1_BASE (PERIPH_BASE + 0x84400) -#define LEUART0_BASE (PERIPH_BASE + 0x84000) -#define LETIMER0_BASE (PERIPH_BASE + 0x82000) -#define BURTC_BASE (PERIPH_BASE + 0x81000) -#define RTC_BASE (PERIPH_BASE + 0x80000) -#define PRS_BASE (PERIPH_BASE + 0xCC000) -#define TIMER3_BASE (PERIPH_BASE + 0x10C00) -#define TIMER2_BASE (PERIPH_BASE + 0x10800) -#define TIMER1_BASE (PERIPH_BASE + 0x10400) -#define TIMER0_BASE (PERIPH_BASE + 0x10000) -#define UART1_BASE (PERIPH_BASE + 0x0E400) -#define UART0_BASE (PERIPH_BASE + 0x0E000) -#define USART2_BASE (PERIPH_BASE + 0x0C800) -#define USART1_BASE (PERIPH_BASE + 0x0C400) -#define USARTRF0_BASE (PERIPH_BASE + 0x0C000) -#define I2C1_BASE (PERIPH_BASE + 0x0A400) -#define I2C0_BASE (PERIPH_BASE + 0x0A000) -#define GPIO_BASE (PERIPH_BASE + 0x06000) -#define DAC0_BASE (PERIPH_BASE + 0x04000) -#define ADC0_BASE (PERIPH_BASE + 0x02000) -#define ACMP1_BASE (PERIPH_BASE + 0x01400) -#define ACMP0_BASE (PERIPH_BASE + 0x01000) -#define VCMP_BASE (PERIPH_BASE + 0x00000) - -#endif diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/msc.h b/libopencm3/include/libopencm3/efm32/ezr32wg/msc.h deleted file mode 100644 index 2f8dd32..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/msc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup msc_defines MSC Defines - * - * @brief Defined Constants and Types for the Memory Systems Controller - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/opamp.h b/libopencm3/include/libopencm3/efm32/ezr32wg/opamp.h deleted file mode 100644 index 1b0ded9..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/opamp.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_EZR32WG_OPAMP_H -#define LIBOPENCM3_EFM32_EZR32WG_OPAMP_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/prs.h b/libopencm3/include/libopencm3/efm32/ezr32wg/prs.h deleted file mode 100644 index 6ce3633..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/prs.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup prs_defines PRS Defines - * - * @brief Defined Constants and Types for the Peripheral Reflex System - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/rmu.h b/libopencm3/include/libopencm3/efm32/ezr32wg/rmu.h deleted file mode 100644 index cad039e..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/rmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rmu_defines RMU Defines - * - * @brief Defined Constants and Types for the Reset Management Unit - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/rtc.h b/libopencm3/include/libopencm3/efm32/ezr32wg/rtc.h deleted file mode 100644 index a45a5e7..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/rtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the Real Time Clock - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/timer.h b/libopencm3/include/libopencm3/efm32/ezr32wg/timer.h deleted file mode 100644 index 439a418..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/timer.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup timer_defines TIMER Defines - * - * @brief Defined Constants and Types for the TIMER module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/uart.h b/libopencm3/include/libopencm3/efm32/ezr32wg/uart.h deleted file mode 100644 index 6f4bf3e..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup uart_defines UART Defines - * - * @brief Defined Constants and Types for the UART module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/usart.h b/libopencm3/include/libopencm3/efm32/ezr32wg/usart.h deleted file mode 100644 index 5db0aae..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/usart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the USART module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/usb.h b/libopencm3/include/libopencm3/efm32/ezr32wg/usb.h deleted file mode 100644 index 2d98089..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/usb.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usb_defines USB Defines - * - * @brief Defined Constants and Types for the USB module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/ezr32wg/wdog.h b/libopencm3/include/libopencm3/efm32/ezr32wg/wdog.h deleted file mode 100644 index e2c7fd9..0000000 --- a/libopencm3/include/libopencm3/efm32/ezr32wg/wdog.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup wdog_defines WDOG Defines - * - * @brief Defined Constants and Types for the Watchdog module - * - * @ingroup EZR32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/g/doc-efm32g.h b/libopencm3/include/libopencm3/efm32/g/doc-efm32g.h deleted file mode 100644 index 6630450..0000000 --- a/libopencm3/include/libopencm3/efm32/g/doc-efm32g.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 EFM32 Gecko - -@version 1.0.0 - -@date 11 November 2012 - -API documentation for Energy Micro EFM32 Gecko Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32G EFM32 Gecko -Libraries for Energy Micro EFM32 Gecko series. - -@version 1.0.0 - -@date 11 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32G_defines EFM32 Gecko Defines - -@brief Defined Constants and Types for the Energy Micro EFM32 Gecko series - -@version 1.0.0 - -@date 11 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/g/irq.json b/libopencm3/include/libopencm3/efm32/g/irq.json deleted file mode 100644 index 59cc38b..0000000 --- a/libopencm3/include/libopencm3/efm32/g/irq.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "acmp01", - "adc0", - "dac0", - "i2c0", - "gpio_odd", - "timer1", - "timer2", - "usart1_rx", - "usart1_tx", - "usart2_rx", - "usart2_tx", - "uart0_rx", - "uart0_tx", - "leuart0", - "leuart1", - "letimer0", - "pcnt0", - "pcnt1", - "pcnt2", - "rtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes" - ], - "partname_humanreadable": "EFM32 Gecko series", - "partname_doxygen": "EFM32G", - "includeguard": "LIBOPENCM3_EFM32G_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/gg/doc-efm32gg.h b/libopencm3/include/libopencm3/efm32/gg/doc-efm32gg.h deleted file mode 100644 index 1466677..0000000 --- a/libopencm3/include/libopencm3/efm32/gg/doc-efm32gg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 EFM32 Giant Gecko - -@version 1.0.0 - -@date 11 November 2012 - -API documentation for Energy Micro EFM32 Giant Gecko Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32GG EFM32 Giant Gecko -Libraries for Energy Micro EFM32 Giant Gecko series. - -@version 1.0.0 - -@date 11 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines - -@brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series - -@version 1.0.0 - -@date 11 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/gg/irq.json b/libopencm3/include/libopencm3/efm32/gg/irq.json deleted file mode 100644 index 43e7e8c..0000000 --- a/libopencm3/include/libopencm3/efm32/gg/irq.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "usb", - "acmp01", - "adc0", - "dac0", - "i2c0", - "i2c1", - "gpio_odd", - "timer1", - "timer2", - "timer3", - "usart1_rx", - "usart1_tx", - "lesense", - "usart2_rx", - "usart2_tx", - "uart0_rx", - "uart0_tx", - "uart1_rx", - "uart1_tx", - "leuart0", - "leuart1", - "letimer0", - "pcnt0", - "pcnt1", - "pcnt2", - "rtc", - "burtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes", - "ebi" - ], - "partname_humanreadable": "EFM32 Giant Gecko series", - "partname_doxygen": "EFM32GG", - "includeguard": "LIBOPENCM3_EFM32GG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/gpio.h b/libopencm3/include/libopencm3/efm32/gpio.h deleted file mode 100644 index 6bd3abf..0000000 --- a/libopencm3/include/libopencm3/efm32/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/hg/cmu.h b/libopencm3/include/libopencm3/efm32/hg/cmu.h deleted file mode 100644 index 6d513bf..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/cmu.h +++ /dev/null @@ -1,685 +0,0 @@ -/** @defgroup cmu_defines CMU Defines - * - * @brief Defined Constants and Types for the EFM32HG Clock Management Unit - * - * @ingroup EFM32HG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#pragma once - -#include -#include - -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTR MMIO32(CMU_BASE + 0x014) -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) -#define CMU_CMD MMIO32(CMU_BASE + 0x024) -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) -#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) -#define CMU_IF MMIO32(CMU_BASE + 0x030) -#define CMU_IFS MMIO32(CMU_BASE + 0x034) -#define CMU_IFC MMIO32(CMU_BASE + 0x038) -#define CMU_IEN MMIO32(CMU_BASE + 0x03C) -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) -#define CMU_LFCCLKEN0 MMIO32(CMU_BASE + 0x064) -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) -#define CMU_USBCRCTRL MMIO32(CMU_BASE + 0x0D0) -#define CMU_USHFRCOCTRL MMIO32(CMU_BASE + 0x0D4) -#define CMU_USHFRCOTUNE MMIO32(CMU_BASE + 0x0D8) -#define CMU_USHFRCOCONF MMIO32(CMU_BASE + 0x0DC) - -/* CMU_CTRL */ -#define CMU_CTRL_CLKOUTSEL1_SHIFT (23) -#define CMU_CTRL_CLKOUTSEL1_MASK (0x7 << CMU_CTRL_CLKOUTSEL1_SHIFT) -#define CMU_CTRL_CLKOUTSEL1(v) \ - (((v) << CMU_CTRL_CLKOUTSEL1_SHIFT) & CMU_CTRL_CLKOUTSEL1_MASK) -#define CMU_CTRL_CLKOUTSEL1_LFRCO CMU_CTRL_CLKOUTSEL1(0) -#define CMU_CTRL_CLKOUTSEL1_LFXO CMU_CTRL_CLKOUTSEL1(1) -#define CMU_CTRL_CLKOUTSEL1_HFCLK CMU_CTRL_CLKOUTSEL1(2) -#define CMU_CTRL_CLKOUTSEL1_LFXOQ CMU_CTRL_CLKOUTSEL1(3) -#define CMU_CTRL_CLKOUTSEL1_HFXOQ CMU_CTRL_CLKOUTSEL1(4) -#define CMU_CTRL_CLKOUTSEL1_LFRCOQ CMU_CTRL_CLKOUTSEL1(5) -#define CMU_CTRL_CLKOUTSEL1_HFRCOQ CMU_CTRL_CLKOUTSEL1(6) -#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ CMU_CTRL_CLKOUTSEL1(7) -#define CMU_CTRL_CLKOUTSEL1_USHFRCO CMU_CTRL_CLKOUTSEL1(8) - -#define CMU_CTRL_CLKOUTSEL0_SHIFT (20) -#define CMU_CTRL_CLKOUTSEL0_MASK (0x7 << CMU_CTRL_CLKOUTSEL0_SHIFT) -#define CMU_CTRL_CLKOUTSEL0(v) \ - (((v) << CMU_CTRL_CLKOUTSEL0_SHIFT) & CMU_CTRL_CLKOUTSEL0_MASK) -#define CMU_CTRL_CLKOUTSEL0_HFRCO CMU_CTRL_CLKOUTSEL0(0) -#define CMU_CTRL_CLKOUTSEL0_HFXO CMU_CTRL_CLKOUTSEL0(1) -#define CMU_CTRL_CLKOUTSEL0_HFCLK2 CMU_CTRL_CLKOUTSEL0(2) -#define CMU_CTRL_CLKOUTSEL0_HFCLK4 CMU_CTRL_CLKOUTSEL0(3) -#define CMU_CTRL_CLKOUTSEL0_HFCLK8 CMU_CTRL_CLKOUTSEL0(4) -#define CMU_CTRL_CLKOUTSEL0_HFCLK16 CMU_CTRL_CLKOUTSEL0(5) -#define CMU_CTRL_CLKOUTSEL0_ULFRCO CMU_CTRL_CLKOUTSEL0(6) -#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO CMU_CTRL_CLKOUTSEL0(7) - -#define CMU_CTRL_LFXOTIMEOUT_SHIFT (18) -#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3 << CMU_CTRL_LFXOTIMEOUT_SHIFT) -#define CMU_CTRL_LFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_LFXOTIMEOUT_SHIFT) & CMU_CTRL_LFXOTIMEOUT_MASK) -#define CMU_CTRL_LFXOTIMEOUT_8CYCLES CMU_CTRL_LFXOTIMEOUT(0) -#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES CMU_CTRL_LFXOTIMEOUT(1) -#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES CMU_CTRL_LFXOTIMEOUT(2) -#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES CMU_CTRL_LFXOTIMEOUT(3) - -#define CMU_CTRL_LFXOBUFCUR (1 << 17) - -#define CMU_CTRL_HFCLKDIV_SHIFT (14) -#define CMU_CTRL_HFCLKDIV_MASK (0x7 << CMU_CTRL_HFCLKDIV_SHIFT) -#define CMU_CTRL_HFCLKDIV(v) \ - (((v) << CMU_CTRL_HFCLKDIV_SHIFT) & CMU_CTRL_HFCLKDIV_MASK) -#define CMU_CTRL_HFCLKDIV_NODIV CMU_CTRL_HFCLKDIV(0) -#define CMU_CTRL_HFCLKDIV_DIV2 CMU_CTRL_HFCLKDIV(1) -#define CMU_CTRL_HFCLKDIV_DIV3 CMU_CTRL_HFCLKDIV(2) -#define CMU_CTRL_HFCLKDIV_DIV4 CMU_CTRL_HFCLKDIV(3) -#define CMU_CTRL_HFCLKDIV_DIV5 CMU_CTRL_HFCLKDIV(4) -#define CMU_CTRL_HFCLKDIV_DIV6 CMU_CTRL_HFCLKDIV(5) -#define CMU_CTRL_HFCLKDIV_DIV7 CMU_CTRL_HFCLKDIV(6) -#define CMU_CTRL_HFCLKDIV_DIV8 CMU_CTRL_HFCLKDIV(7) - -#define CMU_CTRL_LFXOBOOST (1 << 13) - -#define CMU_CTRL_LFXOMODE_SHIFT (11) -#define CMU_CTRL_LFXOMODE_MASK (0x3 << CMU_CTRL_LFXOMODE_SHIFT) -#define CMU_CTRL_LFXOMODE(v) \ - (((v) << CMU_CTRL_LFXOMODE_SHIFT) & CMU_CTRL_LFXOMODE_MASK) -#define CMU_CTRL_LFXOMODE_XTAL CMU_CTRL_LFXOMODE(0) -#define CMU_CTRL_LFXOMODE_BUFEXTCLK CMU_CTRL_LFXOMODE(1) -#define CMU_CTRL_LFXOMODE_DIGEXTCLK CMU_CTRL_LFXOMODE(2) - -#define CMU_CTRL_HFXOTIMEOUT_SHIFT (9) -#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3 << CMU_CTRL_HFXOTIMEOUT_SHIFT) -#define CMU_CTRL_HFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_HFXOTIMEOUT_SHIFT) & CMU_CTRL_HFXOTIMEOUT_MASK) -#define CMU_CTRL_HFXOTIMEOUT_8CYCLES CMU_CTRL_HFXOTIMEOUT(0) -#define CMU_CTRL_HFXOTIMEOUT_256CYCLES CMU_CTRL_HFXOTIMEOUT(1) -#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES CMU_CTRL_HFXOTIMEOUT(2) -#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES CMU_CTRL_HFXOTIMEOUT(3) - -#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) -#define CMU_CTRL_HFXOBUFCUR_MASK (0x3 << 5) - -#define CMU_CTRL_HFXOBOOST_SHIFT (2) -#define CMU_CTRL_HFXOBOOST_MASK (0x3 << CMU_CTRL_HFXOBOOST_SHIFT) -#define CMU_CTRL_HFXOBOOST(v) \ - (((v) << CMU_CTRL_HFXOBOOST_SHIFT) & CMU_CTRL_HFXOBOOST_MASK) -#define CMU_CTRL_HFXOBOOST_50PCENT CMU_CTRL_HFXOBOOST(0) -#define CMU_CTRL_HFXOBOOST_70PCENT CMU_CTRL_HFXOBOOST(1) -#define CMU_CTRL_HFXOBOOST_80PCENT CMU_CTRL_HFXOBOOST(2) -#define CMU_CTRL_HFXOBOOST_100PCENT CMU_CTRL_HFXOBOOST(3) - -#define CMU_CTRL_HFXOMODE_SHIFT (0) -#define CMU_CTRL_HFXOMODE_MASK (0x3 << CMU_CTRL_HFXOMODE_SHIFT) -#define CMU_CTRL_HFXOMODE(v) \ - (((v) << CMU_CTRL_HFXOMODE_SHIFT) & CMU_CTRL_HFXOMODE_MASK) -#define CMU_CTRL_HFXOMODE_XTAL CMU_CTRL_HFXOMODE(0) -#define CMU_CTRL_HFXOMODE_BUFEXTCLK CMU_CTRL_HFXOMODE(1) -#define CMU_CTRL_HFXOMODE_DIGEXTCLK CMU_CTRL_HFXOMODE(2) - -/* CMU_HFCORECLKDIV */ -#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (1 << 8) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT (0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_MASK \ - (0xF << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) -#define CMU_HFCORECLKDIV_HFCORECLKDIV(v) \ - (((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \ - CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK \ - CMU_HFCORECLKDIV_HFCORECLKDIV(0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(1) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(2) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(3) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(4) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(5) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(6) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(7) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(8) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(9) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 - -/* CMU_HFPERCLKDIV */ -#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) - -#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT (0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK \ - (0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) -#define CMU_HFPERCLKDIV_HFPERCLKDIV(v) \ - (((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \ - CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK CMU_HFPERCLKDIV_HFPERCLKDIV(0) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2 CMU_HFPERCLKDIV_HFPERCLKDIV(1) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4 CMU_HFPERCLKDIV_HFPERCLKDIV(2) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK8 CMU_HFPERCLKDIV_HFPERCLKDIV(3) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK16 CMU_HFPERCLKDIV_HFPERCLKDIV(4) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK32 CMU_HFPERCLKDIV_HFPERCLKDIV(5) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK64 CMU_HFPERCLKDIV_HFPERCLKDIV(6) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK128 CMU_HFPERCLKDIV_HFPERCLKDIV(7) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK256 CMU_HFPERCLKDIV_HFPERCLKDIV(8) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512 CMU_HFPERCLKDIV_HFPERCLKDIV(9) - -/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */ -#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 - -/* CMU_HFRCOCTRL */ -#define CMU_HFRCOCTRL_SUDELAY_SHIFT (12) -#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1F << CMU_HFRCOCTRL_SUDELAY_SHIFT) -#define CMU_HFRCOCTRL_SUDELAY(v) \ - ((((v) << CMU_HFRCOCTRL_SUDELAY_SHIFT) & CMU_HFRCOCTRL_SUDELAY_MASK)) - -#define CMU_HFRCOCTRL_BAND_SHIFT (8) -#define CMU_HFRCOCTRL_BAND_MASK (0x7 << CMU_HFRCOCTRL_BAND_SHIFT) -#define CMU_HFRCOCTRL_BAND(v) \ - (((v) << CMU_HFRCOCTRL_BAND_SHIFT) & CMU_HFRCOCTRL_BAND_MASK) -#define CMU_HFRCOCTRL_BAND_1MHZ CMU_HFRCOCTRL_BAND(0) -#define CMU_HFRCOCTRL_BAND_7MHZ CMU_HFRCOCTRL_BAND(1) -#define CMU_HFRCOCTRL_BAND_11MHZ CMU_HFRCOCTRL_BAND(2) -#define CMU_HFRCOCTRL_BAND_14MHZ CMU_HFRCOCTRL_BAND(3) -#define CMU_HFRCOCTRL_BAND_21MHZ CMU_HFRCOCTRL_BAND(4) - -#define CMU_HFRCOCTRL_TUNING_SHIFT (0) -#define CMU_HFRCOCTRL_TUNING_MASK (0xFF << CMU_HFRCOCTRL_TUNING_SHIFT) -#define CMU_HFRCOCTRL_TUNING(v) \ - (((v) << CMU_HFRCOCTRL_TUNING_SHIFT) & CMU_HFRCOCTRL_TUNING_MASK) - -/* CMU_LFRCOCTRL */ -#define CMU_LFRCOCTRL_TUNING_SHIFT (0) -#define CMU_LFRCOCTRL_TUNING_MASK (0xFF << CMU_LFRCOCTRL_TUNING_SHIFT) -#define CMU_LFRCOCTRL_TUNING(v) \ - (((v) << CMU_LFRCOCTRL_TUNING_SHIFT) & CMU_LFRCOCTRL_TUNING_MASK) - -/* CMU_AUXHFRCOCTRL */ -#define CMU_AUXHFRCOCTRL_BAND_SHIFT (8) -#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7 << CMU_AUXHFRCOCTRL_BAND_SHIFT) -#define CMU_AUXHFRCOCTRL_BAND(v) \ - (((v) << CMU_AUXHFRCOCTRL_BAND_SHIFT) & CMU_AUXHFRCOCTRL_BAND_MASK) -#define CMU_AUXHFRCOCTRL_BAND_14MHZ CMU_AUXHFRCOCTRL_BAND(0) -#define CMU_AUXHFRCOCTRL_BAND_11MHZ CMU_AUXHFRCOCTRL_BAND(1) -#define CMU_AUXHFRCOCTRL_BAND_7MHZ CMU_AUXHFRCOCTRL_BAND(2) -#define CMU_AUXHFRCOCTRL_BAND_1MHZ CMU_AUXHFRCOCTRL_BAND(3) -#define CMU_AUXHFRCOCTRL_BAND_28MHZ CMU_AUXHFRCOCTRL_BAND(6) -#define CMU_AUXHFRCOCTRL_BAND_21MHZ CMU_AUXHFRCOCTRL_BAND(7) - -#define CMU_AUXHFRCOCTRL_TUNING_SHIFT (0) -#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xFF << CMU_AUXHFRCOCTRL_TUNING_SHIFT) -#define CMU_AUXHFRCOCTRL_TUNING(v) \ - (((v) << CMU_AUXHFRCOCTRL_TUNING_SHIFT) & CMU_AUXHFRCOCTRL_TUNING_MASK) - -/* CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (1 << 6) - -#define CMU_CALCTRL_DOWNSEL_SHIFT (3) -#define CMU_CALCTRL_DOWNSEL_MASK (0x7 << CMU_CALCTRL_DOWNSEL_SHIFT) -#define CMU_CALCTRL_DOWNSEL(v) \ - (((v) << CMU_CALCTRL_DOWNSEL_SHIFT) & CMU_CALCTRL_DOWNSEL_MASK) -#define CMU_CALCTRL_DOWNSEL_HFCLK CMU_CALCTRL_DOWNSEL(0) -#define CMU_CALCTRL_DOWNSEL_HFXO CMU_CALCTRL_DOWNSEL(1) -#define CMU_CALCTRL_DOWNSEL_LFXO CMU_CALCTRL_DOWNSEL(2) -#define CMU_CALCTRL_DOWNSEL_HFRCO CMU_CALCTRL_DOWNSEL(3) -#define CMU_CALCTRL_DOWNSEL_LFRCO CMU_CALCTRL_DOWNSEL(4) -#define CMU_CALCTRL_DOWNSEL_AUXHFRCO CMU_CALCTRL_DOWNSEL(5) -#define CMU_CALCTRL_DOWNSEL_USHFRCO CMU_CALCTRL_DOWNSEL(6) - -#define CMU_CALCTRL_UPSEL_SHIFT (3) -#define CMU_CALCTRL_UPSEL_MASK (0x7 << CMU_CALCTRL_UPSEL_SHIFT) -#define CMU_CALCTRL_UPSEL(v) \ - (((v) << CMU_CALCTRL_UPSEL_SHIFT) & CMU_CALCTRL_UPSEL_MASK) -#define CMU_CALCTRL_UPSEL_HFXO CMU_CALCTRL_UPSEL(0) -#define CMU_CALCTRL_UPSEL_LFXO CMU_CALCTRL_UPSEL(1) -#define CMU_CALCTRL_UPSEL_HFRCO CMU_CALCTRL_UPSEL(2) -#define CMU_CALCTRL_UPSEL_LFRCO CMU_CALCTRL_UPSEL(3) -#define CMU_CALCTRL_UPSEL_AUXHFRCO CMU_CALCTRL_UPSEL(4) -#define CMU_CALCTRL_UPSEL_USHFRCO CMU_CALCTRL_UPSEL(5) - -/* CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_SHIFT (0) -#define CMU_CALCNT_CALCNT_MASK (0xFFFFF << CMU_CALCNT_CALCNT_SHIFT) -#define CMU_CALCNT_CALCNT(v) \ - (((v) << CMU_CALCNT_CALCNT_SHIFT) & CMU_CALCNT_CALCNT_MASK) - -/* CMU_OSCENCMD */ -/* Bits 31:12 - Reserved */ -#define CMU_OSCENCMD_USHFRCODIS (1 << 11) -#define CMU_OSCENCMD_USHFRCOEN (1 << 10) -#define CMU_OSCENCMD_LFXODIS (1 << 9) -#define CMU_OSCENCMD_LFXOEN (1 << 8) -#define CMU_OSCENCMD_LFRCODIS (1 << 7) -#define CMU_OSCENCMD_LFRCOEN (1 << 6) -#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) -#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) -#define CMU_OSCENCMD_HFXODIS (1 << 3) -#define CMU_OSCENCMD_HFXOEN (1 << 2) -#define CMU_OSCENCMD_HFRCODIS (1 << 1) -#define CMU_OSCENCMD_HFRCOEN (1 << 0) - -/* CMU_CMD */ -#define CMU_CMD_USBCCLKSEL_SHIFT (5) -#define CMU_CMD_USBCCLKSEL_MASK (0x5 << CMU_CMD_USBCCLKSEL_SHIFT) -#define CMU_CMD_USBCCLKSEL(v) \ - (((v) << CMU_CMD_USBCCLKSEL_SHIFT) & CMU_CMD_USBCCLKSEL_MASK) -#define CMU_CMD_USBCCLKSEL_LFXO CMU_CMD_USBCCLKSEL(2) -#define CMU_CMD_USBCCLKSEL_LFRCO CMU_CMD_USBCCLKSEL(3) -#define CMU_CMD_USBCCLKSEL_USHFRCO CMU_CMD_USBCCLKSEL(4) - -#define CMU_CMD_CALSTOP (1 << 4) -#define CMU_CMD_CALSTART (1 << 3) - -#define CMU_CMD_HFCLKSEL_SHIFT (0) -#define CMU_CMD_HFCLKSEL_MASK (0x7 << CMU_CMD_HFCLKSEL_SHIFT) -#define CMU_CMD_HFCLKSEL(v) \ - (((v) << CMU_CMD_HFCLKSEL_SHIFT) & CMU_CMD_HFCLKSEL_MASK) -#define CMU_CMD_HFCLKSEL_HFRCO CMU_CMD_HFCLKSEL(1) -#define CMU_CMD_HFCLKSEL_HFXO CMU_CMD_HFCLKSEL(2) -#define CMU_CMD_HFCLKSEL_LFRCO CMU_CMD_HFCLKSEL(3) -#define CMU_CMD_HFCLKSEL_LFXO CMU_CMD_HFCLKSEL(4) -#define CMU_CMD_HFCLKSEL_USHFRCODIV2 CMU_CMD_HFCLKSEL(5) - -/* CMU_LFCLKSEL */ -/* Bits 31:21 - Reserved */ -#define CMU_LFCLKSEL_LFBE (1 << 20) -/* Bits 19:17 - Reserved */ -#define CMU_LFCLKSEL_LFAE (1 << 16) -/* Bits 15:6 - Reserved */ - -#define CMU_LFCLKSEL_LFC_SHIFT (4) -#define CMU_LFCLKSEL_LFC_MASK (0x3 << CMU_LFCLKSEL_LFC_SHIFT) -#define CMU_LFCLKSEL_LFC(v) \ - (((v) << CMU_LFCLKSEL_LFC_SHIFT) & CMU_LFCLKSEL_LFC_MASK) -#define CMU_LFCLKSEL_LFC_DISABLED CMU_LFCLKSEL_LFC(0) -#define CMU_LFCLKSEL_LFC_LFRCO CMU_LFCLKSEL_LFC(1) -#define CMU_LFCLKSEL_LFC_LFXO CMU_LFCLKSEL_LFC(2) - -#define CMU_LFCLKSEL_LFB_SHIFT (2) -#define CMU_LFCLKSEL_LFB_MASK (0x3 << CMU_LFCLKSEL_LFB_SHIFT) -#define CMU_LFCLKSEL_LFB(v) \ - (((v) << CMU_LFCLKSEL_LFB_SHIFT) & CMU_LFCLKSEL_LFB_MASK) - -#define CMU_LFCLKSEL_LFA_SHIFT (0) -#define CMU_LFCLKSEL_LFA_MASK (0x3 << CMU_LFCLKSEL_LFA_SHIFT) -#define CMU_LFCLKSEL_LFA(v) \ - (((v) << CMU_LFCLKSEL_LFA_SHIFT) & CMU_LFCLKSEL_LFA_MASK) - -/* CMU_STATUS */ -/* Bits 31:27 - Reserved */ -#define CMU_STATUS_USHFRCODIV2SEL (1 << 26) -/* Bits 25:24 - Reserved */ -#define CMU_STATUS_USHFRCOSUSPEND (1 << 23) -#define CMU_STATUS_USHFRCORDY (1 << 22) -#define CMU_STATUS_USHFRCOENS (1 << 21) -#define CMU_STATUS_USBCHFCLKSYNC (1 << 20) -/* Bit 19 - Reserved */ -#define CMU_STATUS_USBCUSHFRCOSEL (1 << 18) -#define CMU_STATUS_USBCLFRCOSEL (1 << 17) -#define CMU_STATUS_USBCLFXOSEL (1 << 16) -/* Bit 15 - Reserved */ -#define CMU_STATUS_CALBSY (1 << 14) -#define CMU_STATUS_LFXOSEL (1 << 13) -#define CMU_STATUS_LFRCOSEL (1 << 12) -#define CMU_STATUS_HFXOSEL (1 << 11) -#define CMU_STATUS_HFRCOSEL (1 << 10) -#define CMU_STATUS_LFXORDY (1 << 9) -#define CMU_STATUS_LFXOENS (1 << 8) -#define CMU_STATUS_LFRCORDY (1 << 7) -#define CMU_STATUS_LFRCOENS (1 << 6) -#define CMU_STATUS_AUXHFRCORDY (1 << 5) -#define CMU_STATUS_AUXHFRCOENS (1 << 4) -#define CMU_STATUS_HFXORDY (1 << 3) -#define CMU_STATUS_HFXOENS (1 << 2) -#define CMU_STATUS_HFRCORDY (1 << 1) -#define CMU_STATUS_HFRCOENS (1 << 0) - -/* CMU_IF */ -/* Bits 31:10 - Reserved */ -#define CMU_IF_USBCHFOSCSEL (1 << 9) -#define CMU_IF_USHFRCORDY (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_IF_CALOF (1 << 6) -#define CMU_IF_CALRDY (1 << 5) -#define CMU_IF_AUXHFRCORDY (1 << 4) -#define CMU_IF_LFXORDY (1 << 3) -#define CMU_IF_LFRCORDY (1 << 2) -#define CMU_IF_HFXORDY (1 << 1) -#define CMU_IF_HFRCORDY (1 << 0) - -/* CMU_IFS */ -/* Bits 31:10 - Reserved */ -#define CMU_IFS_USBCHFOSCSEL (1 << 9) -#define CMU_IFS_USHFRCORDY (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_IFS_CALOF (1 << 6) -#define CMU_IFS_CALRDY (1 << 5) -#define CMU_IFS_AUXHFRCORDY (1 << 4) -#define CMU_IFS_LFXORDY (1 << 3) -#define CMU_IFS_LFRCORDY (1 << 2) -#define CMU_IFS_HFXORDY (1 << 1) -#define CMU_IFS_HFRCORDY (1 << 0) - -/* CMU_IFC */ -/* Bits 31:10 - Reserved */ -#define CMU_IFC_USBCHFOSCSEL (1 << 9) -#define CMU_IFC_USHFRCORDY (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_IFC_CALOF (1 << 6) -#define CMU_IFC_CALRDY (1 << 5) -#define CMU_IFC_AUXHFRCORDY (1 << 4) -#define CMU_IFC_LFXORDY (1 << 3) -#define CMU_IFC_LFRCORDY (1 << 2) -#define CMU_IFC_HFXORDY (1 << 1) -#define CMU_IFC_HFRCORDY (1 << 0) - -/* CMU_IEN */ -/* Bits 31:10 - Reserved */ -#define CMU_IEN_USBCHFOSCSEL (1 << 9) -#define CMU_IEN_USHFRCORDY (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_IEN_CALOF (1 << 6) -#define CMU_IEN_CALRDY (1 << 5) -#define CMU_IEN_AUXHFRCORDY (1 << 4) -#define CMU_IEN_LFXORDY (1 << 3) -#define CMU_IEN_LFRCORDY (1 << 2) -#define CMU_IEN_HFXORDY (1 << 1) -#define CMU_IEN_HFRCORDY (1 << 0) - -/* CMU_HFCORECLKEN0 */ -/* Bits 31:5 - Reserved */ -#define CMU_HFCORECLKEN0_USB (1 << 4) -#define CMU_HFCORECLKEN0_USBC (1 << 3) -#define CMU_HFCORECLKEN0_LE (1 << 2) -#define CMU_HFCORECLKEN0_DMA (1 << 1) -#define CMU_HFCORECLKEN0_AES (1 << 0) - -/* CMU_HFPERCLKEN0 */ -/* Bits 31:12 - Reserved */ -#define CMU_HFPERCLKEN0_I2C0 (1 << 11) -#define CMU_HFPERCLKEN0_ADC0 (1 << 10) -#define CMU_HFPERCLKEN0_VCMP (1 << 9) -#define CMU_HFPERCLKEN0_GPIO (1 << 8) -#define CMU_HFPERCLKEN0_IDAC0 (1 << 7) -#define CMU_HFPERCLKEN0_PRS (1 << 6) -#define CMU_HFPERCLKEN0_ACMP0 (1 << 5) -#define CMU_HFPERCLKEN0_USART1 (1 << 4) -#define CMU_HFPERCLKEN0_USART0 (1 << 3) -#define CMU_HFPERCLKEN0_TIMER2 (1 << 2) -#define CMU_HFPERCLKEN0_TIMER1 (1 << 1) -#define CMU_HFPERCLKEN0_TIMER0 (1 << 0) - -/* CMU_SYNCBUSY */ -/* Bits 31:9 - Reserved */ -#define CMU_SYNCBUSY_LFCCLKEN0 (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) -/* Bit 5 - Reserved */ -#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) -/* Bit 3 - Reserved */ -#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) -/* Bit 1 - Reserved */ -#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) - -/* CMU_FREEZE */ -#define CMU_FREEZE_REGFREEZE (1 << 0) - -/* CMU_LFACLKEN0 */ -#define CMU_LFACLKEN0_RTC (1 << 0) - -/* CMU_LFBCLKEN0 */ -#define CMU_LFBCLKEN0_LEUART0 (1 << 0) - -/* CMU_LFCCLKEN0 */ -#define CMU_LFCCLKEN0_USBLE (1 << 0) - -/* CMU_LFAPRESC0 */ -#define CMU_LFAPRESC0_RTC_SHIFT (0) -#define CMU_LFAPRESC0_RTC_MASK (0xF << CMU_LFAPRESC0_RTC_SHIFT) -#define CMU_LFAPRESC0_RTC(v) \ - (((v) << CMU_LFAPRESC0_RTC_SHIFT) & CMU_LFAPRESC0_RTC_MASK) -#define CMU_LFAPRESC0_RTC_DIV1 CMU_LFAPRESC0_RTC(0) -#define CMU_LFAPRESC0_RTC_DIV2 CMU_LFAPRESC0_RTC(1) -#define CMU_LFAPRESC0_RTC_DIV4 CMU_LFAPRESC0_RTC(2) -#define CMU_LFAPRESC0_RTC_DIV8 CMU_LFAPRESC0_RTC(3) -#define CMU_LFAPRESC0_RTC_DIV16 CMU_LFAPRESC0_RTC(4) -#define CMU_LFAPRESC0_RTC_DIV32 CMU_LFAPRESC0_RTC(5) -#define CMU_LFAPRESC0_RTC_DIV64 CMU_LFAPRESC0_RTC(6) -#define CMU_LFAPRESC0_RTC_DIV128 CMU_LFAPRESC0_RTC(7) -#define CMU_LFAPRESC0_RTC_DIV256 CMU_LFAPRESC0_RTC(8) -#define CMU_LFAPRESC0_RTC_DIV512 CMU_LFAPRESC0_RTC(9) -#define CMU_LFAPRESC0_RTC_DIV1024 CMU_LFAPRESC0_RTC(10) -#define CMU_LFAPRESC0_RTC_DIV2048 CMU_LFAPRESC0_RTC(11) -#define CMU_LFAPRESC0_RTC_DIV4096 CMU_LFAPRESC0_RTC(12) -#define CMU_LFAPRESC0_RTC_DIV8192 CMU_LFAPRESC0_RTC(13) -#define CMU_LFAPRESC0_RTC_DIV16384 CMU_LFAPRESC0_RTC(14) -#define CMU_LFAPRESC0_RTC_DIV32768 CMU_LFAPRESC0_RTC(15) -#define CMU_LFAPRESC0_RTC_NODIV CMU_LFAPRESC0_RTC_DIV1 - -/* CMU_LFBPRESC0 */ -#define CMU_LFBPRESC0_LEUART0_SHIFT (0) -#define CMU_LFBPRESC0_LEUART0_MASK (0x3 << CMU_LFBPRESC0_LEUART0_SHIFT) -#define CMU_LFBPRESC0_LEUART0(v) \ - (((v) << CMU_LFBPRESC0_LEUART0_SHIFT) & CMU_LFBPRESC0_LEUART0_MASK) -#define CMU_LFBPRESC0_LEUART0_DIV1 CMU_LFBPRESC0_LEUART0(0) -#define CMU_LFBPRESC0_LEUART0_DIV2 CMU_LFBPRESC0_LEUART0(1) -#define CMU_LFBPRESC0_LEUART0_DIV4 CMU_LFBPRESC0_LEUART0(2) -#define CMU_LFBPRESC0_LEUART0_DIV8 CMU_LFBPRESC0_LEUART0(3) -#define CMU_LFBPRESC0_LEUART0_NODIV CMU_LFBPRESC0_LEUART0_DIV1 - -/* CMU_PCNTCTRL */ -#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) -#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) - -/* CMU_ROUTE */ -#define CMU_ROUTE_LOCATION_SHIFT (2) -#define CMU_ROUTE_LOCATION_MASK (0x7 << CMU_ROUTE_LOCATION_SHIFT) -#define CMU_ROUTE_LOCATION_LOCx(i) \ - (((i) << CMU_ROUTE_LOCATION_SHIFT) & CMU_ROUTE_LOCATION_MASK) -#define CMU_ROUTE_LOCATION_LOC0 CMU_ROUTE_LOCATION_LOCx(0) -#define CMU_ROUTE_LOCATION_LOC1 CMU_ROUTE_LOCATION_LOCx(1) -#define CMU_ROUTE_LOCATION_LOC2 CMU_ROUTE_LOCATION_LOCx(2) -#define CMU_ROUTE_LOCATION_LOC3 CMU_ROUTE_LOCATION_LOCx(3) - -#define CMU_ROUTE_CLKOUT1PEN (1 << 1) -#define CMU_ROUTE_CLKOUT0PEN (1 << 0) - -/* CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_SHIFT (0) -#define CMU_LOCK_LOCKKEY_MASK (0xFFFF << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCKED (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCKED (0x0001 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCK (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCK (0x580E << CMU_LOCK_LOCKKEY_SHIFT) - -/* CMU_USBCRCTRL */ -#define CMU_USBCRCTRL_LSMODE (1 << 1) -#define CMU_USBCRCTRL_EN (1 << 0) - -/* CMU_USHFRCOCTRL */ -/* Bits 31:20 - Reserved */ -#define CMU_USHFRCOCTRL_TIMEOUT_MASK (0xff << 12) -/* Bits 11:10 - Reserved */ -#define CMU_USHFRCOCTRL_SUSPEND (1 << 9) -#define CMU_USHFRCOCTRL_DITHEN (1 << 8) -/* Bit 7 - Reserved */ -#define CMU_USHFRCOCTRL_TUNING_MASK (0x7f << 0) - -/* CMU_USHFRCOTUNE */ -/* Bits 31:6 - Reserved */ -#define CMU_USHFRCOTUNE_FINETUNING_MASK (0x3f << 0) - -/* CMU_USHFRCOCONF */ -/* Bits 31:5 - Reserved */ -#define CMU_USHFRCOTUNE_USHFRCODIV2DIS (1 << 4) -/* Bit 3 - Reserved */ -#define CMU_USHFRCOCONF_BAND_MASK (0x7 << 0) -#define CMU_USHFRCOCONF_BAND_48MHZ (0x1 << 0) -#define CMU_USHFRCOCONF_BAND_24MHZ (0x3 << 0) - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum cmu_periph_clken { - /* CMU_PCNTCTRL */ - CMU_PCNT0 = _REG_BIT(0x078, 1), - - /* CMU_LFCCLKEN0 */ - CMU_USBLE = _REG_BIT(0x064, 0), - - /* CMU_LFBCLKEN0 */ - CMU_LEUART0 = _REG_BIT(0x060, 0), - - /* CMU_LFACLKEN0 */ - CMU_RTC = _REG_BIT(0x058, 0), - - /* CMU_HFPERCLKEN0 */ - CMU_I2C0 = _REG_BIT(0x044, 11), - CMU_ADC0 = _REG_BIT(0x044, 10), - CMU_VCMP = _REG_BIT(0x044, 9), - CMU_GPIO = _REG_BIT(0x044, 8), - CMU_IDAC0 = _REG_BIT(0x044, 7), - CMU_PRS = _REG_BIT(0x044, 6), - CMU_ACMP0 = _REG_BIT(0x044, 5), - CMU_USART1 = _REG_BIT(0x044, 4), - CMU_USART0 = _REG_BIT(0x044, 3), - CMU_TIMER2 = _REG_BIT(0x044, 2), - CMU_TIMER1 = _REG_BIT(0x044, 1), - CMU_TIMER0 = _REG_BIT(0x044, 0), - - /* CMU_HFCORECLKEN0 */ - CMU_USB = _REG_BIT(0x040, 4), - CMU_USBC = _REG_BIT(0x040, 3), - CMU_LE = _REG_BIT(0x040, 2), - CMU_DMA = _REG_BIT(0x040, 1) -}; - -enum cmu_osc { - HFRCO, /**< Internal, 1 - 28Mhz */ - LFRCO, /**< Internal, 32.768kHz */ - HFXO, /**< External, 4-48Mhz */ - LFXO, /**< External, 32.768kHz */ - AUXHFRCO, /**< Internal, 1-28Mhz */ - USHFRCO, /**< Internal, 48MHz */ - USHFRCODIV2, /**< Internal, 24MHz */ -}; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void cmu_enable_lock(void); -void cmu_disable_lock(void); -bool cmu_get_lock_flag(void); - -void cmu_periph_clock_enable(enum cmu_periph_clken periph); -void cmu_periph_clock_disable(enum cmu_periph_clken periph); - -/* TODO: CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, - * CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_CALCTRL, CMU_CALCNT */ - -void cmu_osc_on(enum cmu_osc osc); -void cmu_osc_off(enum cmu_osc osc); - -/* TODO: CMU_CMD, CMU_LFCLKSEL */ - -/* TODO: portions of CMU_STATUS */ -bool cmu_osc_ready_flag(enum cmu_osc osc); -void cmu_wait_for_osc_ready(enum cmu_osc osc); -void cmu_set_hfclk_source(enum cmu_osc osc); -enum cmu_osc cmu_get_hfclk_source(void); - -void cmu_set_usbclk_source(enum cmu_osc osc); -void cmu_wait_for_usbclk_selected(enum cmu_osc osc); - -/* TODO: CMU_IF, CMU_IFS, CMU_IFC, CMU_IEN */ - -/* TODO: CMU_SYNCBUSY, CMU_FREEZE, CMU_LFACLKEN0 */ - -/* TODO: CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_PCNTCTRL, CMU_LCDCTRL, CMU_ROUTE */ - -END_DECLS - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/hg/doc-efm32hg.h b/libopencm3/include/libopencm3/efm32/hg/doc-efm32hg.h deleted file mode 100644 index e3de840..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/doc-efm32hg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 EFM32 Happy Gecko - -@version 1.0.0 - -@date 28 January 2018 - -API documentation for Energy Micro EFM32 Happy Gecko Cortex M0+ series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32HG EFM32 HappyGecko -Libraries for Energy Micro EFM32 Happy Gecko series. - -@version 1.0.0 - -@date 28 January 2018 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32HG_defines EFM32 Happy Gecko Defines - -@brief Defined Constants and Types for the Energy Micro EFM32 Happy Gecko -series - -@version 1.0.0 - -@date 28 January 2018 - -LGPL License Terms @ref lgpl_license -*/ diff --git a/libopencm3/include/libopencm3/efm32/hg/gpio.h b/libopencm3/include/libopencm3/efm32/hg/gpio.h deleted file mode 100644 index 5be1565..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the EFM32HG GPIO module - * - * @ingroup EFM32HG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/hg/irq.json b/libopencm3/include/libopencm3/efm32/hg/irq.json deleted file mode 100644 index fd89046..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/irq.json +++ /dev/null @@ -1,29 +0,0 @@ -{ - "_source": "The names and sequence are taken from EFM32HG-RM.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "acmp0", - "adc0", - "i2c0", - "gpio_odd", - "timer1", - "usart1_rx", - "usart1_tx", - "leuart0", - "pcnt0", - "rtc", - "cmu", - "vcmp", - "msc", - "aes", - "usart0_rx", - "usart0_tx", - "usb", - "timer2" - ], - "partname_humanreadable": "EFM32 Happy Gecko series", - "partname_doxygen": "EFM32HG", - "includeguard": "LIBOPENCM3_EFM32HG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/hg/memorymap.h b/libopencm3/include/libopencm3/efm32/hg/memorymap.h deleted file mode 100644 index 2589872..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/memorymap.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H -#define LIBOPENCM3_EFM32_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) - -/* Device information */ -#define DI_BASE (0x0FE08000U) - -/* all names are "DI_" + */ -#define DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020) -#define DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028) -#define DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030) -#define DI_ADC0_CAL MMIO32(DI_BASE + 0x040) -#define DI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048) -#define DI_ACMP0_CTRL MMIO32(DI_BASE + 0x050) -#define DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x058) -#define DI_IDAC0_CAL MMIO32(DI_BASE + 0x078) -#define DI_USHFRCOCTRL MMIO32(DI_BASE + 0x098) -#define DI_DI_CRC MMIO16(DI_BASE + 0x1B0) -#define DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2) -#define DI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4) -#define DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6) -#define DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8) -#define DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA) -#define DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC) -#define DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE) -#define DI_IDAC0_CAL_RANGE0 MMIO32(DI_BASE + 0x1C8) -#define DI_IDAC0_CAL_RANGE1 MMIO32(DI_BASE + 0x1C9) -#define DI_IDAC0_CAL_RANGE2 MMIO32(DI_BASE + 0x1CA) -#define DI_IDAC0_CAL_RANGE3 MMIO32(DI_BASE + 0x1CB) -#define DI_USHFRCO_COARSECAL_BAND_25 MMIO32(DI_BASE + 0x1CC) -#define DI_USHFRCO_FINECAL_BAND_25 MMIO32(DI_BASE + 0x1CD) -#define DI_USHFRCO_COARSECAL_BAND_48 MMIO32(DI_BASE + 0x1CE) -#define DI_USHFRCO_FINECAL_BAND_48 MMIO32(DI_BASE + 0x1CF) -#define DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4) -#define DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5) -#define DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6) -#define DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7) -#define DI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8) -#define DI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC) -#define DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD) -#define DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE) -#define DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF) -#define DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0) -#define DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0) -#define DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4) -#define DI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8) -#define DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA) -#define DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC) -#define DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE) -#define DI_PROD_REV MMIO8(DI_BASE + 0x1FF) - -#define AES_BASE (PERIPH_BASE + 0xE0000) -#define PRS_BASE (PERIPH_BASE + 0xCC000) -#define RMU_BASE (PERIPH_BASE + 0xCA000) -#define CMU_BASE (PERIPH_BASE + 0xC8000) -#define EMU_BASE (PERIPH_BASE + 0xC6000) -#define USB_BASE (PERIPH_BASE + 0xC4000) -#define DMA_BASE (PERIPH_BASE + 0xC2000) -#define MSC_BASE (PERIPH_BASE + 0xC0000) -#define WDOG_BASE (PERIPH_BASE + 0x88000) -#define PCNT0_BASE (PERIPH_BASE + 0x86000) -#define LEUART0_BASE (PERIPH_BASE + 0x84000) -#define RTC_BASE (PERIPH_BASE + 0x80000) -#define TIMER2_BASE (PERIPH_BASE + 0x10800) -#define TIMER1_BASE (PERIPH_BASE + 0x10400) -#define TIMER0_BASE (PERIPH_BASE + 0x10000) -#define USART1_BASE (PERIPH_BASE + 0x0C400) -#define USART0_BASE (PERIPH_BASE + 0x0C000) -#define I2C0_BASE (PERIPH_BASE + 0x0A000) -#define GPIO_BASE (PERIPH_BASE + 0x06000) -#define IDAC0_BASE (PERIPH_BASE + 0x04000) -#define ADC0_BASE (PERIPH_BASE + 0x02000) -#define ACMP0_BASE (PERIPH_BASE + 0x01000) -#define VCMP_BASE (PERIPH_BASE + 0x00000) - -#define USB_OTG_FS_BASE (USB_BASE + 0x3C000) - -#endif diff --git a/libopencm3/include/libopencm3/efm32/hg/timer.h b/libopencm3/include/libopencm3/efm32/hg/timer.h deleted file mode 100644 index 9d88c2e..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/timer.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup timer_defines TIMER Defines - * - * @brief Defined Constants and Types for the TIMER module - * - * @ingroup EFM32HG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -/* efm32hg specific registers */ - -/* TIMER_ROUTE */ -#define TIMER_ROUTE_LOCATION_LOC6 TIMER_ROUTE_LOCATION_LOCx(6) - -/* TIMER_CCx_CTRL */ -#define TIMER_CC_CTRL_PRSCONF (1 << 28) diff --git a/libopencm3/include/libopencm3/efm32/hg/usb.h b/libopencm3/include/libopencm3/efm32/hg/usb.h deleted file mode 100644 index b3b45ba..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/usb.h +++ /dev/null @@ -1,70 +0,0 @@ -/** @defgroup usb_defines USB Defines - * - * @brief Defined Constants and Types for the USB module - * - * @ingroup EFM32HG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -#define USB_CTRL MMIO32(USB_BASE + 0x000) -#define USB_STATUS MMIO32(USB_BASE + 0x004) -#define USB_IF MMIO32(USB_BASE + 0x008) -#define USB_IFS MMIO32(USB_BASE + 0x00C) -#define USB_IFC MMIO32(USB_BASE + 0x010) -#define USB_IEN MMIO32(USB_BASE + 0x014) -#define USB_ROUTE MMIO32(USB_BASE + 0x018) - -/* USB_CTRL */ -/* Bits 31:26 - Reserved */ -#define USB_CTRL_BIASPROGEM23_MASK (0x3 << 24) -/* Bits 23:22 - Reserved */ -#define USB_CTRL_BIASPROGEM01_MASK (0x3 << 20) -/* Bits 19:18 - Reserved */ -#define USB_CTRL_VREGOSEN (1 << 17) -#define USB_CTRL_VREGDIS (1 << 16) -/* Bits 15:10 - Reserved */ -#define USB_CTRL_LEMIDLEEN (1 << 9) -/* Bit 8 - Reserved */ -#define USB_CTRL_LEMPHYCTRL (1 << 7) -/* Bit 6 - Reserved */ -#define USB_CTRL_LEMOSCCTRL_MASK (0x3 << 4) -#define USB_CTRL_LEMOSCCTRL_NONE (0x0 << 4) -#define USB_CTRL_LEMOSCCTRL_GATE (0x1 << 4) -/* Bits 3:2 - Reserved */ -#define USB_CTRL_DMPUAP (1 << 1) -/* Bit 0 - Reserved */ - -/* USB_ROUTE */ -/* Bits 31:3 - Reserved */ -#define USB_ROUTE_DMPUPEN (1 << 2) -/* Bit 1 - Reserved */ -#define USB_ROUTE_PHYPEN (1 << 0) - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/efm32/hg/wdog.h b/libopencm3/include/libopencm3/efm32/hg/wdog.h deleted file mode 100644 index 949896b..0000000 --- a/libopencm3/include/libopencm3/efm32/hg/wdog.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @defgroup wdog_defines WDOG Defines - * - * @brief Defined Constants and Types for the Watchdog module - * - * @ingroup EFM32HG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/i2c.h b/libopencm3/include/libopencm3/efm32/i2c.h deleted file mode 100644 index 0f65411..0000000 --- a/libopencm3/include/libopencm3/efm32/i2c.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/letimer.h b/libopencm3/include/libopencm3/efm32/letimer.h deleted file mode 100644 index 1118fdd..0000000 --- a/libopencm3/include/libopencm3/efm32/letimer.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/lg/acmp.h b/libopencm3/include/libopencm3/efm32/lg/acmp.h deleted file mode 100644 index 7b96129..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/acmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup acmp_defines ACMP Defines - * - * @brief Defined Constants and Types for the Analog Comparator module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/adc.h b/libopencm3/include/libopencm3/efm32/lg/adc.h deleted file mode 100644 index 3e8d4f5..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/adc.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the EFM32LG Analog to Digital - * Converter - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - diff --git a/libopencm3/include/libopencm3/efm32/lg/burtc.h b/libopencm3/include/libopencm3/efm32/lg/burtc.h deleted file mode 100644 index fa58033..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/burtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup burtc_defines BURTC Defines - * - * @brief Defined Constants and Types for the Backup RTC - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/cmu.h b/libopencm3/include/libopencm3/efm32/lg/cmu.h deleted file mode 100644 index 9316870..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/cmu.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup cmu_defines CMU Defines - * - * @brief Defined Constants and Types for the EFM32LG Clock Management Unit - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - diff --git a/libopencm3/include/libopencm3/efm32/lg/dac.h b/libopencm3/include/libopencm3/efm32/lg/dac.h deleted file mode 100644 index 3611a24..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/dac.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dac_defines DAC Defines - * - * @brief Defined Constants and Types for the D/A Converter module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/dma.h b/libopencm3/include/libopencm3/efm32/lg/dma.h deleted file mode 100644 index 57d4ddd..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/dma.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @brief Defined Constants and Types for the DMA module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/doc-efm32lg.h b/libopencm3/include/libopencm3/efm32/lg/doc-efm32lg.h deleted file mode 100644 index 93f39ed..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/doc-efm32lg.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @page libopencm3 EFM32 Leopard Gecko - -@version 1.0.0 - -@date 4 March 2013 - -API documentation for Energy Micro EFM32 Leopard Gecko Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32LG EFM32 LeopardGecko -Libraries for Energy Micro EFM32 Leopard Gecko series. - -@version 1.0.0 - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines - -@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko -series - -@version 1.0.0 - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/lg/emu.h b/libopencm3/include/libopencm3/efm32/lg/emu.h deleted file mode 100644 index 92b350c..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/emu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup emu_defines EMU Defines - * - * @brief Defined Constants and Types for the Energy Management Unit - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/gpio.h b/libopencm3/include/libopencm3/efm32/lg/gpio.h deleted file mode 100644 index f0684ba..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the EFM32LG GPIO module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/i2c.h b/libopencm3/include/libopencm3/efm32/lg/i2c.h deleted file mode 100644 index 9ff55f9..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/i2c.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the I²C module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/irq.json b/libopencm3/include/libopencm3/efm32/lg/irq.json deleted file mode 100644 index 3ffdc0d..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/irq.json +++ /dev/null @@ -1,47 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "usb", - "acmp01", - "adc0", - "dac0", - "i2c0", - "i2c1", - "gpio_odd", - "timer1", - "timer2", - "timer3", - "usart1_rx", - "usart1_tx", - "lesense", - "usart2_rx", - "usart2_tx", - "uart0_rx", - "uart0_tx", - "uart1_rx", - "uart1_tx", - "leuart0", - "leuart1", - "letimer0", - "pcnt0", - "pcnt1", - "pcnt2", - "rtc", - "burtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes", - "ebi", - "emu" - ], - "partname_humanreadable": "EFM32 Leopard Gecko series", - "partname_doxygen": "EFM32LG", - "includeguard": "LIBOPENCM3_EFM32LG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/lg/letimer.h b/libopencm3/include/libopencm3/efm32/lg/letimer.h deleted file mode 100644 index 9a12151..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/letimer.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup letimer_defines LETIMER Defines - * - * @brief Defined Constants and Types for the Low Energy Timer - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/memorymap.h b/libopencm3/include/libopencm3/efm32/lg/memorymap.h deleted file mode 100644 index 22c0073..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/memorymap.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H -#define LIBOPENCM3_EFM32_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) - -/* Device information */ -#define DI_BASE (0x0FE08000U) - -/* all names are "DI_" + */ -#define DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020) -#define DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028) -#define DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030) -#define DI_ADC0_CAL MMIO32(DI_BASE + 0x040) -#define DI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048) -#define DI_DAC0_CAL MMIO32(DI_BASE + 0x050) -#define DI_DAC0_BIASPROG MMIO32(DI_BASE + 0x058) -#define DI_ACMP0_CTRL MMIO32(DI_BASE + 0x060) -#define DI_ACMP1_CTRL MMIO32(DI_BASE + 0x068) -#define DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x078) -#define DI_DAC0_OPACTRL MMIO32(DI_BASE + 0x0A0) -#define DI_DAC0_OPAOFFSET MMIO32(DI_BASE + 0x0A8) -#define DI_EMU_BUINACT MMIO32(DI_BASE + 0x0B0) -#define DI_EMU_BUACT MMIO32(DI_BASE + 0x0B8) -#define DI_EMU_BUBODBUVINCAL MMIO32(DI_BASE + 0x0C0) -#define DI_EMU_BUBODUNREGCAL MMIO32(DI_BASE + 0x0C8) -#define DI_DI_CRC MMIO16(DI_BASE + 0x1B0) -#define DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2) -#define DI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4) -#define DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6) -#define DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8) -#define DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA) -#define DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC) -#define DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE) -#define DI_DAC0_CAL_1V25 MMIO32(DI_BASE + 0x1C8) -#define DI_DAC0_CAL_2V5 MMIO32(DI_BASE + 0x1CC) -#define DI_DAC0_CAL_VDD MMIO32(DI_BASE + 0x1D0) -#define DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4) -#define DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5) -#define DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6) -#define DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7) -#define DI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8) -#define DI_AUXHFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1D9) -#define DI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC) -#define DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD) -#define DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE) -#define DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF) -#define DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0) -#define DI_HFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1E1) -#define DI_MEM_INFO_PAGE_SIZE MMIO8(DI_BASE + 0x1E7) -#define DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0) -#define DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4) -#define DI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8) -#define DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA) -#define DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC) -#define DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE) -#define DI_PROD_REV MMIO8(DI_BASE + 0x1FF) - -#define AES_BASE (PERIPH_BASE + 0xE0000) -#define PRS_BASE (PERIPH_BASE + 0xCC000) -#define RMU_BASE (PERIPH_BASE + 0xCA000) -#define CMU_BASE (PERIPH_BASE + 0xC8000) -#define EMU_BASE (PERIPH_BASE + 0xC6000) -#define USB_BASE (PERIPH_BASE + 0xC4000) -#define DMA_BASE (PERIPH_BASE + 0xC2000) -#define MSC_BASE (PERIPH_BASE + 0xC0000) -#define LESENSE_BASE (PERIPH_BASE + 0x8C000) -#define LCD_BASE (PERIPH_BASE + 0x8A000) -#define WDOG_BASE (PERIPH_BASE + 0x88000) -#define PCNT2_BASE (PERIPH_BASE + 0x86800) -#define PCNT1_BASE (PERIPH_BASE + 0x86400) -#define PCNT0_BASE (PERIPH_BASE + 0x86000) -#define LEUART1_BASE (PERIPH_BASE + 0x84400) -#define LEUART0_BASE (PERIPH_BASE + 0x84000) -#define LETIMER0_BASE (PERIPH_BASE + 0x82000) -#define BURTC_BASE (PERIPH_BASE + 0x81000) -#define RTC_BASE (PERIPH_BASE + 0x80000) -#define TIMER3_BASE (PERIPH_BASE + 0x10C00) -#define TIMER2_BASE (PERIPH_BASE + 0x10800) -#define TIMER1_BASE (PERIPH_BASE + 0x10400) -#define TIMER0_BASE (PERIPH_BASE + 0x10000) -#define UART1_BASE (PERIPH_BASE + 0x0E400) -#define UART0_BASE (PERIPH_BASE + 0x0E000) -#define USART2_BASE (PERIPH_BASE + 0x0C800) -#define USART1_BASE (PERIPH_BASE + 0x0C400) -#define USART0_BASE (PERIPH_BASE + 0x0C000) -#define I2C1_BASE (PERIPH_BASE + 0x0A400) -#define I2C0_BASE (PERIPH_BASE + 0x0A000) -#define EBI_BASE (PERIPH_BASE + 0x08000) -#define GPIO_BASE (PERIPH_BASE + 0x06000) -#define DAC0_BASE (PERIPH_BASE + 0x04000) -#define ADC0_BASE (PERIPH_BASE + 0x02000) -#define ACMP1_BASE (PERIPH_BASE + 0x01400) -#define ACMP0_BASE (PERIPH_BASE + 0x01000) -#define VCMP_BASE (PERIPH_BASE + 0x00000) - -#endif diff --git a/libopencm3/include/libopencm3/efm32/lg/msc.h b/libopencm3/include/libopencm3/efm32/lg/msc.h deleted file mode 100644 index f4fed2b..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/msc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup msc_defines MSC Defines - * - * @brief Defined Constants and Types for the Memory Systems Controller - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/opamp.h b/libopencm3/include/libopencm3/efm32/lg/opamp.h deleted file mode 100644 index fe2a1b1..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/opamp.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_LG_OPAMP_H -#define LIBOPENCM3_EFM32_LG_OPAMP_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/efm32/lg/prs.h b/libopencm3/include/libopencm3/efm32/lg/prs.h deleted file mode 100644 index e059892..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/prs.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup prs_defines PRS Defines - * - * @brief Defined Constants and Types for the Peripheral Reflex System - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/rmu.h b/libopencm3/include/libopencm3/efm32/lg/rmu.h deleted file mode 100644 index 97c793f..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/rmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rmu_defines RMU Defines - * - * @brief Defined Constants and Types for the Reset Management Unit - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/rtc.h b/libopencm3/include/libopencm3/efm32/lg/rtc.h deleted file mode 100644 index 0aab324..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/rtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the Real Time Clock - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/timer.h b/libopencm3/include/libopencm3/efm32/lg/timer.h deleted file mode 100644 index aecd0e6..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/timer.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @defgroup timer_defines TIMER Defines - * - * @brief Defined Constants and Types for the TIMER module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/uart.h b/libopencm3/include/libopencm3/efm32/lg/uart.h deleted file mode 100644 index 301a075..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup uart_defines UART Defines - * - * @brief Defined Constants and Types for the UART module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/usart.h b/libopencm3/include/libopencm3/efm32/lg/usart.h deleted file mode 100644 index 0a0a525..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/usart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the USART module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/usb.h b/libopencm3/include/libopencm3/efm32/lg/usb.h deleted file mode 100644 index 8c781b1..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/usb.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usb_defines USB Defines - * - * @brief Defined Constants and Types for the USB module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/lg/wdog.h b/libopencm3/include/libopencm3/efm32/lg/wdog.h deleted file mode 100644 index ba657c2..0000000 --- a/libopencm3/include/libopencm3/efm32/lg/wdog.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @defgroup wdog_defines WDOG Defines - * - * @brief Defined Constants and Types for the Watchdog module - * - * @ingroup EFM32LG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/memorymap.h b/libopencm3/include/libopencm3/efm32/memorymap.h deleted file mode 100644 index 6cee0f1..0000000 --- a/libopencm3/include/libopencm3/efm32/memorymap.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Dispatcher for the base address definitions, depending on the particular - * Gecko family. - * - * @see efm32tg/memorymap.h - * @see efm32lg/memorymap.h - */ - -#if defined(EFM32TG) -# include -#elif defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/msc.h b/libopencm3/include/libopencm3/efm32/msc.h deleted file mode 100644 index 4435ba6..0000000 --- a/libopencm3/include/libopencm3/efm32/msc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/opamp.h b/libopencm3/include/libopencm3/efm32/opamp.h deleted file mode 100644 index 10de5e8..0000000 --- a/libopencm3/include/libopencm3/efm32/opamp.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/prs.h b/libopencm3/include/libopencm3/efm32/prs.h deleted file mode 100644 index 49eb133..0000000 --- a/libopencm3/include/libopencm3/efm32/prs.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/rmu.h b/libopencm3/include/libopencm3/efm32/rmu.h deleted file mode 100644 index cd32486..0000000 --- a/libopencm3/include/libopencm3/efm32/rmu.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/rtc.h b/libopencm3/include/libopencm3/efm32/rtc.h deleted file mode 100644 index 7d5eaa9..0000000 --- a/libopencm3/include/libopencm3/efm32/rtc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/tg/doc-efm32tg.h b/libopencm3/include/libopencm3/efm32/tg/doc-efm32tg.h deleted file mode 100644 index 722cc56..0000000 --- a/libopencm3/include/libopencm3/efm32/tg/doc-efm32tg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 EFM32 Tiny Gecko - -@version 1.0.0 - -@date 4 March 2013 - -API documentation for Energy Micro EFM32 Tiny Gecko Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32TG EFM32 TinyGecko -Libraries for Energy Micro EFM32 Tiny Gecko series. - -@version 1.0.0 - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines - -@brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series - -@version 1.0.0 - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/tg/irq.json b/libopencm3/include/libopencm3/efm32/tg/irq.json deleted file mode 100644 index 95efa85..0000000 --- a/libopencm3/include/libopencm3/efm32/tg/irq.json +++ /dev/null @@ -1,31 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "acmp01", - "adc0", - "dac0", - "i2c0", - "gpio_odd", - "timer1", - "usart1_rx", - "usart1_tx", - "lesense", - "leuart0", - "letimer0", - "pcnt0", - "rtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes" - ], - "partname_humanreadable": "EFM32 Tiny Gecko series", - "partname_doxygen": "EFM32TG", - "includeguard": "LIBOPENCM3_EFM32TG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/tg/memorymap.h b/libopencm3/include/libopencm3/efm32/tg/memorymap.h deleted file mode 100644 index d17bb60..0000000 --- a/libopencm3/include/libopencm3/efm32/tg/memorymap.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Layout of the system address space of Tiny Gecko devices. - * - * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. - */ - -/* The common cortex-m3 definitions were verified from - * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be - * missing there. The details (everything based on SCS_BASE) was verified from - * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but - * there are discrepancies. */ -#include - -#define CODE_BASE (0x00000000U) - -#define SRAM_BASE (0x20000000U) -#define SRAM_BASE_BITBAND (0x22000000U) - -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_BITBAND (0x42000000U) - -/* Details of the "Code" section */ - -#define FLASH_BASE (CODE_BASE + 0x00000000) -#define USERDATA_BASE (CODE_BASE + 0x0fe00000) -#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) -#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) -#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) - -/* Tiny Gecko peripherial definitions */ - -#define VCMP_BASE (PERIPH_BASE + 0x00000000) -#define ACMP0_BASE (PERIPH_BASE + 0x00001000) -#define ACMP1_BASE (PERIPH_BASE + 0x00001400) -#define ADC_BASE (PERIPH_BASE + 0x00002000) -#define DAC0_BASE (PERIPH_BASE + 0x00004000) -#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ -#define I2C0_BASE (PERIPH_BASE + 0x0000a000) -#define USART0_BASE (PERIPH_BASE + 0x0000c000) -#define USART1_BASE (PERIPH_BASE + 0x0000c400) -#define TIMER0_BASE (PERIPH_BASE + 0x00010000) -#define TIMER1_BASE (PERIPH_BASE + 0x00010400) -#define RTC_BASE (PERIPH_BASE + 0x00080000) -#define LETIMER0_BASE (PERIPH_BASE + 0x00082000) -#define LEUART0_BASE (PERIPH_BASE + 0x00084000) -#define PCNT0_BASE (PERIPH_BASE + 0x00086000) -#define WDOG_BASE (PERIPH_BASE + 0x00088000) -#define LCD_BASE (PERIPH_BASE + 0x0008a000) -#define LESENSE_BASE (PERIPH_BASE + 0x0008c000) -#define MSC_BASE (PERIPH_BASE + 0x000c0000) -#define DMA_BASE (PERIPH_BASE + 0x000c2000) -#define EMU_BASE (PERIPH_BASE + 0x000c6000) -#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ -#define RMU_BASE (PERIPH_BASE + 0x000ca000) -#define PRS_BASE (PERIPH_BASE + 0x000cc000) -#define AES_BASE (PERIPH_BASE + 0x000e0000) diff --git a/libopencm3/include/libopencm3/efm32/timer.h b/libopencm3/include/libopencm3/efm32/timer.h deleted file mode 100644 index 572baa7..0000000 --- a/libopencm3/include/libopencm3/efm32/timer.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/uart.h b/libopencm3/include/libopencm3/efm32/uart.h deleted file mode 100644 index ff957f2..0000000 --- a/libopencm3/include/libopencm3/efm32/uart.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/usart.h b/libopencm3/include/libopencm3/efm32/usart.h deleted file mode 100644 index 74c6de6..0000000 --- a/libopencm3/include/libopencm3/efm32/usart.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/usb.h b/libopencm3/include/libopencm3/efm32/usb.h deleted file mode 100644 index b6a4f0c..0000000 --- a/libopencm3/include/libopencm3/efm32/usb.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/wdog.h b/libopencm3/include/libopencm3/efm32/wdog.h deleted file mode 100644 index 7ba7ac5..0000000 --- a/libopencm3/include/libopencm3/efm32/wdog.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(EFM32LG) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32WG) -# include -#elif defined(EZR32WG) -# include -#else -# error "efm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/efm32/wg/acmp.h b/libopencm3/include/libopencm3/efm32/wg/acmp.h deleted file mode 100644 index 6a4c10b..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/acmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup acmp_defines ACMP Defines - * - * @brief Defined Constants and Types for the Analog Comparator module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/adc.h b/libopencm3/include/libopencm3/efm32/wg/adc.h deleted file mode 100644 index bdfadc3..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/adc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the EFM32WG Analog to Digital - * Converter - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/burtc.h b/libopencm3/include/libopencm3/efm32/wg/burtc.h deleted file mode 100644 index 28e605a..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/burtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup burtc_defines BURTC Defines - * - * @brief Defined Constants and Types for the Backup RTC - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/cmu.h b/libopencm3/include/libopencm3/efm32/wg/cmu.h deleted file mode 100644 index 6b6b86c..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/cmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup cmu_defines CMU Defines - * - * @brief Defined Constants and Types for the EFM32WG Clock Management Unit - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/dac.h b/libopencm3/include/libopencm3/efm32/wg/dac.h deleted file mode 100644 index 87538bf..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/dac.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dac_defines DAC Defines - * - * @brief Defined Constants and Types for the D/A Converter module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/dma.h b/libopencm3/include/libopencm3/efm32/wg/dma.h deleted file mode 100644 index 803273f..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/dma.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @brief Defined Constants and Types for the DMA module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/doc-efm32wg.h b/libopencm3/include/libopencm3/efm32/wg/doc-efm32wg.h deleted file mode 100644 index 4f8b105..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/doc-efm32wg.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @page libopencm3 EFM32 Wonder Gecko - -@version 1.0.0 - -@date 12 January 2016 - -API documentation for Silicon Laboratories EFM32 Wonder Gecko Cortex M4 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup EFM32WG EFM32 Wonder Gecko -Libraries for Silicon Laboratories EFM32 Wonder Gecko series. - -@version 1.0.0 - -@date 12 January 2016 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup EFM32WG_defines EFM32 Wonder Gecko Defines - -@brief Defined Constants and Types for the Silicon Laboratories EFM32 -Wonder Gecko series - -@version 1.0.0 - -@date 12 January 2016 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/efm32/wg/emu.h b/libopencm3/include/libopencm3/efm32/wg/emu.h deleted file mode 100644 index 11f38c4..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/emu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup emu_defines EMU Defines - * - * @brief Defined Constants and Types for the Energy Management Unit - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/gpio.h b/libopencm3/include/libopencm3/efm32/wg/gpio.h deleted file mode 100644 index 7dafd83..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the EFM32WG GPIO module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/i2c.h b/libopencm3/include/libopencm3/efm32/wg/i2c.h deleted file mode 100644 index c137f88..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/i2c.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the I²C module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/irq.json b/libopencm3/include/libopencm3/efm32/wg/irq.json deleted file mode 100644 index 1332e7d..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/irq.json +++ /dev/null @@ -1,47 +0,0 @@ -{ - "_source": "The names and sequence are taken from d0233_efm32wg_reference_manual.pdf table 4.1.", - "irqs": [ - "dma", - "gpio_even", - "timer0", - "usart0_rx", - "usart0_tx", - "usb", - "acmp01", - "adc0", - "dac0", - "i2c0", - "i2c1", - "gpio_odd", - "timer1", - "timer2", - "timer3", - "usart1_rx", - "usart1_tx", - "lesense", - "usart2_rx", - "usart2_tx", - "uart0_rx", - "uart0_tx", - "uart1_rx", - "uart1_tx", - "leuart0", - "leuart1", - "letimer0", - "pcnt0", - "pcnt1", - "pcnt2", - "rtc", - "burtc", - "cmu", - "vcmp", - "lcd", - "msc", - "aes", - "ebi", - "emu" - ], - "partname_humanreadable": "EFM32 Wonder Gecko series", - "partname_doxygen": "EFM32WG", - "includeguard": "LIBOPENCM3_EFM32WG_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/efm32/wg/letimer.h b/libopencm3/include/libopencm3/efm32/wg/letimer.h deleted file mode 100644 index ee7473a..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/letimer.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup letimer_defines LETIMER Defines - * - * @brief Defined Constants and Types for the Low Energy Timer - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/memorymap.h b/libopencm3/include/libopencm3/efm32/wg/memorymap.h deleted file mode 100644 index 22c0073..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/memorymap.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Kuldeep Singh Dhaka - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H -#define LIBOPENCM3_EFM32_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) - -/* Device information */ -#define DI_BASE (0x0FE08000U) - -/* all names are "DI_" + */ -#define DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020) -#define DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028) -#define DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030) -#define DI_ADC0_CAL MMIO32(DI_BASE + 0x040) -#define DI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048) -#define DI_DAC0_CAL MMIO32(DI_BASE + 0x050) -#define DI_DAC0_BIASPROG MMIO32(DI_BASE + 0x058) -#define DI_ACMP0_CTRL MMIO32(DI_BASE + 0x060) -#define DI_ACMP1_CTRL MMIO32(DI_BASE + 0x068) -#define DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x078) -#define DI_DAC0_OPACTRL MMIO32(DI_BASE + 0x0A0) -#define DI_DAC0_OPAOFFSET MMIO32(DI_BASE + 0x0A8) -#define DI_EMU_BUINACT MMIO32(DI_BASE + 0x0B0) -#define DI_EMU_BUACT MMIO32(DI_BASE + 0x0B8) -#define DI_EMU_BUBODBUVINCAL MMIO32(DI_BASE + 0x0C0) -#define DI_EMU_BUBODUNREGCAL MMIO32(DI_BASE + 0x0C8) -#define DI_DI_CRC MMIO16(DI_BASE + 0x1B0) -#define DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2) -#define DI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4) -#define DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6) -#define DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8) -#define DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA) -#define DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC) -#define DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE) -#define DI_DAC0_CAL_1V25 MMIO32(DI_BASE + 0x1C8) -#define DI_DAC0_CAL_2V5 MMIO32(DI_BASE + 0x1CC) -#define DI_DAC0_CAL_VDD MMIO32(DI_BASE + 0x1D0) -#define DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4) -#define DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5) -#define DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6) -#define DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7) -#define DI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8) -#define DI_AUXHFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1D9) -#define DI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC) -#define DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD) -#define DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE) -#define DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF) -#define DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0) -#define DI_HFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1E1) -#define DI_MEM_INFO_PAGE_SIZE MMIO8(DI_BASE + 0x1E7) -#define DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0) -#define DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4) -#define DI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8) -#define DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA) -#define DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC) -#define DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE) -#define DI_PROD_REV MMIO8(DI_BASE + 0x1FF) - -#define AES_BASE (PERIPH_BASE + 0xE0000) -#define PRS_BASE (PERIPH_BASE + 0xCC000) -#define RMU_BASE (PERIPH_BASE + 0xCA000) -#define CMU_BASE (PERIPH_BASE + 0xC8000) -#define EMU_BASE (PERIPH_BASE + 0xC6000) -#define USB_BASE (PERIPH_BASE + 0xC4000) -#define DMA_BASE (PERIPH_BASE + 0xC2000) -#define MSC_BASE (PERIPH_BASE + 0xC0000) -#define LESENSE_BASE (PERIPH_BASE + 0x8C000) -#define LCD_BASE (PERIPH_BASE + 0x8A000) -#define WDOG_BASE (PERIPH_BASE + 0x88000) -#define PCNT2_BASE (PERIPH_BASE + 0x86800) -#define PCNT1_BASE (PERIPH_BASE + 0x86400) -#define PCNT0_BASE (PERIPH_BASE + 0x86000) -#define LEUART1_BASE (PERIPH_BASE + 0x84400) -#define LEUART0_BASE (PERIPH_BASE + 0x84000) -#define LETIMER0_BASE (PERIPH_BASE + 0x82000) -#define BURTC_BASE (PERIPH_BASE + 0x81000) -#define RTC_BASE (PERIPH_BASE + 0x80000) -#define TIMER3_BASE (PERIPH_BASE + 0x10C00) -#define TIMER2_BASE (PERIPH_BASE + 0x10800) -#define TIMER1_BASE (PERIPH_BASE + 0x10400) -#define TIMER0_BASE (PERIPH_BASE + 0x10000) -#define UART1_BASE (PERIPH_BASE + 0x0E400) -#define UART0_BASE (PERIPH_BASE + 0x0E000) -#define USART2_BASE (PERIPH_BASE + 0x0C800) -#define USART1_BASE (PERIPH_BASE + 0x0C400) -#define USART0_BASE (PERIPH_BASE + 0x0C000) -#define I2C1_BASE (PERIPH_BASE + 0x0A400) -#define I2C0_BASE (PERIPH_BASE + 0x0A000) -#define EBI_BASE (PERIPH_BASE + 0x08000) -#define GPIO_BASE (PERIPH_BASE + 0x06000) -#define DAC0_BASE (PERIPH_BASE + 0x04000) -#define ADC0_BASE (PERIPH_BASE + 0x02000) -#define ACMP1_BASE (PERIPH_BASE + 0x01400) -#define ACMP0_BASE (PERIPH_BASE + 0x01000) -#define VCMP_BASE (PERIPH_BASE + 0x00000) - -#endif diff --git a/libopencm3/include/libopencm3/efm32/wg/msc.h b/libopencm3/include/libopencm3/efm32/wg/msc.h deleted file mode 100644 index bc33ac4..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/msc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup msc_defines MSC Defines - * - * @brief Defined Constants and Types for the Memory Systems Controller - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/opamp.h b/libopencm3/include/libopencm3/efm32/wg/opamp.h deleted file mode 100644 index d534d55..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/opamp.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EFM32_WG_OPAMP_H -#define LIBOPENCM3_EFM32_WG_OPAMP_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/efm32/wg/prs.h b/libopencm3/include/libopencm3/efm32/wg/prs.h deleted file mode 100644 index 42afc13..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/prs.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup prs_defines PRS Defines - * - * @brief Defined Constants and Types for the Peripheral Reflex System - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/rmu.h b/libopencm3/include/libopencm3/efm32/wg/rmu.h deleted file mode 100644 index 9cc7541..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/rmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rmu_defines RMU Defines - * - * @brief Defined Constants and Types for the Reset Management Unit - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/rtc.h b/libopencm3/include/libopencm3/efm32/wg/rtc.h deleted file mode 100644 index e2a85a6..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/rtc.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the Real Time Clock - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/timer.h b/libopencm3/include/libopencm3/efm32/wg/timer.h deleted file mode 100644 index 9d0a1cd..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/timer.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup timer_defines TIMER Defines - * - * @brief Defined Constants and Types for the TIMER module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/uart.h b/libopencm3/include/libopencm3/efm32/wg/uart.h deleted file mode 100644 index b79d8c8..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/uart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup uart_defines UART Defines - * - * @brief Defined Constants and Types for the UART module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/usart.h b/libopencm3/include/libopencm3/efm32/wg/usart.h deleted file mode 100644 index edba183..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/usart.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the USART module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/usb.h b/libopencm3/include/libopencm3/efm32/wg/usb.h deleted file mode 100644 index cc06673..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/usb.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup usb_defines USB Defines - * - * @brief Defined Constants and Types for the USB module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/efm32/wg/wdog.h b/libopencm3/include/libopencm3/efm32/wg/wdog.h deleted file mode 100644 index 9f32353..0000000 --- a/libopencm3/include/libopencm3/efm32/wg/wdog.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup wdog_defines WDOG Defines - * - * @brief Defined Constants and Types for the Watchdog module - * - * @ingroup EFM32WG_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Bob Miller - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include diff --git a/libopencm3/include/libopencm3/ethernet/mac.h b/libopencm3/include/libopencm3/ethernet/mac.h deleted file mode 100644 index b788706..0000000 --- a/libopencm3/include/libopencm3/ethernet/mac.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @defgroup ethernet_mac_defines MAC Generic Defines - * - * @brief Defined Constants and Types for the Ethernet MAC - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#if defined(STM32F1) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#else -# error "stm32 family not defined." -#endif - -/**@}*/ - - diff --git a/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h b/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h deleted file mode 100644 index bac5e72..0000000 --- a/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h +++ /dev/null @@ -1,771 +0,0 @@ -/** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines - * - * @brief Defined Constants and Types for the Ethernet MAC for STM32Fxx7 - * chips - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ETHERNET_H -#define LIBOPENCM3_ETHERNET_H - -#include -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/**@{*/ - -#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) -#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) -#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) -#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) -#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) -#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) -#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) -#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) -#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) -#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) -/* not available on F1 ?*/ -#define ETH_MACDBGR MMIO32(ETHERNET_BASE + 0x34) -#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) -#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) - -/* i=[0..3] */ -#define ETH_MACAHR(i) MMIO32(ETHERNET_BASE + 0x40+(i)*8) -/* i=[0..3] */ -#define ETH_MACALR(i) MMIO32(ETHERNET_BASE + 0x44+(i)*8) - -/* Ethernet MMC registers */ -#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) -#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) -#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) -#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) -#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) -#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) -#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) -#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) -#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) -#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) -#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) - -/* Ethrenet IEEE 1588 time stamp registers */ -#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) -#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) -#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) -#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) -#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) -#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) -#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) -#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) -#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) -/* not available on F1 ?*/ -#define ETH_PTPTSSR MMIO32(ETHERNET_BASE + 0x728) - -/* Ethernet DMA registers */ -#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) -#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) -#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) -#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) -#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) -#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) -#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) -#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) -#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) -#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) -#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) -#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) -#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) - -/* Ethernet Buffer Descriptors */ -#define ETH_DES(n, base) MMIO32((base) + (n)*4) -#define ETH_DES0(base) ETH_DES(0, base) -#define ETH_DES1(base) ETH_DES(1, base) -#define ETH_DES2(base) ETH_DES(2, base) -#define ETH_DES3(base) ETH_DES(3, base) - -/* Ethernet Extended buffer Descriptors */ -#define ETH_DES4(base) ETH_DES(4, base) -#define ETH_DES5(base) ETH_DES(5, base) -#define ETH_DES6(base) ETH_DES(6, base) -#define ETH_DES7(base) ETH_DES(7, base) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/*---------------------------------------------------------------------------*/ -/* MACCR --------------------------------------------------------------------*/ - -#define ETH_MACCR_RE (1<<2) -#define ETH_MACCR_TE (1<<3) -#define ETH_MACCR_DC (1<<4) - -#define ETH_MACCR_BL_SHIFT 5 -#define ETH_MACCR_BL (3 << ETH_MACCR_BL_SHIFT) -#define ETH_MACCR_BL_MIN10 (0 << ETH_MACCR_BL_SHIFT) -#define ETH_MACCR_BL_MIN8 (1 << ETH_MACCR_BL_SHIFT) -#define ETH_MACCR_BL_MIN4 (2 << ETH_MACCR_BL_SHIFT) -#define ETH_MACCR_BL_MIN1 (3 << ETH_MACCR_BL_SHIFT) - -#define ETH_MACCR_APCS (1<<7) -#define ETH_MACCR_RD (1<<9) -#define ETH_MACCR_IPCO (1<<10) -#define ETH_MACCR_DM (1<<11) -#define ETH_MACCR_LM (1<<12) -#define ETH_MACCR_ROD (1<<13) -#define ETH_MACCR_FES (1<<14) -#define ETH_MACCR_CSD (1<<16) - -#define ETH_MACCR_IFG_SHIFT 17 -#define ETH_MACCR_IFG (7<Defined Constants and Types for the Ethernet PHY - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#ifndef LIBOPENCM3_PHY_H -#define LIBOPENCM3_PHY_H - -#include - -/**@{*/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define PHY_REG_BCR 0x00 -#define PHY_REG_BSR 0x01 -#define PHY_REG_ID1 0x02 -#define PHY_REG_ID2 0x03 -#define PHY_REG_ANTX 0x04 -#define PHY_REG_ANRX 0x05 -#define PHY_REG_ANEXP 0x06 -#define PHY_REG_ANNPTX 0x07 -#define PHY_REG_ANNPRX 0x08 - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -#define PHY_REG_BCR_COLTEST (1 << 7) -#define PHY_REG_BCR_FD (1 << 8) -#define PHY_REG_BCR_ANRST (1 << 9) -#define PHY_REG_BCR_ISOLATE (1 << 10) -#define PHY_REG_BCR_POWERDN (1 << 11) -#define PHY_REG_BCR_AN (1 << 12) -#define PHY_REG_BCR_100M (1 << 13) -#define PHY_REG_BCR_LOOPBACK (1 << 14) -#define PHY_REG_BCR_RESET (1 << 15) - -#define PHY_REG_BSR_JABBER (1 << 1) -#define PHY_REG_BSR_UP (1 << 2) -#define PHY_REG_BSR_FAULT (1 << 4) -#define PHY_REG_BSR_ANDONE (1 << 5) - - - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -#define PHY0 0 -#define PHY1 1 - -enum phy_status { - LINK_DOWN, - LINK_HD_10M, - LINK_HD_100M, - LINK_HD_1000M, - LINK_HD_10000M, - LINK_FD_10M, - LINK_FD_100M, - LINK_FD_1000M, - LINK_FD_10000M, -}; - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -void phy_reset(uint8_t phy); -bool phy_link_isup(uint8_t phy); - -enum phy_status phy_link_status(uint8_t phy); - -void phy_autoneg_force(uint8_t phy, enum phy_status mode); -void phy_autoneg_enable(uint8_t phy); - -END_DECLS - -/**@}*/ - - -#endif /* LIBOPENCM3_PHY_H__ */ diff --git a/libopencm3/include/libopencm3/ethernet/phy_ksz80x1.h b/libopencm3/include/libopencm3/ethernet/phy_ksz80x1.h deleted file mode 100644 index 6d7aba5..0000000 --- a/libopencm3/include/libopencm3/ethernet/phy_ksz80x1.h +++ /dev/null @@ -1,288 +0,0 @@ -/** @defgroup ethernet_phy_ksz80x1_defines PHY KSZ80X1 Defines - * - * @brief Defined Constants and Types for the Ethernet PHY KSZ80X1 chips - * chips - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PHY_KSZ80X1_H -#define LIBOPENCM3_PHY_KSZ80X1_H - -#include - -/**@{*/ - -/* - * Architecture availability: - * - * A stands for KSZ8001 / KSZ8001L - * B stands for KSZ8021RNL / KSZ8031RNL - * C stands for KSZ8041NL / KSZ8041NLJ - * D stands for KSZ8041RNL - * E stands for KSZ8041TL / KSZ8041FTL / KSZ8041MLL - * F stands for KSZ8051MLL - * G stands for KSZ8051MNL / KSZ8051RNL - * H stands for KSZ8051MNLU / KSZ8051RNLU - * I stands for KSZ8081MLX /KSZ8081MNX / KSZ8081RNB - * J stands for KSZ8081RNA / KSZ8081RND - * K stands for KSZ8091MLX / KSZ8091MNX / KSZ8091RNB - * L stands for KSZ8091RNA / KSZ8091RND - * - * No sign marks available for all - */ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define KSZ80X1_BCR 0x00 /* ABCDEFGHIJKL */ -#define KSZ80X1_BSR 0x01 /* ABCDEFGHIJKL */ -#define KSZ80X1_ID1 0x02 /* ABCDEFGHIJKL */ -#define KSZ80X1_ID2 0x03 /* ABCDEFGHIJKL */ -#define KSZ80X1_ANTX 0x04 /* ABCDEFGHIJKL */ -#define KSZ80X1_ANRX 0x05 /* ABCDEFGHIJKL */ -#define KSZ80X1_ANEXP 0x06 /* ABCDEFGHIJKL */ -#define KSZ80X1_ANNPTX 0x07 /* ABCDEFGHIJKL */ -#define KSZ80X1_ANNPRX 0x08 /* ABCDEFGHIJKL */ - -#define KSZ80X1_MMDCR 0x0D /* ----------KL */ -#define KSZ80X1_MMDAR 0x0E /* ----------KL */ - -#define KSZ80X1_DRCTRL 0x10 /* -B-----HIJKL */ -#define KSZ80X1_AFECTRL 0x11 /* -B---FGHIJKL */ -#define KSZ80X1_AFECTRL4 0x13 /* ----------KL */ -#define KSZ80X1_MIICTRL 0x14 /* ---DE------- */ -#define KSZ80X1_RXERCTR 0x15 /* ABCDEFGHIJKL */ -#define KSZ80X1_STRAPOVRD 0x16 /* -B---FGHIJKL */ -#define KSZ80X1_STRAPSTAT 0x17 /* -B---FGHIJKL */ -#define KSZ80X1_ECR 0x18 /* -B---FGHIJKL */ - -#define KSZ80X1_ICSR 0x1B /* ABCDEFGHIJKL */ - -#define KSZ80X1_LINKMD 0x1D /* AB--EFGHIJKL */ -#define KSZ80X1_CR1 0x1E /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2 0x1F /* ABCDEFGHIJKL */ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* KSZ80X1_BCR --------------------------------------------------------------*/ -/* KSZ80X1_BSR --------------------------------------------------------------*/ -/* KSZ80X1_ID1 --------------------------------------------------------------*/ -/* KSZ80X1_ID2 --------------------------------------------------------------*/ -/* KSZ80X1_ANTX -------------------------------------------------------------*/ -/* KSZ80X1_ANRX -------------------------------------------------------------*/ -/* KSZ80X1_ANEXP ------------------------------------------------------------*/ -/* KSZ80X1_ANNPTX -----------------------------------------------------------*/ -/* KSZ80X1_ANNPRX -----------------------------------------------------------*/ - -/* KSZ80X1_MMDCR ------------------------------------------------------------*/ - -#define KSZ80X1_MMDCR_OPMODE (3 << 14) /* ----------KL */ -#define KSZ80X1_MMDCR_OPMODE_REGISTER (0 << 14) /* ----------KL */ -#define KSZ80X1_MMDCR_OPMODE_DATA (1 << 14) /* ----------KL */ -#define KSZ80X1_MMDCR_OPMODE_DATA_POSTINC (2 << 14) /* ----------KL */ -#define KSZ80X1_MMDCR_OPMODE_DATA_WPOSTINC (3 << 14) /* ----------KL */ - -#define KSZ80X1_MMDCR_DEVADDR (31 << 14) /* ----------KL */ - -/* KSZ80X1_MMDAR ------------------------------------------------------------*/ - -/* KSZ80X1_DRCTRL -----------------------------------------------------------*/ - -#define KSZ80X1_DRCTRL_PLLOFF (1 << 4) /* -B-----HIJKL */ - -/* KSZ80X1_AFECTRL ----------------------------------------------------------*/ - -#define KSZ80X1_AFECTRL_SLOWOSC (1 << 5) /* -B---FGHIJKL */ - -/* KSZ80X1_AFECTRL4 ---------------------------------------------------------*/ - -#define KSZ80X1_AFECTRL4_10TE (1 << 4) /* ----------KL */ - -/* KSZ80X1_MIICTRL ----------------------------------------------------------*/ -#define KSZ8051_MIICTRL_PREAM_RESTORE_100M (1 << 7) /* ---DE------ */ -#define KSZ8051_MIICTRL_PREAM_RESTORE_10M (1 << 6) /* ---DE------ */ - -/* KSZ80X1_RXERCTR ----------------------------------------------------------*/ - -/* KSZ8051_STRAPOVRD --------------------------------------------------------*/ - -/* strapping options availability depends on MII/RMII availability on chip */ - -#define KSZ80X1_STRAPOVRD_FACTORY (1 << 15) /* --------IJ-- */ -#define KSZ80X1_STRAPOVRD_PMEWOL (1 << 15) /* ----------KL */ -#define KSZ80X1_STRAPOVRD_BCASTOFF (1 << 9) /* -----FGHIJKL */ -#define KSZ80X1_STRAPOVRD_MIIBTOB (1 << 7) /* -----FGHI-K- */ -#define KSZ80X1_STRAPOVRD_RMIIBTOB (1 << 6) /* -B----GHIJKL */ -#define KSZ80X1_STRAPOVRD_NANDTREE (1 << 5) /* -B---FGHIJK- */ -#define KSZ80X1_STRAPOVRD_RMIIOVRD (1 << 1) /* -B----GHIJKL */ -#define KSZ80X1_STRAPOVRD_MIIOVRD (1 << 0) /* -----FGHI-K- */ - -/* KSZ80X1_STRAPSTAT --------------------------------------------------------*/ - -/* strapping options availability depends on MII/RMII availability on chip */ -/* KSZ8021/KSZ8031/KSZ8091RNA/KSZ8091RND supports phy address 0 and 3 only! */ - -#define KSZ80X1_STRAPSTAT_PHYAD_SHIFT 13 /* -B---FGHIJKL */ -#define KSZ80X1_STRAPSTAT_PHYAD (7 << KSZ8051_STRAPSTAT_PHYAD_SHIFT) - -#define KSZ80X1_STRAPSTAT_BCASTOFF (1 << 9) /* -----FGHI-K- */ -#define KSZ80X1_STRAPSTAT_MIIBTOB (1 << 7) /* -----FGHI-K- */ -#define KSZ80X1_STRAPSTAT_RMIIBTOB (1 << 6) /* ------GHI-K- */ -#define KSZ80X1_STRAPSTAT_NANDTREE (1 << 5) /* -----FGHI-K- */ -#define KSZ80X1_STRAPSTAT_RMII (1 << 1) /* -B----GHIJKL */ -#define KSZ80X1_STRAPSTAT_MII (1 << 0) /* -----FGHI-K- */ - -/* KSZ80X1_ECR --------------------------------------------------------------*/ - -#define KSZ8051_ECR_EDPDDIS (1 << 11) /* -B---FGHIJKL */ -#define KSZ8051_ECR_100TXPREAMBLE (1 << 10) /* -----FGHI-K- */ -#define KSZ8051_ECR_10TXPREAMBLE (1 << 6) /* -----FGHI-K- */ - -/* KSZ80X1_ICSR -------------------------------------------------------------*/ - -#define KSZ80X1_ICSR_JABIE (1 << 15) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_RERRIE (1 << 14) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_PRIE (1 << 13) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_PDFLTIE (1 << 12) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LPACKIE (1 << 11) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LDIE (1 << 10) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_RFAULTIE (1 << 9) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LINKUPIE (1 << 8) /* ABCDEFGHIJKL */ - -#define KSZ80X1_ICSR_JABIF (1 << 7) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_RERRIF (1 << 6) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_PRIF (1 << 5) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_PDFLTIF (1 << 4) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LPACKIF (1 << 3) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LDIF (1 << 2) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_RFAULTIF (1 << 1) /* ABCDEFGHIJKL */ -#define KSZ80X1_ICSR_LINKUPIF (1 << 0) /* ABCDEFGHIJKL */ - -/* KSZ80X1_LINKMD -----------------------------------------------------------*/ - -#define KSZ80X1_LINKMD_TESTEN (1 << 15) /* AB--EFGHIJKL */ - -#define KSZ80X1_LINKMD_TESTRES (3 << 13) /* AB--EFGHIJKL */ -#define KSZ80X1_LINKMD_TESTRES_NORMAL (0 << 13) /* AB--EFGHIJKL */ -#define KSZ80X1_LINKMD_TESTRES_OPEN (1 << 13) /* AB--EFGHIJKL */ -#define KSZ80X1_LINKMD_TESTRES_SHORT (2 << 13) /* AB--EFGHIJKL */ -#define KSZ80X1_LINKMD_TESTRES_FAILED (3 << 13) /* AB--EFGHIJKL */ - -#define KSZ80X1_LINKMD_SHORTCABLE (1 << 12) /* -----FGHIJKL */ -#define KSZ80X1_LINKMD_DISTANCE (0x1FF << 0) /* AB--EFGHIJKL */ - -/* KSZ80X1_CR1 --------------------------------------------------------------*/ - -/* family set 1, "8041" when conflicts arise */ - -#define KSZ80X1_CR1_LEDMODE (3 << 14) /* A-CDE------- */ -#define KSZ80X1_CR1_LEDMODE_COL_FD_SPD_LNK (0 << 14) /* A---------- */ -#define KSZ80X1_CR1_LEDMODE_ACT_FD_SPD_LNK (1 << 14) /* A---------- */ -#define KSZ80X1_CR1_LEDMODE_ACT_FD_100_10 (2 << 14) /* A---------- */ -#define KSZ80X1_CR1_LEDMODE_SPD_LNK (0 << 14) /* --CDE------ */ -#define KSZ80X1_CR1_LEDMODE_ACT_LNK (1 << 14) /* --CDE------ */ -#define KSZ8041_CR1_POLARITY (1 << 13) /* A-CDE------ */ -#define KSZ80X1_CR1_FEFAULT (1 << 12) /* A---E------ */ -#define KSZ8041_CR1_MDIX (1 << 11) /* A-CDE------ */ -#define KSZ80X1_CR1_LOOPBACK (1 << 7) /* A-CDE------ */ - -/* family set 2 */ - -#define KSZ80X1_CR1_FLOWCTRL (1 << 9) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_LINK (1 << 8) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_POLARITY (1 << 7) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MDIX (1 << 5) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_ENERGY (1 << 4) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_ISOLATE (1 << 3) /* -B---FGHIJKL */ - -#define KSZ80X1_CR1_MODE (7 << 0) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MODE_AUTONEG (0 << 0) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MODE_10HD (1 << 0) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MODE_100HD (2 << 0) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MODE_10FD (5 << 0) /* -B---FGHIJKL */ -#define KSZ80X1_CR1_MODE_100FD (6 << 0) /* -B---FGHIJKL */ - -/* KSZ80X1_CR2 --------------------------------------------------------------*/ - -/* refclk options availability depends on RMII availability on chip */ - -#define KSZ80X1_CR2_HPMDIX (1 << 15) /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2_MDIXSEL (1 << 14) /* ABCDEFGHIJKL*/ -#define KSZ80X1_CR2_MDIXEN (1 << 13) /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2_ENERGY (1 << 12) /* A-CDE------- */ -#define KSZ80X1_CR2_FORCE (1 << 11) /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2_POWERSAVE (1 << 10) /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2_IRQLVL (1 << 9) /* ABCDEFGHIJKL */ -#define KSZ80X1_CR2_JABEN (1 << 8) /* ABCDEFGHIJKL */ - -/* family set 1 */ - -#define KSZ80X1_CR2_ANDONE (1 << 7) /* A-CDE------- */ -#define KSZ80X1_CR2_PAUSEEN (1 << 6) /* A-CDE------- */ -#define KSZ80X1_CR2_ISOLATE (1 << 5) /* A-CDE------- */ -#define KSZ80X1_CR2_MODE (7 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_AN (0 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_10HD (1 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_100HD (2 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_DEFAULT (3 << 2) /* A--- */ -#define KSZ80X1_CR2_MODE_10FD (5 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_100FD (6 << 2) /* A-CDE */ -#define KSZ80X1_CR2_MODE_ISOLATE (7 << 2) /* A--- */ - -/* family set 2 */ - -#define KSZ80X1_CR2_REFCLK (1 << 7) /* -B----GHIJKL */ -#define KSZ80X1_CR2_REFCLK_25MHZ (0 << 7) /* -B----GHIJKL */ -#define KSZ80X1_CR2_REFCLK_50MHZ (1 << 7) /* -B----GHIJKL */ -#define KSZ80X1_CR2_LED (3 << 4) /* -B---FGHIJKL */ -#define KSZ80X1_CR2_LED_SPD_LNKACT (0 << 4) /* -B---FGHIJKL */ -#define KSZ80X1_CR2_LED_ACT_LNK (1 << 4) /* -B---FGHIJKL */ -#define KSZ80X1_CR2_TXDIS (1 << 3) /* -B---FGHIJKL */ -#define KSZ80X1_CR2_REMLPB (1 << 2) /* -B---FGHIJKL */ - - -#define KSZ80X1_CR2_SQEEN (1 << 1) /* ABCDEFGHI-KL */ -#define KSZ80X1_CR2_SCRAMBEN (1 << 0) /* ABCDEFGHIJKL */ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -/**@}*/ - - -#endif /* LIBOPENCM3_PHY_KSZ8051_H__ */ diff --git a/libopencm3/include/libopencm3/ethernet/phy_lan87xx.h b/libopencm3/include/libopencm3/ethernet/phy_lan87xx.h deleted file mode 100644 index ca6c065..0000000 --- a/libopencm3/include/libopencm3/ethernet/phy_lan87xx.h +++ /dev/null @@ -1,297 +0,0 @@ -/** @defgroup ethernet_phy_lan87xx_defines PHY LAN8710 Defines - * - * @brief Defined Constants and Types for the Ethernet PHY LAN87xx chips - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 Frantisek Burian - * - * @date 6 February 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PHY_LAN87XX_H -#define LIBOPENCM3_PHY_LAN87XX_H - -#include - -/**@{*/ - -/* - * Architecture availability: - * - * A stands for LAN8700 - * B stands for LAN8710A - * C stands for LAN8720A - * D stands for LAN8740A - * E stands for LAN8741A - * F stands for LAN8742A - */ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define LAN87XX_BCR 0x00 /* ABCDEF */ -#define LAN87XX_BSR 0x01 /* ABCDEF */ -#define LAN87XX_PID1 0x02 /* ABCDEF */ -#define LAN87XX_PID2 0x03 /* ABCDEF */ -#define LAN87XX_ANA 0x04 /* ABCDEF */ -#define LAN87XX_ANLPA 0x05 /* ABCDEF */ -#define LAN87XX_ANE 0x06 /* ABCDEF */ -#define LAN87XX_ANNPTX 0x07 /* ---DEF */ -#define LAN87XX_ANNPRX 0x08 /* ---DEF */ - -#define LAN87XX_MMDACR 0x0D /* ---DEF */ -#define LAN87XX_MMDADR 0x0E /* ---DEF */ - -#define LAN87XX_REVISION 0x10 /* A----- */ -#define LAN87XX_EDPDNLP 0x10 /* ---DEF */ -#define LAN87XX_MCS 0x11 /* ABCDEF */ -#define LAN87XX_SM 0x12 /* ABCDEF */ - -#define LAN87XX_TDRDCR 0x18 /* ---D-F */ -#define LAN87XX_TDRCSR 0x19 /* ---D-F */ -#define LAN87XX_ERRCNT 0x1A /* -BCDEF */ -#define LAN87XX_CSR 0x1B /* ABCDEF */ -#define LAN87XX_CBLN 0x1C /* ---D-F */ -#define LAN87XX_ISR 0x1D /* ABCDEF */ -#define LAN87XX_IMR 0x1E /* ABCDEF */ -#define LAN87XX_SCSR 0x1F /* ABCDEF */ - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* LAN87XX_BCR --------------------------------------------------------------*/ -/* LAN87XX_BSR --------------------------------------------------------------*/ -/* LAN87XX_PID1 -------------------------------------------------------------*/ -/* LAN87XX_PID2 -------------------------------------------------------------*/ -/* LAN87XX_ANA --------------------------------------------------------------*/ -/* LAN87XX_ANLPA ------------------------------------------------------------*/ -/* LAN87XX_ANE --------------------------------------------------------------*/ -/* LAN87XX_ANNPTX -----------------------------------------------------------*/ -/* LAN87XX_ANNPRX -----------------------------------------------------------*/ - -/* LAN87XX_MMDACR -----------------------------------------------------------*/ - -/* the MMD provides register access into bare PHY chip. MMD provides its own - * register address space, completely different between devices. - * It should be implemented later. - */ - -#define LAN87XX_MMDACR_FUNC_SHIFT 14 /* ---DEF */ -#define LAN87XX_MMDACR_FUNC (3 << LAN87XX_MMDACR_FUNC_SHIFT) -#define LAN87XX_MMDACR_FUNC_ADDRESS (0 << LAN87XX_MMDACR_FUNC_SHIFT) -#define LAN87XX_MMDACR_FUNC_DATA (1 << LAN87XX_MMDACR_FUNC_SHIFT) - -#define LAN87XX_MMDACR_DEVAD (31 << 0) /* ---DEF */ -#define LAN87XX_MMDACR_DEVAD_PCS (3 << 0) /* ---DEF */ -#define LAN87XX_MMDACR_DEVAD_ANN (7 << 0) /* ---DE- */ -#define LAN87XX_MMDACR_DEVAD_VENDOR (30 << 0) /* ---DE- */ - -/* LAN87XX_MMDADR -----------------------------------------------------------*/ - -/* LAN87XX_REVISION ---------------------------------------------------------*/ -/* note this register is valid only on original LAN8700 */ - -/* LAN87XX_EDPDNLP ----------------------------------------------------------*/ -/* note this register is valid only on newer than original LAN8700 */ - -#define LAN87XX_EDPDNLP_TXEN (1 << 15) /* ---DEF */ - -#define LAN87XX_EDPDNLP_TXTIM_SHIFT 13 /* ---DEF */ -#define LAN87XX_EDPDNLP_TXTIM (3<Defined Constants and Types for the Ethernet PHY STE100 chip - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 Frantisek Burian - * - * @date 6 February 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PHY_STE100_H -#define LIBOPENCM3_PHY_STE100_H - -#include - -/**@{*/ - -/* - * Architecture availability: - * - */ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define STE100_XCR 0x00 -#define STE100_XSR 0x01 -#define STE100_PID1 0x02 -#define STE100_PID2 0x03 -#define STE100_ANA 0x04 -#define STE100_ANLPA 0x05 -#define STE100_ANE 0x06 - -#define STE100_XCIIS 0x11 -#define STE100_XIE 0x12 -#define STE100_100CTR 0x13 -#define STE100_XMC 0x14 - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* STE100_XCR ---------------------------------------------------------------*/ -/* STE100_XSR ---------------------------------------------------------------*/ -/* STE100_PID1 --------------------------------------------------------------*/ -/* STE100_PID2 --------------------------------------------------------------*/ -/* STE100_ANA ---------------------------------------------------------------*/ -/* STE100_ANLPA -------------------------------------------------------------*/ -/* STE100_ANE ---------------------------------------------------------------*/ - -/* STE100_XCIIS -------------------------------------------------------------*/ - -#define STE100_XCIIS_SPEED (1 << 9) -#define STE100_XCIIS_DUPLEX (1 << 8) -#define STE100_XCIIS_PAUSE (1 << 7) -#define STE100_XCIIS_ANC (1 << 6) -#define STE100_XCIIS_RFD (1 << 5) -#define STE100_XCIIS_LS (1 << 4) -#define STE100_XCIIS_ANAR (1 << 3) -#define STE100_XCIIS_PDF (1 << 2) -#define STE100_XCIIS_ANPR (1 << 1) -#define STE100_XCIIS_REF (1 << 0) - -/* STE100_XIE ---------------------------------------------------------------*/ - -#define STE100_XCIE_ANCE (1 << 6) -#define STE100_XCIE_RFE (1 << 5) -#define STE100_XCIE_LDE (1 << 4) -#define STE100_XCIE_ANAE (1 << 3) -#define STE100_XCIE_PDFE (1 << 2) -#define STE100_XCIE_ANPE (1 << 1) -#define STE100_XCIE_REFE (1 << 0) - -/* STE100_100CTR ------------------------------------------------------------*/ - -#define STE100_100CTR_DISRER (1 << 13) -#define STE100_100CTR_ANC (1 << 12) -#define STE100_100CTR_ENRLB (1 << 9) -#define STE100_100CTR_ENDCR (1 << 8) -#define STE100_100CTR_ENRZI (1 << 7) -#define STE100_100CTR_EN4B5B (1 << 6) -#define STE100_100CTR_ISOTX (1 << 5) - -#define STE100_100CTR_CMODE_SHIFT 2 -#define STE100_100CTR_CMODE (7 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_AN (0 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_10HD (1 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_100HD (2 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_10FD (5 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_100FD (6 << STE100_100CTR_CMODE_SHIFT) -#define STE100_100CTR_CMODE_ISOLATE (7 << STE100_100CTR_CMODE_SHIFT) - -#define STE100_100CTR_DISMLT (1 << 1) -#define STE100_100CTR_DISCRM (1 << 0) - -/* STE100_XMC ---------------------------------------------------------------*/ - -#define STE100_XMC_LD (1 << 11) -#define STE100_XMC_PAD_SHIFT 3 -#define STE100_XMC_PAD (31 << STE100_XMC_PAD_SHIFT) - -#define STE100_XMC_MFPSE (1 << 1) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -/**@}*/ - - -#endif /* LIBOPENCM3_PHY_STE100_H__ */ diff --git a/libopencm3/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h b/libopencm3/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h deleted file mode 100644 index ffbeaa6..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @page libopencm3 GD32F1x0 - -@version 1.0.0 - -API documentation for GigaDevices GD32F1x0 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup GD32F1x0 GD32F1x0xx -Libraries for GigaDevices GD32F1x0xx series. - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup GD32F1x0_defines GD32F1x0xx Defines - -@brief Defined Constants and Types for the GD32F1x0xx series - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/gd32/f1x0/flash.h b/libopencm3/include/libopencm3/gd32/f1x0/flash.h deleted file mode 100644 index e59d27f..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/flash.h +++ /dev/null @@ -1,103 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @brief Defined Constants and Types for the GD32F1x0 Flash memory - * - * @ingroup GD32F1x0_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H -/**@{*/ - -#include -#include -#include - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY_000_024MHZ 0 -#define FLASH_ACR_LATENCY_024_048MHZ 1 -#define FLASH_ACR_LATENCY_048_072MHZ 2 -#define FLASH_ACR_LATENCY_0WS 0 -#define FLASH_ACR_LATENCY_1WS 1 -#define FLASH_ACR_LATENCY_2WS 1 -/**@}*/ - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_EOP (1 << 5) -#define FLASH_SR_WRPRTERR (1 << 4) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_OBL_LAUNCH (1 << 13) - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -#define FLASH_OBR_DATA1_SHIFT 24 -#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT) -#define FLASH_OBR_DATA0_SHIFT 16 -#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT) -#define FLASH_OBR_USER_SHIFT 8 -#define FLASH_OBR_USER (0xFF << FLASH_OBR_USER_SHIFT) - -#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/* Read protection option byte protection level setting */ -#define FLASH_RDP_L0 ((uint8_t)0xa5) -#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */ -#define FLASH_RDP_L2 ((uint8_t)0xcc) - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/gd32/f1x0/gpio.h b/libopencm3/include/libopencm3/gd32/f1x0/gpio.h deleted file mode 100644 index 9c43212..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/gpio.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the GD32F1x0 General Purpose I/O - * - * @ingroup GD32F1x0_defines - * - * @version 1.0.0 - * - * @date 1 July 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/libopencm3/include/libopencm3/gd32/f1x0/irq.json b/libopencm3/include/libopencm3/gd32/f1x0/irq.json deleted file mode 100644 index 87c00d1..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/irq.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "rtc", - "flash", - "rcc", - "exti0_1", - "exti2_3", - "exti4_15", - "tsc", - "dma_channel1", - "dma_channel2_3", - "dma_channel4_5", - "adc_comp", - "tim1_brk_up_trg_com", - "tim1_cc", - "tim2", - "tim3", - "tim6_dac", - "reserved0", - "tim14", - "tim15", - "tim16", - "tim17", - "i2c1_ev", - "i2c2_ev", - "spi1", - "spi2", - "usart1", - "usart2", - "reserved1", - "cec_can", - "reserved2", - "i2c1_er", - "reserved3", - "i2c2_er", - "i2c3_ev", - "i2c3_er", - "usb_lp", - "usb_hp", - "reserved4", - "reserved5", - "reserved6", - "usb_wakeup", - "reserved7", - "reserved8", - "reserved9", - "reserved10", - "reserved11", - "dma_channel6_7", - "reserved12", - "reserved13", - "spi3" - ], - "partname_humanreadable": "GD32F1x0 Series", - "partname_doxygen": "GD32F1x0", - "includeguard": "LIBOPENCM3_GD32F1X0_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/gd32/f1x0/memorymap.h b/libopencm3/include/libopencm3/gd32/f1x0/memorymap.h deleted file mode 100644 index 2c9b86d..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/memorymap.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Iceonwy Zheng - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- GD32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all buses */ -#define FLASH_BASE (0x08000000U) -#define PERIPH_BASE (0x40000000U) -#define INFO_BASE (0x1ffff000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) - -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) - -#define BACKUP_REGS_BASE (RTC_BASE + 0x50) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) -/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) - -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) - -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) - -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) - -#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) - -/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ - -/* AHB1 */ - -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000) - -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000) - -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000) -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000) -#define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000) - - -/* AHB 2 */ - -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) -#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac) -/* Ignore the "reserved for future use" half of the first word */ -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - - -#endif diff --git a/libopencm3/include/libopencm3/gd32/f1x0/rcc.h b/libopencm3/include/libopencm3/gd32/f1x0/rcc.h deleted file mode 100644 index 6377831..0000000 --- a/libopencm3/include/libopencm3/gd32/f1x0/rcc.h +++ /dev/null @@ -1,558 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the GD32F1x0 Reset and Clock - * Control - * - * @ingroup GD32F1x0_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Icenowy Zheng - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) -#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) -#define RCC_CR2 MMIO32(RCC_BASE + 0x34) - - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -#define RCC_CFGR_PLLNODIV (1 << 31) - -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) - -#define RCC_CFGR_PLLMUL_4_SHIFT 27 -#define RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT) - -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0x7 -#define RCC_CFGR_MCO_NOCLK 0 -#define RCC_CFGR_MCO_HSI14 1 -#define RCC_CFGR_MCO_LSI 2 -#define RCC_CFGR_MCO_LSE 3 -#define RCC_CFGR_MCO_SYSCLK 4 -#define RCC_CFGR_MCO_HSI 5 -#define RCC_CFGR_MCO_HSE 6 -#define RCC_CFGR_MCO_PLL 7 - -#define RCC_CFGR_USBPRE_SHIFT 22 -#define RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT) - -#define RCC_CFGR_PLLMUL_0_3_SHIFT 18 -#define RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT) - -#define RCC_CFGR_PLLXTPRE (1 << 17) -#define RCC_CFGR_PLLSRC (1 << 16) - -#define RCC_CFGR_ADCPRE_SHIFT 14 -#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT) - -#define RCC_CFGR_PPRE2_SHIFT 11 -#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT) - -#define RCC_CFGR_PPRE1_SHIFT 8 -#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT) - -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT) - -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) - -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) - -/** @defgroup rcc_cfgr_usbpre USBPRE: USB prescaler (RCC_CFGR[23:22]) - * @{ - */ -#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 -#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 -#define RCC_CFGR_USBPRE_PLL_CLK_DIV2_5 0x2 -#define RCC_CFGR_USBPRE_PLL_CLK_DIV2 0x3 -/**@}*/ - -/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor - * @{ - */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe -/**@}*/ - -/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL entry - * @{ - */ -#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 -#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 -/**@}*/ - -/** @defgroup rcc_cfgr_pcs PLLSRC: PLL entry clock source - * @{ - */ -#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -/**@}*/ - -/** @defgroup rcc_cfgr_adcpre ADCPRE: ADC prescaler - * @{ - */ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 -/**@}*/ - -/** @defgroup rcc_cfgr_apb2pre PPRE2: APB high-speed prescaler (APB2) - * @{ - */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -/**@}*/ - -/** @defgroup rcc_cfgr_apb1pre PPRE1: APB low-speed prescaler (APB1) - * @{ - */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 -/**@}*/ - -/** @defgroup rcc_cfgr_ahbpre HPRE: AHB prescaler - * @{ - */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf -/**@}*/ - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 - -/** @defgroup rcc_cfgr_scs SW: System clock switch - * @{ - */ -#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 -/**@}*/ - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_HSI14RDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_HSI14RDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_HSI14RDYF (1 << 5) -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values values -@{*/ -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_ADCRST (1 << 9) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values values -@{*/ -#define RCC_APB1RSTR_CECRST (1 << 30) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_USBRST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM14RST (1 << 8) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@{*/ -#define RCC_AHBENR_TSCEN (1 << 24) -#define RCC_AHBENR_GPIOFEN (1 << 22) -#define RCC_AHBENR_GPIOEEN (1 << 21) -#define RCC_AHBENR_GPIODEN (1 << 20) -#define RCC_AHBENR_GPIOCEN (1 << 19) -#define RCC_AHBENR_GPIOBEN (1 << 18) -#define RCC_AHBENR_GPIOAEN (1 << 17) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLTFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMAEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@{*/ -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADCEN (1 << 9) -#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_CECEN (1 << 30) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_USBEN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM14EN (1 << 8) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values values -@{*/ -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) -/**@}*/ - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -#define RCC_CFGR2_PREDIV 0xf -#define RCC_CFGR2_PREDIV_NODIV 0x0 -#define RCC_CFGR2_PREDIV_DIV2 0x1 -#define RCC_CFGR2_PREDIV_DIV3 0x2 -#define RCC_CFGR2_PREDIV_DIV4 0x3 -#define RCC_CFGR2_PREDIV_DIV5 0x4 -#define RCC_CFGR2_PREDIV_DIV6 0x5 -#define RCC_CFGR2_PREDIV_DIV7 0x6 -#define RCC_CFGR2_PREDIV_DIV8 0x7 -#define RCC_CFGR2_PREDIV_DIV9 0x8 -#define RCC_CFGR2_PREDIV_DIV10 0x9 -#define RCC_CFGR2_PREDIV_DIV11 0xa -#define RCC_CFGR2_PREDIV_DIV12 0xb -#define RCC_CFGR2_PREDIV_DIV13 0xc -#define RCC_CFGR2_PREDIV_DIV14 0xd -#define RCC_CFGR2_PREDIV_DIV15 0xe -#define RCC_CFGR2_PREDIV_DIV16 0xf - -/* --- RCC_CFGR3 values ---------------------------------------------------- */ - -#define RCC_CFGR3_USART2SW_SHIFT 16 -#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) - -#define RCC_CFGR3_ADCSW (1 << 8) -#define RCC_CFGR3_CECSW (1 << 6) - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_clock_hsi { - RCC_CLOCK_HSI_48MHZ, - RCC_CLOCK_HSI_64MHZ, - RCC_CLOCK_HSI_END -}; - -enum rcc_clock_hse8 { - RCC_CLOCK_HSE8_72MHZ, - RCC_CLOCK_HSE8_END -}; - -struct rcc_clock_scale { - uint8_t pllmul; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - uint8_t adcpre; - uint8_t usbpre; /* Only valid if HSE used */ - bool use_hse; /* PLL source is HSE if set, HSI/2 if unset */ - uint8_t pll_hse_prediv; /* Only valid if HSE used */ - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; -}; - -extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END]; -extern const struct rcc_clock_scale rcc_hse8_configs[RCC_CLOCK_HSE8_END]; - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -/* V = value line F100 - * N = standard line F101, F102, F103 - * C = communication line F105, F107 - */ -enum rcc_periph_clken { - - /* AHB peripherals */ - RCC_DMA = _REG_BIT(0x14, 0), - RCC_SRAM = _REG_BIT(0x14, 2), - RCC_FLTF = _REG_BIT(0x14, 4), - RCC_CRC = _REG_BIT(0x14, 6), - RCC_GPIOA = _REG_BIT(0x14, 17), - RCC_GPIOB = _REG_BIT(0x14, 18), - RCC_GPIOC = _REG_BIT(0x14, 19), - RCC_GPIOD = _REG_BIT(0x14, 20), - RCC_GPIOF = _REG_BIT(0x14, 22), - RCC_TSC = _REG_BIT(0x14, 24), - - /* APB2 peripherals */ - RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), - RCC_ADC = _REG_BIT(0x18, 9), - RCC_TIM1 = _REG_BIT(0x18, 11), - RCC_SPI1 = _REG_BIT(0x18, 12), - RCC_USART1 = _REG_BIT(0x18, 14), - RCC_TIM15 = _REG_BIT(0x18, 16), - RCC_TIM16 = _REG_BIT(0x18, 17), - RCC_TIM17 = _REG_BIT(0x18, 18), - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x1C, 0), - RCC_TIM3 = _REG_BIT(0x1C, 1), - RCC_TIM6 = _REG_BIT(0x1C, 4), - RCC_TIM14 = _REG_BIT(0x1C, 8), - RCC_WWDG = _REG_BIT(0x1C, 11), - RCC_SPI2 = _REG_BIT(0x1C, 14), - RCC_SPI3 = _REG_BIT(0x1C, 15), - RCC_USART2 = _REG_BIT(0x1C, 17), - RCC_I2C1 = _REG_BIT(0x1C, 21), - RCC_I2C2 = _REG_BIT(0x1C, 22), - RCC_USB = _REG_BIT(0x1C, 23), - RCC_PWR = _REG_BIT(0x1C, 28), - RCC_DAC = _REG_BIT(0x1C, 29), - RCC_CEC = _REG_BIT(0x1C, 30), -}; - -enum rcc_periph_rst { - - /* Advanced peripherals */ - RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */ - - /* AHB peripherals */ - RST_GPIOA = _REG_BIT(0x28, 17), - RST_GPIOB = _REG_BIT(0x28, 18), - RST_GPIOC = _REG_BIT(0x28, 19), - RST_GPIOD = _REG_BIT(0x28, 20), - RST_GPIOE = _REG_BIT(0x28, 21), - RST_GPIOF = _REG_BIT(0x28, 22), - RST_TSC = _REG_BIT(0x28, 24), - - /* APB2 peripherals */ - RST_SYSCFG = _REG_BIT(0x0C, 0), - RST_ADC = _REG_BIT(0x0C, 9), - RST_TIM1 = _REG_BIT(0x0C, 11), - RST_SPI1 = _REG_BIT(0x0C, 12), - RST_USART1 = _REG_BIT(0x0C, 14), - RST_TIM15 = _REG_BIT(0x0C, 16), - RST_TIM16 = _REG_BIT(0x0C, 17), - RST_TIM17 = _REG_BIT(0x0C, 18), - - /* APB1 peripherals */ - RST_TIM2 = _REG_BIT(0x10, 0), - RST_TIM3 = _REG_BIT(0x10, 1), - RST_TIM6 = _REG_BIT(0x10, 4), - RST_TIM14 = _REG_BIT(0x10, 8), - RST_WWDG = _REG_BIT(0x10, 11), - RST_SPI2 = _REG_BIT(0x10, 14), - RST_SPI3 = _REG_BIT(0x10, 15), - RST_USART2 = _REG_BIT(0x10, 17), - RST_I2C1 = _REG_BIT(0x10, 21), - RST_I2C2 = _REG_BIT(0x10, 22), - RST_USB = _REG_BIT(0x10, 23), - RST_PWR = _REG_BIT(0x10, 28), - RST_DAC = _REG_BIT(0x10, 29), - RST_CEC = _REG_BIT(0x10, 30), -}; - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_multiplication_factor(uint32_t mul); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_pllxtpre(uint32_t pllxtpre); -uint32_t rcc_rtc_clock_enabled_flag(void); -void rcc_enable_rtc_clock(void); -void rcc_set_rtc_clock_source(enum rcc_osc clock_source); -void rcc_set_adcpre(uint32_t adcpre); -void rcc_set_ppre2(uint32_t ppre1); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_usbpre(uint32_t usbpre); -void rcc_set_prediv(uint32_t prediv); -uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); -void rcc_backupdomain_reset(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/gd32/flash.h b/libopencm3/include/libopencm3/gd32/flash.h deleted file mode 100644 index 38a7328..0000000 --- a/libopencm3/include/libopencm3/gd32/flash.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over GD32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(GD32F1X0) -# include -#else -# error "gd32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/gd32/gpio.h b/libopencm3/include/libopencm3/gd32/gpio.h deleted file mode 100644 index 51c9ff0..0000000 --- a/libopencm3/include/libopencm3/gd32/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over GD32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(GD32F1X0) -# include -#else -# error "gd32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/gd32/memorymap.h b/libopencm3/include/libopencm3/gd32/memorymap.h deleted file mode 100644 index f751fad..0000000 --- a/libopencm3/include/libopencm3/gd32/memorymap.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Icenowy Zheng - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H -#define LIBOPENCM3_MEMORYMAP_COMMON_H - -#if defined(GD32F1X0) -# include -#else -# error "gd32 family not defined." -#endif - -#endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */ diff --git a/libopencm3/include/libopencm3/gd32/rcc.h b/libopencm3/include/libopencm3/gd32/rcc.h deleted file mode 100644 index 3eefd6b..0000000 --- a/libopencm3/include/libopencm3/gd32/rcc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over GD32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(GD32F1X0) -# include -#else -# error "gd32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/license.dox b/libopencm3/include/libopencm3/license.dox deleted file mode 100644 index 3aa9331..0000000 --- a/libopencm3/include/libopencm3/license.dox +++ /dev/null @@ -1,16 +0,0 @@ -/** @page lgpl_license libopencm3 License - -libopencm3 is free software: you can redistribute it and/or modify -it under the terms of the GNU Lesser General Public License as published by the Free -Software Foundation, either version 3 of the License, or (at your option) any -later version. - -libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public License along with this -program. If not, see . - -*/ - diff --git a/libopencm3/include/libopencm3/lm3s/doc-lm3s.h b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h deleted file mode 100644 index 6545140..0000000 --- a/libopencm3/include/libopencm3/lm3s/doc-lm3s.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 LM3S - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for TI Stellaris LM3S Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LM3Sxx LM3S -Libraries for TI Stellaris LM3S series. - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LM3Sxx_defines LM3S Defines - -@brief Defined Constants and Types for the LM3S series - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/lm3s/gpio.h b/libopencm3/include/libopencm3/lm3s/gpio.h deleted file mode 100644 index f7fdd98..0000000 --- a/libopencm3/include/libopencm3/lm3s/gpio.h +++ /dev/null @@ -1,99 +0,0 @@ -/** @defgroup gpio_defines General Purpose I/O Defines - -@brief Defined Constants and Types for the LM3S General Purpose I/O - -@ingroup LM3Sxx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2011 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM3S_GPIO_H -#define LM3S_GPIO_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIOA GPIOA_APB_BASE -#define GPIOB GPIOB_APB_BASE -#define GPIOC GPIOC_APB_BASE -#define GPIOD GPIOD_APB_BASE -#define GPIOE GPIOE_APB_BASE -#define GPIOF GPIOF_APB_BASE -#define GPIOG GPIOG_APB_BASE -#define GPIOH GPIOH_APB_BASE - -/* GPIO number definitions (for convenience) */ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) - -/* --- GPIO registers ------------------------------------------------------ */ - -#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) -#define GPIO_DIR(port) MMIO32((port) + 0x400) -#define GPIO_IS(port) MMIO32((port) + 0x404) -#define GPIO_IBE(port) MMIO32((port) + 0x408) -#define GPIO_IEV(port) MMIO32((port) + 0x40c) -#define GPIO_IM(port) MMIO32((port) + 0x410) -#define GPIO_RIS(port) MMIO32((port) + 0x414) -#define GPIO_MIS(port) MMIO32((port) + 0x418) -#define GPIO_ICR(port) MMIO32((port) + 0x41c) -#define GPIO_AFSEL(port) MMIO32((port) + 0x420) -#define GPIO_DR2R(port) MMIO32((port) + 0x500) -#define GPIO_DR4R(port) MMIO32((port) + 0x504) -#define GPIO_DR8R(port) MMIO32((port) + 0x508) -#define GPIO_ODR(port) MMIO32((port) + 0x50c) -#define GPIO_PUR(port) MMIO32((port) + 0x510) -#define GPIO_PDR(port) MMIO32((port) + 0x514) -#define GPIO_SLR(port) MMIO32((port) + 0x518) -#define GPIO_DEN(port) MMIO32((port) + 0x51c) -#define GPIO_LOCK(port) MMIO32((port) + 0x520) -#define GPIO_CR(port) MMIO32((port) + 0x524) -#define GPIO_AMSEL(port) MMIO32((port) + 0x528) - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint8_t gpios); -void gpio_clear(uint32_t gpioport, uint8_t gpios); - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/lm3s/irq.json b/libopencm3/include/libopencm3/lm3s/irq.json deleted file mode 100644 index 0d8dcfc..0000000 --- a/libopencm3/include/libopencm3/lm3s/irq.json +++ /dev/null @@ -1,126 +0,0 @@ -{ - "_comment": [ - "Although this says LM3S, the interrupt table applies to the", - "LM4F as well Some interrupt vectores marked as reserved in LM3S are", - "used in LM4F, and some vectors in LM3S are marked reserved for LM4F.", - "However, the common vectors are identical, and we can safely use the", - "same interrupt table. Reserved vectors will never be triggered, so", - "having them is perfectly safe." - ], - "irqs": { - "0": "GPIOA", - "1": "GPIOB", - "2": "GPIOC", - "3": "GPIOD", - "4": "GPIOE", - "5": "UART0", - "6": "UART1", - "7": "SSI0", - "8": "I2C0", - "9": "PWM0_FAULT", - "10": "PWM0_0", - "11": "PWM0_1", - "12": "PWM0_2", - "13": "QEI0", - "14": "ADC0SS0", - "15": "ADC0SS1", - "16": "ADC0SS2", - "17": "ADC0SS3", - "18": "WATCHDOG", - "19": "TIMER0A", - "20": "TIMER0B", - "21": "TIMER1A", - "22": "TIMER1B", - "23": "TIMER2A", - "24": "TIMER2B", - "25": "COMP0", - "26": "COMP1", - "27": "COMP2", - "28": "SYSCTL", - "29": "FLASH", - "30": "GPIOF", - "31": "GPIOG", - "32": "GPIOH", - "33": "UART2", - "34": "SSI1", - "35": "TIMER3A", - "36": "TIMER3B", - "37": "I2C1", - "38": "QEI1", - "39": "CAN0", - "40": "CAN1", - "41": "CAN2", - "42": "ETH", - "43": "HIBERNATE", - "44": "USB0", - "45": "PWM0_3", - "46": "UDMA", - "47": "UDMAERR", - "48": "ADC1SS0", - "49": "ADC1SS1", - "50": "ADC1SS2", - "51": "ADC1SS3", - "52": "I2S0", - "53": "EPI0", - "54": "GPIOJ", - "55": "GPIOK", - "56": "GPIOL", - "57": "SSI2", - "58": "SSI3", - "59": "UART3", - "60": "UART4", - "61": "UART5", - "62": "UART6", - "63": "UART7", - "68": "I2C2", - "69": "I2C3", - "70": "TIMER4A", - "71": "TIMER4B", - "92": "TIMER5A", - "93": "TIMER5B", - "94": "WTIMER0A", - "95": "WTIMER0B", - "96": "WTIMER1A", - "97": "WTIMER1B", - "98": "WTIMER2A", - "99": "WTIMER2B", - "100": "WTIMER3A", - "101": "WTIMER3B", - "102": "WTIMER4A", - "103": "WTIMER4B", - "104": "WTIMER5A", - "105": "WTIMER5B", - "106": "SYSEXC", - "107": "PECI0", - "108": "LPC0", - "109": "I2C4", - "110": "I2C5", - "111": "GPIOM", - "112": "GPION", - "114": "FAN0", - "116": "GPIOP0", - "117": "GPIOP1", - "118": "GPIOP2", - "119": "GPIOP3", - "120": "GPIOP4", - "121": "GPIOP5", - "122": "GPIOP6", - "123": "GPIOP7", - "124": "GPIOQ0", - "125": "GPIOQ1", - "126": "GPIOQ2", - "127": "GPIOQ3", - "128": "GPIOQ4", - "129": "GPIOQ5", - "130": "GPIOQ6", - "131": "GPIOQ7", - "134": "PWM1_0", - "135": "PWM1_1", - "136": "PWM1_2", - "137": "PWM1_3", - "138": "PWM1_FAULT" - }, - "partname_humanreadable": "LM3S series", - "partname_doxygen": "LM3S", - "includeguard": "LIBOPENCM3_LM3S_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/lm3s/memorymap.h b/libopencm3/include/libopencm3/lm3s/memorymap.h deleted file mode 100644 index df5d6e3..0000000 --- a/libopencm3/include/libopencm3/lm3s/memorymap.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM3S_MEMORYMAP_H -#define LM3S_MEMORYMAP_H - -#include - -/* --- LM3S specific peripheral definitions ----------------------------- */ - -#define GPIOA_APB_BASE (0x40004000U) -#define GPIOB_APB_BASE (0x40005000U) -#define GPIOC_APB_BASE (0x40006000U) -#define GPIOD_APB_BASE (0x40007000U) -#define GPIOE_APB_BASE (0x40024000U) -#define GPIOF_APB_BASE (0x40025000U) -#define GPIOG_APB_BASE (0x40026000U) -#define GPIOH_APB_BASE (0x40027000U) - -#define GPIOA_BASE (0x40058000U) -#define GPIOB_BASE (0x40059000U) -#define GPIOC_BASE (0x4005A000U) -#define GPIOD_BASE (0x4005B000U) -#define GPIOE_BASE (0x4005C000U) -#define GPIOF_BASE (0x4005D000U) -#define GPIOG_BASE (0x4005E000U) -#define GPIOH_BASE (0x4005F000U) - -#define SYSTEMCONTROL_BASE (0x400FE000U) - -#endif diff --git a/libopencm3/include/libopencm3/lm3s/rcc.h b/libopencm3/include/libopencm3/lm3s/rcc.h deleted file mode 100644 index 853f90e..0000000 --- a/libopencm3/include/libopencm3/lm3s/rcc.h +++ /dev/null @@ -1,107 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the LM3S Reset and Clock - * Control - * - * @ingroup LM3S_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Daniele Lacamera \ - * - * @date 21 November 2015 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Daniele Lacamera - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H -#include - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_RIS MMIO32(0x400FE050) -#define RCC_CR MMIO32(0x400FE060) -#define RCC2_CR MMIO32(0x400FE070) - -/* RCC1 bits */ -#define RCC_SYSDIV_MASK (0x0F << 23) -#define RCC_SYSDIV_12_5MHZ (0x0F << 23) -#define RCC_SYSDIV_50MHZ (0x03 << 23) - -#define RCC_USESYSDIV (1 << 22) -#define RCC_USEPWMDIV (1 << 20) - -#define RCC_PWMDIV_MASK (0x07 << 17) -#define RCC_PWMDIV_64 (0x07 << 17) - -#define RCC_OFF (1 << 13) -#define RCC_BYPASS (1 << 11) - -#define RCC_XTAL_MASK (0x0F << 6) -/* For other values, see datasheet section 23.2.2 - table 23-9 */ -#define RCC_XTAL_6MHZ_RESET (0x0B << 6) -#define RCC_XTAL_8MHZ_400MHZ (0x0D << 6) - - -#define RCC_OSCRC_MASK (0x03 << 4) -#define RCC_OSCRC_MOSC (0x00 << 4) -#define RCC_OSCRC_IOSC (0x01 << 4) -#define RCC_OSCRC_IOSC_Q (0x02 << 4) -#define RCC_OSCRC_30KHZ (0x03 << 4) - -#define RCC_IOSCDIS (1 << 1) -#define RCC_MOSCDIS (1 << 0) - -/* RCC2 bits */ -#define RCC2_USERRCC2 (1 << 31) -#define RCC2_SYSDIV2_MASK 0x7f -#define RCC2_SYSDIV2_SHIFT 23 - -#define RCC2_OFF (1 << 13) -#define RCC2_BYPASS (1 << 11) - -/* RIS bit */ -#define RIS_PLLLRIS (1 << 6) - - -/* From Datasheet description for reset values - * Section 6.4 - Register Descriptions - */ - -/* Register 8: RCC - * Type R/W, reset 0x078E.3AD1 - */ -#define RCC_RESET_VALUE (0x078E3AD1) - -/* Register 10: RCC2 - * Type R/W, reset 0x0780.2810 - */ -#define RCC2_RESET_VALUE (0x07802810) - -BEGIN_DECLS - -int rcc_clock_setup_in_xtal_8mhz_out_50mhz(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/lm3s/systemcontrol.h b/libopencm3/include/libopencm3/lm3s/systemcontrol.h deleted file mode 100644 index dd02f0f..0000000 --- a/libopencm3/include/libopencm3/lm3s/systemcontrol.h +++ /dev/null @@ -1,81 +0,0 @@ -/** @defgroup systemcontrol_defines System Control - -@brief Defined Constants and Types for the LM3S System Control - -@ingroup LM3Sxx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2011 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM3S_SYSTEMCONTROL_H -#define LM3S_SYSTEMCONTROL_H - -/**@{*/ - -#include - -#define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000) -#define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004) -#define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008) -#define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010) -#define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014) -#define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018) -#define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C) -#define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020) -#define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024) -#define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028) -#define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030) -#define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034) -#define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040) -#define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044) -#define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048) -#define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050) -#define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054) -#define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058) -#define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C) -#define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060) -#define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064) -#define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C) -#define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070) -#define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C) -#define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100) -#define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104) -#define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108) -#define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110) -#define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114) -#define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118) -#define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120) -#define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124) -#define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128) -#define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144) - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/lm3s/usart.h b/libopencm3/include/libopencm3/lm3s/usart.h deleted file mode 100644 index d6f8b32..0000000 --- a/libopencm3/include/libopencm3/lm3s/usart.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Daniele Lacamera - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM3S_USART_H -#define LM3S_USART_H - -#include - - - -#define USART0_BASE 0x4000C000 -#define USART1_BASE 0x4000D000 -#define USART2_BASE 0x4000E000 - -/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */ -#define USART_DR(x) MMIO32((x) + 0x0000) -#define USART_IR(x) MMIO32((x) + 0x0004) -#define USART_FR(x) MMIO32((x) + 0x0018) -#define USART_ILPR(x) MMIO32((x) + 0x0020) -#define USART_IBRD(x) MMIO32((x) + 0x0024) -#define USART_FBRD(x) MMIO32((x) + 0x0028) -#define USART_LCRH(x) MMIO32((x) + 0x002c) -#define USART_CTL(x) MMIO32((x) + 0x0030) -#define USART_IFLS(x) MMIO32((x) + 0x0034) -#define USART_IM(x) MMIO32((x) + 0x0038) -#define USART_RIS(x) MMIO32((x) + 0x003c) -#define USART_MIS(x) MMIO32((x) + 0x0040) -#define USART_IC(x) MMIO32((x) + 0x0044) - -/* USART Data Register (USART_DR) */ -/* Bits [31:12] - Reserved */ -#define USART_DR_OE (0x01 << 11) -#define USART_DR_BE (0x01 << 10) -#define USART_DR_PE (0x01 << 9) -#define USART_DR_FE (0x01 << 8) - -/* USART Flags Register (USART_FR) */ -/* Bits [31:8] - Reserved */ -#define USART_FR_TXFE (0x01 << 7) -#define USART_FR_RXFF (0x01 << 6) -#define USART_FR_TXFF (0x01 << 5) -#define USART_FR_RXFE (0x01 << 4) -#define USART_FR_BUSY (0x01 << 3) -/* Bits [2:0] - Reserved */ - -/* USART Interrupt Mask Register (USART_IM) */ -/* Bits [31:11] - Reserved */ -#define USART_IM_OE (0x01 << 10) -#define USART_IM_BE (0x01 << 9) -#define USART_IM_PE (0x01 << 8) -#define USART_IM_FE (0x01 << 7) -#define USART_IM_RT (0x01 << 6) -#define USART_IM_TX (0x01 << 5) -#define USART_IM_RX (0x01 << 4) -/* Bits [3:0] - Reserved */ - -/* USART Interrupt Clear Register (USART_IC) */ -/* Bits [31:11] - Reserved */ -#define USART_IC_OE (0x01 << 10) -#define USART_IC_BE (0x01 << 9) -#define USART_IC_PE (0x01 << 8) -#define USART_IC_FE (0x01 << 7) -#define USART_IC_RT (0x01 << 6) -#define USART_IC_TX (0x01 << 5) -#define USART_IC_RX (0x01 << 4) -/* Bits [3:0] - Reserved */ - -enum usart_stopbits { - USART_STOPBITS_1, - USART_STOPBITS_1_5, - USART_STOPBITS_2, -}; - -enum usart_parity { - USART_PARITY_NONE, - USART_PARITY_ODD, - USART_PARITY_EVEN, -}; - -enum usart_mode { - USART_MODE_DISABLED, - USART_MODE_RX, - USART_MODE_TX, - USART_MODE_TX_RX, -}; - -enum usart_flowcontrol { - USART_FLOWCONTROL_NONE, - USART_FLOWCONTROL_RTS_CTS, -}; - -void usart_send(uint32_t usart, uint16_t data); -uint16_t usart_recv(uint32_t usart); -bool usart_is_send_ready(uint32_t usart); -bool usart_is_recv_ready(uint32_t usart); -void usart_send_blocking(uint32_t usart, uint16_t data); -uint16_t usart_recv_blocking(uint32_t usart); -void usart_enable_rx_interrupt(uint32_t usart); -void usart_disable_rx_interrupt(uint32_t usart); -void usart_clear_rx_interrupt(uint32_t usart); -void usart_enable_tx_interrupt(uint32_t usart); -void usart_disable_tx_interrupt(uint32_t usart); -void usart_clear_tx_interrupt(uint32_t usart); -bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); - -#endif - diff --git a/libopencm3/include/libopencm3/lm4f/doc-lm4f.h b/libopencm3/include/libopencm3/lm4f/doc-lm4f.h deleted file mode 100644 index 9812dbc..0000000 --- a/libopencm3/include/libopencm3/lm4f/doc-lm4f.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 LM4F - -@version 1.0.0 - -@date 22 November 2012 - -API documentation for TI Stellaris LM4F Cortex M4F series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LM4Fxx LM4F -Libraries for TI Stellaris LM4F series. - -@version 1.0.0 - -@date 22 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LM4Fxx_defines LM4F Defines - -@brief Defined Constants and Types for the LM4F series - -@version 1.0.0 - -@date 22 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/lm4f/gpio.h b/libopencm3/include/libopencm3/lm4f/gpio.h deleted file mode 100644 index a2b02b5..0000000 --- a/libopencm3/include/libopencm3/lm4f/gpio.h +++ /dev/null @@ -1,380 +0,0 @@ -/** @defgroup gpio_defines General Purpose I/O Defines - * - * @brief Defined Constants and Types for the LM4F General Purpose I/O - * - * @ingroup LM4Fxx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2011 - * Gareth McMullin - * @author @htmlonly © @endhtmlonly 2013 - * Alexandru Gagniuc - * - * @date 16 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2013 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM4F_GPIO_H -#define LM4F_GPIO_H - -/**@{*/ - -#include -#include - -/* ============================================================================= - * Convenience macros - * ---------------------------------------------------------------------------*/ -/** @defgroup gpio_reg_base GPIO register base addresses - * @{*/ -#define GPIOA GPIOA_BASE -#define GPIOB GPIOB_BASE -#define GPIOC GPIOC_BASE -#define GPIOD GPIOD_BASE -#define GPIOE GPIOE_BASE -#define GPIOF GPIOF_BASE -#define GPIOG GPIOG_BASE -#define GPIOH GPIOH_BASE -#define GPIOJ GPIOJ_BASE -#define GPIOK GPIOK_BASE -#define GPIOL GPIOL_BASE -#define GPIOM GPIOM_BASE -#define GPION GPION_BASE -#define GPIOP GPIOP_BASE -#define GPIOQ GPIOQ_BASE -/** @} */ - -/* ============================================================================= - * GPIO number definitions (for convenience) - * - * These are usable across all GPIO registers, - * except GPIO_LOCK and GPIO_PCTL - * ---------------------------------------------------------------------------*/ -/** @defgroup gpio_pin_id GPIO pin identifiers - * @{*/ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO_ALL 0xff -/** @} */ - -/* ============================================================================= - * GPIO registers - * ---------------------------------------------------------------------------*/ - -/* GPIO Data */ -#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) - -/* GPIO Direction */ -#define GPIO_DIR(port) MMIO32((port) + 0x400) - -/* GPIO Interrupt Sense */ -#define GPIO_IS(port) MMIO32((port) + 0x404) - -/* GPIO Interrupt Both Edges */ -#define GPIO_IBE(port) MMIO32((port) + 0x408) - -/* GPIO Interrupt Event */ -#define GPIO_IEV(port) MMIO32((port) + 0x40c) - -/* GPIO Interrupt Mask */ -#define GPIO_IM(port) MMIO32((port) + 0x410) - -/* GPIO Raw Interrupt Status */ -#define GPIO_RIS(port) MMIO32((port) + 0x414) - -/* GPIO Masked Interrupt Status */ -#define GPIO_MIS(port) MMIO32((port) + 0x418) - -/* GPIO Interrupt Clear */ -#define GPIO_ICR(port) MMIO32((port) + 0x41c) - -/* GPIO Alternate Function Select */ -#define GPIO_AFSEL(port) MMIO32((port) + 0x420) - -/* GPIO 2-mA Drive Select */ -#define GPIO_DR2R(port) MMIO32((port) + 0x500) - -/* GPIO 4-mA Drive Select */ -#define GPIO_DR4R(port) MMIO32((port) + 0x504) - -/* GPIO 8-mA Drive Select */ -#define GPIO_DR8R(port) MMIO32((port) + 0x508) - -/* GPIO Open Drain Select */ -#define GPIO_ODR(port) MMIO32((port) + 0x50c) - -/* GPIO Pull-Up Select */ -#define GPIO_PUR(port) MMIO32((port) + 0x510) - -/* GPIO Pull-Down Select */ -#define GPIO_PDR(port) MMIO32((port) + 0x514) - -/* GPIO Slew Rate Control Select */ -#define GPIO_SLR(port) MMIO32((port) + 0x518) - -/* GPIO Digital Enable */ -#define GPIO_DEN(port) MMIO32((port) + 0x51c) - -/* GPIO Lock */ -#define GPIO_LOCK(port) MMIO32((port) + 0x520) - -/* GPIO Commit */ -#define GPIO_CR(port) MMIO32((port) + 0x524) - -/* GPIO Analog Mode Select */ -#define GPIO_AMSEL(port) MMIO32((port) + 0x528) - -/* GPIO Port Control */ -#define GPIO_PCTL(port) MMIO32((port) + 0x52C) - -/* GPIO ADC Control */ -#define GPIO_ADCCTL(port) MMIO32((port) + 0x530) - -/* GPIO DMA Control */ -#define GPIO_DMACTL(port) MMIO32((port) + 0x534) - -/* GPIO Peripheral Identification */ -#define GPIO_PERIPH_ID4(port) MMIO32((port) + 0xFD0) -#define GPIO_PERIPH_ID5(port) MMIO32((port) + 0xFD4) -#define GPIO_PERIPH_ID6(port) MMIO32((port) + 0xFD8) -#define GPIO_PERIPH_ID7(port) MMIO32((port) + 0xFDC) -#define GPIO_PERIPH_ID0(port) MMIO32((port) + 0xFE0) -#define GPIO_PERIPH_ID1(port) MMIO32((port) + 0xFE4) -#define GPIO_PERIPH_ID2(port) MMIO32((port) + 0xFE8) -#define GPIO_PERIPH_ID3(port) MMIO32((port) + 0xFEC) - -/* GPIO PrimeCell Identification */ -#define GPIO_PCELL_ID0(port) MMIO32((port) + 0xFF0) -#define GPIO_PCELL_ID1(port) MMIO32((port) + 0xFF4) -#define GPIO_PCELL_ID2(port) MMIO32((port) + 0xFF8) -#define GPIO_PCELL_ID3(port) MMIO32((port) + 0xFFC) - -/* ============================================================================= - * Convenience enums - * ---------------------------------------------------------------------------*/ -enum gpio_mode { - GPIO_MODE_OUTPUT, /**< Configure pin as output */ - GPIO_MODE_INPUT, /**< Configure pin as input */ - GPIO_MODE_ANALOG, /**< Configure pin as analog function */ -}; - -enum gpio_pullup { - GPIO_PUPD_NONE, /**< Do not pull the pin high or low */ - GPIO_PUPD_PULLUP, /**< Pull the pin high */ - GPIO_PUPD_PULLDOWN, /**< Pull the pin low */ -}; - -enum gpio_output_type { - GPIO_OTYPE_PP, /**< Push-pull configuration */ - GPIO_OTYPE_OD, /**< Open drain configuration */ -}; - -enum gpio_drive_strength { - GPIO_DRIVE_2MA, /**< 2mA drive */ - GPIO_DRIVE_4MA, /**< 4mA drive */ - GPIO_DRIVE_8MA, /**< 8mA drive */ - GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */ -}; - -enum gpio_trigger { - GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */ - GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */ - GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */ - GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger*/ - GPIO_TRIG_EDGE_BOTH, /**< Falling and Rising edges trigger*/ -}; -/* ============================================================================= - * Function prototypes - * ---------------------------------------------------------------------------*/ -BEGIN_DECLS - -void gpio_enable_ahb_aperture(void); -void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, - enum gpio_pullup pullup, uint8_t gpios); -void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype, - enum gpio_drive_strength drive, uint8_t gpios); -void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios); - -void gpio_toggle(uint32_t gpioport, uint8_t gpios); -void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios); - -/* Let's keep these ones inlined. GPIO control should be fast */ -/** @ingroup gpio_control - * @{ */ - -/** - * \brief Get status of a Group of Pins (atomic) - * - * Reads the level of the given pins. Bit 0 of the returned data corresponds to - * GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked - * pins (corresponding bit of gpios parameter set to zero) are returned as 0. - * - * This is an atomic operation. - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - * - * @return The level of the GPIO port. The pins not specified in gpios are - * masked to zero. - */ -static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios) -{ - return GPIO_DATA(gpioport)[gpios]; -} - -/** - * \brief Set level of a Group of Pins (atomic) - * - * Sets the level of the given pins. Bit 0 of the data parameter corresponds to - * GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios - * parameter set to zero) are returned not affected. - * - * This is an atomic operation. - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit - * 1 to GPIO1. and so on. - */ -static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data) -{ - /* ipaddr[9:2] mask the bits to be set, hence the array index */ - GPIO_DATA(gpioport)[gpios] = data; -} - -/** - * \brief Set a Group of Pins (atomic) - * - * Set one or more pins of the given GPIO port. This is an atomic operation. - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - */ -static inline void gpio_set(uint32_t gpioport, uint8_t gpios) -{ - gpio_write(gpioport, gpios, 0xff); -} - -/** - * \brief Clear a Group of Pins (atomic) - * - * Clear one or more pins of the given GPIO port. This is an atomic operation. - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - */ -static inline void gpio_clear(uint32_t gpioport, uint8_t gpios) -{ - gpio_write(gpioport, gpios, 0); -} - -/** - * \brief Read level of all pins from a port (atomic) - * - * Read the current value of the given GPIO port. This is an atomic operation. - * - * This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL). - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * - * @return The level of all the pins on the GPIO port. - */ -static inline uint8_t gpio_port_read(uint32_t gpioport) -{ - return gpio_read(gpioport, GPIO_ALL); -} - -/** - * \brief Set level of of all pins from a port (atomic) - * - * Set the level of all pins on the given GPIO port. This is an atomic - * operation. - * - * This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data). - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit - * 1 to GPIO1. and so on. - */ -static inline void gpio_port_write(uint32_t gpioport, uint8_t data) -{ - gpio_write(gpioport, GPIO_ALL, data); -} -/** @} */ - -void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, - uint8_t gpios); -void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios); -void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios); - - -/* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */ -/** @ingroup gpio_irq - * @{ */ -/** \brief Determine if interrupt is generated by the given pin - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] srcpins source pin or group of pins to check. - */ -static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins) -{ - return GPIO_MIS(gpioport) & srcpins; -} - -/** - * \brief Mark interrupt as serviced - * - * After an interrupt is services, its flag must be cleared. If the flag is not - * cleared, then execution will jump back to the start of the ISR after the ISR - * returns. - * - * @param[in] gpioport GPIO block register address base @ref gpio_reg_base - * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified - * by OR'ing then together. - */ -static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) -{ - GPIO_ICR(gpioport) |= gpios; -} - -/** @} */ -END_DECLS - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/lm4f/memorymap.h b/libopencm3/include/libopencm3/lm4f/memorymap.h deleted file mode 100644 index e2f6060..0000000 --- a/libopencm3/include/libopencm3/lm4f/memorymap.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM4F_MEMORYMAP_H -#define LM4F_MEMORYMAP_H - -#include - -/* --- LM4F specific peripheral definitions ----------------------------- */ - -#define GPIOA_APB_BASE (0x40004000U) -#define GPIOB_APB_BASE (0x40005000U) -#define GPIOC_APB_BASE (0x40006000U) -#define GPIOD_APB_BASE (0x40007000U) -#define GPIOE_APB_BASE (0x40024000U) -#define GPIOF_APB_BASE (0x40025000U) -#define GPIOG_APB_BASE (0x40026000U) -#define GPIOH_APB_BASE (0x40027000U) -#define GPIOJ_APB_BASE (0x4003D000U) - -#define GPIOA_BASE (0x40058000U) -#define GPIOB_BASE (0x40059000U) -#define GPIOC_BASE (0x4005A000U) -#define GPIOD_BASE (0x4005B000U) -#define GPIOE_BASE (0x4005C000U) -#define GPIOF_BASE (0x4005D000U) -#define GPIOG_BASE (0x4005E000U) -#define GPIOH_BASE (0x4005F000U) -#define GPIOJ_BASE (0x40060000U) -#define GPIOK_BASE (0x40061000U) -#define GPIOL_BASE (0x40062000U) -#define GPIOM_BASE (0x40063000U) -#define GPION_BASE (0x40064000U) -#define GPIOP_BASE (0x40065000U) -#define GPIOQ_BASE (0x40066000U) - -#define TIMER0_BASE (0x40030000U) -#define TIMER1_BASE (0x40031000U) -#define TIMER2_BASE (0x40032000U) -#define TIMER3_BASE (0x40033000U) -#define TIMER4_BASE (0x40034000U) -#define TIMER5_BASE (0x40035000U) - -#define WTIMER0 (0x40036000U) -#define WTIMER1 (0x40037000U) -#define WTIMER2 (0x4004C000U) -#define WTIMER3 (0x4004D000U) -#define WTIMER4 (0x4004E000U) -#define WTIMER5 (0x4004F000U) - -#define UART0_BASE (0x4000C000U) -#define UART1_BASE (0x4000D000U) -#define UART2_BASE (0x4000E000U) -#define UART3_BASE (0x4000F000U) -#define UART4_BASE (0x40010000U) -#define UART5_BASE (0x40011000U) -#define UART6_BASE (0x40012000U) -#define UART7_BASE (0x40013000U) - -#define SSI0_BASE (0x40008000U) -#define SSI1_BASE (0x40009000U) -#define SSI2_BASE (0x4000A000U) -#define SSI3_BASE (0x4000B000U) - -#define USB_BASE (0x40050000U) - -#define SYSCTL_BASE (0x400FE000U) - -#endif diff --git a/libopencm3/include/libopencm3/lm4f/nvic.h b/libopencm3/include/libopencm3/lm4f/nvic.h deleted file mode 100644 index 841367f..0000000 --- a/libopencm3/include/libopencm3/lm4f/nvic.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @defgroup nvic_defines Nested Vectored Interrupt Controller - -@brief Defined Constants and Types for the LM4F Nested Vectored Interrupt -Controller - -@ingroup LM4Fxx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 -Alexandru Gagniuc - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LM4F_NVIC_H -#define LIBOPENCM3_LM4F_NVIC_H - -/**@{*/ - -#include - -/** @ingroup nvic_defines - * The LM3S interrupt table applies to the LM4F as well. Some interrupt - * vectors marked as reserved in LM3S are used in LM4F, and some vectors in - * LM3S are marked reserved for LM4F. However, the common vectors are - * identical, and we can safely use the same interrupt table. Reserved vectors - * will never be triggered, so having them is perfectly safe. - */ -#include - -/**@}*/ - -#endif /* LIBOPENCM3_LM4F_NVIC_H */ diff --git a/libopencm3/include/libopencm3/lm4f/rcc.h b/libopencm3/include/libopencm3/lm4f/rcc.h deleted file mode 100644 index 98a92cf..0000000 --- a/libopencm3/include/libopencm3/lm4f/rcc.h +++ /dev/null @@ -1,133 +0,0 @@ -/** @defgroup rcc_defines Reset and Clock Control - -@brief Defined Constants and Types for the LM4F Reset and Clock Control - -@ingroup LM4Fxx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 -Alexandru Gagniuc - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM4F_RCC_H -#define LM4F_RCC_H - -/**@{*/ - -#include - -/** - * \brief Oscillator source values - * - * Possible values of the oscillator source. - */ -enum osc_src { - OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC, - OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC, - OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4, - OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K, - OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768, -}; - -/** - * \brief PWM clock divisor values - * - * Possible values of the binary divisor used to predivide the system clock down - * for use as the timing reference for the PWM module. - */ -enum pwm_clkdiv { - PWMDIV_2 = SYSCTL_RCC_PWMDIV_2, - PWMDIV_4 = SYSCTL_RCC_PWMDIV_4, - PWMDIV_8 = SYSCTL_RCC_PWMDIV_8, - PWMDIV_16 = SYSCTL_RCC_PWMDIV_16, - PWMDIV_32 = SYSCTL_RCC_PWMDIV_32, - PWMDIV_64 = SYSCTL_RCC_PWMDIV_64, -}; - -/** - * \brief Predefined crystal values - * - * Predefined crystal values for the XTAL field in SYSCTL_RCC. - * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and - * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock - * of 400MHz. - */ -enum xtal_t { - XTAL_4M = SYSCTL_RCC_XTAL_4M, - XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096, - XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152, - XTAL_5M = SYSCTL_RCC_XTAL_5M, - XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12, - XTAL_6M = SYSCTL_RCC_XTAL_6M, - XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144, - XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728, - XTAL_8M = SYSCTL_RCC_XTAL_8M, - XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192, - XTAL_10M = SYSCTL_RCC_XTAL_10M, - XTAL_12M = SYSCTL_RCC_XTAL_12M, - XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288, - XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56, - XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818, - XTAL_16M = SYSCTL_RCC_XTAL_16M, - XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384, - XTAL_18M = SYSCTL_RCC_XTAL_18M, - XTAL_20M = SYSCTL_RCC_XTAL_20M, - XTAL_24M = SYSCTL_RCC_XTAL_24M, - XTAL_25M = SYSCTL_RCC_XTAL_25M, -}; - -/* ============================================================================= - * Function prototypes - * ---------------------------------------------------------------------------*/ -BEGIN_DECLS -/* Low-level clock API */ -void rcc_configure_xtal(enum xtal_t xtal); -void rcc_disable_main_osc(void); -void rcc_disable_interal_osc(void); -void rcc_enable_main_osc(void); -void rcc_enable_interal_osc(void); -void rcc_enable_rcc2(void); -void rcc_pll_off(void); -void rcc_pll_on(void); -void rcc_set_osc_source(enum osc_src src); -void rcc_pll_bypass_disable(void); -void rcc_pll_bypass_enable(void); -void rcc_set_pll_divisor(uint8_t div400); -void rcc_set_pwm_divisor(enum pwm_clkdiv div); -void rcc_usb_pll_off(void); -void rcc_usb_pll_on(void); -void rcc_wait_for_pll_ready(void); -/* High-level clock API */ -void rcc_change_pll_divisor(uint8_t plldiv400); -uint32_t rcc_get_system_clock_frequency(void); -void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400); - -END_DECLS - -/**@}*/ - -#endif /* LM4F_RCC_H */ diff --git a/libopencm3/include/libopencm3/lm4f/ssi.h b/libopencm3/include/libopencm3/lm4f/ssi.h deleted file mode 100644 index 77a7555..0000000 --- a/libopencm3/include/libopencm3/lm4f/ssi.h +++ /dev/null @@ -1,118 +0,0 @@ -/** @defgroup ssi_defines Synchronous Serial Interface - * - * @brief Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI) - * - * @ingroup LM4Fxx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Tiago Costa - * - * @date 11 June 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Tiago Costa - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM4F_SSI_H -#define LM4F_SSI_H - -/**@{*/ - -#include -#include - -/* ============================================================================= - * Convenience macros - * ---------------------------------------------------------------------------*/ -/** @defgroup ssi_base SSI register base addresses - * @{*/ -#define SSI0 SSI0_BASE -#define SSI1 SSI1_BASE -#define SSI2 SSI2_BASE -#define SSI3 SSI3_BASE -/** @} */ - -/* ============================================================================= - * SSI registers - * ---------------------------------------------------------------------------*/ - -/* SSI Control 0 */ -#define SSI_CR0(port) MMIO32((port) + 0x000) - -/* SSI Control 1 */ -#define SSI_CR1(port) MMIO32((port) + 0x004) - -/* SSI Data */ -#define SSI_DR(port) MMIO32((port) + 0x008) - -/* SSI Satus */ -#define SSI_SR(port) MMIO32((port) + 0x00C) - -/* SSI Clock Prescale */ -#define SSI_CPSR(port) MMIO32((port) + 0x010) - -/* SSI Interrupt Mask */ -#define SSI_IM(port) MMIO32((port) + 0x014) - -/* SSI Raw Interrupt Status */ -#define SSI_RIS(port) MMIO32((port) + 0x018) - -/* SSI Masked Interrupt Status */ -#define SSI_MIS(port) MMIO32((port) + 0x01C) - -/* SSI Interrupt Clear */ -#define SSI_ICR(port) MMIO32((port) + 0x020) - -/* SSI DMA Control */ -#define SSI_DMACTL(port) MMIO32((port) + 0x024) - -/* SSI Clock Configuration */ -#define SSI_CC(port) MMIO32((port) + 0xFC8) - -/* SSI Peripheral Identification */ -#define SSI_PERIPH_ID4(port) MMIO32((port) + 0xFD0) -#define SSI_PERIPH_ID5(port) MMIO32((port) + 0xFD4) -#define SSI_PERIPH_ID6(port) MMIO32((port) + 0xFD8) -#define SSI_PERIPH_ID7(port) MMIO32((port) + 0xFDC) -#define SSI_PERIPH_ID0(port) MMIO32((port) + 0xFE0) -#define SSI_PERIPH_ID1(port) MMIO32((port) + 0xFE4) -#define SSI_PERIPH_ID2(port) MMIO32((port) + 0xFE8) -#define SSI_PERIPH_ID3(port) MMIO32((port) + 0xFEC) - -/* SSI PrimeCell Identification */ -#define SSI_PCELL_ID0(port) MMIO32((port) + 0xFF0) -#define SSI_PCELL_ID1(port) MMIO32((port) + 0xFF4) -#define SSI_PCELL_ID2(port) MMIO32((port) + 0xFF8) -#define SSI_PCELL_ID3(port) MMIO32((port) + 0xFFC) - -/* ============================================================================= - * Function prototypes - * ---------------------------------------------------------------------------*/ -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif /* LM4F_SSI_H */ - diff --git a/libopencm3/include/libopencm3/lm4f/systemcontrol.h b/libopencm3/include/libopencm3/lm4f/systemcontrol.h deleted file mode 100644 index 62e2231..0000000 --- a/libopencm3/include/libopencm3/lm4f/systemcontrol.h +++ /dev/null @@ -1,743 +0,0 @@ -/** @defgroup systemcontrol_defines System Control - -@brief Defined Constants and Types for the LM4F System Control - -@ingroup LM4Fxx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 -Alexandru Gagniuc - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LM4F_SYSTEMCONTROL_H -#define LM4F_SYSTEMCONTROL_H - -/**@{*/ - -#include -#include - -#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) -#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) -#define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030) -#define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034) -#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) -#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) -#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) -#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) -#define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060) -#define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064) -#define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C) -#define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070) -#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) -#define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144) -#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) -#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) -#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) -#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) -#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) -#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) -/* Peripheral present */ -#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) -#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) -#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) -#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) -#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) -#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) -#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) -#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) -#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) -#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) -#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) -#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) -#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) -#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) -#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) -#define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C) -/* Peripheral software reset */ -#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) -#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) -#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) -#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) -#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) -#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) -#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) -#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) -#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) -#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) -#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) -#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) -#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) -#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) -#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) -#define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C) -/* Peripheral run mode clock gating control */ -#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) -#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) -#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) -#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) -#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) -#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) -#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) -#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) -#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) -#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) -#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) -#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) -#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) -#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) -#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) -#define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C) -/* Peripheral sleep mode clock gating control */ -#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) -#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) -#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) -#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) -#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) -#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) -#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) -#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) -#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) -#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) -#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) -#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) -#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) -#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) -#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) -#define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C) -/* Peripheral deep-sleep mode clock gating control */ -#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) -#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) -#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) -#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) -#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) -#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) -#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) -#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) -#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) -#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) -#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) -#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) -#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) -#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) -#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) -#define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C) -/* Peripheral ready */ -#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) -#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) -#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) -#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) -#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) -#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) -#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) -#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) -#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) -#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) -#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) -#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) -#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) -#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) -#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) -#define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C) -/* ============================================================================= - * System Control Legacy Registers - * ---------------------------------------------------------------------------*/ -#ifdef LM4F_LEGACY_SYSCTL -#define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008) -#define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010) -#define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014) -#define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018) -#define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C) -#define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020) -#define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024) -#define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028) -#define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C) -#define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040) -#define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044) -#define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048) -#define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100) -#define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104) -#define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108) -#define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110) -#define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114) -#define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118) -#define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120) -#define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124) -#define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128) -#define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190) -#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) -#endif /* LM4F_LEGACY_SYSCTL */ - -/* ============================================================================= - * SYSCTL_DID0 values - * ---------------------------------------------------------------------------*/ -/** DID0 version */ -#define SYSCTL_DID0_VER_MASK (7 << 28) -/** Device class */ -#define SYSCTL_DID0_CLASS_MASK (0xFF << 16) -/** Major revision */ -#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) -/** Minor revision */ -#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) - -/* ============================================================================= - * SYSCTL_DID1 values - * ---------------------------------------------------------------------------*/ -/** DID1 version */ -#define SYSCTL_DID1_VER_MASK (0xF << 28) -/** Family */ -#define SYSCTL_DID1_FAM_MASK (0xF << 24) -/** Part number */ -#define SYSCTL_DID1_PARTNO_MASK (0xFF << 16) -/** Pin count */ -#define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13) -#define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13) -#define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13) -#define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13) -#define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13) -#define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13) -#define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13) -/** Temperature range */ -#define SYSCTL_DID1_TEMP_MASK (0x7 << 5) -#define SYSCTL_DID1_TEMP_0_70 (0x0 << 5) -#define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5) -#define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5) -/** Package */ -#define SYSCTL_DID1_PKG_MASK (0x3 << 5) -#define SYSCTL_DID1_PKG_SOIC (0x0 << 5) -#define SYSCTL_DID1_PKG_LQFP (0x1 << 5) -#define SYSCTL_DID1_PKG_BGA (0x2 << 5) -/** ROHS compliance */ -#define SYSCTL_DID1_ROHS (1 << 2) -/** Qualification status */ -#define SYSCTL_DID1_QUAL_MASK (3 << 0) - -/* ============================================================================= - * SYSCTL_PBORCTL values - * ---------------------------------------------------------------------------*/ -/** BOR interrupt or reset */ -#define SYSCTL_PBORCTL_BORIOR (1 << 1) - -/* ============================================================================= - * SYSCTL_RIS values - * ---------------------------------------------------------------------------*/ -/** MOSC Power Up Raw Interrupt Status */ -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) -/** USB PLL Lock Raw Interrupt Status */ -#define SYSCTL_RIS_USBPLLLRIS (1 << 7) -/** PLL Lock Raw Interrupt Status */ -#define SYSCTL_RIS_PLLLRIS (1 << 6) -/** Main Oscillator Failure Raw Interrupt Status */ -#define SYSCTL_RIS_MOFRIS (1 << 3) -/** Brown-Out Reset Raw Interrupt Status */ -#define SYSCTL_RIS_BORRIS (1 << 1) - -/* ============================================================================= - * SYSCTL_IMC values - * ---------------------------------------------------------------------------*/ -/** MOSC Power Up Raw Interrupt Status */ -#define SYSCTL_IMC_MOSCPUPIM (1 << 8) -/** USB PLL Lock Raw Interrupt Status */ -#define SYSCTL_IMC_USBPLLLIM (1 << 7) -/** PLL Lock Raw Interrupt Status */ -#define SYSCTL_IMC_PLLLIM (1 << 6) -/** Main Oscillator Failure Raw Interrupt Status */ -#define SYSCTL_IMC_MOFIM (1 << 3) -/** Brown-Out Reset Raw Interrupt Status */ -#define SYSCTL_IMC_BORIM (1 << 1) - -/* ============================================================================= - * SYSCTL_MISC values - * ---------------------------------------------------------------------------*/ -/** MOSC Power Up Raw Interrupt Status */ -#define SYSCTL_MISC_MOSCPUPMIS (1 << 8) -/** USB PLL Lock Raw Interrupt Status */ -#define SYSCTL_MISC_USBPLLLMIS (1 << 7) -/** PLL Lock Raw Interrupt Status */ -#define SYSCTL_MISC_PLLLMIS (1 << 6) -/** Main Oscillator Failure Raw Interrupt Status */ -#define SYSCTL_MISC_MOFMIS (1 << 3) -/** Brown-Out Reset Raw Interrupt Status */ -#define SYSCTL_MISC_BORMIS (1 << 1) - -/* ============================================================================= - * SYSCTL_RESC values - * ---------------------------------------------------------------------------*/ -/** MOSC Failure Reset */ -#define SYSCTL_RESC_MOSCFAIL (1 << 18) -/** Watchdog Timer 1 Reset */ -#define SYSCTL_RESC_WDT1 (1 << 5) -/** Software Reset */ -#define SYSCTL_RESC_SW (1 << 4) -/** Watchdog Timer 0 Reset */ -#define SYSCTL_RESC_WDT0 (1 << 3) -/** Brown-Out Reset */ -#define SYSCTL_RESC_BOR (1 << 2) -/** Power-On Reset */ -#define SYSCTL_RESC_POR (1 << 1) -/** External Reset */ -#define SYSCTL_RESC_EXT (1 << 0) - -/* ============================================================================= - * SYSCTL_RCC values - * ---------------------------------------------------------------------------*/ -/** Auto Clock Gating */ -#define SYSCTL_RCC_ACG (1 << 27) -/** System Clock Divisor */ -#define SYSCTL_RCC_SYSDIV_MASK (0xF << 23) -/** Enable System Clock Divider */ -#define SYSCTL_RCC_USESYSDIV (1 << 22) -/** Enable PWM Clock Divisor */ -#define SYSCTL_RCC_USEPWMDIV (1 << 20) -/** PWM Unit Clock Divisor */ -#define SYSCTL_RCC_PWMDIV_MASK (0xF << 17) -#define SYSCTL_RCC_PWMDIV_2 (0x0 << 17) -#define SYSCTL_RCC_PWMDIV_4 (0x1 << 17) -#define SYSCTL_RCC_PWMDIV_8 (0x2 << 17) -#define SYSCTL_RCC_PWMDIV_16 (0x3 << 17) -#define SYSCTL_RCC_PWMDIV_32 (0x4 << 17) -#define SYSCTL_RCC_PWMDIV_64 (0x5 << 17) -/** PLL Power Down */ -#define SYSCTL_RCC_PWRDN (1 << 13) -/** PLL Bypass */ -#define SYSCTL_RCC_BYPASS (1 << 11) -/** Crystal Value */ -#define SYSCTL_RCC_XTAL_MASK (0x1F << 6) -#define SYSCTL_RCC_XTAL_4M (0x06 << 6) -#define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6) -#define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6) -#define SYSCTL_RCC_XTAL_5M (0x09 << 6) -#define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6) -#define SYSCTL_RCC_XTAL_6M (0x0B << 6) -#define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6) -#define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6) -#define SYSCTL_RCC_XTAL_8M (0x0E << 6) -#define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6) -#define SYSCTL_RCC_XTAL_10M (0x10 << 6) -#define SYSCTL_RCC_XTAL_12M (0x11 << 6) -#define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6) -#define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6) -#define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6) -#define SYSCTL_RCC_XTAL_16M (0x15 << 6) -#define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6) -#define SYSCTL_RCC_XTAL_18M (0x17 << 6) -#define SYSCTL_RCC_XTAL_20M (0x18 << 6) -#define SYSCTL_RCC_XTAL_24M (0x19 << 6) -#define SYSCTL_RCC_XTAL_25M (0x1A << 6) -/** Oscillator Source */ -#define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4) -#define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4) -#define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4) -#define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4) -#define SYSCTL_RCC_OSCSRC_30K (0x3 << 4) -/** Precision Internal Oscillator Disable */ -#define SYSCTL_RCC_IOSCDIS (1 << 1) -/** Main Oscillator Disable */ -#define SYSCTL_RCC_MOSCDIS (1 << 0) - -/* ============================================================================= - * SYSCTL_GPIOHBCTL values - * ---------------------------------------------------------------------------*/ -#define SYSCTL_GPIOHBCTL_PORTQ (1 << 14) -#define SYSCTL_GPIOHBCTL_PORTP (1 << 13) -#define SYSCTL_GPIOHBCTL_PORTN (1 << 12) -#define SYSCTL_GPIOHBCTL_PORTM (1 << 11) -#define SYSCTL_GPIOHBCTL_PORTL (1 << 10) -#define SYSCTL_GPIOHBCTL_PORTK (1 << 9) -#define SYSCTL_GPIOHBCTL_PORTJ (1 << 8) -#define SYSCTL_GPIOHBCTL_PORTH (1 << 7) -#define SYSCTL_GPIOHBCTL_PORTG (1 << 6) -#define SYSCTL_GPIOHBCTL_PORTF (1 << 5) -#define SYSCTL_GPIOHBCTL_PORTE (1 << 4) -#define SYSCTL_GPIOHBCTL_PORTD (1 << 3) -#define SYSCTL_GPIOHBCTL_PORTC (1 << 2) -#define SYSCTL_GPIOHBCTL_PORTB (1 << 1) -#define SYSCTL_GPIOHBCTL_PORTA (1 << 0) - -/* ============================================================================= - * SYSCTL_RCC2 values - * ---------------------------------------------------------------------------*/ -/** RCC2 overides RCC */ -#define SYSCTL_RCC2_USERCC2 (1 << 31) -/** Divide PLL as 400 MHz vs. 200 MHz */ -#define SYSCTL_RCC2_DIV400 (1 << 30) -/** Auto Clock Gating */ -#define SYSCTL_RCC2_ACG (1 << 27) -/** System Clock Divisor 2 */ -#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23) -/** Additional LSB for SYSDIV2 */ -#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22) -/** System clock divisor mask when RCC2_DIV400 is set */ -#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22) -/** Power-Down USB PLL */ -#define SYSCTL_RCC2_USBPWRDN (1 << 14) -/** PLL Power Down 2 */ -#define SYSCTL_RCC2_PWRDN2 (1 << 13) -/** PLL Bypass 2 */ -#define SYSCTL_RCC2_BYPASS2 (1 << 11) -/** Oscillator Source 2 */ -#define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4) -#define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4) -#define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4) -#define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4) -#define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4) -#define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4) - -/* ============================================================================= - * SYSCTL_MOSCCTL values - * ---------------------------------------------------------------------------*/ -/** No Crystal Connected */ -#define SYSCTL_MOSCCTL_NOXTAL (1 << 2) -/** MOSC Failure Action */ -#define SYSCTL_MOSCCTL_MOSCIM (1 << 1) -/** Clock Validation for MOSC */ -#define SYSCTL_MOSCCTL_CVAL (1 << 0) - -/* ============================================================================= - * SYSCTL_DSLPCLKCFG values - * ---------------------------------------------------------------------------*/ -/*TODO*/ - -/* ============================================================================= - * SYSCTL_SYSPROP values - * ---------------------------------------------------------------------------*/ -/** FPU present */ -#define SYSCTL_SYSPROP_FPU (1 << 0) - -/* ============================================================================= - * SYSCTL_PIOSCCAL values - * ---------------------------------------------------------------------------*/ -/** Use User Trim Value */ -#define SYSCTL_PIOSCCAL_UTEN (1 << 31) -/** Start calibration */ -#define SYSCTL_PIOSCCAL_CAL (1 << 9) -/** Update trim */ -#define SYSCTL_PIOSCCAL_UPDATE (1 << 8) -/** User Trim Value */ -#define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0) - -/* ============================================================================= - * SYSCTL_PIOSCSTAT values - * ---------------------------------------------------------------------------*/ -/** Default Trim Value */ -#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16) -/** Calibration result */ -#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8) -/** Calibration Trim Value */ -#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0) -/* ============================================================================= - * SYSCTL_PLLFREQ0 values - * ---------------------------------------------------------------------------*/ -/** PLL M fractional value */ -#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10) -/** PLL M integer value */ -#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0) - -/* ============================================================================= - * SYSCTL_PLLFREQ1 values - * ---------------------------------------------------------------------------*/ -/** PLL Q value */ -#define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8) -/** PLL N value */ -#define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0) - -/* ============================================================================= - * SYSCTL_PLLSTAT values - * ---------------------------------------------------------------------------*/ -/** PLL lock */ -#define SYSCTL_PLLSTAT_LOCK (1 << 0) - -/* ============================================================================= - * Convenience definitions for a readable API - * ---------------------------------------------------------------------------*/ -/** - * \brief Clock enable definitions - * - * The definitions are specified in the form - * 31:5 register offset from SYSCTL_BASE for the clock register - * 4:0 bit offset for the given peripheral - * - * The names have the form [clock_type]_[periph_type]_[periph_number] - * Where clock_type is - * RCC for run clock - * SCC for sleep clock - * DCC for deep-sleep clock - */ -enum lm4f_clken { - /* - * Run clock control - */ - RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5, - RCC_WD1, - - RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5, - RCC_TIMER1, - RCC_TIMER2, - RCC_TIMER3, - RCC_TIMER4, - RCC_TIMER5, - - RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, - RCC_GPIOB, - RCC_GPIOC, - RCC_GPIOD, - RCC_GPIOE, - RCC_GPIOF, - RCC_GPIOG, - RCC_GPIOH, - RCC_GPIOJ, - RCC_GPIOK, - RCC_GPIOL, - RCC_GPIOM, - RCC_GPION, - RCC_GPIOP, - RCC_GPIOQ, - - RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5, - - RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, - - RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5, - RCC_UART1, - RCC_UART2, - RCC_UART3, - RCC_UART4, - RCC_UART5, - RCC_UART6, - RCC_UART7, - - RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5, - RCC_SSI1, - RCC_SSI2, - RCC_SSI3, - - RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5, - RCC_I2C1, - RCC_I2C2, - RCC_I2C3, - RCC_I2C4, - RCC_I2C5, - - RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5, - - RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5, - RCC_CAN1, - - RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5, - RCC_ADC1, - - RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5, - - RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5, - RCC_PWM1, - - RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5, - RCC_QEI1, - - RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5, - - RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5, - RCC_WTIMER1, - RCC_WTIMER2, - RCC_WTIMER3, - RCC_WTIMER4, - RCC_WTIMER5, - - - /* - * Sleep clock control - */ - SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5, - SCC_WD1, - - SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5, - SCC_TIMER1, - SCC_TIMER2, - SCC_TIMER3, - SCC_TIMER4, - SCC_TIMER5, - - SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, - SCC_GPIOB, - SCC_GPIOC, - SCC_GPIOD, - SCC_GPIOE, - SCC_GPIOF, - SCC_GPIOG, - SCC_GPIOH, - SCC_GPIOJ, - SCC_GPIOK, - SCC_GPIOL, - SCC_GPIOM, - SCC_GPION, - SCC_GPIOP, - SCC_GPIOQ, - - SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5, - - SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, - - SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5, - SCC_UART1, - SCC_UART2, - SCC_UART3, - SCC_UART4, - SCC_UART5, - SCC_UART6, - SCC_UART7, - - SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5, - SCC_SSI1, - SCC_SSI2, - SCC_SSI3, - - SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5, - SCC_I2C1, - SCC_I2C2, - SCC_I2C3, - SCC_I2C4, - SCC_I2C5, - - SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5, - - SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5, - SCC_CAN1, - - SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5, - SCC_ADC1, - - SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5, - - SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5, - SCC_PWM1, - - SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5, - SCC_QEI1, - - SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5, - - SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5, - SCC_WTIMER1, - SCC_WTIMER2, - SCC_WTIMER3, - SCC_WTIMER4, - SCC_WTIMER5, - - /* - * Deep-sleep clock control - */ - DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5, - DCC_WD1, - - DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5, - DCC_TIMER1, - DCC_TIMER2, - DCC_TIMER3, - DCC_TIMER4, - DCC_TIMER5, - - DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, - DCC_GPIOB, - DCC_GPIOC, - DCC_GPIOD, - DCC_GPIOE, - DCC_GPIOF, - DCC_GPIOG, - DCC_GPIOH, - DCC_GPIOJ, - DCC_GPIOK, - DCC_GPIOL, - DCC_GPIOM, - DCC_GPION, - DCC_GPIOP, - DCC_GPIOQ, - - DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5, - - DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, - - DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5, - DCC_UART1, - DCC_UART2, - DCC_UART3, - DCC_UART4, - DCC_UART5, - DCC_UART6, - DCC_UART7, - - DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5, - DCC_SSI1, - DCC_SSI2, - DCC_SSI3, - - DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5, - DCC_I2C1, - DCC_I2C2, - DCC_I2C3, - DCC_I2C4, - DCC_I2C5, - - DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5, - - DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5, - DCC_CAN1, - - DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5, - DCC_ADC1, - - DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5, - - DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5, - DCC_PWM1, - - DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5, - DCC_QEI1, - - DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5, - - DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5, - DCC_WTIMER1, - DCC_WTIMER2, - DCC_WTIMER3, - DCC_WTIMER4, - DCC_WTIMER5, - -}; - -/* ============================================================================ - * Function prototypes - * --------------------------------------------------------------------------*/ -BEGIN_DECLS - -void periph_clock_enable(enum lm4f_clken periph); -void periph_clock_disable(enum lm4f_clken periph); - -END_DECLS - -/**@}*/ - -#endif /* LM4F_SYSTEMCONTROL_H */ - diff --git a/libopencm3/include/libopencm3/lm4f/timer.h b/libopencm3/include/libopencm3/lm4f/timer.h deleted file mode 100644 index ae90ca8..0000000 --- a/libopencm3/include/libopencm3/lm4f/timer.h +++ /dev/null @@ -1,99 +0,0 @@ -/** @defgroup timer_defines General Purpose Timers - * - * @brief Defined Constants and Types for the LM4F General Purpose Timers - * - * @ingroup LM4Fxx_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright 2018 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include -#include - -/**@{*/ - -/** @defgroup timer_registers GP Timer registers - * Unless otherwise specified, these registers are RW - *@{*/ - -/** Configuration */ -#define GPTMCFG(tim_base) MMIO32((tim_base) + 0) -/** Timer A mode */ -#define GPTMTAMR(tim_base) MMIO32((tim_base) + 0x4) -/** Timer B mode */ -#define GPTMTBMR(tim_base) MMIO32((tim_base) + 0x8) -/** Control */ -#define GPTMCTL(tim_base) MMIO32((tim_base) + 0xc) -/** Synchronize */ -#define GPTMSYNC(tim_base) MMIO32((tim_base) + 0x10) -/** Interrupt mask */ -#define GPTMIMR(tim_base) MMIO32((tim_base) + 0x18) -/** Raw interrupt status (RO) */ -#define GPTMRIS(tim_base) MMIO32((tim_base) + 0x1c) -/** Masked interrupt status (RO) */ -#define GPTMMIS(tim_base) MMIO32((tim_base) + 0x20) -/** Interrupt clear (W1C) */ -#define GPTMICR(tim_base) MMIO32((tim_base) + 0x24) -/** Timer A Interval load */ -#define GPTMTAILR(tim_base) MMIO32((tim_base) + 0x28) -/** Timer B Interval load */ -#define GPTMTBILR(tim_base) MMIO32((tim_base) + 0x2c) -/** Timer A match */ -#define GPTMTAMATCHR(tim_base) MMIO32((tim_base) + 0x30) -/** Timer B match */ -#define GPTMTBMATCHR(tim_base) MMIO32((tim_base) + 0x34) -/** Timer A prescale */ -#define GPTMTAPR(tim_base) MMIO32((tim_base) + 0x38) -/** Timer B prescale */ -#define GPTMTBPR(tim_base) MMIO32((tim_base) + 0x3c) -/** Timer A prescale match */ -#define GPTMTAPMR(tim_base) MMIO32((tim_base) + 0x40) -/** Timer A prescale match */ -#define GPTMTBPMR(tim_base) MMIO32((tim_base) + 0x44) -/* Timer A (RO) */ -#define GPTMTAR(tim_base) MMIO32((tim_base) + 0x48) -/* Timer B (RO) */ -#define GPTMTBR(tim_base) MMIO32((tim_base) + 0x4c) -/* Timer A value */ -#define GPTMTAV(tim_base) MMIO32((tim_base) + 0x50) -/* Timer B value */ -#define GPTMTBV(tim_base) MMIO32((tim_base) + 0x54) -/** RTC Predivide (RO) */ -#define GPTMRTCPD(tim_base) MMIO32((tim_base) + 0x58) -/** Timer A prescale snapshot (RO) */ -#define GPTMTAPS(tim_base) MMIO32((tim_base) + 0x5c) -/** Timer B prescale snapshot (RO) */ -#define GPTMTBPS(tim_base) MMIO32((tim_base) + 0x60) -/** Timer A prescale value (RO) */ -#define GPTMTAPV(tim_base) MMIO32((tim_base) + 0x64) -/** Timer B prescale value (RO) */ -#define GPTMTBPV(tim_base) MMIO32((tim_base) + 0x68) -/** Peripheral properties (RO) */ -#define GPTMPP(tim_base) MMIO32((tim_base) + 0xfc0) - -/**@}*/ - -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lm4f/uart.h b/libopencm3/include/libopencm3/lm4f/uart.h deleted file mode 100644 index f36556e..0000000 --- a/libopencm3/include/libopencm3/lm4f/uart.h +++ /dev/null @@ -1,550 +0,0 @@ -/** @defgroup uart_defines UART Control - * - * @brief Defined Constants and Types for the LM4F UART Control - * - * @ingroup LM4Fxx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Alexandru Gagniuc - * - * @date 07 May 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LM4F_UART_H -#define LIBOPENCM3_LM4F_UART_H - -/**@{*/ - -#include -#include - -/* ============================================================================= - * Convenience macros - * ---------------------------------------------------------------------------*/ -/** @defgroup uart_reg_base UART register base addresses - * @{*/ -#define UART0 UART0_BASE -#define UART1 UART1_BASE -#define UART2 UART2_BASE -#define UART3 UART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -#define UART6 UART6_BASE -#define UART7 UART7_BASE -/** @} */ - -/* ============================================================================= - * UART registers - * ---------------------------------------------------------------------------*/ - -/* UART data register */ -#define UART_DR(uart_base) MMIO32((uart_base) + 0x00) - -/* UART Receive Status/Error Clear register */ -#define UART_RSR(uart_base) MMIO32((uart_base) + 0x04) -#define UART_ECR(uart_base) MMIO32((uart_base) + 0x04) - -/* UART Flag register */ -#define UART_FR(uart_base) MMIO32((uart_base) + 0x18) - -/* UART IrDA Low-Power register */ -#define UART_ILPR(uart_base) MMIO32((uart_base) + 0x20) - -/* UART Integer baudrate divisor */ -#define UART_IBRD(uart_base) MMIO32((uart_base) + 0x24) - -/* UART Fractional baudrate divisor */ -#define UART_FBRD(uart_base) MMIO32((uart_base) + 0x28) - -/* UART Line control */ -#define UART_LCRH(uart_base) MMIO32((uart_base) + 0x2C) - -/* UART Control */ -#define UART_CTL(uart_base) MMIO32((uart_base) + 0x30) - -/* UART Interrupt FIFO level select */ -#define UART_IFLS(uart_base) MMIO32((uart_base) + 0x34) - -/* UART Interrupt mask */ -#define UART_IM(uart_base) MMIO32((uart_base) + 0x38) - -/* UART Raw interrupt status */ -#define UART_RIS(uart_base) MMIO32((uart_base) + 0x3C) - -/* UART Masked Interrupt status */ -#define UART_MIS(uart_base) MMIO32((uart_base) + 0x40) - -/* UART Interrupt Clear */ -#define UART_ICR(uart_base) MMIO32((uart_base) + 0x44) - -/* UART DMA control */ -#define UART_DMACTL(uart_base) MMIO32((uart_base) + 0x48) - -/* UART LIN control */ -#define UART_LCTL(uart_base) MMIO32((uart_base) + 0x90) - -/* UART LIN snap shot */ -#define UART_LSS(uart_base) MMIO32((uart_base) + 0x94) - -/* UART LIN timer */ -#define UART_LTIM(uart_base) MMIO32((uart_base) + 0x98) - -/* UART 9-Bit self address */ -#define UART_9BITADDR(uart_base) MMIO32((uart_base) + 0xA4) - -/* UART 9-Bit self address mask */ -#define UART_9BITAMASK(uart_base) MMIO32((uart_base) + 0xA8) - -/* UART Peripheral properties */ -#define UART_PP(uart_base) MMIO32((uart_base) + 0xFC0) - -/* UART Clock configuration */ -#define UART_CC(uart_base) MMIO32((uart_base) + 0xFC8) - -/* UART Peripheral Identification 4 */ -#define UART_PERIPH_ID4(uart_base) MMIO32((uart_base) + 0xFD0) - -/* UART Peripheral Identification 5 */ -#define UART_PERIPH_ID5(uart_base) MMIO32((uart_base) + 0xFD4) - -/* UART Peripheral Identification 6 */ -#define UART_PERIPH_ID6(uart_base) MMIO32((uart_base) + 0xFD8) - -/* UART Peripheral Identification 7 */ -#define UART_PERIPH_ID7(uart_base) MMIO32((uart_base) + 0xFDC) - -/* UART Peripheral Identification 0 */ -#define UART_PERIPH_ID0(uart_base) MMIO32((uart_base) + 0xFE0) - -/* UART Peripheral Identification 1 */ -#define UART_PERIPH_ID1(uart_base) MMIO32((uart_base) + 0xFE4) - -/* UART Peripheral Identification 2 */ -#define UART_PERIPH_ID2(uart_base) MMIO32((uart_base) + 0xFE8) - -/* UART Peripheral Identification 3 */ -#define UART_PERIPH_ID3(uart_base) MMIO32((uart_base) + 0xFEC) - -/* UART PrimeCell Identification 0 */ -#define UART_PCELL_ID0(uart_base) MMIO32((uart_base) + 0xFF0) - -/* UART PrimeCell Identification 1 */ -#define UART_PCELL_ID1(uart_base) MMIO32((uart_base) + 0xFF4) - -/* UART PrimeCell Identification 2 */ -#define UART_PCELL_ID2(uart_base) MMIO32((uart_base) + 0xFF8) - -/* UART PrimeCell Identification 3 */ -#define UART_PCELL_ID3(uart_base) MMIO32((uart_base) + 0xFFC) - - -/* ============================================================================= - * UART_DR values - * ---------------------------------------------------------------------------*/ -/** Overrun Error */ -#define UART_DR_OE (1 << 11) -/** Break Error */ -#define UART_DR_BE (1 << 10) -/** Parity Error */ -#define UART_DR_PE (1 << 9) -/** Framing Error */ -#define UART_DR_FE (1 << 8) -/** Data transmitted or received */ -#define UART_DR_DATA_MASK (0xFF << 0) - -/* ============================================================================= - * Readonly UART_RSR values - * ---------------------------------------------------------------------------*/ -/** Overrun Error */ -#define UART_RSR_OE (1 << 3) -/** Break Error */ -#define UART_RSR_BE (1 << 2) -/** Parity Error */ -#define UART_RSR_PE (1 << 1) -/** Framing Error */ -#define UART_RSR_FE (1 << 0) - -/* ============================================================================= - * UART_FR values - * ---------------------------------------------------------------------------*/ -/** Tx FIFO empty */ -#define UART_FR_TXFE (1 << 7) -/** Rx FIFO full */ -#define UART_FR_RXFF (1 << 6) -/** Tx FIFO full */ -#define UART_FR_TXFF (1 << 5) -/** Rx FIFO empty */ -#define UART_FR_RXFE (1 << 4) -/** UART Busy */ -#define UART_FR_BUSY (1 << 3) -/** Clear To Send */ -#define UART_FR_CTS (1 << 0) - -/* ============================================================================= - * UART_LCRH values - * ---------------------------------------------------------------------------*/ -/** Stick parity select */ -#define UART_LCRH_SPS (1 << 7) -/** Word length */ -#define UART_LCRH_WLEN_MASK (3 << 5) -#define UART_LCRH_WLEN_5 (0 << 5) -#define UART_LCRH_WLEN_6 (1 << 5) -#define UART_LCRH_WLEN_7 (2 << 5) -#define UART_LCRH_WLEN_8 (3 << 5) -/** Enable FIFOs */ -#define UART_LCRH_FEN (1 << 4) -/** Two stop bits select */ -#define UART_LCRH_STP2 (1 << 3) -/** Even parity select */ -#define UART_LCRH_EPS (1 << 2) -/** Parity enable */ -#define UART_LCRH_PEN (1 << 1) -/** Send break */ -#define UART_LCRH_BRK (1 << 0) - -/* ============================================================================= - * UART_CTL values - * ---------------------------------------------------------------------------*/ -/** Enable Clear To Send */ -#define UART_CTL_CTSEN (1 << 15) -/** Enable Request To Send */ -#define UART_CTL_RTSEN (1 << 14) -/** Request To Send */ -#define UART_CTL_RTS (1 << 11) -/** Data terminal ready */ -#define UART_CTL_DTR (1 << 10) -/** Rx Enable */ -#define UART_CTL_RXE (1 << 9) -/** Tx Enable */ -#define UART_CTL_TXE (1 << 8) -/** Loop back enable */ -#define UART_CTL_LBE (1 << 7) -/** LIN mode enable */ -#define UART_CTL_LIN (1 << 6) -/** High speed Enable */ -#define UART_CTL_HSE (1 << 5) -/** End of transmission */ -#define UART_CTL_EOT (1 << 4) -/** ISO 7816 Smart Card support */ -#define UART_CTL_SMART (1 << 3) -/** SIR low-power mode */ -#define UART_CTL_SIRLIP (1 << 2) -/** SIR enable */ -#define UART_CTL_SIREN (1 << 1) -/** UART enable */ -#define UART_CTL_UARTEN (1 << 0) - -/* ============================================================================= - * UART_IFLS values - * ---------------------------------------------------------------------------*/ -/** UART Rx interrupt FIFO level select */ -#define UART_IFLS_RXIFLSEL_MASK (7 << 3) -#define UART_IFLS_RXIFLSEL_1_8 (0 << 3) -#define UART_IFLS_RXIFLSEL_1_4 (1 << 3) -#define UART_IFLS_RXIFLSEL_1_2 (2 << 3) -#define UART_IFLS_RXIFLSEL_3_4 (3 << 3) -#define UART_IFLS_RXIFLSEL_7_8 (4 << 3) -/** UART Tx interrupt FIFO level select */ -#define UART_IFLS_TXIFLSEL_MASK (7 << 0) -#define UART_IFLS_TXIFLSEL_7_8 (0 << 0) -#define UART_IFLS_TXIFLSEL_3_4 (1 << 0) -#define UART_IFLS_TXIFLSEL_1_2 (2 << 0) -#define UART_IFLS_TXIFLSEL_1_4 (3 << 0) -#define UART_IFLS_TXIFLSEL_1_8 (4 << 0) - -/* ============================================================================= - * UART interrupt mask values - * - * These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR - * registers. - * ---------------------------------------------------------------------------*/ -/** LIN mode edge 5 interrupt mask */ -#define UART_IM_LME5IM (1 << 15) -/** LIN mode edge 1 interrupt mask */ -#define UART_IM_LME1IM (1 << 14) -/** LIN mode sync break interrupt mask */ -#define UART_IM_LMSBIM (1 << 13) -/** 9-bit mode interrupt mask */ -#define UART_IM_9BITIM (1 << 12) -/** Overrun error interrupt mask */ -#define UART_IM_OEIM (1 << 10) -/** Break error interrupt mask */ -#define UART_IM_BEIM (1 << 9) -/** Parity error interrupt mask */ -#define UART_IM_PEIM (1 << 8) -/** Framing error interrupt mask */ -#define UART_IM_FEIM (1 << 7) -/** Receive time-out interrupt mask */ -#define UART_IM_RTIM (1 << 6) -/** Transmit interrupt mask */ -#define UART_IM_TXIM (1 << 5) -/** Receive interrupt mask */ -#define UART_IM_RXIM (1 << 4) -/** Data Set Ready modem interrupt mask */ -#define UART_IM_DSRIM (1 << 3) -/** Data Carrier Detect modem interrupt mask */ -#define UART_IM_DCDIM (1 << 2) -/** Clear To Send modem interrupt mask */ -#define UART_IM_CTSIM (1 << 1) -/** Ring Indicator modem interrupt mask */ -#define UART_IM_RIIM (1 << 0) - -/* ============================================================================= - * UART_DMACTL values - * ---------------------------------------------------------------------------*/ -/** DMA on error */ -#define UART_DMACTL_DMAERR (1 << 2) -/** Transmit DMA enable */ -#define UART_DMACTL_TXDMAE (1 << 1) -/** Receive DMA enable */ -#define UART_DMACTL_RXDMAE (1 << 0) - -/* ============================================================================= - * UART_LCTL values - * ---------------------------------------------------------------------------*/ -/** Sync break length */ -#define UART_LCTL_BLEN_MASK (3 << 4) -#define UART_LCTL_BLEN_16T (3 << 4) -#define UART_LCTL_BLEN_15T (2 << 4) -#define UART_LCTL_BLEN_14T (1 << 4) -#define UART_LCTL_BLEN_13T (0 << 4) -/** LIN master enable */ -#define UART_LCTL_MASTER (1 << 0) - -/* ============================================================================= - * UART_9BITADDR values - * ---------------------------------------------------------------------------*/ -/** Enable 9-bit mode */ -#define UART_UART_9BITADDR_9BITEN (1 << 15) -/** Self-address for 9-bit mode */ -#define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0) - -/* ============================================================================= - * UART_PP values - * ---------------------------------------------------------------------------*/ -/** 9-bit support */ -#define UART_UART_PP_NB (1 << 1) -/** Smart Card support */ -#define UART_UART_PP_SC (1 << 0) - -/* ============================================================================= - * UART_CC values - * ---------------------------------------------------------------------------*/ -/** UART baud clock source */ -#define UART_CC_CS_MASK (0xF << 0) -#define UART_CC_CS_SYSCLK (0x0 << 0) -#define UART_CC_CS_PIOSC (0x5 << 0) - -/* ============================================================================= - * Convenience enums - * ---------------------------------------------------------------------------*/ -enum uart_parity { - UART_PARITY_NONE, - UART_PARITY_ODD, - UART_PARITY_EVEN, - UART_PARITY_STICK_0, - UART_PARITY_STICK_1, -}; - -enum uart_flowctl { - UART_FLOWCTL_NONE, - UART_FLOWCTL_RTS, - UART_FLOWCTL_CTS, - UART_FLOWCTL_RTS_CTS, -}; - -/** - * \brief UART interrupt masks - * - * These masks can be OR'ed together to specify more than one interrupt. For - * example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt. - */ -enum uart_interrupt_flag { - - UART_INT_LME5 = UART_IM_LME5IM, - UART_INT_LME1 = UART_IM_LME1IM, - UART_INT_LMSB = UART_IM_LMSBIM, - UART_INT_9BIT = UART_IM_9BITIM, - UART_INT_OE = UART_IM_OEIM, - UART_INT_BE = UART_IM_BEIM, - UART_INT_PE = UART_IM_PEIM, - UART_INT_FE = UART_IM_FEIM, - UART_INT_RT = UART_IM_RTIM, - UART_INT_TX = UART_IM_TXIM, - UART_INT_RX = UART_IM_RXIM, - UART_INT_DSR = UART_IM_DSRIM, - UART_INT_DCD = UART_IM_DCDIM, - UART_INT_CTS = UART_IM_CTSIM, - UART_INT_RI = UART_IM_RIIM, -}; - -/** - * \brief UART RX FIFO interrupt trigger levels - * - * The levels indicate how full the FIFO should be before an interrupt is - * generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when - * the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being - * triggered by a single character. - */ -enum uart_fifo_rx_trigger_level { - UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8, - UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4, - UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2, - UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4, - UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8 -}; - -/** - * \brief UART TX FIFO interrupt trigger levels - * - * The levels indicate how empty the FIFO should be before an interrupt is - * generated. Note that this indicates the emptiness of the FIFO and not the - * fullness. This is somewhat confusing, but it follows the wording of the - * LM4F120H5QR datasheet. - * - * UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is - * 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered - * by a single character. - */ -enum uart_fifo_tx_trigger_level { - UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8, - UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4, - UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2, - UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4, - UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8 -}; - -/* ============================================================================= - * Function prototypes - * ---------------------------------------------------------------------------*/ -BEGIN_DECLS - -void uart_set_baudrate(uint32_t uart, uint32_t baud); -void uart_set_databits(uint32_t uart, uint8_t databits); -void uart_set_stopbits(uint32_t uart, uint8_t stopbits); -void uart_set_parity(uint32_t uart, enum uart_parity parity); -void uart_set_mode(uint32_t uart, uint32_t mode); -void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow); -void uart_enable(uint32_t uart); -void uart_disable(uint32_t uart); -void uart_clock_from_piosc(uint32_t uart); -void uart_clock_from_sysclk(uint32_t uart); - -void uart_send(uint32_t uart, uint16_t data); -uint16_t uart_recv(uint32_t uart); -void uart_wait_send_ready(uint32_t uart); -void uart_wait_recv_ready(uint32_t uart); -void uart_send_blocking(uint32_t uart, uint16_t data); -uint16_t uart_recv_blocking(uint32_t uart); - -void uart_enable_rx_dma(uint32_t uart); -void uart_disable_rx_dma(uint32_t uart); -void uart_enable_tx_dma(uint32_t uart); -void uart_disable_tx_dma(uint32_t uart); - -void uart_enable_fifo(uint32_t uart); -void uart_disable_fifo(uint32_t uart); -void uart_set_fifo_trigger_levels(uint32_t uart, - enum uart_fifo_rx_trigger_level rx_level, - enum uart_fifo_tx_trigger_level tx_level); - -/* We inline FIFO full/empty checks as they are intended to be called from ISRs - * */ -/** @ingroup uart_fifo - * @{ - * \brief Determine if the TX fifo is full - * - * @param[in] uart UART block register address base @ref uart_reg_base - */ -static inline -bool uart_is_tx_fifo_full(uint32_t uart) -{ - return UART_FR(uart) & UART_FR_TXFF; -} - - -/** - * \brief Determine if the TX fifo is empty - * - * @param[in] uart UART block register address base @ref uart_reg_base - */ -static inline -bool uart_is_tx_fifo_empty(uint32_t uart) -{ - return UART_FR(uart) & UART_FR_TXFE; -} - -/** - * \brief Determine if the RX fifo is full - * - * @param[in] uart UART block register address base @ref uart_reg_base - */ -static inline -bool uart_is_rx_fifo_full(uint32_t uart) -{ - return UART_FR(uart) & UART_FR_RXFF; -} - -/** - * \brief Determine if the RX fifo is empty - * - * @param[in] uart UART block register address base @ref uart_reg_base - */ -static inline -bool uart_is_rx_fifo_empty(uint32_t uart) -{ - return UART_FR(uart) & UART_FR_RXFE; -} -/**@}*/ - -void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); -void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); -void uart_enable_rx_interrupt(uint32_t uart); -void uart_disable_rx_interrupt(uint32_t uart); -void uart_enable_tx_interrupt(uint32_t uart); -void uart_disable_tx_interrupt(uint32_t uart); -void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints); - -/* Let's keep this one inlined. It's designed to be used in ISRs */ -/** @ingroup uart_irq - * @{ - * \brief Determine if interrupt is generated by the given source - * - * @param[in] uart UART block register address base @ref uart_reg_base - * @param[in] source source to check. - */ -static inline -bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source) -{ - return UART_MIS(uart) & source; -} -/**@}*/ - -END_DECLS - -/**@}*/ - -#endif /* LIBOPENCM3_LM4F_UART_H */ diff --git a/libopencm3/include/libopencm3/lm4f/usb.h b/libopencm3/include/libopencm3/lm4f/usb.h deleted file mode 100644 index 0463d4b..0000000 --- a/libopencm3/include/libopencm3/lm4f/usb.h +++ /dev/null @@ -1,422 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @defgroup usb_defines USB Controller - * - * @brief Defined Constants and Types for the LM4F USB Controller - * - * @ingroup LM4Fxx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc - * - * @date 15 May 2013 - * - * LGPL License Terms @ref lgpl_license - */ - - -#ifndef LIBOPENCM3_LM4F_USB_H -#define LIBOPENCM3_LM4F_USB_H - -/**@{*/ - -#include -#include - -/* ============================================================================ - * USB registers - * --------------------------------------------------------------------------*/ - -/* USB Device Functional Address */ -#define USB_FADDR MMIO8(USB_BASE + 0x00) - -/* USB Power */ -#define USB_POWER MMIO8(USB_BASE + 0x01) - -/* USB Transmit Interrupt Status */ -#define USB_TXIS MMIO16(USB_BASE + 0x02) - -/* USB Receive Interrupt Status */ -#define USB_RXIS MMIO16(USB_BASE + 0x04) - -/* USB Transmit Interrupt Enable */ -#define USB_TXIE MMIO16(USB_BASE + 0x06) - -/* USB Receive Interrupt Enable */ -#define USB_RXIE MMIO16(USB_BASE + 0x08) - -/* USB General Interrupt Status */ -#define USB_IS MMIO8(USB_BASE + 0x0A) - -/* USB Interrupt Enable */ -#define USB_IE MMIO8(USB_BASE + 0x0B) - -/* USB Frame Value */ -#define USB_FRAME MMIO16(USB_BASE + 0x0C) - -/* USB Endpoint Index */ -#define USB_EPIDX MMIO8(USB_BASE + 0x0E) - -/* USB Test Mode */ -#define USB_TEST MMIO8(USB_BASE + 0x0F) - -/* USB FIFO Endpoint [0-7] */ -#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + (n)*0x04) -#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + (n)*0x04) -#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + (n)*0x04) - -/* USB Transmit Dynamic FIFO Sizing */ -#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62) - -/* USB Receive Dynamic FIFO Sizing */ -#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63) - -/* USB Transmit FIFO Start Address */ -#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64) - -/* USB Receive FIFO Start Address */ -#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66) - -/* USB Connect Timing */ -#define USB_CONTIM MMIO8(USB_BASE + 0x7A) - -/* USB Full-Speed Last Transaction to End of Frame Timing */ -#define USB_FSEOF MMIO8(USB_BASE + 0x7D) - -/* USB Low-Speed Last Transaction to End of Frame Timing */ -#define USB_LSEOF MMIO8(USB_BASE + 0x7E) - -/* USB Control and Status Endpoint 0 Low */ -#define USB_CSRL0 MMIO8(USB_BASE + 0x102) - -/* USB Control and Status Endpoint 0 High */ -#define USB_CSRH0 MMIO8(USB_BASE + 0x103) - -/* USB Receive Byte Count Endpoint 0 */ -#define USB_COUNT0 MMIO8(USB_BASE + 0x108) - -/* USB Maximum Transmit Data Endpoint [1-7] */ -#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + (n)*0x10) - -/* USB Transmit Control and Status Endpoint [1-7] Low */ -#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + (n)*0x10) - -/* USB Transmit Control and Status Endpoint [1-7] High */ -#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + (n)*0x10) - -/* USB Maximum Receive Data Endpoint [1-7] */ -#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + (n)*0x10) - -/* USB Receive Control and Status Endpoint [1-7] Low */ -#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + (n)*0x10) - -/* USB Receive Control and Status Endpoint [1-7] High */ -#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + (n)*0x10) - -/* USB Receive Byte Count Endpoint [1-7] */ -#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + (n)*0x10) - -/* USB Receive Double Packet Buffer Disable */ -#define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340) - -/* USB Transmit Double Packet Buffer Disable */ -#define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342) - -/* USB Device RESUME Raw Interrupt Status */ -#define USB_DRRIS MMIO32(USB_BASE + 0x410) - -/* USB Device RESUME Interrupt Mask */ -#define USB_DRIM MMIO32(USB_BASE + 0x414) - -/* USB Device RESUME Interrupt Status and Clear */ -#define USB_DRISC MMIO32(USB_BASE + 0x418) - -/* USB DMA Select */ -#define USB_DMASEL MMIO32(USB_BASE + 0x450) - -/* USB Peripheral Properties */ -#define USB_PP MMIO32(USB_BASE + 0xFC0) - - -/* ============================================================================= - * USB_FADDR values - * ---------------------------------------------------------------------------*/ -/** Function Address */ -#define USB_FADDR_FUNCADDR_MASK (0x3f << 0) - -/* ============================================================================= - * USB_POWER values - * ---------------------------------------------------------------------------*/ -/** Isochronous Update */ -#define USB_POWER_ISOUP (1 << 7) -/** Soft Connect/Disconnect */ -#define USB_POWER_SOFTCONN (1 << 6) -/** RESET signaling */ -#define USB_POWER_RESET (1 << 3) -/** RESUME signaling */ -#define USB_POWER_RESUME (1 << 2) -/** SUSPEND mode */ -#define USB_POWER_SUSPEND (1 << 1) -/** Power down PHY */ -#define USB_POWER_PWRDNPHY (1 << 0) - -/* ============================================================================= - * Endpoint bitmasks for interrupt status and control registers - * Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS, - * USB_TXDPKTBUFDIS - * ---------------------------------------------------------------------------*/ -#define USB_EP7 (1 << 7) -#define USB_EP6 (1 << 6) -#define USB_EP5 (1 << 5) -#define USB_EP4 (1 << 4) -#define USB_EP3 (1 << 3) -#define USB_EP2 (1 << 2) -#define USB_EP1 (1 << 1) -#define USB_EP0 (1 << 0) - -/* ============================================================================= - * USB interrupt mask values - * - * These are interchangeable across USB_IS, and USB_IE registers. - * ---------------------------------------------------------------------------*/ -/** USB disconnect interrupt */ -#define USB_IM_DISCON (1 << 5) -/** Start of frame */ -#define USB_IM_SOF (1 << 3) -/** RESET signaling detected */ -#define USB_IM_RESET (1 << 2) -/** RESUME signaling detected */ -#define USB_IM_RESUME (1 << 1) -/** SUSPEND signaling detected */ -#define USB_IM_SUSPEND (1 << 0) - -/* ============================================================================= - * USB_FRAME values - * ---------------------------------------------------------------------------*/ -/** Frame number */ -#define USB_FRAME_MASK (0x03FF) - -/* ============================================================================= - * USB_IDX values - * ---------------------------------------------------------------------------*/ -/** Endpoint Index */ -#define USB_EPIDX_MASK (0x0F) - -/* ============================================================================= - * USB_TEST values - * ---------------------------------------------------------------------------*/ -/** FIFO access */ -#define USB_TEST_FIFOACC (1 << 6) -/** Force full-speed mode */ -#define USB_TEST_FORCEFS (1 << 5) - -/* ============================================================================= - * USB_TXFIFOSZ and USB_RXFIFOSZ values - * ---------------------------------------------------------------------------*/ -/** Double packet buffer support */ -#define USB_FIFOSZ_DPB (1 << 4) -/* USB Transmit Dynamic FIFO Sizing */ -#define USB_FIFOSZ_SIZE_MASK (0x0F << 0) -#define USB_FIFOSZ_SIZE_8 (0x00 << 0) -#define USB_FIFOSZ_SIZE_16 (0x01 << 0) -#define USB_FIFOSZ_SIZE_32 (0x02 << 0) -#define USB_FIFOSZ_SIZE_64 (0x03 << 0) -#define USB_FIFOSZ_SIZE_128 (0x04 << 0) -#define USB_FIFOSZ_SIZE_256 (0x05 << 0) -#define USB_FIFOSZ_SIZE_512 (0x06 << 0) -#define USB_FIFOSZ_SIZE_1024 (0x07 << 0) -#define USB_FIFOSZ_SIZE_2048 (0x08 << 0) - - -/* ============================================================================= - * USB_CONTIM values - * ---------------------------------------------------------------------------*/ -/** Connect wait */ -#define USB_CONTIM_WTCON_MASK (0x0F << 4) -/** Wait ID */ -#define USB_CONTIM_WTID_MASK (0x0F << 0) - -/* ============================================================================= - * USB_CSRL0 values - * ---------------------------------------------------------------------------*/ -/** Setup End Clear */ -#define USB_CSRL0_SETENDC (1 << 7) -/** RXRDY Clear */ -#define USB_CSRL0_RXRDYC (1 << 6) -/** Send Stall */ -#define USB_CSRL0_STALL (1 << 5) -/** Setup End */ -#define USB_CSRL0_SETEND (1 << 4) -/** Data End */ -#define USB_CSRL0_DATAEND (1 << 3) -/** Endpoint Stalled */ -#define USB_CSRL0_STALLED (1 << 2) -/** Transmit Packet Ready */ -#define USB_CSRL0_TXRDY (1 << 1) -/** Receive Packet Ready */ -#define USB_CSRL0_RXRDY (1 << 0) - -/* ============================================================================= - * USB_CSRH0 values - * ---------------------------------------------------------------------------*/ -/** Flush FIFO */ -#define USB_CSRH0_FLUSH (1 << 0) - -/* ============================================================================= - * USB_TXCSRLx values - * ---------------------------------------------------------------------------*/ -/** Clear data toggle */ -#define USB_TXCSRL_CLRDT (1 << 6) -/** Endpoint Stalled */ -#define USB_TXCSRL_STALLED (1 << 5) -/** Send Stall */ -#define USB_TXCSRL_STALL (1 << 4) -/** Flush FIFO */ -#define USB_TXCSRL_FLUSH (1 << 3) -/** Underrun */ -#define USB_TXCSRL_UNDRN (1 << 2) -/** FIFO not empty */ -#define USB_TXCSRL_FIFONE (1 << 1) -/** Transmit Packet Ready */ -#define USB_TXCSRL_TXRDY (1 << 0) - -/* ============================================================================= - * USB_TXCSRHx values - * ---------------------------------------------------------------------------*/ -/** Auto set */ -#define USB_TXCSRH_AUTOSET (1 << 7) -/** Isochronous transfers */ -#define USB_TXCSRH_ISO (1 << 6) -/** Mode */ -#define USB_TXCSRH_MODE (1 << 5) -/** DMA request enable */ -#define USB_TXCSRH_DMAEN (1 << 4) -/** Force data toggle */ -#define USB_TXCSRH_FDT (1 << 3) -/** DMA request mode */ -#define USB_TXCSRH_DMAMOD (1 << 2) - -/* ============================================================================= - * USB_RXCSRLx values - * ---------------------------------------------------------------------------*/ -/** Clear data toggle */ -#define USB_RXCSRL_CLRDT (1 << 7) -/** Endpoint Stalled */ -#define USB_RXCSRL_STALLED (1 << 6) -/** Send Stall */ -#define USB_RXCSRL_STALL (1 << 5) -/** Flush FIFO */ -#define USB_RXCSRL_FLUSH (1 << 4) -/** Data error */ -#define USB_RXCSRL_DATAERR (1 << 2) -/** Overrun */ -#define USB_RXCSRL_OVER (1 << 2) -/** FIFO full */ -#define USB_RXCSRL_FULL (1 << 1) -/** Receive Packet Ready */ -#define USB_RXCSRL_RXRDY (1 << 0) - -/* ============================================================================= - * USB_RXCSRHx values - * ---------------------------------------------------------------------------*/ -/** Auto clear */ -#define USB_RXCSRH_AUTOCL (1 << 7) -/** Isochronous transfers */ -#define USB_RXCSRH_ISO (1 << 6) -/** DMA request enable */ -#define USB_RXCSRH_DMAEN (1 << 5) -/** Disable NYET / PID error */ -#define USB_RXCSRH_PIDERR (1 << 4) -/** DMA request mode */ -#define USB_RXCSRH_DMAMOD (1 << 3) - -/* ============================================================================= - * USB_DRRIS values - * ---------------------------------------------------------------------------*/ -/** RESUME interrupt status */ -#define USB_DRRIS_RESUME (1 << 0) - -/* ============================================================================= - * USB_DRIM values - * ---------------------------------------------------------------------------*/ -/** RESUME interrupt mask */ -#define USB_DRIM_RESUME (1 << 0) - -/* ============================================================================= - * USB_DRISC values - * ---------------------------------------------------------------------------*/ -/** RESUME interrupt status and clear */ -#define USB_DRISC_RESUME (1 << 0) - -/* ============================================================================= - * USB_PP values - * ---------------------------------------------------------------------------*/ -/** Endpoint count */ -#define USB_PP_ECNT_MASK (0xFF << 8) -/** USB capability */ -#define USB_PP_USB_MASK (0x03 << 6) -#define USB_PP_USB_NA (0x00 << 6) -#define USB_PP_USB_DEVICE (0x01 << 6) -#define USB_PP_USB_HOST (0x02 << 6) -#define USB_PP_USB_OTG (0x03 << 6) -/** PHY present */ -#define USB_PP_PHY (1 << 4) -/** Controller type */ -#define USB_PP_TYPE_MASK (0x0F << 0) - -/* ============================================================================= - * Convenience enums - * ---------------------------------------------------------------------------*/ -enum usb_interrupt { - USB_INT_DISCON = USB_IM_DISCON, - USB_INT_SOF = USB_IM_SOF, - USB_INT_RESET = USB_IM_RESET, - USB_INT_RESUME = USB_IM_RESUME, - USB_INT_SUSPEND = USB_IM_SUSPEND, -}; - -enum usb_ep_interrupt { - USB_EP0_INT = USB_EP0, - USB_EP1_INT = USB_EP1, - USB_EP2_INT = USB_EP2, - USB_EP3_INT = USB_EP3, - USB_EP4_INT = USB_EP4, - USB_EP5_INT = USB_EP5, - USB_EP6_INT = USB_EP6, - USB_EP7_INT = USB_EP7, -}; -/* ============================================================================= - * Function prototypes - * ---------------------------------------------------------------------------*/ -BEGIN_DECLS - -void usb_enable_interrupts(enum usb_interrupt ints, - enum usb_ep_interrupt rx_ints, - enum usb_ep_interrupt tx_ints); -void usb_disable_interrupts(enum usb_interrupt ints, - enum usb_ep_interrupt rx_ints, - enum usb_ep_interrupt tx_ints); - -END_DECLS - -/**@}*/ - -#endif /* LIBOPENCM3_LM4F_USB_H */ diff --git a/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h b/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h deleted file mode 100644 index 963ec0a..0000000 --- a/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 LPC13xx - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for NXP Semiconductors LPC13xx Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC13xx LPC13xx -Libraries for NXP Semiconductors LPC13xx series. - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC13xx_defines LPC13xx Defines - -@brief Defined Constants and Types for the LPC13xx series - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/lpc13xx/gpio.h b/libopencm3/include/libopencm3/lpc13xx/gpio.h deleted file mode 100644 index f827eca..0000000 --- a/libopencm3/include/libopencm3/lpc13xx/gpio.h +++ /dev/null @@ -1,124 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the LPC13xx General Purpose I/O - -@ingroup LPC13xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LPC13XX_GPIO_H -#define LPC13XX_GPIO_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIO0 GPIO_PIO0_BASE -#define GPIO1 GPIO_PIO1_BASE -#define GPIO2 GPIO_PIO2_BASE -#define GPIO3 GPIO_PIO3_BASE - -/* --- GPIO registers ------------------------------------------------------ */ - -/* GPIO data register (GPIOn_DATA) */ -#define GPIO_DATA(port) MMIO32((port) + 0x3ffc) -#define GPIO0_DATA GPIO_DATA(GPIO0) -#define GPIO1_DATA GPIO_DATA(GPIO1) -#define GPIO2_DATA GPIO_DATA(GPIO2) -#define GPIO3_DATA GPIO_DATA(GPIO3) - -/* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32((port) + 0x00) -#define GPIO0_DIR GPIO_DIR(GPIO0) -#define GPIO1_DIR GPIO_DIR(GPIO1) -#define GPIO2_DIR GPIO_DIR(GPIO2) -#define GPIO3_DIR GPIO_DIR(GPIO3) - -/* GPIO interrupt sense register (GPIOn_IS) */ -#define GPIO_IS(port) MMIO32((port) + 0x04) -#define GPIO0_IS GPIO_IS(GPIO0) -#define GPIO1_IS GPIO_IS(GPIO1) -#define GPIO2_IS GPIO_IS(GPIO2) -#define GPIO3_IS GPIO_IS(GPIO3) - -/* GPIO interrupt both edges sense register (GPIOn_IBE) */ -#define GPIO_IBE(port) MMIO32((port) + 0x08) -#define GPIO0_IBE GPIO_IBE(GPIO0) -#define GPIO1_IBE GPIO_IBE(GPIO1) -#define GPIO2_IBE GPIO_IBE(GPIO2) -#define GPIO3_IBE GPIO_IBE(GPIO3) - -/* GPIO interrupt event register (GPIOn_IEV) */ -#define GPIO_IEV(port) MMIO32((port) + 0x0c) -#define GPIO0_IEV GPIO_IEV(GPIO0) -#define GPIO1_IEV GPIO_IEV(GPIO1) -#define GPIO2_IEV GPIO_IEV(GPIO2) -#define GPIO3_IEV GPIO_IEV(GPIO3) - -/* GPIO interrupt mask register (GPIOn_IE) */ -#define GPIO_IE(port) MMIO16((port) + 0x10) -#define GPIO0_IE GPIO_IE(GPIO0) -#define GPIO1_IE GPIO_IE(GPIO1) -#define GPIO2_IE GPIO_IE(GPIO2) -#define GPIO3_IE GPIO_IE(GPIO3) - -/* FIXME: IRS or RIS? Datasheet is not consistent here. */ -/* GPIO raw interrupt status register (GPIOn_IRS) */ -#define GPIO_IRS(port) MMIO16((port) + 0x14) -#define GPIO0_IRS GPIO_IRS(GPIO0) -#define GPIO1_IRS GPIO_IRS(GPIO1) -#define GPIO2_IRS GPIO_IRS(GPIO2) -#define GPIO3_IRS GPIO_IRS(GPIO3) - -/* GPIO masked interrupt status register (GPIOn_MIS) */ -#define GPIO_MIS(port) MMIO16((port) + 0x18) -#define GPIO0_MIS GPIO_MIS(GPIO0) -#define GPIO1_MIS GPIO_MIS(GPIO1) -#define GPIO2_MIS GPIO_MIS(GPIO2) -#define GPIO3_MIS GPIO_MIS(GPIO3) - -/* GPIO interrupt clear register (GPIOn_IC) */ -#define GPIO_IC(port) MMIO16((port) + 0x1c) -#define GPIO0_IC GPIO_IC(GPIO0) -#define GPIO1_IC GPIO_IC(GPIO1) -#define GPIO2_IC GPIO_IC(GPIO2) -#define GPIO3_IC GPIO_IC(GPIO3) - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint16_t gpios); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc13xx/irq.json b/libopencm3/include/libopencm3/lpc13xx/irq.json deleted file mode 100644 index d9ac31f..0000000 --- a/libopencm3/include/libopencm3/lpc13xx/irq.json +++ /dev/null @@ -1,63 +0,0 @@ -{ - "irqs": { - "0": "pio0_0", - "1": "pio0_1", - "2": "pio0_2", - "3": "pio0_3", - "4": "pio0_4", - "5": "pio0_5", - "6": "pio0_6", - "7": "pio0_7", - "8": "pio0_8", - "9": "pio0_9", - "10": "pio0_10", - "11": "pio0_11", - "12": "pio1_0", - "13": "pio1_1", - "14": "pio1_2", - "15": "pio1_3", - "16": "pio1_4", - "17": "pio1_5", - "18": "pio1_6", - "19": "pio1_7", - "20": "pio1_8", - "21": "pio1_9", - "22": "pio1_10", - "23": "pio1_11", - "24": "pio2_0", - "25": "pio2_1", - "26": "pio2_2", - "27": "pio2_3", - "28": "pio2_4", - "29": "pio2_5", - "30": "pio2_6", - "31": "pio2_7", - "32": "pio2_8", - "33": "pio2_9", - "34": "pio2_10", - "35": "pio2_11", - "36": "pio3_0", - "37": "pio3_1", - "38": "pio3_2", - "39": "pio3_3", - "40": "i2c0", - "41": "ct16b0", - "42": "ct16b1", - "43": "ct32b0", - "44": "ct32b1", - "45": "ssp0", - "46": "uart", - "47": "usb", - "48": "usb_fiq", - "49": "adc", - "50": "wdt", - "51": "bod", - "53": "pio3", - "54": "pio2", - "55": "pio1", - "56": "ssp1" - }, - "partname_humanreadable": "LPC 13xx series", - "partname_doxygen": "LPC13xx", - "includeguard": "LIBOPENCM3_LPC13xx_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc13xx/memorymap.h b/libopencm3/include/libopencm3/lpc13xx/memorymap.h deleted file mode 100644 index 01b94b2..0000000 --- a/libopencm3/include/libopencm3/lpc13xx/memorymap.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC13XX_MEMORYMAP_H -#define LPC13XX_MEMORYMAP_H - -#include - -/* --- LPC13XX specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE_APB (0x40000000U) -#define PERIPH_BASE_AHB (0x50000000U) - -/* Register boundary addresses */ - -/* APB */ -#define I2C_BASE (PERIPH_BASE_APB + 0x00000) -#define WDT_BASE (PERIPH_BASE_APB + 0x04000) -#define UART_BASE (PERIPH_BASE_APB + 0x08000) -#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000) -#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000) -#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000) -#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000) -#define ADC_BASE (PERIPH_BASE_APB + 0x1c000) -#define USB_BASE (PERIPH_BASE_APB + 0x20000) -/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */ -#define PMU_BASE (PERIPH_BASE_APB + 0x38000) -#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000) -#define SSP_BASE (PERIPH_BASE_APB + 0x40000) -#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000) -#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000) -/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */ - -/* AHB */ -#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000) -#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000) -#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000) -#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000) -/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */ - -#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/clock.h b/libopencm3/include/libopencm3/lpc17xx/clock.h deleted file mode 100644 index 8ad6f47..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/clock.h +++ /dev/null @@ -1,160 +0,0 @@ -/** @defgroup clock_defines Clock Defines - -@brief Defined Constants and Types for the LPC17xx Clock - -@ingroup LPC17xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2013 Silvio Gissi - -@date 17 August 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Silvio Gissi - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC17XX_CLOCK_H -#define LPC17XX_CLOCK_H - -#include -#include - -/* --- Clock registers ----------------------------------------------------- */ -/* System Control and Status */ -#define CLK_SCS MMIO32(SYSCON_BASE + 0x1a0) -/* Clock Source Selection */ -#define CLK_CLKSRCSEL MMIO32(SYSCON_BASE + 0x10c) -/* PLL0: Main */ -#define CLK_PLL0CON MMIO32(SYSCON_BASE + 0x080) -#define CLK_PLL0CFG MMIO32(SYSCON_BASE + 0x084) -#define CLK_PLL0STAT MMIO32(SYSCON_BASE + 0x088) -#define CLK_PLL0FEED MMIO32(SYSCON_BASE + 0x08c) -/* PLL1: USB */ -#define CLK_PLL1CON MMIO32(SYSCON_BASE + 0x0a0) -#define CLK_PLL1CFG MMIO32(SYSCON_BASE + 0x0a4) -#define CLK_PLL1STAT MMIO32(SYSCON_BASE + 0x0a8) -#define CLK_PLL1FEED MMIO32(SYSCON_BASE + 0x0ac) -/* Clock Dividers */ -#define CLK_CCLKCFG MMIO32(SYSCON_BASE + 0x104) -#define CLK_USBCLKCFG MMIO32(SYSCON_BASE + 0x108) -#define CLK_PCLKSEL0 MMIO32(SYSCON_BASE + 0x1a8) -#define CLK_PCLKSEL1 MMIO32(SYSCON_BASE + 0x1ac) -/* Clock Output */ -#define CLK_CLKOUTCFG MMIO32(SYSCON_BASE + 0x1c8) - -/* CLK_SCS Values*/ -/* Reserved: [3:0] */ -#define CLK_SCS_OSCRANGE_01_TO_20MHZ (0) -#define CLK_SCS_OSCRANGE_15_TO_25MHZ (1 << 4) -#define CLK_SCS_OSCEN (1 << 5) -#define CLK_SCS_OSCSTAT (1 << 6) -/* Reserved: [31:7] */ - -/* CLK_CLKSRCSEL Values*/ -#define CLK_CLKSRCSEL_IRC (0) -#define CLK_CLKSRCSEL_MAIN (1 << 0) -#define CLK_CLKSRCSEL_RTC (1 << 1) -/* Reserved: value 11b */ -/* Reserved: [31:2] */ - -/* CLK_PLL0CON and CLK_PLL1CON Values */ -#define CLK_PLLCON_ENABLE (1 << 0) -#define CLK_PLLCON_CONNECT (1 << 1) -/* Reserved: [31:2] */ - -/* CLK_PLL0CFG and CLK_PLL0STAT Values */ -#define CLK_PLL0_MSEL_SHIFT 0 -#define CLK_PLL0_MSEL_MASK 0x7fff -/* Reserved: [15] */ -#define CLK_PLL0_NSEL_SHIFT 16 -#define CLK_PLL0_NSEL_MASK 0xff -/* CFG Reserved: [31:24] */ -#define CLK_PLL0STAT_ENABLE (1 << 24) -#define CLK_PLL0STAT_CONNECT (1 << 25) -#define CLK_PLL0STAT_PLOCK (1 << 26) -/* STAT Reserved: [31:27] */ - -/* CLK_PLL1CFG and CLK_PLL1STAT Values */ -#define CLK_PLL1_MSEL_SHIFT 0 -#define CLK_PLL1_MSEL_MASK 0x1f -#define CLK_PLL1_PSEL_SHIFT 5 -#define CLK_PLL1_PSEL_MASK 0x3 -/* CFG Reserved: [31:7] */ -#define CLK_PLL1STAT_ENABLE (1 << 8) -#define CLK_PLL1STAT_CONNECT (1 << 9) -#define CLK_PLL1STAT_PLOCK (1 << 10) -/* STAT Reserved: [31:11] */ - -/* CLK_USBCLKCFG Values */ -#define CLK_USBCLKCFG_DIV6 0x5 -#define CLK_USBCLKCFG_DIV8 0x7 -#define CLK_USBCLKCFG_DIV10 0x9 - -/* CLK_PCLKSEL0 and CLK_PCLKSEL1 Values */ -#define CLK_PCLKSEL_DIV4 0x00 -#define CLK_PCLKSEL_DIV1 0x01 -#define CLK_PCLKSEL_DIV2 0x02 -#define CLK_PCLKSEL_DIV8 0x03 -#define CLK_PCLKSEL0_WDT_SHIFT 0 -#define CLK_PCLKSEL0_TIMER0_SHIFT 2 -#define CLK_PCLKSEL0_TIMER1_SHIFT 4 -#define CLK_PCLKSEL0_UART0_SHIFT 6 -#define CLK_PCLKSEL0_UART1_SHIFT 8 -/* Reserved: [11:10]*/ -#define CLK_PCLKSEL0_PWM1_SHIFT 12 -#define CLK_PCLKSEL0_I2C0_SHIFT 14 -#define CLK_PCLKSEL0_SPI_SHIFT 16 -/* Reserved: [19:18]*/ -#define CLK_PCLKSEL0_SSP1_SHIFT 20 -#define CLK_PCLKSEL0_DAC_SHIFT 22 -#define CLK_PCLKSEL0_ADC_SHIFT 24 -#define CLK_PCLKSEL0_CAN1_SHIFT 26 -#define CLK_PCLKSEL0_CAN2_SHIFT 28 -#define CLK_PCLKSEL0_ACF_SHIFT 30 -#define CLK_PCLKSEL1_QEI_SHIFT 0 -#define CLK_PCLKSEL1_GPIOINT_SHIFT 2 -#define CLK_PCLKSEL1_PCB_SHIFT 4 -#define CLK_PCLKSEL1_I2C1_SHIFT 6 -/* Reserved: [9:8]*/ -#define CLK_PCLKSEL1_SSP0_SHIFT 10 -#define CLK_PCLKSEL1_TIMER2_SHIFT 12 -#define CLK_PCLKSEL1_TIMER3_SHIFT 14 -#define CLK_PCLKSEL1_UART2_SHIFT 16 -#define CLK_PCLKSEL1_UART3_SHIFT 18 -#define CLK_PCLKSEL1_I2C2_SHIFT 20 -#define CLK_PCLKSEL1_I2S_SHIFT 22 -/* Reserved: [25:24]*/ -#define CLK_PCLKSEL1_RIT_SHIFT 26 -#define CLK_PCLKSEL1_SYSCON_SHIFT 28 -#define CLK_PCLKSEL1_MCPWM_SHIFT 30 - -/* CLK_CLKOUTCFG Values */ -#define CLK_CLKOUTCFG_SEL_CPU 0x00 -#define CLK_CLKOUTCFG_SEL_MAIN 0x01 -#define CLK_CLKOUTCFG_SEL_IRC 0x02 -#define CLK_CLKOUTCFG_SEL_USB 0x03 -#define CLK_CLKOUTCFG_SEL_RTC 0x04 -#define CLK_CLKOUTCFG_DIV_SHIFT 4 -#define CLK_CLKOUTCFG_ENABLE (1 << 8) -#define CLK_CLKOUTCFG_ACTIVITY (1 << 9) -/* Reserved: [31:10]*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h b/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h deleted file mode 100644 index e574617..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 LPC17xx - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for NXP Semiconductors LPC17xx Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC17xx LPC17xx -Libraries for NXP Semiconductors LPC17xx series. - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC17xx_defines LPC17xx Defines - -@brief Defined Constants and Types for the LPC17xx series - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/lpc17xx/gpio.h b/libopencm3/include/libopencm3/lpc17xx/gpio.h deleted file mode 100644 index c357f47..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/gpio.h +++ /dev/null @@ -1,160 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the LPC17xx General Purpose I/O - -@ingroup LPC17xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC17XX_GPIO_H -#define LPC17XX_GPIO_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIO0 GPIO_PIO0_BASE -#define GPIO1 GPIO_PIO1_BASE -#define GPIO2 GPIO_PIO2_BASE -#define GPIO3 GPIO_PIO3_BASE -#define GPIO4 GPIO_PIO4_BASE - -/* GPIO number definitions (for convenience) */ -#define GPIOPIN0 (1 << 0) -#define GPIOPIN1 (1 << 1) -#define GPIOPIN2 (1 << 2) -#define GPIOPIN3 (1 << 3) -#define GPIOPIN4 (1 << 4) -#define GPIOPIN5 (1 << 5) -#define GPIOPIN6 (1 << 6) -#define GPIOPIN7 (1 << 7) -#define GPIOPIN8 (1 << 8) -#define GPIOPIN9 (1 << 9) -#define GPIOPIN10 (1 << 10) -#define GPIOPIN11 (1 << 11) -#define GPIOPIN12 (1 << 12) -#define GPIOPIN13 (1 << 13) -#define GPIOPIN14 (1 << 14) -#define GPIOPIN15 (1 << 15) -#define GPIOPIN16 (1 << 16) -#define GPIOPIN17 (1 << 17) -#define GPIOPIN18 (1 << 18) -#define GPIOPIN19 (1 << 19) -#define GPIOPIN20 (1 << 20) -#define GPIOPIN21 (1 << 21) -#define GPIOPIN22 (1 << 22) -#define GPIOPIN23 (1 << 23) -#define GPIOPIN24 (1 << 24) -#define GPIOPIN25 (1 << 25) -#define GPIOPIN26 (1 << 26) -#define GPIOPIN27 (1 << 27) -#define GPIOPIN28 (1 << 28) -#define GPIOPIN29 (1 << 29) -#define GPIOPIN30 (1 << 30) -#define GPIOPIN31 (1 << 31) - -/* --- GPIO registers ------------------------------------------------------ */ - -/* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32((port) + 0x00) -#define GPIO0_DIR GPIO_DIR(GPIO0) -#define GPIO1_DIR GPIO_DIR(GPIO1) -#define GPIO2_DIR GPIO_DIR(GPIO2) -#define GPIO3_DIR GPIO_DIR(GPIO3) -#define GPIO4_DIR GPIO_DIR(GPIO4) - -/* GPIO fast mask register (GPIOn_DIR) */ -#define GPIO_MASK(port) MMIO32((port) + 0x10) -#define GPIO0_MASK GPIO_MASK(GPIO0) -#define GPIO1_MASK GPIO_MASK(GPIO1) -#define GPIO2_MASK GPIO_MASK(GPIO2) -#define GPIO3_MASK GPIO_MASK(GPIO3) -#define GPIO4_MASK GPIO_MASK(GPIO4) - -/* GPIO port pin value register (GPIOn_PIN) */ -#define GPIO_PIN(port) MMIO32((port) + 0x14) -#define GPIO0_PIN GPIO_PIN(GPIO0) -#define GPIO1_PIN GPIO_PIN(GPIO1) -#define GPIO2_PIN GPIO_PIN(GPIO2) -#define GPIO3_PIN GPIO_PIN(GPIO3) -#define GPIO4_PIN GPIO_PIN(GPIO4) - -/* GPIO port output set register (GPIOn_SET) */ -#define GPIO_SET(port) MMIO32((port) + 0x18) -#define GPIO0_SET GPIO_SET(GPIO0) -#define GPIO1_SET GPIO_SET(GPIO1) -#define GPIO2_SET GPIO_SET(GPIO2) -#define GPIO3_SET GPIO_SET(GPIO3) -#define GPIO4_SET GPIO_SET(GPIO4) - -/* GPIO port output clear register (GPIOn_CLR) */ -#define GPIO_CLR(port) MMIO32((port) + 0x1C) -#define GPIO0_CLR GPIO_CLR(GPIO0) -#define GPIO1_CLR GPIO_CLR(GPIO1) -#define GPIO2_CLR GPIO_CLR(GPIO2) -#define GPIO3_CLR GPIO_CLR(GPIO3) -#define GPIO4_CLR GPIO_CLR(GPIO4) - -/* GPIO interrupt register map */ -/* Interrupt enable rising edge */ -#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90) -#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0) - -/* Interrupt enable falling edge */ -#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94) -#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4) - -/* Interrupt status rising edge */ -#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84) -#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4) - -/* Interrupt status falling edge */ -#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88) -#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8) - -/* Interrupt clear */ -#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C) -#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC) - -/* Overall interrupt status */ -#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80) - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint32_t gpios); -void gpio_clear(uint32_t gpioport, uint32_t gpios); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/irq.json b/libopencm3/include/libopencm3/lpc17xx/irq.json deleted file mode 100644 index 94eec07..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/irq.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "irqs": { - "0": "wdt", - "1": "timer0", - "2": "timer1", - "3": "timer2", - "4": "timer3", - "5": "uart0", - "6": "uart1", - "7": "uart2", - "8": "uart3", - "9": "pwm", - "10": "i2c0", - "11": "i2c1", - "12": "i2c2", - "13": "spi", - "14": "ssp0", - "15": "ssp1", - "16": "pll0", - "17": "rtc", - "18": "eint0", - "19": "eint1", - "20": "eint2", - "21": "eint3", - "22": "adc", - "23": "bod", - "24": "usb", - "25": "can", - "26": "gpdma", - "27": "i2s", - "28": "ethernet", - "29": "rit", - "30": "motor_pwm", - "31": "qei", - "32": "pll1", - "33": "usb_act", - "34": "can_act" - }, - "partname_humanreadable": "LPC 17xx series", - "partname_doxygen": "LPC17xx", - "includeguard": "LIBOPENCM3_LPC17xx_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc17xx/memorymap.h b/libopencm3/include/libopencm3/lpc17xx/memorymap.h deleted file mode 100644 index 4fab750..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/memorymap.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2012 Silvio Gissi - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC17XX_MEMORYMAP_H -#define LPC17XX_MEMORYMAP_H - -#include - -/* --- LPC17XX specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE_GPIO (0x2009C000U) -#define PERIPH_BASE_APB0 (0x40000000U) -#define PERIPH_BASE_APB1 (0x40080000U) -#define PERIPH_BASE_AHB (0x50000000U) - -/* Register boundary addresses */ - -/* GPIO */ -#define GPIO_PIO0_BASE (PERIPH_BASE_GPIO + 0x00) -#define GPIO_PIO1_BASE (PERIPH_BASE_GPIO + 0x20) -#define GPIO_PIO2_BASE (PERIPH_BASE_GPIO + 0x40) -#define GPIO_PIO3_BASE (PERIPH_BASE_GPIO + 0x60) -#define GPIO_PIO4_BASE (PERIPH_BASE_GPIO + 0x80) - -/* APB0 */ -#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000) -#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) -#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000) -#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) -#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) -/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */ -#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) -#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000) -#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000) -#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000) -#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000) -#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000) -#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000) -#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000) -#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) -#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) -#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) -#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) -#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) -/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */ -#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) -/* PERIPH_BASE_APB0 + 0X60000 (0x4006 0000 - 0x4007 BFFF): Reserved */ - -/* APB1 */ -/* PERIPH_BASE_APB1 + 0X00000 (0x4008 0000 - 0x4008 7FFF): Reserved */ -#define SSP0_BASE (PERIPH_BASE_APB1 + 0x08000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x0c000) -#define TIMER2_BASE (PERIPH_BASE_APB1 + 0x10000) -#define TIMER3_BASE (PERIPH_BASE_APB1 + 0x14000) -#define UART2_BASE (PERIPH_BASE_APB1 + 0x18000) -#define UART3_BASE (PERIPH_BASE_APB1 + 0x1c000) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x20000) -/* PERIPH_BASE_APB1 + 0X24000 (0x400A 4000 - 0x400A 7FFF): Reserved */ -#define I2S_BASE (PERIPH_BASE_APB1 + 0x28000) -/* PERIPH_BASE_APB1 + 0X2C000 (0x400A C000 - 0x400A FFFF): Reserved */ -#define RIT_BASE (PERIPH_BASE_APB1 + 0x30000) -/* PERIPH_BASE_APB1 + 0X34000 (0x400B 4000 - 0x400B 7FFF): Reserved */ -#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x38000) -#define QEI_BASE (PERIPH_BASE_APB1 + 0x3c000) -/* PERIPH_BASE_APB1 + 0X40000 (0x400C 0000 - 0x400F BFFF): Reserved */ -#define SYSCON_BASE (PERIPH_BASE_APB1 + 0x7c000) - -/* AHB */ -#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x00000) -#define GPDMA_BASE (PERIPH_BASE_AHB + 0x04000) -/* PERIPH_BASE_AHB + 0X08000 (0x5000 8000 - 0x5000 BFFF): Reserved */ -#define USB_BASE (PERIPH_BASE_AHB + 0x0c000) -/* PERIPH_BASE_AHB + 0X10000 (0x5001 0000 - 0x501F FFFF): Reserved */ - -#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/pwr.h b/libopencm3/include/libopencm3/lpc17xx/pwr.h deleted file mode 100644 index 7b42b63..0000000 --- a/libopencm3/include/libopencm3/lpc17xx/pwr.h +++ /dev/null @@ -1,102 +0,0 @@ -/** @defgroup pwr_defines Power Defines - -@brief Defined Constants and Types for the LPC17xx Power Control - -@ingroup LPC17xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2013 Silvio Gissi - -@date 17 August 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Silvio Gissi - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC17XX_POWER_H -#define LPC17XX_POWER_H - -#include -#include - -/* --- Clock registers ----------------------------------------------------- */ -/* Power Control */ -#define PWR_PCON MMIO32(SYSCON_BASE + 0x0c0) -#define PWR_PCONP MMIO32(SYSCON_BASE + 0x0c4) - -/* PWR_PCON Values */ -#define PWR_PCON_MODE_SLEEP 0x00 -#define PWR_PCON_MODE_POWER_DOWN 0x01 -/* PWR_PCON_MODE_RESERVED 0x02*/ -#define PWR_PCON_MODE_DEEPSLEEP 0x03 -#define PWR_PCON_BODRPM (1 << 2) -#define PWR_PCON_BOGD (1 << 3) -#define PWR_PCON_BORD (1 << 4) -/* Reserved: [7:5] */ -#define PWR_PCON_SMFLAG (1 << 8) -#define PWR_PCON_DSFLAG (1 << 9) -#define PWR_PCON_PDFLAG (1 << 10) -#define PWR_PCON_DPDFLAG (1 << 11) -/* Reserved: [31:12] */ - -/* PWR_PCONP Values */ -/* Reserved: [0] */ -#define PWR_PCONP_TIMER0 (1 << 1) -#define PWR_PCONP_TIMER1 (1 << 2) -#define PWR_PCONP_UART0 (1 << 3) -#define PWR_PCONP_UART1 (1 << 4) -/* Reserved: [5] */ -#define PWR_PCONP_PWM1 (1 << 6) -#define PWR_PCONP_I2C0 (1 << 7) -#define PWR_PCONP_SPI (1 << 8) -#define PWR_PCONP_RTC (1 << 9) -#define PWR_PCONP_SSP1 (1 << 10) -/* Reserved: [11] */ -#define PWR_PCONP_ADC (1 << 12) -#define PWR_PCONP_CAN1 (1 << 13) -#define PWR_PCONP_CAN2 (1 << 14) -#define PWR_PCONP_GPIO (1 << 15) -#define PWR_PCONP_RIT (1 << 16) -#define PWR_PCONP_MCPWM (1 << 17) -#define PWR_PCONP_QEI (1 << 18) -#define PWR_PCONP_I2C1 (1 << 19) -/* Reserved: [20] */ -#define PWR_PCONP_SSP0 (1 << 21) -#define PWR_PCONP_TIMER2 (1 << 22) -#define PWR_PCONP_TIMER3 (1 << 23) -#define PWR_PCONP_UART2 (1 << 24) -#define PWR_PCONP_UART3 (1 << 25) -#define PWR_PCONP_I2C2 (1 << 26) -#define PWR_PCONP_I2S (1 << 27) -/* Reserved: [28] */ -#define PWR_PCONP_GPDMA (1 << 29) -#define PWR_PCONP_ETHERNET (1 << 30) -#define PWR_PCONP_USB (1 << 31) - -BEGIN_DECLS - -void pwr_enable_peripherals(uint32_t peripherals); -void pwr_disable_peripherals(uint32_t peripherals); -/* TODO Sleep, Deep Sleep, Power Down and Deep Power Down modes */ - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/adc.h b/libopencm3/include/libopencm3/lpc43xx/adc.h deleted file mode 100644 index d506524..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/adc.h +++ /dev/null @@ -1,113 +0,0 @@ -/** @defgroup adc_defines ADC Defines - -@brief Defined Constants and Types for the LPC43xx A/D Converter - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_ADC_H -#define LPC43XX_ADC_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* ADC port base addresses (for convenience) */ -#define ADC0 ADC0_BASE -#define ADC1 ADC1_BASE - - -/* --- ADC registers ------------------------------------------------------- */ - -/* A/D Control Register */ -#define ADC_CR(port) MMIO32((port) + 0x000) -#define ADC0_CR ADC_CR(ADC0) -#define ADC1_CR ADC_CR(ADC1) - -/* A/D Global Data Register */ -#define ADC_GDR(port) MMIO32((port) + 0x004) -#define ADC0_GDR ADC_GDR(ADC0) -#define ADC1_GDR ADC_GDR(ADC1) - -/* A/D Interrupt Enable Register */ -#define ADC_INTEN(port) MMIO32((port) + 0x00C) -#define ADC0_INTEN ADC_INTEN(ADC0) -#define ADC1_INTEN ADC_INTEN(ADC1) - -/* A/D Channel 0 Data Register */ -#define ADC_DR0(port) MMIO32((port) + 0x010) -#define ADC0_DR0 ADC_DR0(ADC0) -#define ADC1_DR0 ADC_DR0(ADC1) - -/* A/D Channel 1 Data Register */ -#define ADC_DR1(port) MMIO32((port) + 0x014) -#define ADC0_DR1 ADC_DR1(ADC0) -#define ADC1_DR1 ADC_DR1(ADC1) - -/* A/D Channel 2 Data Register */ -#define ADC_DR2(port) MMIO32((port) + 0x018) -#define ADC0_DR2 ADC_DR2(ADC0) -#define ADC1_DR2 ADC_DR2(ADC1) - -/* A/D Channel 3 Data Register */ -#define ADC_DR3(port) MMIO32((port) + 0x01C) -#define ADC0_DR3 ADC_DR3(ADC0) -#define ADC1_DR3 ADC_DR3(ADC1) - -/* A/D Channel 4 Data Register */ -#define ADC_DR4(port) MMIO32((port) + 0x020) -#define ADC0_DR4 ADC_DR4(ADC0) -#define ADC1_DR4 ADC_DR4(ADC1) - -/* A/D Channel 5 Data Register */ -#define ADC_DR5(port) MMIO32((port) + 0x024) -#define ADC0_DR5 ADC_DR5(ADC0) -#define ADC1_DR5 ADC_DR5(ADC1) - -/* A/D Channel 6 Data Register */ -#define ADC_DR6(port) MMIO32((port) + 0x028) -#define ADC0_DR6 ADC_DR6(ADC0) -#define ADC1_DR6 ADC_DR6(ADC1) - -/* A/D Channel 7 Data Register */ -#define ADC_DR7(port) MMIO32((port) + 0x02C) -#define ADC0_DR7 ADC_DR7(ADC0) -#define ADC1_DR7 ADC_DR7(ADC1) - -/* A/D Status Register */ -#define ADC_STAT(port) MMIO32((port) + 0x030) -#define ADC0_STAT ADC_STAT(ADC0) -#define ADC1_STAT ADC_STAT(ADC1) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/atimer.h b/libopencm3/include/libopencm3/lpc43xx/atimer.h deleted file mode 100644 index cbb70d7..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/atimer.h +++ /dev/null @@ -1,70 +0,0 @@ -/** @defgroup atimer_defines Alarm Timer Defines - -@brief Defined Constants and Types for the LPC43xx Alarm Timer - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_ATIMER_H -#define LPC43XX_ATIMER_H - -/**@{*/ - -#include -#include - -/* --- Alarm Timer registers ----------------------------------------------- */ - -/* Downcounter register */ -#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000) - -/* Preset value register */ -#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004) - -/* Interrupt clear enable register */ -#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8) - -/* Interrupt set enable register */ -#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC) - -/* Status register */ -#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0) - -/* Enable register */ -#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4) - -/* Clear register */ -#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8) - -/* Set register */ -#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ccu.h b/libopencm3/include/libopencm3/lpc43xx/ccu.h deleted file mode 100644 index d3b1d50..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/ccu.h +++ /dev/null @@ -1,402 +0,0 @@ -/** @defgroup ccu_defines Clock Control Unit Defines - -@brief Defined Constants and Types for the LPC43xx Clock Control Unit - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_CCU_H -#define LPC43XX_CCU_H - -/**@{*/ - -#include -#include - -/* --- CCU1 registers ------------------------------------------------------ */ - -/* CCU1 power mode register */ -#define CCU1_PM MMIO32(CCU1_BASE + 0x000) - -/* CCU1 base clock status register */ -#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004) - -/* CLK_APB3_BUS clock configuration register */ -#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100) - -/* CLK_APB3_BUS clock status register */ -#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104) - -/* CLK_APB3_I2C1 configuration register */ -#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108) - -/* CLK_APB3_I2C1 status register */ -#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C) - -/* CLK_APB3_DAC configuration register */ -#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110) - -/* CLK_APB3_DAC status register */ -#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114) - -/* CLK_APB3_ADC0 configuration register */ -#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118) - -/* CLK_APB3_ADC0 status register */ -#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C) - -/* CLK_APB3_ADC1 configuration register */ -#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120) - -/* CLK_APB3_ADC1 status register */ -#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124) - -/* CLK_APB3_CAN0 configuration register */ -#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128) - -/* CLK_APB3_CAN0 status register */ -#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C) - -/* CLK_APB1_BUS configuration register */ -#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200) - -/* CLK_APB1_BUS status register */ -#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204) - -/* CLK_APB1_MOTOCON configuration register */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208) - -/* CLK_APB1_MOTOCON status register */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C) - -/* CLK_APB1_I2C0 configuration register */ -#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210) - -/* CLK_APB1_I2C0 status register */ -#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214) - -/* CLK_APB1_I2S configuration register */ -#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218) - -/* CLK_APB1_I2S status register */ -#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C) - -/* CLK_APB3_CAN1 configuration register */ -#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220) - -/* CLK_APB3_CAN1 status register */ -#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224) - -/* CLK_SPIFI configuration register */ -#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300) - -/* CLK_SPIFI status register */ -#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304) - -/* CLK_M4_BUS configuration register */ -#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400) - -/* CLK_M4_BUS status register */ -#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404) - -/* CLK_M4_SPIFI configuration register */ -#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408) - -/* CLK_M4_SPIFI status register */ -#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C) - -/* CLK_M4_GPIO configuration register */ -#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410) - -/* CLK_M4_GPIO status register */ -#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414) - -/* CLK_M4_LCD configuration register */ -#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418) - -/* CLK_M4_LCD status register */ -#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C) - -/* CLK_M4_ETHERNET configuration register */ -#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420) - -/* CLK_M4_ETHERNET status register */ -#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424) - -/* CLK_M4_USB0 configuration register */ -#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428) - -/* CLK_M4_USB0 status register */ -#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C) - -/* CLK_M4_EMC configuration register */ -#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430) - -/* CLK_M4_EMC status register */ -#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434) - -/* CLK_M4_SDIO configuration register */ -#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438) - -/* CLK_M4_SDIO status register */ -#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C) - -/* CLK_M4_DMA configuration register */ -#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440) - -/* CLK_M4_DMA status register */ -#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444) - -/* CLK_M4_M4CORE configuration register */ -#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448) - -/* CLK_M4_M4CORE status register */ -#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C) - -/* CLK_M4_SCT configuration register */ -#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468) - -/* CLK_M4_SCT status register */ -#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C) - -/* CLK_M4_USB1 configuration register */ -#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470) - -/* CLK_M4_USB1 status register */ -#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474) - -/* CLK_M4_EMCDIV configuration register */ -#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478) - -/* CLK_M4_EMCDIV status register */ -#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C) - -/* CLK_M4_M0_CFG configuration register */ -#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490) - -/* CLK_M4_M0_STAT status register */ -#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494) - -/* CLK_M4_VADC_CFG configuration register */ -#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498) - -/* CLK_M4_VADC_STAT configuration register */ -#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C) - -/* CLK_M4_WWDT configuration register */ -#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500) - -/* CLK_M4_WWDT status register */ -#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504) - -/* CLK_M4_UART0 configuration register */ -#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508) - -/* CLK_M4_UART0 status register */ -#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C) - -/* CLK_M4_UART1 configuration register */ -#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510) - -/* CLK_M4_UART1 status register */ -#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514) - -/* CLK_M4_SSP0 configuration register */ -#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518) - -/* CLK_M4_SSP0 status register */ -#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C) - -/* CLK_M4_TIMER0 configuration register */ -#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520) - -/* CLK_M4_TIMER0 status register */ -#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524) - -/* CLK_M4_TIMER1 configuration register */ -#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528) - -/* CLK_M4_TIMER1 status register */ -#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C) - -/* CLK_M4_SCU configuration register */ -#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530) - -/* CLK_M4_SCU status register */ -#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534) - -/* CLK_M4_CREG configuration register */ -#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538) - -/* CLK_M4_CREG status register */ -#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C) - -/* CLK_M4_RITIMER configuration register */ -#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600) - -/* CLK_M4_RITIMER status register */ -#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604) - -/* CLK_M4_UART2 configuration register */ -#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608) - -/* CLK_M4_UART2 status register */ -#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C) - -/* CLK_M4_UART3 configuration register */ -#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610) - -/* CLK_M4_UART3 status register */ -#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614) - -/* CLK_M4_TIMER2 configuration register */ -#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618) - -/* CLK_M4_TIMER2 status register */ -#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C) - -/* CLK_M4_TIMER3 configuration register */ -#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620) - -/* CLK_M4_TIMER3 status register */ -#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624) - -/* CLK_M4_SSP1 configuration register */ -#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628) - -/* CLK_M4_SSP1 status register */ -#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C) - -/* CLK_M4_QEI configuration register */ -#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630) - -/* CLK_M4_QEI status register */ -#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634) - -/* CLK_PERIPH_BUS configuration register */ -#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700) - -/* CLK_PERIPH_BUS status register */ -#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704) - -/* CLK_PERIPH_CORE configuration register */ -#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710) - -/* CLK_PERIPH_CORE status register */ -#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714) - -/* CLK_PERIPH_SGPIO configuration register */ -#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718) - -/* CLK_PERIPH_SGPIO status register */ -#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C) - -/* CLK_USB0 configuration register */ -#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800) - -/* CLK_USB0 status register */ -#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804) - -/* CLK_USB1 configuration register */ -#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900) - -/* CLK_USB1 status register */ -#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904) - -/* CLK_SPI configuration register */ -#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00) - -/* CLK_SPI status register */ -#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04) - -/* CLK_VADC configuration register */ -#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00) - -/* CLK_VADC status register */ -#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04) - -/* --- CCU2 registers ------------------------------------------------------ */ - -/* CCU2 power mode register */ -#define CCU2_PM MMIO32(CCU2_BASE + 0x000) - -/* CCU2 base clocks status register */ -#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004) - -/* CLK_APLL configuration register */ -#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100) - -/* CLK_APLL status register */ -#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104) - -/* CLK_APB2_UART3 configuration register */ -#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200) - -/* CLK_APB2_UART3 status register */ -#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204) - -/* CLK_APB2_UART2 configuration register */ -#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300) - -/* CLK_APB2_UART2 status register */ -#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304) - -/* CLK_APB0_UART1 configuration register */ -#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400) - -/* CLK_APB0_UART1 status register */ -#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404) - -/* CLK_APB0_UART0 configuration register */ -#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500) - -/* CLK_APB0_UART0 status register */ -#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504) - -/* CLK_APB2_SSP1 configuration register */ -#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600) - -/* CLK_APB2_SSP1 status register */ -#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604) - -/* CLK_APB0_SSP0 configuration register */ -#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700) - -/* CLK_APB0_SSP0 status register */ -#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704) - -/* CLK_SDIO configuration register (for SD/MMC) */ -#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800) - -/* CLK_SDIO status register (for SD/MMC) */ -#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/cgu.h b/libopencm3/include/libopencm3/lpc43xx/cgu.h deleted file mode 100644 index 0a169fd..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/cgu.h +++ /dev/null @@ -1,964 +0,0 @@ -/** @defgroup cgu_defines Clock Generation Unit Defines - * - * @brief Defined Constants and Types for the LPC43xx Clock Generation - * Unit - * - * @ingroup LPC43xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann - * - * - * @date 10 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_CGU_H -#define CGU_LPC43XX_CGU_H - -/**@{*/ - -#include -#include - -/* --- CGU registers ------------------------------------------------------- */ - -/* Frequency monitor register */ -#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014) - -/* Crystal oscillator control register */ -#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018) - -/* PLL0USB status register */ -#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C) - -/* PLL0USB control register */ -#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020) - -/* PLL0USB M-divider register */ -#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024) - -/* PLL0USB N/P-divider register */ -#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028) - -/* PLL0AUDIO status register */ -#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C) - -/* PLL0AUDIO control register */ -#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030) - -/* PLL0AUDIO M-divider register */ -#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034) - -/* PLL0AUDIO N/P-divider register */ -#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038) - -/* PLL0AUDIO fractional divider register */ -#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C) - -/* PLL1 status register */ -#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040) - -/* PLL1 control register */ -#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044) - -/* Integer divider A control register */ -#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048) - -/* Integer divider B control register */ -#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C) - -/* Integer divider C control register */ -#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050) - -/* Integer divider D control register */ -#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054) - -/* Integer divider E control register */ -#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058) - -/* Output stage 0 control register */ -#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C) - -/* Output stage 1 control register for base clock */ -#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060) - -/* Output stage 2 control register for base clock */ -#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064) - -/* Output stage 3 control register for base clock */ -#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068) - -/* Output stage 4 control register for base clock */ -#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C) - -/* Output stage 5 control register for base clock */ -#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070) - -/* Output stage 6 control register for base clock */ -#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074) - -/* Output stage 7 control register for base clock */ -#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078) - -/* Output stage 8 control register for base clock */ -#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C) - -/* Output stage 9 control register for base clock */ -#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080) - -/* Output stage 10 control register for base clock */ -#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084) - -/* Output stage 11 control register for base clock */ -#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088) - -/* Output stage 12 control register for base clock */ -#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C) - -/* Output stage 13 control register for base clock */ -#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090) - -/* Output stage 14 control register for base clock */ -#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094) - -/* Output stage 15 control register for base clock */ -#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098) - -/* Output stage 16 control register for base clock */ -#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C) - -/* Output stage 17 control register for base clock */ -#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0) - -/* Output stage 18 control register for base clock */ -#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4) - -/* Output stage 19 control register for base clock */ -#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8) - -/* Output stage 20 control register for base clock */ -#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC) - -/* Reserved output stage */ -#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0) - -/* Reserved output stage */ -#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4) - -/* Reserved output stage */ -#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8) - -/* Reserved output stage */ -#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC) - -/* Output stage 25 control register for base clock */ -#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0) - -/* Output stage 26 control CLK register for base clock */ -#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4) - -/* Output stage 27 control CLK register for base clock */ -#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) - -/* --- CGU_FREQ_MON values -------------------------------------- */ - -/* RCNT: 9-bit reference clock-counter value */ -#define CGU_FREQ_MON_RCNT_SHIFT (0) -#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) -#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) - -/* FCNT: 14-bit selected clock-counter value */ -#define CGU_FREQ_MON_FCNT_SHIFT (9) -#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) -#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) - -/* MEAS: Measure frequency */ -#define CGU_FREQ_MON_MEAS_SHIFT (23) -#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) - -/* CLK_SEL: Clock-source selection for the clock to be measured */ -#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) -#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) -#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) - -/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ - -/* ENABLE: Oscillator-pad enable */ -#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) -#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) - -/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ -#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) -#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) - -/* HF: Select frequency range */ -#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) -#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) - -/* --- CGU_PLL0USB_STAT values ---------------------------------- */ - -/* LOCK: PLL0 lock indicator */ -#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) -#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) - -/* FR: PLL0 free running indicator */ -#define CGU_PLL0USB_STAT_FR_SHIFT (1) -#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) - -/* --- CGU_PLL0USB_CTRL values ---------------------------------- */ - -/* PD: PLL0 power down */ -#define CGU_PLL0USB_CTRL_PD_SHIFT (0) -#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) - -/* BYPASS: Input clock bypass control */ -#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) - -/* DIRECTI: PLL0 direct input */ -#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) -#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) - -/* DIRECTO: PLL0 direct output */ -#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) -#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) - -/* CLKEN: PLL0 clock enable */ -#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) -#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) - -/* FRM: Free running mode */ -#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) -#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_PLL0USB_MDIV values ---------------------------------- */ - -/* MDEC: Decoded M-divider coefficient value */ -#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) -#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) -#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) - -/* SELP: Bandwidth select P value */ -#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) -#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) -#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) - -/* SELI: Bandwidth select I value */ -#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) -#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) -#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) - -/* SELR: Bandwidth select R value */ -#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) -#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) -#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) - -/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ - -/* PDEC: Decoded P-divider coefficient value */ -#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) -#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) -#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) - -/* NDEC: Decoded N-divider coefficient value */ -#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) -#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) -#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) - -/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ - -/* LOCK: PLL0 lock indicator */ -#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) -#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) - -/* FR: PLL0 free running indicator */ -#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) -#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) - -/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ - -/* PD: PLL0 power down */ -#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) -#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) - -/* BYPASS: Input clock bypass control */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) - -/* DIRECTI: PLL0 direct input */ -#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) -#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) - -/* DIRECTO: PLL0 direct output */ -#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) -#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) - -/* CLKEN: PLL0 clock enable */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) -#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) - -/* FRM: Free running mode */ -#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) -#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \ - (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) - -/* PLLFRACT_REQ: Fractional PLL word write request */ -#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) -#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \ - (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) - -/* SEL_EXT: Select fractional divider */ -#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) -#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) - -/* MOD_PD: Sigma-Delta modulator power-down */ -#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) -#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \ - (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \ - ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ - -/* MDEC: Decoded M-divider coefficient value */ -#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) -#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \ - (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) -#define CGU_PLL0AUDIO_MDIV_MDEC(x) \ - ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) - -/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ - -/* PDEC: Decoded P-divider coefficient value */ -#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) -#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \ - (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) -#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \ - ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) - -/* NDEC: Decoded N-divider coefficient value */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) -#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \ - (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) -#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \ - ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) - -/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */ - -/* PLLFRACT_CTRL: PLL fractional divider control word */ -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \ - (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \ - ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) - -/* --- CGU_PLL1_STAT values ------------------------------------- */ - -/* LOCK: PLL1 lock indicator */ -#define CGU_PLL1_STAT_LOCK_SHIFT (0) -#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) - -/* --- CGU_PLL1_CTRL values ------------------------------------- */ - -/* PD: PLL1 power down */ -#define CGU_PLL1_CTRL_PD_SHIFT (0) -#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) - -/* BYPASS: Input clock bypass control */ -#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) - -/* FBSEL: PLL feedback select */ -#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) -#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) - -/* DIRECT: PLL direct CCO output */ -#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) -#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) - -/* PSEL: Post-divider division ratio P */ -#define CGU_PLL1_CTRL_PSEL_SHIFT (8) -#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) -#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) - -/* NSEL: Pre-divider division ratio N */ -#define CGU_PLL1_CTRL_NSEL_SHIFT (12) -#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) -#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) - -/* MSEL: Feedback-divider division ratio (M) */ -#define CGU_PLL1_CTRL_MSEL_SHIFT (16) -#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) -#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) - -/* CLK_SEL: Clock-source selection */ -#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_IDIVA_CTRL values ------------------------------------ */ - -/* PD: Integer divider power down */ -#define CGU_IDIVA_CTRL_PD_SHIFT (0) -#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) - -/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ -#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) -#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_IDIVB_CTRL values ------------------------------------ */ - -/* PD: Integer divider power down */ -#define CGU_IDIVB_CTRL_PD_SHIFT (0) -#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) - -/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ -#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) -#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_IDIVC_CTRL values ------------------------------------ */ - -/* PD: Integer divider power down */ -#define CGU_IDIVC_CTRL_PD_SHIFT (0) -#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) - -/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ -#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) -#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_IDIVD_CTRL values ------------------------------------ */ - -/* PD: Integer divider power down */ -#define CGU_IDIVD_CTRL_PD_SHIFT (0) -#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) - -/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ -#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) -#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_IDIVE_CTRL values ------------------------------------ */ - -/* PD: Integer divider power down */ -#define CGU_IDIVE_CTRL_PD_SHIFT (0) -#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) - -/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ -#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) -#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SAFE_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) -#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_USB0_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_USB0_CLK_PD_SHIFT (0) -#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_USB0_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) -#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \ - (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_USB1_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_USB1_CLK_PD_SHIFT (0) -#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_USB1_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_M4_CLK values ----------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_M4_CLK_PD_SHIFT (0) -#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) -#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \ - (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SPI_CLK values ---------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SPI_CLK_PD_SHIFT (0) -#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) -#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \ - (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) -#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \ - (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_APB1_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_APB1_CLK_PD_SHIFT (0) -#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_APB3_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_APB3_CLK_PD_SHIFT (0) -#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_LCD_CLK values ---------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_LCD_CLK_PD_SHIFT (0) -#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_VADC_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_VADC_CLK_PD_SHIFT (0) -#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SDIO_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) -#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SSP0_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) -#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_SSP1_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) -#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_UART0_CLK values -------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_UART0_CLK_PD_SHIFT (0) -#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART0_CLK_AUTOBLOCK \ - (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART0_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_UART1_CLK values -------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_UART1_CLK_PD_SHIFT (0) -#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART1_CLK_AUTOBLOCK \ - (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART1_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_UART2_CLK values -------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_UART2_CLK_PD_SHIFT (0) -#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART2_CLK_AUTOBLOCK \ - (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART2_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_UART3_CLK values -------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_UART3_CLK_PD_SHIFT (0) -#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART3_CLK_AUTOBLOCK \ - (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART3_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_OUT_CLK values ---------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_OUT_CLK_PD_SHIFT (0) -#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_APLL_CLK values --------------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_APLL_CLK_PD_SHIFT (0) -#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) -#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \ - (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ - -/* PD: Output stage power down */ -#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) -#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) - -/* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \ - (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) - -/* CLK_SEL: Clock source selection */ -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \ - (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \ - ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) - -/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ - -#define CGU_SRC_32K 0x00 -#define CGU_SRC_IRC 0x01 -#define CGU_SRC_ENET_RX 0x02 -#define CGU_SRC_ENET_TX 0x03 -#define CGU_SRC_GP_CLKIN 0x04 -#define CGU_SRC_XTAL 0x06 -#define CGU_SRC_PLL0USB 0x07 -#define CGU_SRC_PLL0AUDIO 0x08 -#define CGU_SRC_PLL1 0x09 -#define CGU_SRC_IDIVA 0x0C -#define CGU_SRC_IDIVB 0x0D -#define CGU_SRC_IDIVC 0x0E -#define CGU_SRC_IDIVD 0x0F -#define CGU_SRC_IDIVE 0x10 - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/creg.h b/libopencm3/include/libopencm3/lpc43xx/creg.h deleted file mode 100644 index 2c69551..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/creg.h +++ /dev/null @@ -1,354 +0,0 @@ -/** @defgroup creg_defines Configuration Registers Defines - -@brief Defined Constants and Types for the LPC43xx Configuration -Registers - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_CREG_H -#define LPC43XX_CREG_H - -/**@{*/ - -#include -#include - -/* --- CREG registers ----------------------------------------------------- */ - -/* - * Chip configuration register 32 kHz oscillator output and BOD control - * register - */ -#define CREG_CREG0 MMIO32(CREG_BASE + 0x004) - -/* ARM Cortex-M4 memory mapping */ -#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100) - -/* Chip configuration register 1 */ -#define CREG_CREG1 MMIO32(CREG_BASE + 0x108) - -/* Chip configuration register 2 */ -#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C) - -/* Chip configuration register 3 */ -#define CREG_CREG3 MMIO32(CREG_BASE + 0x110) - -/* Chip configuration register 4 */ -#define CREG_CREG4 MMIO32(CREG_BASE + 0x114) - -/* Chip configuration register 5 */ -#define CREG_CREG5 MMIO32(CREG_BASE + 0x118) - -/* DMA muxing control */ -#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C) - -/* Flash accelerator configuration register for flash bank A */ -#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120) - -/* Flash accelerator configuration register for flash bank B */ -#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124) - -/* ETB RAM configuration */ -#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128) - -/* - * Chip configuration register 6. Controls multiple functions: Ethernet - * interface, SCT output, I2S0/1 inputs, EMC clock. - */ -#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C) - -/* Cortex-M4 TXEV event clear */ -#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130) - -/* Part ID (Boundary scan ID code, read-only) */ -#define CREG_CHIPID MMIO32(CREG_BASE + 0x200) - -/* Cortex-M0 TXEV event clear */ -#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400) - -/* ARM Cortex-M0 memory mapping */ -#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404) - -/* USB0 frame length adjust register */ -#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500) - -/* USB1 frame length adjust register */ -#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600) - -/* --- CREG_CREG0 values ---------------------------------------- */ - -/* EN1KHZ: Enable 1 kHz output */ -#define CREG_CREG0_EN1KHZ_SHIFT (0) -#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) - -/* EN32KHZ: Enable 32 kHz output */ -#define CREG_CREG0_EN32KHZ_SHIFT (1) -#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) - -/* RESET32KHZ: 32 kHz oscillator reset */ -#define CREG_CREG0_RESET32KHZ_SHIFT (2) -#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) - -/* PD32KHZ: 32 kHz power control */ -#define CREG_CREG0_PD32KHZ_SHIFT (3) -#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) - -/* USB0PHY: USB0 PHY power control */ -#define CREG_CREG0_USB0PHY_SHIFT (5) -#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) - -/* ALARMCTRL: RTC_ALARM pin output control */ -#define CREG_CREG0_ALARMCTRL_SHIFT (6) -#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) -#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT) - -/* BODLVL1: BOD trip level to generate an interrupt */ -#define CREG_CREG0_BODLVL1_SHIFT (8) -#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) -#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT) - -/* BODLVL2: BOD trip level to generate a reset */ -#define CREG_CREG0_BODLVL2_SHIFT (10) -#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) -#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT) - -/* SAMPLECTRL: SAMPLE pin input/output control */ -#define CREG_CREG0_SAMPLECTRL_SHIFT (12) -#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) -#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) - -/* WAKEUP0CTRL: WAKEUP0 pin input/output control */ -#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14) -#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) -#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) - -/* WAKEUP1CTRL: WAKEUP1 pin input/output control */ -#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16) -#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) -#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) - -/* --- CREG_M4MEMMAP values ------------------------------------- */ - -/* M4MAP: Shadow address when accessing memory at address 0x00000000 */ -#define CREG_M4MEMMAP_M4MAP_SHIFT (12) -#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) -#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) - -/* --- CREG_CREG5 values ---------------------------------------- */ - -/* M4TAPSEL: JTAG debug select for M4 core */ -#define CREG_CREG5_M4TAPSEL_SHIFT (6) -#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) - -/* M0APPTAPSEL: JTAG debug select for M0 co-processor */ -#define CREG_CREG5_M0APPTAPSEL_SHIFT (9) -#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) - -/* --- CREG_DMAMUX values --------------------------------------- */ - -/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */ -#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0) -#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) -#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) - -/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */ -#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2) -#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) -#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) - -/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */ -#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4) -#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) -#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) - -/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */ -#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6) -#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) -#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) - -/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */ -#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8) -#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) -#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) - -/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */ -#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10) -#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) -#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) - -/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */ -#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12) -#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) -#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) - -/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */ -#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14) -#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) -#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) - -/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */ -#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16) -#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) -#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) - -/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */ -#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18) -#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) -#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) - -/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */ -#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20) -#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) -#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) - -/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */ -#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22) -#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) -#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) - -/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */ -#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24) -#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) -#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) - -/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */ -#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26) -#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) -#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) - -/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */ -#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28) -#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) -#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) - -/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */ -#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30) -#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) -#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) - -/* --- CREG_FLASHCFGA values ------------------------------------ */ - -/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number - * of BASE_M4_CLK clocks used for a flash access */ -#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) -#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) -#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) - -/* POW: Flash bank A power control */ -#define CREG_FLASHCFGA_POW_SHIFT (31) -#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) - -/* --- CREG_FLASHCFGB values ------------------------------------ */ - -/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number - * of BASE_M4_CLK clocks used for a flash access */ -#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) -#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) -#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) - -/* POW: Flash bank B power control */ -#define CREG_FLASHCFGB_POW_SHIFT (31) -#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) - -/* --- CREG_ETBCFG values --------------------------------------- */ - -/* ETB: Select SRAM interface */ -#define CREG_ETBCFG_ETB_SHIFT (0) -#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) - -/* --- CREG_CREG6 values ---------------------------------------- */ - -/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the - * PHY interface */ -#define CREG_CREG6_ETHMODE_SHIFT (0) -#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) -#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) - -/* CTOUTCTRL: Selects the functionality of the SCT outputs */ -#define CREG_CREG6_CTOUTCTRL_SHIFT (4) -#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) - -/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */ -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12) -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) - -/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */ -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13) -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) - -/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */ -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14) -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) - -/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */ -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15) -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) - -/* EMC_CLK_SEL: EMC_CLK divided clock select */ -#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16) -#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) - -/* --- CREG_M4TXEVENT values ------------------------------------ */ - -/* TXEVCLR: Cortex-M4 TXEV event */ -#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0) -#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) - -/* --- CREG_M0TXEVENT values ------------------------------------ */ - -/* TXEVCLR: Cortex-M0 TXEV event */ -#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0) -#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) - -/* --- CREG_M0APPMEMMAP values ---------------------------------- */ - -/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ -#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) -#define CREG_M0APPMEMMAP_M0APPMAP_MASK \ - (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) -#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) - -/* --- CREG_USB0FLADJ values ------------------------------------ */ - -/* FLTV: Frame length timing value */ -#define CREG_USB0FLADJ_FLTV_SHIFT (0) -#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) -#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT) - -/* --- CREG_USB1FLADJ values ------------------------------------ */ - -/* FLTV: Frame length timing value */ -#define CREG_USB1FLADJ_FLTV_SHIFT (0) -#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) -#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h deleted file mode 100644 index b5687d8..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 LPC43xx - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for NXP Semiconductors LPC43xx Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC43xx LPC43xx -Libraries for NXP Semiconductors LPC43xx series. - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup LPC43xx_defines LPC43xx Defines - -@brief Defined Constants and Types for the LPC43xx series - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/lpc43xx/eventrouter.h b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h deleted file mode 100644 index d27c67c..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/eventrouter.h +++ /dev/null @@ -1,70 +0,0 @@ -/** @defgroup eventrouter_defines Event Router Defines - -@brief Defined Constants and Types for the LPC43xx Event Router - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_EVENTROUTER_H -#define LPC43XX_EVENTROUTER_H - -/**@{*/ - -#include -#include - -/* --- Event Router registers ---------------------------------------------- */ - -/* Level configuration register */ -#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000) - -/* Edge configuration */ -#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004) - -/* Clear event enable register */ -#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8) - -/* Set event enable register */ -#define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC) - -/* Event Status register */ -#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0) - -/* Event Enable register */ -#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4) - -/* Clear event status register */ -#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8) - -/* Set event status register */ -#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gima.h b/libopencm3/include/libopencm3/lpc43xx/gima.h deleted file mode 100644 index 6a36c76..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/gima.h +++ /dev/null @@ -1,137 +0,0 @@ -/** @defgroup gima_defines Global Input Multiplexer Array Defines - -@brief Defined Constants and Types for the LPC43xx Global Input Multiplexer -Array - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_GIMA_H -#define LPC43XX_GIMA_H - -/**@{*/ - -#include -#include - -/* --- GIMA registers ----------------------------------------------------- */ - -/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ -#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000) - -/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ -#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004) - -/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ -#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008) - -/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ -#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C) - -/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ -#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010) - -/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ -#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014) - -/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ -#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018) - -/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ -#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C) - -/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ -#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020) - -/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ -#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024) - -/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ -#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028) - -/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ -#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C) - -/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ -#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030) - -/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ -#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034) - -/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ -#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038) - -/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ -#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C) - -/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */ -#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040) - -/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */ -#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044) - -/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */ -#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048) - -/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */ -#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C) - -/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */ -#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050) - -/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */ -#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054) - -/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */ -#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058) - -/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */ -#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C) - -/* VADC trigger input multiplexer (GIMA output 24) */ -#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060) - -/* Event router input 13 multiplexer (GIMA output 25) */ -#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064) - -/* Event router input 14 multiplexer (GIMA output 26) */ -#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068) - -/* Event router input 16 multiplexer (GIMA output 27) */ -#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C) - -/* ADC start0 input multiplexer (GIMA output 28) */ -#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070) - -/* ADC start1 input multiplexer (GIMA output 29) */ -#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpdma.h b/libopencm3/include/libopencm3/lpc43xx/gpdma.h deleted file mode 100644 index 9df6698..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/gpdma.h +++ /dev/null @@ -1,552 +0,0 @@ -/** @defgroup gpdma_defines General Purpose DMA Defines - * - * @brief Defined Constants and Types for the LPC43xx General Purpose DMA - * - * @ingroup LPC43xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann - * - * @date 10 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_GPDMA_H -#define LPC43XX_GPDMA_H - -/**@{*/ - -#include -#include - -/* --- GPDMA registers ----------------------------------------------------- */ - -/* General registers */ - -/* DMA Interrupt Status Register */ -#define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000) - -/* DMA Interrupt Terminal Count Request Status Register */ -#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004) - -/* DMA Interrupt Terminal Count Request Clear Register */ -#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008) - -/* DMA Interrupt Error Status Register */ -#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C) - -/* DMA Interrupt Error Clear Register */ -#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010) - -/* DMA Raw Interrupt Terminal Count Status Register */ -#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014) - -/* DMA Raw Error Interrupt Status Register */ -#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018) - -/* DMA Enabled Channel Register */ -#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C) - -/* DMA Software Burst Request Register */ -#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020) - -/* DMA Software Single Request Register */ -#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024) - -/* DMA Software Last Burst Request Register */ -#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028) - -/* DMA Software Last Single Request Register */ -#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C) - -/* DMA Configuration Register */ -#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030) - -/* DMA Synchronization Register */ -#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034) - - -/* Channel registers */ - -/* Source Address Register */ -#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \ - (channel * 0x20)) -#define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0) -#define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1) -#define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2) -#define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3) -#define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4) -#define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5) -#define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6) -#define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7) - -/* Destination Address Register */ -#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \ - (channel * 0x20)) -#define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0) -#define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1) -#define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2) -#define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3) -#define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4) -#define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5) -#define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6) -#define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7) - -/* Linked List Item Register */ -#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \ - (channel * 0x20)) -#define GPDMA_C0LLI GPDMA_CLLI(0) -#define GPDMA_C1LLI GPDMA_CLLI(1) -#define GPDMA_C2LLI GPDMA_CLLI(2) -#define GPDMA_C3LLI GPDMA_CLLI(3) -#define GPDMA_C4LLI GPDMA_CLLI(4) -#define GPDMA_C5LLI GPDMA_CLLI(5) -#define GPDMA_C6LLI GPDMA_CLLI(6) -#define GPDMA_C7LLI GPDMA_CLLI(7) - -/* Control Register */ -#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \ - (channel * 0x20)) -#define GPDMA_C0CONTROL GPDMA_CCONTROL(0) -#define GPDMA_C1CONTROL GPDMA_CCONTROL(1) -#define GPDMA_C2CONTROL GPDMA_CCONTROL(2) -#define GPDMA_C3CONTROL GPDMA_CCONTROL(3) -#define GPDMA_C4CONTROL GPDMA_CCONTROL(4) -#define GPDMA_C5CONTROL GPDMA_CCONTROL(5) -#define GPDMA_C6CONTROL GPDMA_CCONTROL(6) -#define GPDMA_C7CONTROL GPDMA_CCONTROL(7) - -/* Configuration Register */ -#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \ - (channel * 0x20)) -#define GPDMA_C0CONFIG GPDMA_CCONFIG(0) -#define GPDMA_C1CONFIG GPDMA_CCONFIG(1) -#define GPDMA_C2CONFIG GPDMA_CCONFIG(2) -#define GPDMA_C3CONFIG GPDMA_CCONFIG(3) -#define GPDMA_C4CONFIG GPDMA_CCONFIG(4) -#define GPDMA_C5CONFIG GPDMA_CCONFIG(5) -#define GPDMA_C6CONFIG GPDMA_CCONFIG(6) -#define GPDMA_C7CONFIG GPDMA_CCONFIG(7) - -/* --- Common fields -------------------------------------------- */ - -#define GPDMA_CSRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT) -#define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT) - -#define GPDMA_CDESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_CDESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) -#define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT) - -#define GPDMA_CLLI_LM_SHIFT (0) -#define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT) -#define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT) - -#define GPDMA_CLLI_LLI_SHIFT (2) -#define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT) -#define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT) - -#define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_CCONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) - -#define GPDMA_CCONTROL_SBSIZE_SHIFT (12) -#define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT) -#define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT) - -#define GPDMA_CCONTROL_DBSIZE_SHIFT (15) -#define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT) -#define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT) - -#define GPDMA_CCONTROL_SWIDTH_SHIFT (18) -#define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT) -#define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT) - -#define GPDMA_CCONTROL_DWIDTH_SHIFT (21) -#define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT) -#define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT) - -#define GPDMA_CCONTROL_S_SHIFT (24) -#define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT) -#define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT) - -#define GPDMA_CCONTROL_D_SHIFT (25) -#define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT) -#define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT) - -#define GPDMA_CCONTROL_SI_SHIFT (26) -#define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT) -#define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT) - -#define GPDMA_CCONTROL_DI_SHIFT (27) -#define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT) -#define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT) - -#define GPDMA_CCONTROL_PROT1_SHIFT (28) -#define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT) -#define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT) - -#define GPDMA_CCONTROL_PROT2_SHIFT (29) -#define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT) -#define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT) - -#define GPDMA_CCONTROL_PROT3_SHIFT (30) -#define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT) -#define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT) - -#define GPDMA_CCONTROL_I_SHIFT (31) -#define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT) -#define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT) - -#define GPDMA_CCONFIG_E_SHIFT (0) -#define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT) -#define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT) - -#define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) - -#define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) - -#define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) - -#define GPDMA_CCONFIG_IE_SHIFT (14) -#define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT) -#define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT) - -#define GPDMA_CCONFIG_ITC_SHIFT (15) -#define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT) -#define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT) - -#define GPDMA_CCONFIG_L_SHIFT (16) -#define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT) -#define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT) - -#define GPDMA_CCONFIG_A_SHIFT (17) -#define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT) -#define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT) - -#define GPDMA_CCONFIG_H_SHIFT (18) -#define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT) -#define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT) - -/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ - -/* --- GPDMA_NTSTAT values -------------------------------------- */ - -/* INTSTAT: Status of DMA channel interrupts after masking */ -#define GPDMA_NTSTAT_INTSTAT_SHIFT (0) -#define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT) -#define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT) - -/* --- GPDMA_INTTCSTAT values ----------------------------------- */ - -/* INTTCSTAT: Terminal count interrupt request status for DMA channels */ -#define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0) -#define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) -#define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) - -/* --- GPDMA_INTTCCLEAR values ---------------------------------- */ - -/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) - for DMA channels */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0) -#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \ - (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) -#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \ - ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) - -/* --- GPDMA_INTERRSTAT values ---------------------------------- */ - -/* INTERRSTAT: Interrupt error status for DMA channels */ -#define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0) -#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \ - (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) -#define GPDMA_INTERRSTAT_INTERRSTAT(x) \ - ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) - -/* --- GPDMA_INTERRCLR values ----------------------------------- */ - -/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) - for DMA channels */ -#define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0) -#define GPDMA_INTERRCLR_INTERRCLR_MASK \ - (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) -#define GPDMA_INTERRCLR_INTERRCLR(x) \ - ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) - -/* --- GPDMA_RAWINTTCSTAT values -------------------------------- */ - -/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels - prior to masking */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0) -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \ - (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \ - ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) - -/* --- GPDMA_RAWINTERRSTAT values ------------------------------- */ - -/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to - masking */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0) -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \ - (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \ - ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) - -/* --- GPDMA_ENBLDCHNS values ----------------------------------- */ - -/* ENABLEDCHANNELS: Enable status for DMA channels */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0) -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \ - (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \ - ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) - -/* --- GPDMA_SOFTBREQ values ------------------------------------ */ - -/* SOFTBREQ: Software burst request flags for each of 16 possible sources */ -#define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0) -#define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) -#define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) - -/* --- GPDMA_SOFTSREQ values ------------------------------------ */ - -/* SOFTSREQ: Software single transfer request flags for each of 16 possible - sources */ -#define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0) -#define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) -#define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) - -/* --- GPDMA_SOFTLBREQ values ----------------------------------- */ - -/* SOFTLBREQ: Software last burst request flags for each of 16 possible - sources */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0) -#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \ - (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) -#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \ - ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) - -/* --- GPDMA_SOFTLSREQ values ----------------------------------- */ - -/* SOFTLSREQ: Software last single transfer request flags for each of 16 - possible sources */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0) -#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \ - (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) -#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \ - ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) - -/* --- GPDMA_CONFIG values -------------------------------------- */ - -/* E: DMA Controller enable */ -#define GPDMA_CONFIG_E_SHIFT (0) -#define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT) -#define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT) - -/* M0: AHB Master 0 endianness configuration */ -#define GPDMA_CONFIG_M0_SHIFT (1) -#define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT) -#define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT) - -/* M1: AHB Master 1 endianness configuration */ -#define GPDMA_CONFIG_M1_SHIFT (2) -#define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT) -#define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT) - -/* --- GPDMA_SYNC values ---------------------------------------- */ - -/* DMACSYNC: Controls the synchronization logic for DMA request signals */ -#define GPDMA_SYNC_DMACSYNC_SHIFT (0) -#define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT) -#define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT) - -/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_CxSRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT) -#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_CxDESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT) -#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C[0..7]LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_CxLLI_LM_SHIFT (0) -#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT) -#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_CxLLI_LLI_SHIFT (2) -#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT) -#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT) - -/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12) -#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT) -#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15) -#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT) -#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18) -#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT) -#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21) -#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT) -#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_CxCONTROL_S_SHIFT (24) -#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT) -#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_CxCONTROL_D_SHIFT (25) -#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT) -#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_CxCONTROL_SI_SHIFT (26) -#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT) -#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_CxCONTROL_DI_SHIFT (27) -#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT) -#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_CxCONTROL_PROT1_SHIFT (28) -#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT) -#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or not - bufferable */ -#define GPDMA_CxCONTROL_PROT2_SHIFT (29) -#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT) -#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_CxCONTROL_PROT3_SHIFT (30) -#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) -#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_CxCONTROL_I_SHIFT (31) -#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT) -#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT) - -/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_CxCONFIG_E_SHIFT (0) -#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT) -#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_CxCONFIG_IE_SHIFT (14) -#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT) -#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_CxCONFIG_ITC_SHIFT (15) -#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT) -#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_CxCONFIG_L_SHIFT (16) -#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT) -#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_CxCONFIG_A_SHIFT (17) -#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT) -#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_CxCONFIG_H_SHIFT (18) -#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT) -#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpio.h b/libopencm3/include/libopencm3/lpc43xx/gpio.h deleted file mode 100644 index c97521a..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/gpio.h +++ /dev/null @@ -1,784 +0,0 @@ -/** @defgroup gpio_defines General Purpose I/O Defines - -@brief Defined Constants and Types for the LPC43xx General Purpose I/O - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_GPIO_H -#define LPC43XX_GPIO_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIO0 (GPIO_PORT_BASE + 0x2000) -#define GPIO1 (GPIO_PORT_BASE + 0x2004) -#define GPIO2 (GPIO_PORT_BASE + 0x2008) -#define GPIO3 (GPIO_PORT_BASE + 0x200C) -#define GPIO4 (GPIO_PORT_BASE + 0x2010) -#define GPIO5 (GPIO_PORT_BASE + 0x2014) -#define GPIO6 (GPIO_PORT_BASE + 0x2018) -#define GPIO7 (GPIO_PORT_BASE + 0x201C) - -/* GPIO number definitions (for convenience) */ -#define GPIOPIN0 (1 << 0) -#define GPIOPIN1 (1 << 1) -#define GPIOPIN2 (1 << 2) -#define GPIOPIN3 (1 << 3) -#define GPIOPIN4 (1 << 4) -#define GPIOPIN5 (1 << 5) -#define GPIOPIN6 (1 << 6) -#define GPIOPIN7 (1 << 7) -#define GPIOPIN8 (1 << 8) -#define GPIOPIN9 (1 << 9) -#define GPIOPIN10 (1 << 10) -#define GPIOPIN11 (1 << 11) -#define GPIOPIN12 (1 << 12) -#define GPIOPIN13 (1 << 13) -#define GPIOPIN14 (1 << 14) -#define GPIOPIN15 (1 << 15) -#define GPIOPIN16 (1 << 16) -#define GPIOPIN17 (1 << 17) -#define GPIOPIN18 (1 << 18) -#define GPIOPIN19 (1 << 19) -#define GPIOPIN20 (1 << 20) -#define GPIOPIN21 (1 << 21) -#define GPIOPIN22 (1 << 22) -#define GPIOPIN23 (1 << 23) -#define GPIOPIN24 (1 << 24) -#define GPIOPIN25 (1 << 25) -#define GPIOPIN26 (1 << 26) -#define GPIOPIN27 (1 << 27) -#define GPIOPIN28 (1 << 28) -#define GPIOPIN29 (1 << 29) -#define GPIOPIN30 (1 << 30) -#define GPIOPIN31 (1 << 31) - -/* --- GPIO registers ------------------------------------------------------ */ - -/* GPIO pin interrupts */ - -/* Pin Interrupt Mode register */ -#define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000) - -/* Pin interrupt level (rising edge) interrupt enable register */ -#define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004) - -/* Pin interrupt level (rising edge) interrupt set register */ -#define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008) - -/* Pin interrupt level (rising edge interrupt) clear register */ -#define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C) - -/* Pin interrupt active level (falling edge) interrupt enable register */ -#define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010) - -/* Pin interrupt active level (falling edge) interrupt set register */ -#define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014) - -/* Pin interrupt active level (falling edge) interrupt clear register */ -#define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018) - -/* Pin interrupt rising edge register */ -#define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C) - -/* Pin interrupt falling edge register */ -#define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020) - -/* Pin interrupt status register */ -#define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024) - -/* GPIO GROUP0 interrupt */ - -/* GPIO grouped interrupt control register */ -#define GPIO_GROUP0_INTERRUPT_CTRL \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) - -/* GPIO grouped interrupt port [0..7] polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4)) - -/* GPIO grouped interrupt port [0..7] enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4)) - -/* GPIO GROUP1 interrupt */ - -/* GPIO grouped interrupt control register */ -#define GPIO_GROUP1_INTERRUPT_CTRL \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) - -/* GPIO grouped interrupt port [0..7] polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4)) - -/* GPIO grouped interrupt port [0..7] enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4)) - -/* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ -#define GPIO_B0 (GPIO_PORT_BASE + 0x0000) -#define GPIO_B1 (GPIO_PORT_BASE + 0x0001) -#define GPIO_B2 (GPIO_PORT_BASE + 0x0002) -#define GPIO_B3 (GPIO_PORT_BASE + 0x0003) -#define GPIO_B4 (GPIO_PORT_BASE + 0x0004) -#define GPIO_B5 (GPIO_PORT_BASE + 0x0005) -#define GPIO_B6 (GPIO_PORT_BASE + 0x0006) -#define GPIO_B7 (GPIO_PORT_BASE + 0x0007) -#define GPIO_B8 (GPIO_PORT_BASE + 0x0008) -#define GPIO_B9 (GPIO_PORT_BASE + 0x0009) -#define GPIO_B10 (GPIO_PORT_BASE + 0x000A) -#define GPIO_B11 (GPIO_PORT_BASE + 0x000B) -#define GPIO_B12 (GPIO_PORT_BASE + 0x000C) -#define GPIO_B13 (GPIO_PORT_BASE + 0x000D) -#define GPIO_B14 (GPIO_PORT_BASE + 0x000E) -#define GPIO_B15 (GPIO_PORT_BASE + 0x000F) -#define GPIO_B16 (GPIO_PORT_BASE + 0x0010) -#define GPIO_B17 (GPIO_PORT_BASE + 0x0011) -#define GPIO_B18 (GPIO_PORT_BASE + 0x0012) -#define GPIO_B19 (GPIO_PORT_BASE + 0x0013) -#define GPIO_B20 (GPIO_PORT_BASE + 0x0014) -#define GPIO_B21 (GPIO_PORT_BASE + 0x0015) -#define GPIO_B22 (GPIO_PORT_BASE + 0x0016) -#define GPIO_B23 (GPIO_PORT_BASE + 0x0017) -#define GPIO_B24 (GPIO_PORT_BASE + 0x0018) -#define GPIO_B25 (GPIO_PORT_BASE + 0x0019) -#define GPIO_B26 (GPIO_PORT_BASE + 0x001A) -#define GPIO_B27 (GPIO_PORT_BASE + 0x001B) -#define GPIO_B28 (GPIO_PORT_BASE + 0x001C) -#define GPIO_B29 (GPIO_PORT_BASE + 0x001D) -#define GPIO_B30 (GPIO_PORT_BASE + 0x001E) -#define GPIO_B31 (GPIO_PORT_BASE + 0x001F) - -/* Byte pin registers port 1 (R/W) */ -#define GPIO_B32 (GPIO_PORT_BASE + 0x0020) -#define GPIO_B33 (GPIO_PORT_BASE + 0x0021) -#define GPIO_B34 (GPIO_PORT_BASE + 0x0022) -#define GPIO_B35 (GPIO_PORT_BASE + 0x0023) -#define GPIO_B36 (GPIO_PORT_BASE + 0x0024) -#define GPIO_B37 (GPIO_PORT_BASE + 0x0025) -#define GPIO_B38 (GPIO_PORT_BASE + 0x0026) -#define GPIO_B39 (GPIO_PORT_BASE + 0x0027) -#define GPIO_B40 (GPIO_PORT_BASE + 0x0028) -#define GPIO_B41 (GPIO_PORT_BASE + 0x0029) -#define GPIO_B42 (GPIO_PORT_BASE + 0x002A) -#define GPIO_B43 (GPIO_PORT_BASE + 0x002B) -#define GPIO_B44 (GPIO_PORT_BASE + 0x002C) -#define GPIO_B45 (GPIO_PORT_BASE + 0x002D) -#define GPIO_B46 (GPIO_PORT_BASE + 0x002E) -#define GPIO_B47 (GPIO_PORT_BASE + 0x002F) -#define GPIO_B48 (GPIO_PORT_BASE + 0x0030) -#define GPIO_B49 (GPIO_PORT_BASE + 0x0031) -#define GPIO_B50 (GPIO_PORT_BASE + 0x0032) -#define GPIO_B51 (GPIO_PORT_BASE + 0x0033) -#define GPIO_B52 (GPIO_PORT_BASE + 0x0034) -#define GPIO_B53 (GPIO_PORT_BASE + 0x0035) -#define GPIO_B54 (GPIO_PORT_BASE + 0x0036) -#define GPIO_B55 (GPIO_PORT_BASE + 0x0037) -#define GPIO_B56 (GPIO_PORT_BASE + 0x0038) -#define GPIO_B57 (GPIO_PORT_BASE + 0x0039) -#define GPIO_B58 (GPIO_PORT_BASE + 0x003A) -#define GPIO_B59 (GPIO_PORT_BASE + 0x003B) -#define GPIO_B60 (GPIO_PORT_BASE + 0x003C) -#define GPIO_B61 (GPIO_PORT_BASE + 0x003D) -#define GPIO_B62 (GPIO_PORT_BASE + 0x003E) -#define GPIO_B63 (GPIO_PORT_BASE + 0x003F) - -/* Byte pin registers port 2 (R/W) */ -#define GPIO_B64 (GPIO_PORT_BASE + 0x0040) -#define GPIO_B65 (GPIO_PORT_BASE + 0x0041) -#define GPIO_B66 (GPIO_PORT_BASE + 0x0042) -#define GPIO_B67 (GPIO_PORT_BASE + 0x0043) -#define GPIO_B68 (GPIO_PORT_BASE + 0x0044) -#define GPIO_B69 (GPIO_PORT_BASE + 0x0045) -#define GPIO_B70 (GPIO_PORT_BASE + 0x0046) -#define GPIO_B71 (GPIO_PORT_BASE + 0x0047) -#define GPIO_B72 (GPIO_PORT_BASE + 0x0048) -#define GPIO_B73 (GPIO_PORT_BASE + 0x0049) -#define GPIO_B74 (GPIO_PORT_BASE + 0x004A) -#define GPIO_B75 (GPIO_PORT_BASE + 0x004B) -#define GPIO_B76 (GPIO_PORT_BASE + 0x004C) -#define GPIO_B77 (GPIO_PORT_BASE + 0x004D) -#define GPIO_B78 (GPIO_PORT_BASE + 0x004E) -#define GPIO_B79 (GPIO_PORT_BASE + 0x004F) -#define GPIO_B80 (GPIO_PORT_BASE + 0x0050) -#define GPIO_B81 (GPIO_PORT_BASE + 0x0051) -#define GPIO_B82 (GPIO_PORT_BASE + 0x0052) -#define GPIO_B83 (GPIO_PORT_BASE + 0x0053) -#define GPIO_B84 (GPIO_PORT_BASE + 0x0054) -#define GPIO_B85 (GPIO_PORT_BASE + 0x0055) -#define GPIO_B86 (GPIO_PORT_BASE + 0x0056) -#define GPIO_B87 (GPIO_PORT_BASE + 0x0057) -#define GPIO_B88 (GPIO_PORT_BASE + 0x0058) -#define GPIO_B89 (GPIO_PORT_BASE + 0x0059) -#define GPIO_B90 (GPIO_PORT_BASE + 0x005A) -#define GPIO_B91 (GPIO_PORT_BASE + 0x005B) -#define GPIO_B92 (GPIO_PORT_BASE + 0x005C) -#define GPIO_B93 (GPIO_PORT_BASE + 0x005D) -#define GPIO_B94 (GPIO_PORT_BASE + 0x005E) -#define GPIO_B95 (GPIO_PORT_BASE + 0x005F) - -/* Byte pin registers port 3 (R/W) */ -#define GPIO_B96 (GPIO_PORT_BASE + 0x0060) -#define GPIO_B97 (GPIO_PORT_BASE + 0x0061) -#define GPIO_B98 (GPIO_PORT_BASE + 0x0062) -#define GPIO_B99 (GPIO_PORT_BASE + 0x0063) -#define GPIO_B100 (GPIO_PORT_BASE + 0x0064) -#define GPIO_B101 (GPIO_PORT_BASE + 0x0065) -#define GPIO_B102 (GPIO_PORT_BASE + 0x0066) -#define GPIO_B103 (GPIO_PORT_BASE + 0x0067) -#define GPIO_B104 (GPIO_PORT_BASE + 0x0068) -#define GPIO_B105 (GPIO_PORT_BASE + 0x0069) -#define GPIO_B106 (GPIO_PORT_BASE + 0x006A) -#define GPIO_B107 (GPIO_PORT_BASE + 0x006B) -#define GPIO_B108 (GPIO_PORT_BASE + 0x006C) -#define GPIO_B109 (GPIO_PORT_BASE + 0x006D) -#define GPIO_B110 (GPIO_PORT_BASE + 0x006E) -#define GPIO_B111 (GPIO_PORT_BASE + 0x006F) -#define GPIO_B112 (GPIO_PORT_BASE + 0x0070) -#define GPIO_B113 (GPIO_PORT_BASE + 0x0071) -#define GPIO_B114 (GPIO_PORT_BASE + 0x0072) -#define GPIO_B115 (GPIO_PORT_BASE + 0x0073) -#define GPIO_B116 (GPIO_PORT_BASE + 0x0074) -#define GPIO_B117 (GPIO_PORT_BASE + 0x0075) -#define GPIO_B118 (GPIO_PORT_BASE + 0x0076) -#define GPIO_B119 (GPIO_PORT_BASE + 0x0077) -#define GPIO_B120 (GPIO_PORT_BASE + 0x0078) -#define GPIO_B121 (GPIO_PORT_BASE + 0x0079) -#define GPIO_B122 (GPIO_PORT_BASE + 0x007A) -#define GPIO_B123 (GPIO_PORT_BASE + 0x007B) -#define GPIO_B124 (GPIO_PORT_BASE + 0x007C) -#define GPIO_B125 (GPIO_PORT_BASE + 0x007D) -#define GPIO_B126 (GPIO_PORT_BASE + 0x007E) -#define GPIO_B127 (GPIO_PORT_BASE + 0x007F) - -/* Byte pin registers port 4 (R/W) */ -#define GPIO_B128 (GPIO_PORT_BASE + 0x0080) -#define GPIO_B129 (GPIO_PORT_BASE + 0x0081) -#define GPIO_B130 (GPIO_PORT_BASE + 0x0082) -#define GPIO_B131 (GPIO_PORT_BASE + 0x0083) -#define GPIO_B132 (GPIO_PORT_BASE + 0x0084) -#define GPIO_B133 (GPIO_PORT_BASE + 0x0085) -#define GPIO_B134 (GPIO_PORT_BASE + 0x0086) -#define GPIO_B135 (GPIO_PORT_BASE + 0x0087) -#define GPIO_B136 (GPIO_PORT_BASE + 0x0088) -#define GPIO_B137 (GPIO_PORT_BASE + 0x0089) -#define GPIO_B138 (GPIO_PORT_BASE + 0x008A) -#define GPIO_B139 (GPIO_PORT_BASE + 0x008B) -#define GPIO_B140 (GPIO_PORT_BASE + 0x008C) -#define GPIO_B141 (GPIO_PORT_BASE + 0x008D) -#define GPIO_B142 (GPIO_PORT_BASE + 0x008E) -#define GPIO_B143 (GPIO_PORT_BASE + 0x008F) -#define GPIO_B144 (GPIO_PORT_BASE + 0x0090) -#define GPIO_B145 (GPIO_PORT_BASE + 0x0091) -#define GPIO_B146 (GPIO_PORT_BASE + 0x0092) -#define GPIO_B147 (GPIO_PORT_BASE + 0x0093) -#define GPIO_B148 (GPIO_PORT_BASE + 0x0094) -#define GPIO_B149 (GPIO_PORT_BASE + 0x0095) -#define GPIO_B150 (GPIO_PORT_BASE + 0x0096) -#define GPIO_B151 (GPIO_PORT_BASE + 0x0097) -#define GPIO_B152 (GPIO_PORT_BASE + 0x0098) -#define GPIO_B153 (GPIO_PORT_BASE + 0x0099) -#define GPIO_B154 (GPIO_PORT_BASE + 0x009A) -#define GPIO_B155 (GPIO_PORT_BASE + 0x009B) -#define GPIO_B156 (GPIO_PORT_BASE + 0x009C) -#define GPIO_B157 (GPIO_PORT_BASE + 0x009D) -#define GPIO_B158 (GPIO_PORT_BASE + 0x009E) -#define GPIO_B159 (GPIO_PORT_BASE + 0x009F) - -/* Byte pin registers port 5 (R/W) */ -#define GPIO_B160 (GPIO_PORT_BASE + 0x00A0) -#define GPIO_B161 (GPIO_PORT_BASE + 0x00A1) -#define GPIO_B162 (GPIO_PORT_BASE + 0x00A2) -#define GPIO_B163 (GPIO_PORT_BASE + 0x00A3) -#define GPIO_B164 (GPIO_PORT_BASE + 0x00A4) -#define GPIO_B165 (GPIO_PORT_BASE + 0x00A5) -#define GPIO_B166 (GPIO_PORT_BASE + 0x00A6) -#define GPIO_B167 (GPIO_PORT_BASE + 0x00A7) -#define GPIO_B168 (GPIO_PORT_BASE + 0x00A8) -#define GPIO_B169 (GPIO_PORT_BASE + 0x00A9) -#define GPIO_B170 (GPIO_PORT_BASE + 0x00AA) -#define GPIO_B171 (GPIO_PORT_BASE + 0x00AB) -#define GPIO_B172 (GPIO_PORT_BASE + 0x00AC) -#define GPIO_B173 (GPIO_PORT_BASE + 0x00AD) -#define GPIO_B174 (GPIO_PORT_BASE + 0x00AE) -#define GPIO_B175 (GPIO_PORT_BASE + 0x00AF) -#define GPIO_B176 (GPIO_PORT_BASE + 0x00B0) -#define GPIO_B177 (GPIO_PORT_BASE + 0x00B1) -#define GPIO_B178 (GPIO_PORT_BASE + 0x00B2) -#define GPIO_B179 (GPIO_PORT_BASE + 0x00B3) -#define GPIO_B180 (GPIO_PORT_BASE + 0x00B4) -#define GPIO_B181 (GPIO_PORT_BASE + 0x00B5) -#define GPIO_B182 (GPIO_PORT_BASE + 0x00B6) -#define GPIO_B183 (GPIO_PORT_BASE + 0x00B7) -#define GPIO_B184 (GPIO_PORT_BASE + 0x00B8) -#define GPIO_B185 (GPIO_PORT_BASE + 0x00B9) -#define GPIO_B186 (GPIO_PORT_BASE + 0x00BA) -#define GPIO_B187 (GPIO_PORT_BASE + 0x00BB) -#define GPIO_B188 (GPIO_PORT_BASE + 0x00BC) -#define GPIO_B189 (GPIO_PORT_BASE + 0x00BD) -#define GPIO_B190 (GPIO_PORT_BASE + 0x00BE) -#define GPIO_B191 (GPIO_PORT_BASE + 0x00BF) - -/* Byte pin registers port 6 (R/W) */ -#define GPIO_B192 (GPIO_PORT_BASE + 0x00C0) -#define GPIO_B193 (GPIO_PORT_BASE + 0x00C1) -#define GPIO_B194 (GPIO_PORT_BASE + 0x00C2) -#define GPIO_B195 (GPIO_PORT_BASE + 0x00C3) -#define GPIO_B196 (GPIO_PORT_BASE + 0x00C4) -#define GPIO_B197 (GPIO_PORT_BASE + 0x00C5) -#define GPIO_B198 (GPIO_PORT_BASE + 0x00C6) -#define GPIO_B199 (GPIO_PORT_BASE + 0x00C7) -#define GPIO_B200 (GPIO_PORT_BASE + 0x00C8) -#define GPIO_B201 (GPIO_PORT_BASE + 0x00C9) -#define GPIO_B202 (GPIO_PORT_BASE + 0x00CA) -#define GPIO_B203 (GPIO_PORT_BASE + 0x00CB) -#define GPIO_B204 (GPIO_PORT_BASE + 0x00CC) -#define GPIO_B205 (GPIO_PORT_BASE + 0x00CD) -#define GPIO_B206 (GPIO_PORT_BASE + 0x00CE) -#define GPIO_B207 (GPIO_PORT_BASE + 0x00CF) -#define GPIO_B208 (GPIO_PORT_BASE + 0x00D0) -#define GPIO_B209 (GPIO_PORT_BASE + 0x00D1) -#define GPIO_B210 (GPIO_PORT_BASE + 0x00D2) -#define GPIO_B211 (GPIO_PORT_BASE + 0x00D3) -#define GPIO_B212 (GPIO_PORT_BASE + 0x00D4) -#define GPIO_B213 (GPIO_PORT_BASE + 0x00D5) -#define GPIO_B214 (GPIO_PORT_BASE + 0x00D6) -#define GPIO_B215 (GPIO_PORT_BASE + 0x00D7) -#define GPIO_B216 (GPIO_PORT_BASE + 0x00D8) -#define GPIO_B217 (GPIO_PORT_BASE + 0x00D9) -#define GPIO_B218 (GPIO_PORT_BASE + 0x00DA) -#define GPIO_B219 (GPIO_PORT_BASE + 0x00DB) -#define GPIO_B220 (GPIO_PORT_BASE + 0x00DC) -#define GPIO_B221 (GPIO_PORT_BASE + 0x00DD) -#define GPIO_B222 (GPIO_PORT_BASE + 0x00DE) -#define GPIO_B223 (GPIO_PORT_BASE + 0x00DF) - -/* Byte pin registers port 7 (R/W) */ -#define GPIO_B224 (GPIO_PORT_BASE + 0x00E0) -#define GPIO_B225 (GPIO_PORT_BASE + 0x00E1) -#define GPIO_B226 (GPIO_PORT_BASE + 0x00E2) -#define GPIO_B227 (GPIO_PORT_BASE + 0x00E3) -#define GPIO_B228 (GPIO_PORT_BASE + 0x00E4) -#define GPIO_B229 (GPIO_PORT_BASE + 0x00E5) -#define GPIO_B230 (GPIO_PORT_BASE + 0x00E6) -#define GPIO_B231 (GPIO_PORT_BASE + 0x00E7) -#define GPIO_B232 (GPIO_PORT_BASE + 0x00E8) -#define GPIO_B233 (GPIO_PORT_BASE + 0x00E9) -#define GPIO_B234 (GPIO_PORT_BASE + 0x00EA) -#define GPIO_B235 (GPIO_PORT_BASE + 0x00EB) -#define GPIO_B236 (GPIO_PORT_BASE + 0x00EC) -#define GPIO_B237 (GPIO_PORT_BASE + 0x00ED) -#define GPIO_B238 (GPIO_PORT_BASE + 0x00EE) -#define GPIO_B239 (GPIO_PORT_BASE + 0x00EF) -#define GPIO_B240 (GPIO_PORT_BASE + 0x00F0) -#define GPIO_B241 (GPIO_PORT_BASE + 0x00F1) -#define GPIO_B242 (GPIO_PORT_BASE + 0x00F2) -#define GPIO_B243 (GPIO_PORT_BASE + 0x00F3) -#define GPIO_B244 (GPIO_PORT_BASE + 0x00F4) -#define GPIO_B245 (GPIO_PORT_BASE + 0x00F5) -#define GPIO_B246 (GPIO_PORT_BASE + 0x00F6) -#define GPIO_B247 (GPIO_PORT_BASE + 0x00F7) -#define GPIO_B248 (GPIO_PORT_BASE + 0x00F8) -#define GPIO_B249 (GPIO_PORT_BASE + 0x00F9) -#define GPIO_B250 (GPIO_PORT_BASE + 0x00FA) -#define GPIO_B251 (GPIO_PORT_BASE + 0x00FB) -#define GPIO_B252 (GPIO_PORT_BASE + 0x00FC) -#define GPIO_B253 (GPIO_PORT_BASE + 0x00FD) -#define GPIO_B254 (GPIO_PORT_BASE + 0x00FE) -#define GPIO_B255 (GPIO_PORT_BASE + 0x00FF) - -/* Word pin registers port 0 (R/W) */ -#define GPIO_W0 (GPIO_PORT_BASE + 0x1000) -#define GPIO_W1 (GPIO_PORT_BASE + 0x1004) -#define GPIO_W2 (GPIO_PORT_BASE + 0x1008) -#define GPIO_W3 (GPIO_PORT_BASE + 0x100C) -#define GPIO_W4 (GPIO_PORT_BASE + 0x1010) -#define GPIO_W5 (GPIO_PORT_BASE + 0x1014) -#define GPIO_W6 (GPIO_PORT_BASE + 0x1018) -#define GPIO_W7 (GPIO_PORT_BASE + 0x101C) -#define GPIO_W8 (GPIO_PORT_BASE + 0x1020) -#define GPIO_W9 (GPIO_PORT_BASE + 0x1024) -#define GPIO_W10 (GPIO_PORT_BASE + 0x1028) -#define GPIO_W11 (GPIO_PORT_BASE + 0x102C) -#define GPIO_W12 (GPIO_PORT_BASE + 0x1030) -#define GPIO_W13 (GPIO_PORT_BASE + 0x1034) -#define GPIO_W14 (GPIO_PORT_BASE + 0x1038) -#define GPIO_W15 (GPIO_PORT_BASE + 0x103C) -#define GPIO_W16 (GPIO_PORT_BASE + 0x1040) -#define GPIO_W17 (GPIO_PORT_BASE + 0x1044) -#define GPIO_W18 (GPIO_PORT_BASE + 0x1048) -#define GPIO_W19 (GPIO_PORT_BASE + 0x104C) -#define GPIO_W20 (GPIO_PORT_BASE + 0x1050) -#define GPIO_W21 (GPIO_PORT_BASE + 0x1054) -#define GPIO_W22 (GPIO_PORT_BASE + 0x1058) -#define GPIO_W23 (GPIO_PORT_BASE + 0x105C) -#define GPIO_W24 (GPIO_PORT_BASE + 0x1060) -#define GPIO_W25 (GPIO_PORT_BASE + 0x1064) -#define GPIO_W26 (GPIO_PORT_BASE + 0x1068) -#define GPIO_W27 (GPIO_PORT_BASE + 0x106C) -#define GPIO_W28 (GPIO_PORT_BASE + 0x1070) -#define GPIO_W29 (GPIO_PORT_BASE + 0x1074) -#define GPIO_W30 (GPIO_PORT_BASE + 0x1078) -#define GPIO_W31 (GPIO_PORT_BASE + 0x107C) - -/* Word pin registers port 1 (R/W) */ -#define GPIO_W32 (GPIO_PORT_BASE + 0x1080) -#define GPIO_W33 (GPIO_PORT_BASE + 0x1084) -#define GPIO_W34 (GPIO_PORT_BASE + 0x1088) -#define GPIO_W35 (GPIO_PORT_BASE + 0x108C) -#define GPIO_W36 (GPIO_PORT_BASE + 0x1090) -#define GPIO_W37 (GPIO_PORT_BASE + 0x1094) -#define GPIO_W38 (GPIO_PORT_BASE + 0x1098) -#define GPIO_W39 (GPIO_PORT_BASE + 0x109C) -#define GPIO_W40 (GPIO_PORT_BASE + 0x10A0) -#define GPIO_W41 (GPIO_PORT_BASE + 0x10A4) -#define GPIO_W42 (GPIO_PORT_BASE + 0x10A8) -#define GPIO_W43 (GPIO_PORT_BASE + 0x10AC) -#define GPIO_W44 (GPIO_PORT_BASE + 0x10B0) -#define GPIO_W45 (GPIO_PORT_BASE + 0x10B4) -#define GPIO_W46 (GPIO_PORT_BASE + 0x10B8) -#define GPIO_W47 (GPIO_PORT_BASE + 0x10BC) -#define GPIO_W48 (GPIO_PORT_BASE + 0x10C0) -#define GPIO_W49 (GPIO_PORT_BASE + 0x10C4) -#define GPIO_W50 (GPIO_PORT_BASE + 0x10C8) -#define GPIO_W51 (GPIO_PORT_BASE + 0x10CC) -#define GPIO_W52 (GPIO_PORT_BASE + 0x10D0) -#define GPIO_W53 (GPIO_PORT_BASE + 0x10D4) -#define GPIO_W54 (GPIO_PORT_BASE + 0x10D8) -#define GPIO_W55 (GPIO_PORT_BASE + 0x10DC) -#define GPIO_W56 (GPIO_PORT_BASE + 0x10E0) -#define GPIO_W57 (GPIO_PORT_BASE + 0x10E4) -#define GPIO_W58 (GPIO_PORT_BASE + 0x10E8) -#define GPIO_W59 (GPIO_PORT_BASE + 0x10EC) -#define GPIO_W60 (GPIO_PORT_BASE + 0x10F0) -#define GPIO_W61 (GPIO_PORT_BASE + 0x10F4) -#define GPIO_W62 (GPIO_PORT_BASE + 0x10F8) -#define GPIO_W63 (GPIO_PORT_BASE + 0x10FC) - -/* Word pin registers port 2 (R/W) */ -#define GPIO_W64 (GPIO_PORT_BASE + 0x1100) -#define GPIO_W65 (GPIO_PORT_BASE + 0x1104) -#define GPIO_W66 (GPIO_PORT_BASE + 0x1108) -#define GPIO_W67 (GPIO_PORT_BASE + 0x110C) -#define GPIO_W68 (GPIO_PORT_BASE + 0x1110) -#define GPIO_W69 (GPIO_PORT_BASE + 0x1114) -#define GPIO_W70 (GPIO_PORT_BASE + 0x1118) -#define GPIO_W71 (GPIO_PORT_BASE + 0x111C) -#define GPIO_W72 (GPIO_PORT_BASE + 0x1120) -#define GPIO_W73 (GPIO_PORT_BASE + 0x1124) -#define GPIO_W74 (GPIO_PORT_BASE + 0x1128) -#define GPIO_W75 (GPIO_PORT_BASE + 0x112C) -#define GPIO_W76 (GPIO_PORT_BASE + 0x1130) -#define GPIO_W77 (GPIO_PORT_BASE + 0x1134) -#define GPIO_W78 (GPIO_PORT_BASE + 0x1138) -#define GPIO_W79 (GPIO_PORT_BASE + 0x113C) -#define GPIO_W80 (GPIO_PORT_BASE + 0x1140) -#define GPIO_W81 (GPIO_PORT_BASE + 0x1144) -#define GPIO_W82 (GPIO_PORT_BASE + 0x1148) -#define GPIO_W83 (GPIO_PORT_BASE + 0x114C) -#define GPIO_W84 (GPIO_PORT_BASE + 0x1150) -#define GPIO_W85 (GPIO_PORT_BASE + 0x1154) -#define GPIO_W86 (GPIO_PORT_BASE + 0x1158) -#define GPIO_W87 (GPIO_PORT_BASE + 0x115C) -#define GPIO_W88 (GPIO_PORT_BASE + 0x1160) -#define GPIO_W89 (GPIO_PORT_BASE + 0x1164) -#define GPIO_W90 (GPIO_PORT_BASE + 0x1168) -#define GPIO_W91 (GPIO_PORT_BASE + 0x116C) -#define GPIO_W92 (GPIO_PORT_BASE + 0x1170) -#define GPIO_W93 (GPIO_PORT_BASE + 0x1174) -#define GPIO_W94 (GPIO_PORT_BASE + 0x1178) -#define GPIO_W95 (GPIO_PORT_BASE + 0x117C) - -/* Word pin registers port 3 (R/W) */ -#define GPIO_W96 (GPIO_PORT_BASE + 0x1180) -#define GPIO_W97 (GPIO_PORT_BASE + 0x1184) -#define GPIO_W98 (GPIO_PORT_BASE + 0x1188) -#define GPIO_W99 (GPIO_PORT_BASE + 0x118C) -#define GPIO_W100 (GPIO_PORT_BASE + 0x1190) -#define GPIO_W101 (GPIO_PORT_BASE + 0x1194) -#define GPIO_W102 (GPIO_PORT_BASE + 0x1198) -#define GPIO_W103 (GPIO_PORT_BASE + 0x119C) -#define GPIO_W104 (GPIO_PORT_BASE + 0x11A0) -#define GPIO_W105 (GPIO_PORT_BASE + 0x11A4) -#define GPIO_W106 (GPIO_PORT_BASE + 0x11A8) -#define GPIO_W107 (GPIO_PORT_BASE + 0x11AC) -#define GPIO_W108 (GPIO_PORT_BASE + 0x11B0) -#define GPIO_W109 (GPIO_PORT_BASE + 0x11B4) -#define GPIO_W110 (GPIO_PORT_BASE + 0x11B8) -#define GPIO_W111 (GPIO_PORT_BASE + 0x11BC) -#define GPIO_W112 (GPIO_PORT_BASE + 0x11C0) -#define GPIO_W113 (GPIO_PORT_BASE + 0x11C4) -#define GPIO_W114 (GPIO_PORT_BASE + 0x11C8) -#define GPIO_W115 (GPIO_PORT_BASE + 0x11CC) -#define GPIO_W116 (GPIO_PORT_BASE + 0x11D0) -#define GPIO_W117 (GPIO_PORT_BASE + 0x11D4) -#define GPIO_W118 (GPIO_PORT_BASE + 0x11D8) -#define GPIO_W119 (GPIO_PORT_BASE + 0x11DC) -#define GPIO_W120 (GPIO_PORT_BASE + 0x11E0) -#define GPIO_W121 (GPIO_PORT_BASE + 0x11E4) -#define GPIO_W122 (GPIO_PORT_BASE + 0x11E8) -#define GPIO_W123 (GPIO_PORT_BASE + 0x11EC) -#define GPIO_W124 (GPIO_PORT_BASE + 0x11F0) -#define GPIO_W125 (GPIO_PORT_BASE + 0x11F4) -#define GPIO_W126 (GPIO_PORT_BASE + 0x11F8) -#define GPIO_W127 (GPIO_PORT_BASE + 0x11FC) - -/* Word pin registers port 4 (R/W) */ -#define GPIO_W128 (GPIO_PORT_BASE + 0x1200) -#define GPIO_W129 (GPIO_PORT_BASE + 0x1204) -#define GPIO_W130 (GPIO_PORT_BASE + 0x1208) -#define GPIO_W131 (GPIO_PORT_BASE + 0x120C) -#define GPIO_W132 (GPIO_PORT_BASE + 0x1210) -#define GPIO_W133 (GPIO_PORT_BASE + 0x1214) -#define GPIO_W134 (GPIO_PORT_BASE + 0x1218) -#define GPIO_W135 (GPIO_PORT_BASE + 0x121C) -#define GPIO_W136 (GPIO_PORT_BASE + 0x1220) -#define GPIO_W137 (GPIO_PORT_BASE + 0x1224) -#define GPIO_W138 (GPIO_PORT_BASE + 0x1228) -#define GPIO_W139 (GPIO_PORT_BASE + 0x122C) -#define GPIO_W140 (GPIO_PORT_BASE + 0x1230) -#define GPIO_W141 (GPIO_PORT_BASE + 0x1234) -#define GPIO_W142 (GPIO_PORT_BASE + 0x1238) -#define GPIO_W143 (GPIO_PORT_BASE + 0x123C) -#define GPIO_W144 (GPIO_PORT_BASE + 0x1240) -#define GPIO_W145 (GPIO_PORT_BASE + 0x1244) -#define GPIO_W146 (GPIO_PORT_BASE + 0x1248) -#define GPIO_W147 (GPIO_PORT_BASE + 0x124C) -#define GPIO_W148 (GPIO_PORT_BASE + 0x1250) -#define GPIO_W149 (GPIO_PORT_BASE + 0x1254) -#define GPIO_W150 (GPIO_PORT_BASE + 0x1258) -#define GPIO_W151 (GPIO_PORT_BASE + 0x125C) -#define GPIO_W152 (GPIO_PORT_BASE + 0x1260) -#define GPIO_W153 (GPIO_PORT_BASE + 0x1264) -#define GPIO_W154 (GPIO_PORT_BASE + 0x1268) -#define GPIO_W155 (GPIO_PORT_BASE + 0x126C) -#define GPIO_W156 (GPIO_PORT_BASE + 0x1270) -#define GPIO_W157 (GPIO_PORT_BASE + 0x1274) -#define GPIO_W158 (GPIO_PORT_BASE + 0x1278) -#define GPIO_W159 (GPIO_PORT_BASE + 0x127C) - -/* Word pin registers port 5 (R/W) */ -#define GPIO_W160 (GPIO_PORT_BASE + 0x1280) -#define GPIO_W161 (GPIO_PORT_BASE + 0x1284) -#define GPIO_W162 (GPIO_PORT_BASE + 0x1288) -#define GPIO_W163 (GPIO_PORT_BASE + 0x128C) -#define GPIO_W164 (GPIO_PORT_BASE + 0x1290) -#define GPIO_W165 (GPIO_PORT_BASE + 0x1294) -#define GPIO_W166 (GPIO_PORT_BASE + 0x1298) -#define GPIO_W167 (GPIO_PORT_BASE + 0x129C) -#define GPIO_W168 (GPIO_PORT_BASE + 0x12A0) -#define GPIO_W169 (GPIO_PORT_BASE + 0x12A4) -#define GPIO_W170 (GPIO_PORT_BASE + 0x12A8) -#define GPIO_W171 (GPIO_PORT_BASE + 0x12AC) -#define GPIO_W172 (GPIO_PORT_BASE + 0x12B0) -#define GPIO_W173 (GPIO_PORT_BASE + 0x12B4) -#define GPIO_W174 (GPIO_PORT_BASE + 0x12B8) -#define GPIO_W175 (GPIO_PORT_BASE + 0x12BC) -#define GPIO_W176 (GPIO_PORT_BASE + 0x12C0) -#define GPIO_W177 (GPIO_PORT_BASE + 0x12C4) -#define GPIO_W178 (GPIO_PORT_BASE + 0x12C8) -#define GPIO_W179 (GPIO_PORT_BASE + 0x12CC) -#define GPIO_W180 (GPIO_PORT_BASE + 0x12D0) -#define GPIO_W181 (GPIO_PORT_BASE + 0x12D4) -#define GPIO_W182 (GPIO_PORT_BASE + 0x12D8) -#define GPIO_W183 (GPIO_PORT_BASE + 0x12DC) -#define GPIO_W184 (GPIO_PORT_BASE + 0x12E0) -#define GPIO_W185 (GPIO_PORT_BASE + 0x12E4) -#define GPIO_W186 (GPIO_PORT_BASE + 0x12E8) -#define GPIO_W187 (GPIO_PORT_BASE + 0x12EC) -#define GPIO_W188 (GPIO_PORT_BASE + 0x12F0) -#define GPIO_W189 (GPIO_PORT_BASE + 0x12F4) -#define GPIO_W190 (GPIO_PORT_BASE + 0x12F8) -#define GPIO_W191 (GPIO_PORT_BASE + 0x12FC) - -/* Word pin registers port 6 (R/W) */ -#define GPIO_W192 (GPIO_PORT_BASE + 0x1300) -#define GPIO_W193 (GPIO_PORT_BASE + 0x1304) -#define GPIO_W194 (GPIO_PORT_BASE + 0x1308) -#define GPIO_W195 (GPIO_PORT_BASE + 0x130C) -#define GPIO_W196 (GPIO_PORT_BASE + 0x1310) -#define GPIO_W197 (GPIO_PORT_BASE + 0x1314) -#define GPIO_W198 (GPIO_PORT_BASE + 0x1318) -#define GPIO_W199 (GPIO_PORT_BASE + 0x131C) -#define GPIO_W200 (GPIO_PORT_BASE + 0x1320) -#define GPIO_W201 (GPIO_PORT_BASE + 0x1324) -#define GPIO_W202 (GPIO_PORT_BASE + 0x1328) -#define GPIO_W203 (GPIO_PORT_BASE + 0x132C) -#define GPIO_W204 (GPIO_PORT_BASE + 0x1330) -#define GPIO_W205 (GPIO_PORT_BASE + 0x1334) -#define GPIO_W206 (GPIO_PORT_BASE + 0x1338) -#define GPIO_W207 (GPIO_PORT_BASE + 0x133C) -#define GPIO_W208 (GPIO_PORT_BASE + 0x1340) -#define GPIO_W209 (GPIO_PORT_BASE + 0x1344) -#define GPIO_W210 (GPIO_PORT_BASE + 0x1348) -#define GPIO_W211 (GPIO_PORT_BASE + 0x134C) -#define GPIO_W212 (GPIO_PORT_BASE + 0x1350) -#define GPIO_W213 (GPIO_PORT_BASE + 0x1354) -#define GPIO_W214 (GPIO_PORT_BASE + 0x1358) -#define GPIO_W215 (GPIO_PORT_BASE + 0x135C) -#define GPIO_W216 (GPIO_PORT_BASE + 0x1360) -#define GPIO_W217 (GPIO_PORT_BASE + 0x1364) -#define GPIO_W218 (GPIO_PORT_BASE + 0x1368) -#define GPIO_W219 (GPIO_PORT_BASE + 0x136C) -#define GPIO_W220 (GPIO_PORT_BASE + 0x1370) -#define GPIO_W221 (GPIO_PORT_BASE + 0x1374) -#define GPIO_W222 (GPIO_PORT_BASE + 0x1378) -#define GPIO_W223 (GPIO_PORT_BASE + 0x137C) - -/* Word pin registers port 7 (R/W) */ -#define GPIO_W224 (GPIO_PORT_BASE + 0x1380) -#define GPIO_W225 (GPIO_PORT_BASE + 0x1384) -#define GPIO_W226 (GPIO_PORT_BASE + 0x1388) -#define GPIO_W227 (GPIO_PORT_BASE + 0x138C) -#define GPIO_W228 (GPIO_PORT_BASE + 0x1390) -#define GPIO_W229 (GPIO_PORT_BASE + 0x1394) -#define GPIO_W230 (GPIO_PORT_BASE + 0x1398) -#define GPIO_W231 (GPIO_PORT_BASE + 0x139C) -#define GPIO_W232 (GPIO_PORT_BASE + 0x13A0) -#define GPIO_W233 (GPIO_PORT_BASE + 0x13A4) -#define GPIO_W234 (GPIO_PORT_BASE + 0x13A8) -#define GPIO_W235 (GPIO_PORT_BASE + 0x13AC) -#define GPIO_W236 (GPIO_PORT_BASE + 0x13B0) -#define GPIO_W237 (GPIO_PORT_BASE + 0x13B4) -#define GPIO_W238 (GPIO_PORT_BASE + 0x13B8) -#define GPIO_W239 (GPIO_PORT_BASE + 0x13BC) -#define GPIO_W240 (GPIO_PORT_BASE + 0x13C0) -#define GPIO_W241 (GPIO_PORT_BASE + 0x13C4) -#define GPIO_W242 (GPIO_PORT_BASE + 0x13C8) -#define GPIO_W243 (GPIO_PORT_BASE + 0x13CC) -#define GPIO_W244 (GPIO_PORT_BASE + 0x13D0) -#define GPIO_W245 (GPIO_PORT_BASE + 0x13D4) -#define GPIO_W246 (GPIO_PORT_BASE + 0x13D8) -#define GPIO_W247 (GPIO_PORT_BASE + 0x13DC) -#define GPIO_W248 (GPIO_PORT_BASE + 0x13E0) -#define GPIO_W249 (GPIO_PORT_BASE + 0x13E4) -#define GPIO_W250 (GPIO_PORT_BASE + 0x13E8) -#define GPIO_W251 (GPIO_PORT_BASE + 0x13EC) -#define GPIO_W252 (GPIO_PORT_BASE + 0x13F0) -#define GPIO_W253 (GPIO_PORT_BASE + 0x13F4) -#define GPIO_W254 (GPIO_PORT_BASE + 0x13F8) -#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC) - -/* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32((port) + 0x00) -#define GPIO0_DIR GPIO_DIR(GPIO0) -#define GPIO1_DIR GPIO_DIR(GPIO1) -#define GPIO2_DIR GPIO_DIR(GPIO2) -#define GPIO3_DIR GPIO_DIR(GPIO3) -#define GPIO4_DIR GPIO_DIR(GPIO4) -#define GPIO5_DIR GPIO_DIR(GPIO5) -#define GPIO6_DIR GPIO_DIR(GPIO6) -#define GPIO7_DIR GPIO_DIR(GPIO7) - -/* GPIO fast mask register (GPIOn_MASK) */ -#define GPIO_MASK(port) MMIO32((port) + 0x80) -#define GPIO0_MASK GPIO_MASK(GPIO0) -#define GPIO1_MASK GPIO_MASK(GPIO1) -#define GPIO2_MASK GPIO_MASK(GPIO2) -#define GPIO3_MASK GPIO_MASK(GPIO3) -#define GPIO4_MASK GPIO_MASK(GPIO4) -#define GPIO5_MASK GPIO_MASK(GPIO5) -#define GPIO6_MASK GPIO_MASK(GPIO6) -#define GPIO7_MASK GPIO_MASK(GPIO7) - -/* GPIO port pin value register (GPIOn_PIN) */ -#define GPIO_PIN(port) MMIO32((port) + 0x100) -#define GPIO0_PIN GPIO_PIN(GPIO0) -#define GPIO1_PIN GPIO_PIN(GPIO1) -#define GPIO2_PIN GPIO_PIN(GPIO2) -#define GPIO3_PIN GPIO_PIN(GPIO3) -#define GPIO4_PIN GPIO_PIN(GPIO4) -#define GPIO5_PIN GPIO_PIN(GPIO5) -#define GPIO6_PIN GPIO_PIN(GPIO6) -#define GPIO7_PIN GPIO_PIN(GPIO7) - -/* GPIO port masked pin value register (GPIOn_MPIN) */ -#define GPIO_MPIN(port) MMIO32((port) + 0x180) -#define GPIO0_MPIN GPIO_MPIN(GPIO0) -#define GPIO1_MPIN GPIO_MPIN(GPIO1) -#define GPIO2_MPIN GPIO_MPIN(GPIO2) -#define GPIO3_MPIN GPIO_MPIN(GPIO3) -#define GPIO4_MPIN GPIO_MPIN(GPIO4) -#define GPIO5_MPIN GPIO_MPIN(GPIO5) -#define GPIO6_MPIN GPIO_MPIN(GPIO6) -#define GPIO7_MPIN GPIO_MPIN(GPIO7) - -/* GPIO port output set register (GPIOn_SET) */ -#define GPIO_SET(port) MMIO32((port) + 0x200) -#define GPIO0_SET GPIO_SET(GPIO0) -#define GPIO1_SET GPIO_SET(GPIO1) -#define GPIO2_SET GPIO_SET(GPIO2) -#define GPIO3_SET GPIO_SET(GPIO3) -#define GPIO4_SET GPIO_SET(GPIO4) -#define GPIO5_SET GPIO_SET(GPIO5) -#define GPIO6_SET GPIO_SET(GPIO6) -#define GPIO7_SET GPIO_SET(GPIO7) - -/* GPIO port output clear register (GPIOn_CLR) */ -#define GPIO_CLR(port) MMIO32((port) + 0x280) -#define GPIO0_CLR GPIO_CLR(GPIO0) -#define GPIO1_CLR GPIO_CLR(GPIO1) -#define GPIO2_CLR GPIO_CLR(GPIO2) -#define GPIO3_CLR GPIO_CLR(GPIO3) -#define GPIO4_CLR GPIO_CLR(GPIO4) -#define GPIO5_CLR GPIO_CLR(GPIO5) -#define GPIO6_CLR GPIO_CLR(GPIO6) -#define GPIO7_CLR GPIO_CLR(GPIO7) - -/* GPIO port toggle register (GPIOn_NOT) */ -#define GPIO_NOT(port) MMIO32((port) + 0x300) -#define GPIO0_NOT GPIO_NOT(GPIO0) -#define GPIO1_NOT GPIO_NOT(GPIO1) -#define GPIO2_NOT GPIO_NOT(GPIO2) -#define GPIO3_NOT GPIO_NOT(GPIO3) -#define GPIO4_NOT GPIO_NOT(GPIO4) -#define GPIO5_NOT GPIO_NOT(GPIO5) -#define GPIO6_NOT GPIO_NOT(GPIO6) -#define GPIO7_NOT GPIO_NOT(GPIO7) - -/* TODO interrupts */ - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint32_t gpios); -void gpio_clear(uint32_t gpioport, uint32_t gpios); -void gpio_toggle(uint32_t gpioport, uint32_t gpios); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2c.h b/libopencm3/include/libopencm3/lpc43xx/i2c.h deleted file mode 100644 index 23c8896..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/i2c.h +++ /dev/null @@ -1,164 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the LPC43xx I2C - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_I2C_H -#define LPC43XX_I2C_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C port base addresses (for convenience) */ -#define I2C0 I2C0_BASE -#define I2C1 I2C1_BASE - -/* --- I2C registers ------------------------------------------------------- */ - -/* I2C Control Set Register */ -#define I2C_CONSET(port) MMIO32((port) + 0x000) -#define I2C0_CONSET I2C_CONSET(I2C0) -#define I2C1_CONSET I2C_CONSET(I2C1) - -/* I2C Status Register */ -#define I2C_STAT(port) MMIO32((port) + 0x004) -#define I2C0_STAT I2C_STAT(I2C0) -#define I2C1_STAT I2C_STAT(I2C1) - -/* I2C Data Register */ -#define I2C_DAT(port) MMIO32((port) + 0x008) -#define I2C0_DAT I2C_DAT(I2C0) -#define I2C1_DAT I2C_DAT(I2C1) - -/* I2C Slave Address Register 0 */ -#define I2C_ADR0(port) MMIO32((port) + 0x00C) -#define I2C0_ADR0 I2C_ADR0(I2C0) -#define I2C1_ADR0 I2C_ADR0(I2C1) - -/* SCH Duty Cycle Register High Half Word */ -#define I2C_SCLH(port) MMIO32((port) + 0x010) -#define I2C0_SCLH I2C_SCLH(I2C0) -#define I2C1_SCLH I2C_SCLH(I2C1) - -/* SCL Duty Cycle Register Low Half Word */ -#define I2C_SCLL(port) MMIO32((port) + 0x014) -#define I2C0_SCLL I2C_SCLL(I2C0) -#define I2C1_SCLL I2C_SCLL(I2C1) - -/* I2C Control Clear Register */ -#define I2C_CONCLR(port) MMIO32((port) + 0x018) -#define I2C0_CONCLR I2C_CONCLR(I2C0) -#define I2C1_CONCLR I2C_CONCLR(I2C1) - -/* Monitor mode control register */ -#define I2C_MMCTRL(port) MMIO32((port) + 0x01C) -#define I2C0_MMCTRL I2C_MMCTRL(I2C0) -#define I2C1_MMCTRL I2C_MMCTRL(I2C1) - -/* I2C Slave Address Register 1 */ -#define I2C_ADR1(port) MMIO32((port) + 0x020) -#define I2C0_ADR1 I2C_ADR1(I2C0) -#define I2C1_ADR1 I2C_ADR1(I2C1) - -/* I2C Slave Address Register 2 */ -#define I2C_ADR2(port) MMIO32((port) + 0x024) -#define I2C0_ADR2 I2C_ADR2(I2C0) -#define I2C1_ADR2 I2C_ADR2(I2C1) - -/* I2C Slave Address Register 3 */ -#define I2C_ADR3(port) MMIO32((port) + 0x028) -#define I2C0_ADR3 I2C_ADR3(I2C0) -#define I2C1_ADR3 I2C_ADR3(I2C1) - -/* Data buffer register */ -#define I2C_DATA_BUFFER(port) MMIO32((port) + 0x02C) -#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0) -#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1) - -/* I2C Slave address mask register 0 */ -#define I2C_MASK0(port) MMIO32((port) + 0x030) -#define I2C0_MASK0 I2C_MASK0(I2C0) -#define I2C1_MASK0 I2C_MASK0(I2C1) - -/* I2C Slave address mask register 1 */ -#define I2C_MASK1(port) MMIO32((port) + 0x034) -#define I2C0_MASK1 I2C_MASK1(I2C0) -#define I2C1_MASK1 I2C_MASK1(I2C1) - -/* I2C Slave address mask register 2 */ -#define I2C_MASK2(port) MMIO32((port) + 0x038) -#define I2C0_MASK2 I2C_MASK2(I2C0) -#define I2C1_MASK2 I2C_MASK2(I2C1) - -/* I2C Slave address mask register 3 */ -#define I2C_MASK3(port) MMIO32((port) + 0x03C) -#define I2C0_MASK3 I2C_MASK3(I2C0) -#define I2C1_MASK3 I2C_MASK3(I2C1) - -/* --- I2Cx_CONCLR values -------------------------------------------------- */ - -#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ -#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ -#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ -#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ - -/* --- I2Cx_CONSET values -------------------------------------------------- */ - -#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ - -/* --- I2C const definitions ----------------------------------------------- */ - -#define I2C_WRITE 0 -#define I2C_READ 1 - -/* --- I2C function prototypes --------------------------------------------- */ - -BEGIN_DECLS - -void i2c0_init(const uint16_t duty_cycle_count); -void i2c0_tx_start(void); -void i2c0_tx_byte(uint8_t byte); -uint8_t i2c0_rx_byte(void); -void i2c0_stop(void); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2s.h b/libopencm3/include/libopencm3/lpc43xx/i2s.h deleted file mode 100644 index 442f5bd..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/i2s.h +++ /dev/null @@ -1,122 +0,0 @@ -/** @defgroup i2s_defines I2S Defines - -@brief Defined Constants and Types for the LPC43xx I2S - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_I2S_H -#define LPC43XX_I2S_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2S port base addresses (for convenience) */ -#define I2S0 I2S0_BASE -#define I2S1 I2S1_BASE - -/* --- I2S registers ------------------------------------------------------- */ - -/* I2S Digital Audio Output Register */ -#define I2S_DAO(port) MMIO32((port) + 0x000) -#define I2S0_DAO I2S_DAO(I2S0) -#define I2S1_DAO I2S_DAO(I2S1) - -/* I2S Digital Audio Input Register */ -#define I2S_DAI(port) MMIO32((port) + 0x004) -#define I2S0_DAI I2S_DAI(I2S0) -#define I2S1_DAI I2S_DAI(I2S1) - -/* I2S Transmit FIFO */ -#define I2S_TXFIFO(port) MMIO32((port) + 0x008) -#define I2S0_TXFIFO I2S_TXFIFO(I2S0) -#define I2S1_TXFIFO I2S_TXFIFO(I2S1) - -/* I2S Receive FIFO */ -#define I2S_RXFIFO(port) MMIO32((port) + 0x00C) -#define I2S0_RXFIFO I2S_RXFIFO(I2S0) -#define I2S1_RXFIFO I2S_RXFIFO(I2S1) - -/* I2S Status Feedback Register */ -#define I2S_STATE(port) MMIO32((port) + 0x010) -#define I2S0_STATE I2S_STATE(I2S0) -#define I2S1_STATE I2S_STATE(I2S1) - -/* I2S DMA Configuration Register 1 */ -#define I2S_DMA1(port) MMIO32((port) + 0x014) -#define I2S0_DMA1 I2S_DMA1(I2S0) -#define I2S1_DMA1 I2S_DMA1(I2S1) - -/* I2S DMA Configuration Register 2 */ -#define I2S_DMA2(port) MMIO32((port) + 0x018) -#define I2S0_DMA2 I2S_DMA2(I2S0) -#define I2S1_DMA2 I2S_DMA2(I2S1) - -/* I2S Interrupt Request Control Register */ -#define I2S_IRQ(port) MMIO32((port) + 0x01C) -#define I2S0_IRQ I2S_IRQ(I2S0) -#define I2S1_IRQ I2S_IRQ(I2S1) - -/* I2S Transmit MCLK divider */ -#define I2S_TXRATE(port) MMIO32((port) + 0x020) -#define I2S0_TXRATE I2S_TXRATE(I2S0) -#define I2S1_TXRATE I2S_TXRATE(I2S1) - -/* I2S Receive MCLK divider */ -#define I2S_RXRATE(port) MMIO32((port) + 0x024) -#define I2S0_RXRATE I2S_RXRATE(I2S0) -#define I2S1_RXRATE I2S_RXRATE(I2S1) - -/* I2S Transmit bit rate divider */ -#define I2S_TXBITRATE(port) MMIO32((port) + 0x028) -#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0) -#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1) - -/* I2S Receive bit rate divider */ -#define I2S_RXBITRATE(port) MMIO32((port) + 0x02C) -#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0) -#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1) - -/* I2S Transmit mode control */ -#define I2S_TXMODE(port) MMIO32((port) + 0x030) -#define I2S0_TXMODE I2S_TXMODE(I2S0) -#define I2S1_TXMODE I2S_TXMODE(I2S1) - -/* I2S Receive mode control */ -#define I2S_RXMODE(port) MMIO32((port) + 0x034) -#define I2S0_RXMODE I2S_RXMODE(I2S0) -#define I2S1_RXMODE I2S_RXMODE(I2S1) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ipc.h b/libopencm3/include/libopencm3/lpc43xx/ipc.h deleted file mode 100644 index ddd81b8..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/ipc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* -* This file is part of the libopencm3 project. -* -* Copyright (C) 2012 Benjamin Vernoux -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published by -* the Free Software Foundation, either version 3 of the License, or -* (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -*/ - -#ifndef LPC43XX_IPC_H -#define LPC43XX_IPC_H - -#include -#include - -void ipc_halt_m0(void); - -void ipc_start_m0(uint32_t cm0_baseaddr); - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/m0/irq.json b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json deleted file mode 100644 index 828c1dd..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/m0/irq.json +++ /dev/null @@ -1,36 +0,0 @@ -{ - "irqs": { - "0": "rtc", - "1": "m4core", - "2": "dma", - "4": "flasheepromat", - "5": "ethernet", - "6": "sdio", - "7": "lcd", - "8": "usb0", - "9": "usb1", - "10": "sct", - "11": "ritimer_or_wwdt", - "12": "timer0", - "13": "gint1", - "14": "pin_int4", - "15": "timer3", - "16": "mcpwm", - "17": "adc0", - "18": "i2c0_or_irc1", - "19": "sgpio", - "20": "spi_or_dac", - "21": "adc1", - "22": "ssp0_or_ssp1", - "23": "eventrouter", - "24": "usart0", - "25": "uart1", - "26": "usart2_or_c_can1", - "27": "usart3", - "28": "i2s0_or_i2s1", - "29": "c_can0" - }, - "partname_humanreadable": "LPC 43xx series M0 core", - "partname_doxygen": "LPC43xx (M0)", - "includeguard": "LIBOPENCM3_LPC43xx_M0_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/m4/irq.json b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json deleted file mode 100644 index 376fab1..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/m4/irq.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "irqs": { - "0": "dac", - "1": "m0core", - "2": "dma", - "5": "ethernet", - "6": "sdio", - "7": "lcd", - "8": "usb0", - "9": "usb1", - "10": "sct", - "11": "ritimer", - "12": "timer0", - "13": "timer1", - "14": "timer2", - "15": "timer3", - "16": "mcpwm", - "17": "adc0", - "18": "i2c0", - "19": "i2c1", - "20": "spi", - "21": "adc1", - "22": "ssp0", - "23": "ssp1", - "24": "usart0", - "25": "uart1", - "26": "usart2", - "27": "usart3", - "28": "i2s0", - "29": "i2s1", - "30": "spifi", - "31": "sgpio", - "32": "pin_int0", - "33": "pin_int1", - "34": "pin_int2", - "35": "pin_int3", - "36": "pin_int4", - "37": "pin_int5", - "38": "pin_int6", - "39": "pin_int7", - "40": "gint0", - "41": "gint1", - "42": "eventrouter", - "43": "c_can1", - "46": "atimer", - "47": "rtc", - "49": "wwdt", - "51": "c_can0", - "52": "qei" - }, - "partname_humanreadable": "LPC 43xx series M4 core", - "partname_doxygen": "LPC43xx (M4)", - "includeguard": "LIBOPENCM3_LPC43xx_M4_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/memorymap.h b/libopencm3/include/libopencm3/lpc43xx/memorymap.h deleted file mode 100644 index 5d2bdc4..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/memorymap.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_MEMORYMAP_H -#define LPC43XX_MEMORYMAP_H - -#include - -/* --- LPC43XX specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE_AHB (0x40000000U) -#define PERIPH_BASE_APB0 (0x40080000U) -#define PERIPH_BASE_APB1 (0x400A0000U) -#define PERIPH_BASE_APB2 (0x400C0000U) -#define PERIPH_BASE_APB3 (0x400E0000U) - -/* Register boundary addresses */ - -/* AHB (0x4000 0000 - 0x4001 2000) */ -#define SCT_BASE (PERIPH_BASE_AHB + 0x00000) -/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */ -#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000) -#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000) -#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000) -#define EMC_BASE (PERIPH_BASE_AHB + 0x05000) -#define USB0_BASE (PERIPH_BASE_AHB + 0x06000) -#define USB1_BASE (PERIPH_BASE_AHB + 0x07000) -#define LCD_BASE (PERIPH_BASE_AHB + 0x08000) -/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) - -/* 0x4001 2000 - 0x4003 FFFF Reserved */ - -/* RTC domain peripherals */ -#define ATIMER_BASE (0x40040000U) -#define BACKUP_REG_BASE (0x40041000U) -#define PMC_BASE (0x40042000U) -#define CREG_BASE (0x40043000U) -#define EVENTROUTER_BASE (0x40044000U) -#define OTP_BASE (0x40045000U) -#define RTC_BASE (0x40046000U) -/* 0x4004 7000 - 0x4004 FFFF Reserved */ - -/* clocking/reset control peripherals */ -#define CGU_BASE (0x40050000U) -#define CCU1_BASE (0x40051000U) -#define CCU2_BASE (0x40052000U) -#define RGU_BASE (0x40053000U) -/* 0x4005 4000 - 0x4005 FFFF Reserved */ - -/* 0x4006 0000 - 0x4007 FFFF Reserved */ - -/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */ -#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000) -#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000) -#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000) -#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000) -#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) -#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000) -#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000) -#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000) -#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000) -#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000) -/* 0x4008 A000 - 0x4008 FFFF Reserved */ - -/* 0x4009 0000 - 0x4009 FFFF Reserved */ - -/* APB1 (0x400A 0000 - 0x400A FFFF) */ -#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000) -#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000) -#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000) -#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000) -#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000) -/* 0x400A 5000 - 0x400A FFFF Reserved */ - -/* 0x400B 0000 - 0x400B FFFF Reserved */ - -/* APB2 (0x400C 0000 - 0x400C FFFF) */ -#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000) -#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000) -#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000) -#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000) -#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000) -#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000) -#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000) -#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000) -/* 0x400C 8000 - 0x400C FFFF Reserved */ - -/* 0x400D 0000 - 0x400D FFFF Reserved */ - -/* APB3 (0x400E 0000 - 0x400E FFFF) */ -#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000) -#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000) -#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000) -#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000) -#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000) -/* 0x400E 5000 - 0x400E FFFF Reserved */ - -/* 0x400F 0000 - 0x400F 0FFF Reserved */ - -#define AES_BASE (0x400F1000U) - -/* 0x400F 2000 - 0x400F 3FFF Reserved */ - -#define GPIO_PORT_BASE (0x400F4000U) - -/* 0x400F 8000 - 0x400F FFFF Reserved */ - -#define SPI_PORT_BASE (0x40100000U) -#define SGPIO_PORT_BASE (0x40101000U) - -/* 0x4010 2000 - 0x41FF FFFF Reserved */ - -/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */ - -/* 0x4400 0000 - 0x5FFF FFFF Reserved */ - -/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/rgu.h b/libopencm3/include/libopencm3/lpc43xx/rgu.h deleted file mode 100644 index 0ec0146..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/rgu.h +++ /dev/null @@ -1,1206 +0,0 @@ -/** @defgroup rgu_defines Reset Generation Unit Defines - -@brief Defined Constants and Types for the LPC43xx Reset Generation Unit - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_RGU_H -#define LPC43XX_RGU_H - -/**@{*/ - -#include -#include - -/* --- RGU registers ------------------------------------------------------- */ - -/* Reset control register 0 */ -#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100) - -/* Reset control register 1 */ -#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104) - -/* Reset status register 0 */ -#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110) - -/* Reset status register 1 */ -#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114) - -/* Reset status register 2 */ -#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118) - -/* Reset status register 3 */ -#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C) - -/* Reset active status register 0 */ -#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150) - -/* Reset active status register 1 */ -#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154) - -/* Reset external status register 0 for CORE_RST */ -#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400) - -/* Reset external status register 1 for PERIPH_RST */ -#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404) - -/* Reset external status register 2 for MASTER_RST */ -#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408) - -/* Reserved */ -#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C) - -/* Reset external status register 4 for WWDT_RST */ -#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410) - -/* Reset external status register 5 for CREG_RST */ -#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414) - -/* Reserved */ -#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418) - -/* Reserved */ -#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C) - -/* Reset external status register 8 for BUS_RST */ -#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420) - -/* Reset external status register 9 for SCU_RST */ -#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424) - -/* Reserved */ -#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428) - -/* Reserved */ -#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C) - -/* Reserved */ -#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430) - -/* Reset external status register 13 for M4_RST */ -#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434) - -/* Reserved */ -#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438) - -/* Reserved */ -#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C) - -/* Reset external status register 16 for LCD_RST */ -#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440) - -/* Reset external status register 17 for USB0_RST */ -#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444) - -/* Reset external status register 18 for USB1_RST */ -#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448) - -/* Reset external status register 19 for DMA_RST */ -#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C) - -/* Reset external status register 20 for SDIO_RST */ -#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450) - -/* Reset external status register 21 for EMC_RST */ -#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454) - -/* Reset external status register 22 for ETHERNET_RST */ -#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458) - -/* Reserved */ -#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C) - -/* Reserved */ -#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460) - -/* Reserved */ -#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464) - -/* Reserved */ -#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468) - -/* Reserved */ -#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C) - -/* Reset external status register 28 for GPIO_RST */ -#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470) - -/* Reserved */ -#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474) - -/* Reserved */ -#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478) - -/* Reserved */ -#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C) - -/* Reset external status register 32 for TIMER0_RST */ -#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480) - -/* Reset external status register 33 for TIMER1_RST */ -#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484) - -/* Reset external status register 34 for TIMER2_RST */ -#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488) - -/* Reset external status register 35 for TIMER3_RST */ -#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C) - -/* Reset external status register 36 for RITIMER_RST */ -#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490) - -/* Reset external status register 37 for SCT_RST */ -#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494) - -/* Reset external status register 38 for MOTOCONPWM_RST */ -#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498) - -/* Reset external status register 39 for QEI_RST */ -#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C) - -/* Reset external status register 40 for ADC0_RST */ -#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0) - -/* Reset external status register 41 for ADC1_RST */ -#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4) - -/* Reset external status register 42 for DAC_RST */ -#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8) - -/* Reserved */ -#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC) - -/* Reset external status register 44 for UART0_RST */ -#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0) - -/* Reset external status register 45 for UART1_RST */ -#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4) - -/* Reset external status register 46 for UART2_RST */ -#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8) - -/* Reset external status register 47 for UART3_RST */ -#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC) - -/* Reset external status register 48 for I2C0_RST */ -#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0) - -/* Reset external status register 49 for I2C1_RST */ -#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4) - -/* Reset external status register 50 for SSP0_RST */ -#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8) - -/* Reset external status register 51 for SSP1_RST */ -#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC) - -/* Reset external status register 52 for I2S_RST */ -#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0) - -/* Reset external status register 53 for SPIFI_RST */ -#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4) - -/* Reset external status register 54 for CAN1_RST */ -#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8) - -/* Reset external status register 55 for CAN0_RST */ -#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC) - -/* Reset external status register 56 for M0APP_RST */ -#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0) - -/* Reset external status register 57 for SGPIO_RST */ -#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4) - -/* Reset external status register 58 for SPI_RST */ -#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8) - -/* Reserved */ -#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC) - -/* Reserved */ -#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0) - -/* Reserved */ -#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4) - -/* Reserved */ -#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8) - -/* Reserved */ -#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) - -/* --- RESET_CTRL0 values --------------------------------------- */ - -/* CORE_RST: Writing a one activates the reset */ -#define RESET_CTRL0_CORE_RST_SHIFT (0) -#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) - -/* PERIPH_RST: Writing a one activates the reset */ -#define RESET_CTRL0_PERIPH_RST_SHIFT (1) -#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) - -/* MASTER_RST: Writing a one activates the reset */ -#define RESET_CTRL0_MASTER_RST_SHIFT (2) -#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) - -/* WWDT_RST: Writing a one to this bit has no effect */ -#define RESET_CTRL0_WWDT_RST_SHIFT (4) -#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) - -/* CREG_RST: Writing a one to this bit has no effect */ -#define RESET_CTRL0_CREG_RST_SHIFT (5) -#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) - -/* BUS_RST: Writing a one activates the reset */ -#define RESET_CTRL0_BUS_RST_SHIFT (8) -#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) - -/* SCU_RST: Writing a one activates the reset */ -#define RESET_CTRL0_SCU_RST_SHIFT (9) -#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) - -/* M4_RST: Writing a one activates the reset */ -#define RESET_CTRL0_M4_RST_SHIFT (13) -#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) - -/* LCD_RST: Writing a one activates the reset */ -#define RESET_CTRL0_LCD_RST_SHIFT (16) -#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) - -/* USB0_RST: Writing a one activates the reset */ -#define RESET_CTRL0_USB0_RST_SHIFT (17) -#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) - -/* USB1_RST: Writing a one activates the reset */ -#define RESET_CTRL0_USB1_RST_SHIFT (18) -#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) - -/* DMA_RST: Writing a one activates the reset */ -#define RESET_CTRL0_DMA_RST_SHIFT (19) -#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) - -/* SDIO_RST: Writing a one activates the reset */ -#define RESET_CTRL0_SDIO_RST_SHIFT (20) -#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) - -/* EMC_RST: Writing a one activates the reset */ -#define RESET_CTRL0_EMC_RST_SHIFT (21) -#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) - -/* ETHERNET_RST: Writing a one activates the reset */ -#define RESET_CTRL0_ETHERNET_RST_SHIFT (22) -#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) - -/* FLASHA_RST: Writing a one activates the reset */ -#define RESET_CTRL0_FLASHA_RST_SHIFT (25) -#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) - -/* EEPROM_RST: Writing a one activates the reset */ -#define RESET_CTRL0_EEPROM_RST_SHIFT (27) -#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) - -/* GPIO_RST: Writing a one activates the reset */ -#define RESET_CTRL0_GPIO_RST_SHIFT (28) -#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) - -/* FLASHB_RST: Writing a one activates the reset */ -#define RESET_CTRL0_FLASHB_RST_SHIFT (29) -#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) - -/* --- RESET_CTRL1 values --------------------------------------- */ - -/* TIMER0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_TIMER0_RST_SHIFT (0) -#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) - -/* TIMER1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_TIMER1_RST_SHIFT (1) -#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) - -/* TIMER2_RST: Writing a one activates the reset */ -#define RESET_CTRL1_TIMER2_RST_SHIFT (2) -#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) - -/* TIMER3_RST: Writing a one activates the reset */ -#define RESET_CTRL1_TIMER3_RST_SHIFT (3) -#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) - -/* RTIMER_RST: Writing a one activates the reset */ -#define RESET_CTRL1_RTIMER_RST_SHIFT (4) -#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) - -/* SCT_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SCT_RST_SHIFT (5) -#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) - -/* MOTOCONPWM_RST: Writing a one activates the reset */ -#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) -#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) - -/* QEI_RST: Writing a one activates the reset */ -#define RESET_CTRL1_QEI_RST_SHIFT (7) -#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) - -/* ADC0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_ADC0_RST_SHIFT (8) -#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) - -/* ADC1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_ADC1_RST_SHIFT (9) -#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) - -/* DAC_RST: Writing a one activates the reset */ -#define RESET_CTRL1_DAC_RST_SHIFT (10) -#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) - -/* UART0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_UART0_RST_SHIFT (12) -#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) - -/* UART1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_UART1_RST_SHIFT (13) -#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) - -/* UART2_RST: Writing a one activates the reset */ -#define RESET_CTRL1_UART2_RST_SHIFT (14) -#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) - -/* UART3_RST: Writing a one activates the reset */ -#define RESET_CTRL1_UART3_RST_SHIFT (15) -#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) - -/* I2C0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_I2C0_RST_SHIFT (16) -#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) - -/* I2C1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_I2C1_RST_SHIFT (17) -#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) - -/* SSP0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SSP0_RST_SHIFT (18) -#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) - -/* SSP1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SSP1_RST_SHIFT (19) -#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) - -/* I2S_RST: Writing a one activates the reset */ -#define RESET_CTRL1_I2S_RST_SHIFT (20) -#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) - -/* SPIFI_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SPIFI_RST_SHIFT (21) -#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) - -/* CAN1_RST: Writing a one activates the reset */ -#define RESET_CTRL1_CAN1_RST_SHIFT (22) -#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) - -/* CAN0_RST: Writing a one activates the reset */ -#define RESET_CTRL1_CAN0_RST_SHIFT (23) -#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) - -/* M0APP_RST: Writing a one activates the reset */ -#define RESET_CTRL1_M0APP_RST_SHIFT (24) -#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) - -/* SGPIO_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SGPIO_RST_SHIFT (25) -#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) - -/* SPI_RST: Writing a one activates the reset */ -#define RESET_CTRL1_SPI_RST_SHIFT (26) -#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) - -/* --- RESET_STATUS0 values ------------------------------------- */ - -/* CORE_RST: Status of the CORE_RST reset generator output */ -#define RESET_STATUS0_CORE_RST_SHIFT (0) -#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) -#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) - -/* PERIPH_RST: Status of the PERIPH_RST reset generator output */ -#define RESET_STATUS0_PERIPH_RST_SHIFT (2) -#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) -#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) - -/* MASTER_RST: Status of the MASTER_RST reset generator output */ -#define RESET_STATUS0_MASTER_RST_SHIFT (4) -#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) -#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) - -/* WWDT_RST: Status of the WWDT_RST reset generator output */ -#define RESET_STATUS0_WWDT_RST_SHIFT (8) -#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) -#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) - -/* CREG_RST: Status of the CREG_RST reset generator output */ -#define RESET_STATUS0_CREG_RST_SHIFT (10) -#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) -#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) - -/* BUS_RST: Status of the BUS_RST reset generator output */ -#define RESET_STATUS0_BUS_RST_SHIFT (16) -#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) -#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) - -/* SCU_RST: Status of the SCU_RST reset generator output */ -#define RESET_STATUS0_SCU_RST_SHIFT (18) -#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) -#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) - -/* M4_RST: Status of the M4_RST reset generator output */ -#define RESET_STATUS0_M4_RST_SHIFT (26) -#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) -#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) - -/* --- RESET_STATUS1 values ------------------------------------- */ - -/* LCD_RST: Status of the LCD_RST reset generator output */ -#define RESET_STATUS1_LCD_RST_SHIFT (0) -#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) -#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) - -/* USB0_RST: Status of the USB0_RST reset generator output */ -#define RESET_STATUS1_USB0_RST_SHIFT (2) -#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) -#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) - -/* USB1_RST: Status of the USB1_RST reset generator output */ -#define RESET_STATUS1_USB1_RST_SHIFT (4) -#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) -#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) - -/* DMA_RST: Status of the DMA_RST reset generator output */ -#define RESET_STATUS1_DMA_RST_SHIFT (6) -#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) -#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) - -/* SDIO_RST: Status of the SDIO_RST reset generator output */ -#define RESET_STATUS1_SDIO_RST_SHIFT (8) -#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) -#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) - -/* EMC_RST: Status of the EMC_RST reset generator output */ -#define RESET_STATUS1_EMC_RST_SHIFT (10) -#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) -#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) - -/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ -#define RESET_STATUS1_ETHERNET_RST_SHIFT (12) -#define RESET_STATUS1_ETHERNET_RST_MASK \ - (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) -#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) - -/* FLASHA_RST: Status of the FLASHA_RST reset generator output */ -#define RESET_STATUS1_FLASHA_RST_SHIFT (18) -#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) -#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) - -/* EEPROM_RST: Status of the EEPROM_RST reset generator output */ -#define RESET_STATUS1_EEPROM_RST_SHIFT (22) -#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) -#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) - -/* GPIO_RST: Status of the GPIO_RST reset generator output */ -#define RESET_STATUS1_GPIO_RST_SHIFT (24) -#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) -#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) - -/* FLASHB_RST: Status of the FLASHB_RST reset generator output */ -#define RESET_STATUS1_FLASHB_RST_SHIFT (26) -#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) -#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) - -/* --- RESET_STATUS2 values ------------------------------------- */ - -/* TIMER0_RST: Status of the TIMER0_RST reset generator output */ -#define RESET_STATUS2_TIMER0_RST_SHIFT (0) -#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) -#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) - -/* TIMER1_RST: Status of the TIMER1_RST reset generator output */ -#define RESET_STATUS2_TIMER1_RST_SHIFT (2) -#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) -#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) - -/* TIMER2_RST: Status of the TIMER2_RST reset generator output */ -#define RESET_STATUS2_TIMER2_RST_SHIFT (4) -#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) -#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) - -/* TIMER3_RST: Status of the TIMER3_RST reset generator output */ -#define RESET_STATUS2_TIMER3_RST_SHIFT (6) -#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) -#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) - -/* RITIMER_RST: Status of the RITIMER_RST reset generator output */ -#define RESET_STATUS2_RITIMER_RST_SHIFT (8) -#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) -#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) - -/* SCT_RST: Status of the SCT_RST reset generator output */ -#define RESET_STATUS2_SCT_RST_SHIFT (10) -#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) -#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) - -/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ -#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) -#define RESET_STATUS2_MOTOCONPWM_RST_MASK \ - (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) -#define RESET_STATUS2_MOTOCONPWM_RST(x) \ - ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) - -/* QEI_RST: Status of the QEI_RST reset generator output */ -#define RESET_STATUS2_QEI_RST_SHIFT (14) -#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) -#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) - -/* ADC0_RST: Status of the ADC0_RST reset generator output */ -#define RESET_STATUS2_ADC0_RST_SHIFT (16) -#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) -#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) - -/* ADC1_RST: Status of the ADC1_RST reset generator output */ -#define RESET_STATUS2_ADC1_RST_SHIFT (18) -#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) -#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) - -/* DAC_RST: Status of the DAC_RST reset generator output */ -#define RESET_STATUS2_DAC_RST_SHIFT (20) -#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) -#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) - -/* UART0_RST: Status of the UART0_RST reset generator output */ -#define RESET_STATUS2_UART0_RST_SHIFT (24) -#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) -#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) - -/* UART1_RST: Status of the UART1_RST reset generator output */ -#define RESET_STATUS2_UART1_RST_SHIFT (26) -#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) -#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) - -/* UART2_RST: Status of the UART2_RST reset generator output */ -#define RESET_STATUS2_UART2_RST_SHIFT (28) -#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) -#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) - -/* UART3_RST: Status of the UART3_RST reset generator output */ -#define RESET_STATUS2_UART3_RST_SHIFT (30) -#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) -#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) - -/* --- RESET_STATUS3 values ------------------------------------- */ - -/* I2C0_RST: Status of the I2C0_RST reset generator output */ -#define RESET_STATUS3_I2C0_RST_SHIFT (0) -#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) -#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) - -/* I2C1_RST: Status of the I2C1_RST reset generator output */ -#define RESET_STATUS3_I2C1_RST_SHIFT (2) -#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) -#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) - -/* SSP0_RST: Status of the SSP0_RST reset generator output */ -#define RESET_STATUS3_SSP0_RST_SHIFT (4) -#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) -#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) - -/* SSP1_RST: Status of the SSP1_RST reset generator output */ -#define RESET_STATUS3_SSP1_RST_SHIFT (6) -#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) -#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) - -/* I2S_RST: Status of the I2S_RST reset generator output */ -#define RESET_STATUS3_I2S_RST_SHIFT (8) -#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) -#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) - -/* SPIFI_RST: Status of the SPIFI_RST reset generator output */ -#define RESET_STATUS3_SPIFI_RST_SHIFT (10) -#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) -#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) - -/* CAN1_RST: Status of the CAN1_RST reset generator output */ -#define RESET_STATUS3_CAN1_RST_SHIFT (12) -#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) -#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) - -/* CAN0_RST: Status of the CAN0_RST reset generator output */ -#define RESET_STATUS3_CAN0_RST_SHIFT (14) -#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) -#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) - -/* M0APP_RST: Status of the M0APP_RST reset generator output */ -#define RESET_STATUS3_M0APP_RST_SHIFT (16) -#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) -#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) - -/* SGPIO_RST: Status of the SGPIO_RST reset generator output */ -#define RESET_STATUS3_SGPIO_RST_SHIFT (18) -#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) -#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) - -/* SPI_RST: Status of the SPI_RST reset generator output */ -#define RESET_STATUS3_SPI_RST_SHIFT (20) -#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) -#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) - -/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */ - -/* CORE_RST: Current status of the CORE_RST */ -#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) -#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) - -/* PERIPH_RST: Current status of the PERIPH_RST */ -#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) -#define RESET_ACTIVE_STATUS0_PERIPH_RST \ - (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) - -/* MASTER_RST: Current status of the MASTER_RST */ -#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) -#define RESET_ACTIVE_STATUS0_MASTER_RST \ - (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) - -/* WWDT_RST: Current status of the WWDT_RST */ -#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) -#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) - -/* CREG_RST: Current status of the CREG_RST */ -#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) -#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) - -/* BUS_RST: Current status of the BUS_RST */ -#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) -#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) - -/* SCU_RST: Current status of the SCU_RST */ -#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) -#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) - -/* M4_RST: Current status of the M4_RST */ -#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) -#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) - -/* LCD_RST: Current status of the LCD_RST */ -#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) -#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) - -/* USB0_RST: Current status of the USB0_RST */ -#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) -#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) - -/* USB1_RST: Current status of the USB1_RST */ -#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) -#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) - -/* DMA_RST: Current status of the DMA_RST */ -#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) -#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) - -/* SDIO_RST: Current status of the SDIO_RST */ -#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) -#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) - -/* EMC_RST: Current status of the EMC_RST */ -#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) -#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) - -/* ETHERNET_RST: Current status of the ETHERNET_RST */ -#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) -#define RESET_ACTIVE_STATUS0_ETHERNET_RST \ - (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) - -/* FLASHA_RST: Current status of the FLASHA_RST */ -#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) -#define RESET_ACTIVE_STATUS0_FLASHA_RST \ - (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) - -/* EEPROM_RST: Current status of the EEPROM_RST */ -#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) -#define RESET_ACTIVE_STATUS0_EEPROM_RST \ - (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) - -/* GPIO_RST: Current status of the GPIO_RST */ -#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) -#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) - -/* FLASHB_RST: Current status of the FLASHB_RST */ -#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) -#define RESET_ACTIVE_STATUS0_FLASHB_RST \ - (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) - -/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ - -/* TIMER0_RST: Current status of the TIMER0_RST */ -#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) -#define RESET_ACTIVE_STATUS1_TIMER0_RST \ - (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) - -/* TIMER1_RST: Current status of the TIMER1_RST */ -#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) -#define RESET_ACTIVE_STATUS1_TIMER1_RST \ - (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) - -/* TIMER2_RST: Current status of the TIMER2_RST */ -#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) -#define RESET_ACTIVE_STATUS1_TIMER2_RST \ - (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) - -/* TIMER3_RST: Current status of the TIMER3_RST */ -#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) -#define RESET_ACTIVE_STATUS1_TIMER3_RST \ - (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) - -/* RITIMER_RST: Current status of the RITIMER_RST */ -#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) -#define RESET_ACTIVE_STATUS1_RITIMER_RST \ - (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) - -/* SCT_RST: Current status of the SCT_RST */ -#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) -#define RESET_ACTIVE_STATUS1_SCT_RST \ - (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) - -/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ -#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) -#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \ - (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) - -/* QEI_RST: Current status of the QEI_RST */ -#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) -#define RESET_ACTIVE_STATUS1_QEI_RST \ - (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) - -/* ADC0_RST: Current status of the ADC0_RST */ -#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) -#define RESET_ACTIVE_STATUS1_ADC0_RST \ - (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) - -/* ADC1_RST: Current status of the ADC1_RST */ -#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) -#define RESET_ACTIVE_STATUS1_ADC1_RST \ - (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) - -/* DAC_RST: Current status of the DAC_RST */ -#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) -#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) - -/* UART0_RST: Current status of the UART0_RST */ -#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) -#define RESET_ACTIVE_STATUS1_UART0_RST \ - (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) - -/* UART1_RST: Current status of the UART1_RST */ -#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) -#define RESET_ACTIVE_STATUS1_UART1_RST \ - (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) - -/* UART2_RST: Current status of the UART2_RST */ -#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) -#define RESET_ACTIVE_STATUS1_UART2_RST \ - (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) - -/* UART3_RST: Current status of the UART3_RST */ -#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) -#define RESET_ACTIVE_STATUS1_UART3_RST \ - (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) - -/* I2C0_RST: Current status of the I2C0_RST */ -#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) -#define RESET_ACTIVE_STATUS1_I2C0_RST \ - (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) - -/* I2C1_RST: Current status of the I2C1_RST */ -#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) -#define RESET_ACTIVE_STATUS1_I2C1_RST \ - (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) - -/* SSP0_RST: Current status of the SSP0_RST */ -#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) -#define RESET_ACTIVE_STATUS1_SSP0_RST \ - (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) - -/* SSP1_RST: Current status of the SSP1_RST */ -#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) -#define RESET_ACTIVE_STATUS1_SSP1_RST \ - (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) - -/* I2S_RST: Current status of the I2S_RST */ -#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) -#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) - -/* SPIFI_RST: Current status of the SPIFI_RST */ -#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) -#define RESET_ACTIVE_STATUS1_SPIFI_RST \ - (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) - -/* CAN1_RST: Current status of the CAN1_RST */ -#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) -#define RESET_ACTIVE_STATUS1_CAN1_RST \ - (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) - -/* CAN0_RST: Current status of the CAN0_RST */ -#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) -#define RESET_ACTIVE_STATUS1_CAN0_RST \ - (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) - -/* M0APP_RST: Current status of the M0APP_RST */ -#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) -#define RESET_ACTIVE_STATUS1_M0APP_RST \ - (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) - -/* SGPIO_RST: Current status of the SGPIO_RST */ -#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) -#define RESET_ACTIVE_STATUS1_SGPIO_RST \ - (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) - -/* SPI_RST: Current status of the SPI_RST */ -#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) -#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) - -/* --- RESET_EXT_STAT0 values ----------------------------------- */ - -/* EXT_RESET: Reset activated by external reset from reset pin */ -#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0) -#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) - -/* BOD_RESET: Reset activated by BOD reset */ -#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4) -#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) - -/* WWDT_RESET: Reset activated by WWDT time-out */ -#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) -#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) - -/* --- RESET_EXT_STAT1 values ----------------------------------- */ - -/* CORE_RESET: Reset activated by CORE_RST output */ -#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1) -#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) - -/* --- RESET_EXT_STAT2 values ----------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT2_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT4 values ----------------------------------- */ - -/* CORE_RESET: Reset activated by CORE_RST output */ -#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1) -#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) - -/* --- RESET_EXT_STAT5 values ----------------------------------- */ - -/* CORE_RESET: Reset activated by CORE_RST output */ -#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1) -#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) - -/* --- RESET_EXT_STAT8 values ----------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT8_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT9 values ----------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT9_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT13 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT16 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT17 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT18 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT19 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT20 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT21 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT22 values ---------------------------------- */ - -/* MASTER_RESET: Reset activated by MASTER_RST output */ -#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) -#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) - -/* --- RESET_EXT_STAT25 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT25_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT27 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT27_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT28 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT28_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT29 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT29_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT32 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT32_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT33 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT33_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT34 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT34_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT35 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT35_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT36 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT36_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT37 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT37_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT38 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT38_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT39 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT39_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT40 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT40_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT41 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT41_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT42 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT42_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT44 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT44_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT45 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT45_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT46 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT46_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT47 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT47_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT48 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT48_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT49 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT49_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT50 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT50_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT51 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT51_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT52 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT52_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT53 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT53_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT54 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT54_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT55 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT55_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT56 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT56_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT57 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT57_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) - -/* --- RESET_EXT_STAT58 values ---------------------------------- */ - -/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ -#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT58_PERIPHERAL_RESET \ - (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ritimer.h b/libopencm3/include/libopencm3/lpc43xx/ritimer.h deleted file mode 100644 index e736bc3..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/ritimer.h +++ /dev/null @@ -1,59 +0,0 @@ -/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines - -@brief Defined Constants and Types for the LPC43xx Repetitive Interrupt -Timer - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_RITIMER_H -#define LPC43XX_RITIMER_H - -/**@{*/ - -#include -#include - -/* --- Repetitive Interrupt Timer registers -------------------------------- */ - -/* Compare register */ -#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000) - -/* Mask register */ -#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004) - -/* Control register */ -#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008) - -/* 32-bit counter */ -#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/scu.h b/libopencm3/include/libopencm3/lpc43xx/scu.h deleted file mode 100644 index 548ac88..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/scu.h +++ /dev/null @@ -1,780 +0,0 @@ -/** @defgroup scu_defines System Control Unit Defines - -@brief Defined Constants and Types for the LPC43xx System Control Unit - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* -* This file is part of the libopencm3 project. -* -* Copyright (C) 2012 Michael Ossmann -* Copyright (C) 2012 Benjamin Vernoux -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published by -* the Free Software Foundation, either version 3 of the License, or -* (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -*/ - -#ifndef LPC43XX_SCU_H -#define LPC43XX_SCU_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* Pin group base addresses */ -#define PIN_GROUP0 (SCU_BASE + 0x000) -#define PIN_GROUP1 (SCU_BASE + 0x080) -#define PIN_GROUP2 (SCU_BASE + 0x100) -#define PIN_GROUP3 (SCU_BASE + 0x180) -#define PIN_GROUP4 (SCU_BASE + 0x200) -#define PIN_GROUP5 (SCU_BASE + 0x280) -#define PIN_GROUP6 (SCU_BASE + 0x300) -#define PIN_GROUP7 (SCU_BASE + 0x380) -#define PIN_GROUP8 (SCU_BASE + 0x400) -#define PIN_GROUP9 (SCU_BASE + 0x480) -#define PIN_GROUPA (SCU_BASE + 0x500) -#define PIN_GROUPB (SCU_BASE + 0x580) -#define PIN_GROUPC (SCU_BASE + 0x600) -#define PIN_GROUPD (SCU_BASE + 0x680) -#define PIN_GROUPE (SCU_BASE + 0x700) -#define PIN_GROUPF (SCU_BASE + 0x780) - -#define PIN0 0x000 -#define PIN1 0x004 -#define PIN2 0x008 -#define PIN3 0x00C -#define PIN4 0x010 -#define PIN5 0x014 -#define PIN6 0x018 -#define PIN7 0x01C -#define PIN8 0x020 -#define PIN9 0x024 -#define PIN10 0x028 -#define PIN11 0x02C -#define PIN12 0x030 -#define PIN13 0x034 -#define PIN14 0x038 -#define PIN15 0x03C -#define PIN16 0x040 -#define PIN17 0x044 -#define PIN18 0x048 -#define PIN19 0x04C -#define PIN20 0x050 - - -/* --- SCU registers ------------------------------------------------------- */ - -/* Pin configuration registers */ - -#define SCU_SFS(group, pin) MMIO32((group) + (pin)) - -/* Pins P0_n */ -#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) -#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) - -/* Pins P1_n */ -#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) -#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) -#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) -#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) -#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) -#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) -#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) -#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) -#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) -#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) -#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) -#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) -#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) -#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) -#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) -#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) -#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) -#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) -#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) -#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) -#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) - -/* Pins P2_n */ -#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) -#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) -#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) -#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) -#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) -#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) -#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) -#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) -#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) -#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) -#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) -#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) -#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) -#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) - -/* Pins P3_n */ -#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) -#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) -#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) -#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) -#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) -#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) -#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) -#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) -#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) - -/* Pins P4_n */ -#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) -#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) -#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) -#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) -#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) -#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) -#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) -#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) -#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) -#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) -#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) - -/* Pins P5_n */ -#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) -#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) -#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) -#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) -#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) -#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) -#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) -#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) - -/* Pins P6_n */ -#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) -#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) -#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) -#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) -#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) -#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) -#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) -#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) -#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) -#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) -#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) -#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) -#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) - -/* Pins P7_n */ -#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) -#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) -#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) -#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) -#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) -#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) -#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) -#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) - -/* Pins P8_n */ -#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) -#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) -#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) -#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) -#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) -#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) -#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) -#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) -#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) - -/* Pins P9_n */ -#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) -#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) -#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) -#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) -#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) -#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) -#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) - -/* Pins PA_n */ -#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) -#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) -#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) -#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) -#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) - -/* Pins PB_n */ -#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) -#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) -#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) -#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) -#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) -#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) -#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) - -/* Pins PC_n */ -#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) -#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) -#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) -#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) -#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) -#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) -#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) -#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) -#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) -#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) -#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) -#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) -#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) -#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) -#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) - -/* Pins PD_n */ -#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) -#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) -#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) -#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) -#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) -#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) -#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) -#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) -#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) -#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) -#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) -#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) -#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) -#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) -#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) -#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) -#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) - -/* Pins PE_n */ -#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) -#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) -#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) -#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) -#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) -#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) -#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) -#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) -#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) -#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) -#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) -#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) -#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) -#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) -#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) -#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) - -/* Pins PF_n */ -#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) -#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) -#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) -#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) -#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) -#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) -#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) -#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) -#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) -#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) -#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) -#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) - -/* CLKn pins */ -#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) -#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) -#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) -#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) - -/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ -#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) -#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) - -/* ADC pin select registers */ - -/* ADC0 function select register */ -#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) - -/* ADC1 function select register */ -#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) - -/* Analog function select register */ -#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) - -/* EMC clock delay register */ -#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) - -/* Pin interrupt select registers */ - -/* Pin interrupt select register for pin interrupts 0 to 3 */ -#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) - -/* Pin interrupt select register for pin interrupts 4 to 7 */ -#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) - -/**************************/ -/* SCU I2C0 Configuration */ -/**************************/ -/* -* Select input glitch filter time constant for the SCL pin. -* 0 = 50 ns glitch filter. -* 1 = 3ns glitch filter. -*/ -#define SCU_SCL_EFP (BIT0) - -/* BIT1 Reserved. Always write a 0 to this bit. */ - -/* -* Select I2C mode for the SCL pin. -* 0 = Standard/Fast mode transmit. -* 1 = Fast-mode Plus transmit. -*/ -#define SCU_SCL_EHD (BIT2) - -/* -* Enable the input receiver for the SCL pin. -* Always write a 1 to this bit when using the -* I2C0. -* 0 = Disabled. -* 1 = Enabled. -*/ -#define SCU_SCL_EZI_EN (BIT3) - -/* BIT4-6 Reserved. */ - -/* -* Enable or disable input glitch filter for the -* SCL pin. The filter time constant is -* determined by bit EFP. -* 0 = Enable input filter. -* 1 = Disable input filter. -*/ -#define SCU_SCL_ZIF_DIS (BIT7) - -/* -* Select input glitch filter time constant for the SDA pin. -* 0 = 50 ns glitch filter. -* 1 = 3ns glitch filter. -*/ -#define SCU_SDA_EFP (BIT8) - -/* BIT9 Reserved. Always write a 0 to this bit. */ - -/* -* Select I2C mode for the SDA pin. -* 0 = Standard/Fast mode transmit. -* 1 = Fast-mode Plus transmit. -*/ -#define SCU_SDA_EHD (BIT10) - -/* -* Enable the input receiver for the SDA pin. -* Always write a 1 to this bit when using the -* I2C0. -* 0 = Disabled. -* 1 = Enabled. -*/ -#define SCU_SDA_EZI_EN (BIT11) - -/* BIT 12-14 - Reserved */ - -/* -* Enable or disable input glitch filter for the -* SDA pin. The filter time constant is -* determined by bit SDA_EFP. -* 0 = Enable input filter. -* 1 = Disable input filter. -*/ -#define SCU_SDA_ZIF_DIS (BIT15) - -/* Standard mode for I2C SCL/SDA Standard/Fast mode */ -#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) - -/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ -#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \ - SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \ - SCU_SDA_EZI_EN) - -/* -* SCU PIN Normal Drive: -* The configuration registers for normal-drive pins control the following pins: -* - P0_0 and P0_1 -* - P1_0 to P1_16 and P1_18 to P1_20 -* - P2_0 to P2_2 and P2_6 to P2_13 -* - P3_0 to P3_2 and P3_4 to P3_8 -* - P4_0 to P4_10 -* - P5_0 to P5_7 -* - P6_0 to P6_12 -* - P7_0 to P7_7 -* - P8_3 to P8_8 -* - P9_0 to P9_6 -* - PA_0 and PA_4 -* - PB_0 to PB_6 -* - PC_0 to PC_14 -* - PE_0 to PE_15 -* - PF_0 to PF_11 -* -* Pin configuration registers for High-Drive pins. -* The configuration registers for high-drive pins control the following pins: -* - P1_17 -* - P2_3 to P2_5 -* - P8_0 to P8_2 -* - PA_1 to PA_3 -* -* Pin configuration registers for High-Speed pins. -* This register controls the following pins: -* - P3_3 and pins CLK0 to CLK3. -*/ -typedef enum { - /* Group Port 0 */ - P0_0 = (PIN_GROUP0+PIN0), - P0_1 = (PIN_GROUP0+PIN1), - - /* Group Port 1 */ - P1_0 = (PIN_GROUP1+PIN0), - P1_1 = (PIN_GROUP1+PIN1), - P1_2 = (PIN_GROUP1+PIN2), - P1_3 = (PIN_GROUP1+PIN3), - P1_4 = (PIN_GROUP1+PIN4), - P1_5 = (PIN_GROUP1+PIN5), - P1_6 = (PIN_GROUP1+PIN6), - P1_7 = (PIN_GROUP1+PIN7), - P1_8 = (PIN_GROUP1+PIN8), - P1_9 = (PIN_GROUP1+PIN9), - P1_10 = (PIN_GROUP1+PIN10), - P1_11 = (PIN_GROUP1+PIN11), - P1_12 = (PIN_GROUP1+PIN12), - P1_13 = (PIN_GROUP1+PIN13), - P1_14 = (PIN_GROUP1+PIN14), - P1_15 = (PIN_GROUP1+PIN15), - P1_16 = (PIN_GROUP1+PIN16), - - /* P1_17 is High-Drive pin */ - P1_17 = (PIN_GROUP1+PIN17), - - P1_18 = (PIN_GROUP1+PIN18), - P1_19 = (PIN_GROUP1+PIN19), - P1_20 = (PIN_GROUP1+PIN20), - - /* Group Port 2 */ - P2_0 = (PIN_GROUP2+PIN0), - P2_1 = (PIN_GROUP2+PIN1), - P2_2 = (PIN_GROUP2+PIN2), - - /* P2_3 to P2_5 are High-Drive pins */ - P2_3 = (PIN_GROUP2+PIN3), - P2_4 = (PIN_GROUP2+PIN4), - P2_5 = (PIN_GROUP2+PIN5), - - P2_6 = (PIN_GROUP2+PIN6), - P2_7 = (PIN_GROUP2+PIN7), - P2_8 = (PIN_GROUP2+PIN8), - P2_9 = (PIN_GROUP2+PIN9), - P2_10 = (PIN_GROUP2+PIN10), - P2_11 = (PIN_GROUP2+PIN11), - P2_12 = (PIN_GROUP2+PIN12), - P2_13 = (PIN_GROUP2+PIN13), - - /* Group Port 3 */ - P3_0 = (PIN_GROUP3+PIN0), - P3_1 = (PIN_GROUP3+PIN1), - P3_2 = (PIN_GROUP3+PIN2), - - /* P3_3 is High-Speed pin */ - P3_3 = (PIN_GROUP3+PIN3), - - P3_4 = (PIN_GROUP3+PIN4), - P3_5 = (PIN_GROUP3+PIN5), - P3_6 = (PIN_GROUP3+PIN6), - P3_7 = (PIN_GROUP3+PIN7), - P3_8 = (PIN_GROUP3+PIN8), - - /* Group Port 4 */ - P4_0 = (PIN_GROUP4+PIN0), - P4_1 = (PIN_GROUP4+PIN1), - P4_2 = (PIN_GROUP4+PIN2), - P4_3 = (PIN_GROUP4+PIN3), - P4_4 = (PIN_GROUP4+PIN4), - P4_5 = (PIN_GROUP4+PIN5), - P4_6 = (PIN_GROUP4+PIN6), - P4_7 = (PIN_GROUP4+PIN7), - P4_8 = (PIN_GROUP4+PIN8), - P4_9 = (PIN_GROUP4+PIN9), - P4_10 = (PIN_GROUP4+PIN10), - - /* Group Port 5 */ - P5_0 = (PIN_GROUP5+PIN0), - P5_1 = (PIN_GROUP5+PIN1), - P5_2 = (PIN_GROUP5+PIN2), - P5_3 = (PIN_GROUP5+PIN3), - P5_4 = (PIN_GROUP5+PIN4), - P5_5 = (PIN_GROUP5+PIN5), - P5_6 = (PIN_GROUP5+PIN6), - P5_7 = (PIN_GROUP5+PIN7), - - /* Group Port 6 */ - P6_0 = (PIN_GROUP6+PIN0), - P6_1 = (PIN_GROUP6+PIN1), - P6_2 = (PIN_GROUP6+PIN2), - P6_3 = (PIN_GROUP6+PIN3), - P6_4 = (PIN_GROUP6+PIN4), - P6_5 = (PIN_GROUP6+PIN5), - P6_6 = (PIN_GROUP6+PIN6), - P6_7 = (PIN_GROUP6+PIN7), - P6_8 = (PIN_GROUP6+PIN8), - P6_9 = (PIN_GROUP6+PIN9), - P6_10 = (PIN_GROUP6+PIN10), - P6_11 = (PIN_GROUP6+PIN11), - P6_12 = (PIN_GROUP6+PIN12), - - /* Group Port 7 */ - P7_0 = (PIN_GROUP7+PIN0), - P7_1 = (PIN_GROUP7+PIN1), - P7_2 = (PIN_GROUP7+PIN2), - P7_3 = (PIN_GROUP7+PIN3), - P7_4 = (PIN_GROUP7+PIN4), - P7_5 = (PIN_GROUP7+PIN5), - P7_6 = (PIN_GROUP7+PIN6), - P7_7 = (PIN_GROUP7+PIN7), - - /* Group Port 8 */ - /* P8_0 to P8_2 are High-Drive pins */ - P8_0 = (PIN_GROUP8+PIN0), - P8_1 = (PIN_GROUP8+PIN1), - P8_2 = (PIN_GROUP8+PIN2), - - P8_3 = (PIN_GROUP8+PIN3), - P8_4 = (PIN_GROUP8+PIN4), - P8_5 = (PIN_GROUP8+PIN5), - P8_6 = (PIN_GROUP8+PIN6), - P8_7 = (PIN_GROUP8+PIN7), - P8_8 = (PIN_GROUP8+PIN8), - - /* Group Port 9 */ - P9_0 = (PIN_GROUP9+PIN0), - P9_1 = (PIN_GROUP9+PIN1), - P9_2 = (PIN_GROUP9+PIN2), - P9_3 = (PIN_GROUP9+PIN3), - P9_4 = (PIN_GROUP9+PIN4), - P9_5 = (PIN_GROUP9+PIN5), - P9_6 = (PIN_GROUP9+PIN6), - - /* Group Port A */ - PA_0 = (PIN_GROUPA+PIN0), - /* PA_1 to PA_3 are Normal & High-Drive Pins */ - PA_1 = (PIN_GROUPA+PIN1), - PA_2 = (PIN_GROUPA+PIN2), - PA_3 = (PIN_GROUPA+PIN3), - PA_4 = (PIN_GROUPA+PIN4), - - /* Group Port B */ - PB_0 = (PIN_GROUPB+PIN0), - PB_1 = (PIN_GROUPB+PIN1), - PB_2 = (PIN_GROUPB+PIN2), - PB_3 = (PIN_GROUPB+PIN3), - PB_4 = (PIN_GROUPB+PIN4), - PB_5 = (PIN_GROUPB+PIN5), - PB_6 = (PIN_GROUPB+PIN6), - - /* Group Port C */ - PC_0 = (PIN_GROUPC+PIN0), - PC_1 = (PIN_GROUPC+PIN1), - PC_2 = (PIN_GROUPC+PIN2), - PC_3 = (PIN_GROUPC+PIN3), - PC_4 = (PIN_GROUPC+PIN4), - PC_5 = (PIN_GROUPC+PIN5), - PC_6 = (PIN_GROUPC+PIN6), - PC_7 = (PIN_GROUPC+PIN7), - PC_8 = (PIN_GROUPC+PIN8), - PC_9 = (PIN_GROUPC+PIN9), - PC_10 = (PIN_GROUPC+PIN10), - PC_11 = (PIN_GROUPC+PIN11), - PC_12 = (PIN_GROUPC+PIN12), - PC_13 = (PIN_GROUPC+PIN13), - PC_14 = (PIN_GROUPC+PIN14), - - /* Group Port D (seems not configurable through SCU, not defined in - * UM10503.pdf Rev.1, keep it here) - */ - PD_0 = (PIN_GROUPD+PIN0), - PD_1 = (PIN_GROUPD+PIN1), - PD_2 = (PIN_GROUPD+PIN2), - PD_3 = (PIN_GROUPD+PIN3), - PD_4 = (PIN_GROUPD+PIN4), - PD_5 = (PIN_GROUPD+PIN5), - PD_6 = (PIN_GROUPD+PIN6), - PD_7 = (PIN_GROUPD+PIN7), - PD_8 = (PIN_GROUPD+PIN8), - PD_9 = (PIN_GROUPD+PIN9), - PD_10 = (PIN_GROUPD+PIN10), - PD_11 = (PIN_GROUPD+PIN11), - PD_12 = (PIN_GROUPD+PIN12), - PD_13 = (PIN_GROUPD+PIN13), - PD_14 = (PIN_GROUPD+PIN14), - PD_15 = (PIN_GROUPD+PIN15), - PD_16 = (PIN_GROUPD+PIN16), - - /* Group Port E */ - PE_0 = (PIN_GROUPE+PIN0), - PE_1 = (PIN_GROUPE+PIN1), - PE_2 = (PIN_GROUPE+PIN2), - PE_3 = (PIN_GROUPE+PIN3), - PE_4 = (PIN_GROUPE+PIN4), - PE_5 = (PIN_GROUPE+PIN5), - PE_6 = (PIN_GROUPE+PIN6), - PE_7 = (PIN_GROUPE+PIN7), - PE_8 = (PIN_GROUPE+PIN8), - PE_9 = (PIN_GROUPE+PIN9), - PE_10 = (PIN_GROUPE+PIN10), - PE_11 = (PIN_GROUPE+PIN11), - PE_12 = (PIN_GROUPE+PIN12), - PE_13 = (PIN_GROUPE+PIN13), - PE_14 = (PIN_GROUPE+PIN14), - PE_15 = (PIN_GROUPE+PIN15), - - /* Group Port F */ - PF_0 = (PIN_GROUPF+PIN0), - PF_1 = (PIN_GROUPF+PIN1), - PF_2 = (PIN_GROUPF+PIN2), - PF_3 = (PIN_GROUPF+PIN3), - PF_4 = (PIN_GROUPF+PIN4), - PF_5 = (PIN_GROUPF+PIN5), - PF_6 = (PIN_GROUPF+PIN6), - PF_7 = (PIN_GROUPF+PIN7), - PF_8 = (PIN_GROUPF+PIN8), - PF_9 = (PIN_GROUPF+PIN9), - PF_10 = (PIN_GROUPF+PIN10), - PF_11 = (PIN_GROUPF+PIN11), - - /* Group Clock 0 to 3 High-Speed pins */ - CLK0 = (SCU_BASE + 0xC00), - CLK1 = (SCU_BASE + 0xC04), - CLK2 = (SCU_BASE + 0xC08), - CLK3 = (SCU_BASE + 0xC0C) - -} scu_grp_pin_t; - -/* -* Pin Configuration to be used for scu_pinmux() parameter scu_conf -* For normal-drive pins, high-drive pins, high-speed pins -*/ -/* -* Function BIT0 to 2. -* Common to normal-drive pins, high-drive pins, high-speed pins. -*/ -#define SCU_CONF_FUNCTION0 (0x0) -#define SCU_CONF_FUNCTION1 (0x1) -#define SCU_CONF_FUNCTION2 (0x2) -#define SCU_CONF_FUNCTION3 (0x3) -#define SCU_CONF_FUNCTION4 (0x4) -#define SCU_CONF_FUNCTION5 (0x5) -#define SCU_CONF_FUNCTION6 (0x6) -#define SCU_CONF_FUNCTION7 (0x7) - -/* -* Enable pull-down resistor at pad -* By default=0 Disable pull-down. -* Available to normal-drive pins, high-drive pins, high-speed pins -*/ -#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) - -/* -* Disable pull-up resistor at pad. -* By default=0 the pull-up resistor is enabled at reset. -* Available to normal-drive pins, high-drive pins, high-speed pins -*/ -#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) - -/* -* Select Slew Rate. -* By Default=0 Slow. -* Available to normal-drive and high-speed pins, reserved for high-drive pins. -*/ -#define SCU_CONF_EHS_FAST (BIT5) - -/* -* Input buffer enable. -* By Default=0 Disable Input Buffer. -* The input buffer is disabled by default at reset and must be enabled for -* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer -* to the pad(in high-drive pins). -* Available to normal-drive pins, high-drive pins, high-speed pins. -*/ -#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) - -/* -* Input glitch filter. Disable the input glitch filter for clocking signals -* higher than 30 MHz. -* Available to normal-drive pins, high-drive pins, high-speed pins. -*/ -#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) - -/* -* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). -* Available to high-drive pins, reserved for others. -*/ -#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) -#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) -#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) - -/* BIT10 to 31 are Reserved */ - -/* Configuration for different I/O pins types */ -#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EPD_EN_PULLDOWN | \ - SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EPD_EN_PULLDOWN | \ - SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \ - SCU_CONF_EHS_FAST | \ - SCU_CONF_EZI_EN_IN_BUFFER | \ - SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) - -BEGIN_DECLS - -void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sdio.h b/libopencm3/include/libopencm3/lpc43xx/sdio.h deleted file mode 100644 index 164dda4..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/sdio.h +++ /dev/null @@ -1,151 +0,0 @@ -/** @defgroup sdio_defines SDIO - -@brief Defined Constants and Types for the LPC43xx SDIO - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_SDIO_H -#define LPC43XX_SDIO_H - -/**@{*/ - -#include -#include - -/* --- SDIO registers ----------------------------------------------------- */ - -/* Control Register */ -#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000) - -/* Power Enable Register */ -#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004) - -/* Clock Divider Register */ -#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008) - -/* SD Clock Source Register */ -#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C) - -/* Clock Enable Register */ -#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010) - -/* Time-out Register */ -#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014) - -/* Card Type Register */ -#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018) - -/* Block Size Register */ -#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C) - -/* Byte Count Register */ -#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020) - -/* Interrupt Mask Register */ -#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024) - -/* Command Argument Register */ -#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028) - -/* Command Register */ -#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C) - -/* Response Register 0 */ -#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030) - -/* Response Register 1 */ -#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034) - -/* Response Register 2 */ -#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038) - -/* Response Register 3 */ -#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C) - -/* Masked Interrupt Status Register */ -#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040) - -/* Raw Interrupt Status Register */ -#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044) - -/* Status Register */ -#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048) - -/* FIFO Threshold Watermark Register */ -#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C) - -/* Card Detect Register */ -#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050) - -/* Write Protect Register */ -#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054) - -/* Transferred CIU Card Byte Count Register */ -#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C) - -/* Transferred Host to BIU-FIFO Byte Count Register */ -#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060) - -/* Debounce Count Register */ -#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064) - -/* UHS-1 Register */ -#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074) - -/* Hardware Reset */ -#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078) - -/* Bus Mode Register */ -#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080) - -/* Poll Demand Register */ -#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084) - -/* Descriptor List Base Address Register */ -#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088) - -/* Internal DMAC Status Register */ -#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C) - -/* Internal DMAC Interrupt Enable Register */ -#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090) - -/* Current Host Descriptor Address Register */ -#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094) - -/* Current Buffer Descriptor Address Register */ -#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098) - -/* Data FIFO read/write */ -#define SDIO_DATA MMIO32(SDIO_BASE + 0x100) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sgpio.h b/libopencm3/include/libopencm3/lpc43xx/sgpio.h deleted file mode 100644 index 4b8d5b6..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/sgpio.h +++ /dev/null @@ -1,691 +0,0 @@ -/** @defgroup sgpio_defines Serial General Purpose I/O - -@brief Defined Constants and Types for the LPC43xx Serial General Purpose -I/O - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/** @defgroup sdio_defines SDIO - -@brief Defined Constants and Types for the LPC43xx SDIO - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Jared Boone - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_SGPIO_H -#define LPC43XX_SGPIO_H - -/**@{*/ - -#include -#include - -/* --- SGPIO registers ----------------------------------------------------- */ - -/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */ -#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04)) -#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00) -#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04) -#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08) -#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C) -#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10) -#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14) -#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18) -#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C) -#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20) -#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24) -#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28) -#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C) -#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30) -#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34) -#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38) -#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C) - -/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */ -#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \ - (slice * 0x04)) -#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40) -#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44) -#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48) -#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C) -#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50) -#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54) -#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58) -#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C) -#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60) -#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64) -#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68) -#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C) -#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70) -#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74) -#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78) -#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C) - -/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */ -#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \ - (slice * 0x04)) -#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80) -#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84) -#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88) -#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C) -#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90) -#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94) -#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98) -#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C) -#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0) -#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4) -#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8) -#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC) -#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0) -#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4) -#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8) -#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC) - -/* Slice data registers (REG0 to 15) */ -#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \ - (slice * 0x04)) -#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0) -#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4) -#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8) -#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC) -#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0) -#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4) -#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8) -#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC) -#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0) -#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4) -#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8) -#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC) -#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0) -#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4) -#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8) -#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC) - -/* Slice data shadow registers (REG_SS0 to 15) */ -#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \ - (slice * 0x04)) -#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100) -#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104) -#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108) -#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C) -#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110) -#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114) -#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118) -#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C) -#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120) -#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124) -#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128) -#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C) -#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130) -#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134) -#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138) -#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C) - -/* Reload registers (PRESET0 to 15) */ -#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \ - (slice * 0x04)) -#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140) -#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144) -#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148) -#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C) -#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150) -#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154) -#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158) -#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C) -#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160) -#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164) -#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168) -#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C) -#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170) -#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174) -#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178) -#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C) - -/* Down counter registers (COUNT0 to 15) */ -#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \ - (slice * 0x04)) -#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180) -#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184) -#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188) -#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C) -#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190) -#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194) -#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198) -#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C) -#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0) -#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4) -#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8) -#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC) -#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0) -#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4) -#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8) -#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC) - -/* Position registers (POS0 to 15) */ -#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \ - (slice * 0x04)) -#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0) -#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4) -#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8) -#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC) -#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0) -#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4) -#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8) -#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC) -#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0) -#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4) -#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8) -#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC) -#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0) -#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4) -#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8) -#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC) - -/* Slice name to slice index mapping */ -#define SGPIO_SLICE_A 0 -#define SGPIO_SLICE_B 1 -#define SGPIO_SLICE_C 2 -#define SGPIO_SLICE_D 3 -#define SGPIO_SLICE_E 4 -#define SGPIO_SLICE_F 5 -#define SGPIO_SLICE_G 6 -#define SGPIO_SLICE_H 7 -#define SGPIO_SLICE_I 8 -#define SGPIO_SLICE_J 9 -#define SGPIO_SLICE_K 10 -#define SGPIO_SLICE_L 11 -#define SGPIO_SLICE_M 12 -#define SGPIO_SLICE_N 13 -#define SGPIO_SLICE_O 14 -#define SGPIO_SLICE_P 15 - -/* Mask for pattern match function of slice A */ -#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200) - -/* Mask for pattern match function of slice H */ -#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204) - -/* Mask for pattern match function of slice I */ -#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208) - -/* Mask for pattern match function of slice P */ -#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C) - -/* GPIO input status register */ -#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210) - -/* GPIO output control register */ -#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214) - -/* GPIO OE control register */ -#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218) - -/* Enables the slice COUNT counter */ -#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C) - -/* Disables the slice COUNT counter */ -#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220) - -/* Shift clock interrupt clear mask */ -#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00) - -/* Shift clock interrupt set mask */ -#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04) - -/* Shift clock interrupt enable */ -#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08) - -/* Shift clock interrupt status */ -#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C) - -/* Shift clock interrupt clear status */ -#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10) - -/* Shift clock interrupt set status */ -#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14) - -/* Exchange clock interrupt clear mask */ -#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20) - -/* Exchange clock interrupt set mask */ -#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24) - -/* Exchange clock interrupt enable */ -#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28) - -/* Exchange clock interrupt status */ -#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C) - -/* Exchange clock interrupt clear status */ -#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30) - -/* Exchange clock interrupt set status */ -#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34) - -/* Pattern match interrupt clear mask */ -#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40) - -/* Pattern match interrupt set mask */ -#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44) - -/* Pattern match interrupt enable */ -#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48) - -/* Pattern match interrupt status */ -#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C) - -/* Pattern match interrupt clear status */ -#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50) - -/* Pattern match interrupt set status */ -#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54) - -/* Input interrupt clear mask */ -#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60) - -/* Input bit match interrupt set mask */ -#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64) - -/* Input bit match interrupt enable */ -#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68) - -/* Input bit match interrupt status */ -#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C) - -/* Input bit match interrupt clear status */ -#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70) - -/* Input bit match interrupt set status */ -#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74) - -/* --- Common register fields ----------------------------------- */ -/* TODO: Generate this stuff with the gen.py script as well! */ - -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) - -#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) - -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \ - (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \ - ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) - -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) - -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) - -#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) - -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) - -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) - -#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \ - (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \ - ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) - -#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \ - (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \ - (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \ - (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \ - (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \ - (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \ - (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) - -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \ - (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \ - ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) - -#define SGPIO_POS_POS_SHIFT (0) -#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) -#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) - -#define SGPIO_POS_POS_RESET_SHIFT (8) -#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) -#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) - -/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ - -/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) - -/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFGx_CONCAT_ENABLE \ - (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \ - (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \ - (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \ - (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \ - (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \ - (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \ - (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \ - ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \ - (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT) - - -/* --- SGPIO_POS[0..15] values -------------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POSx_POS_SHIFT (0) -#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT) -#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POSx_POS_RESET_SHIFT (8) -#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT) -#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT) - - -/* SGPIO structure for faster/better code generation (especially when optimized - * with -O2/-O3) - */ -/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 - * September 2012 - */ -typedef struct { - /* Pin multiplexer configuration registers. RW */ - volatile uint32_t OUT_MUX_CFG[16]; - /* SGPIO multiplexer configuration registers. RW */ - volatile uint32_t SGPIO_MUX_CFG[16]; - /* Slice multiplexer configuration registers. RW */ - volatile uint32_t SLICE_MUX_CFG[16]; - /* Slice data registers. RW */ - volatile uint32_t REG[16]; - /* Slice data shadow registers. Each time POS reaches 0x0 the contents - * of REG_SS is exchanged with the content of REG. RW - */ - volatile uint32_t REG_SS[16]; - /* Reload registers. Counter reload value; loaded when COUNT reaches - * 0x0 RW - */ - volatile uint32_t PRESET[16]; - /* Down counter registers, counts down each shift clock cycle. RW */ - volatile uint32_t COUNT[16]; - /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. - * POS_RESET Reload value for POS after POS reaches 0x0. RW - */ - volatile uint32_t POS[16]; - /* Slice A mask register. Mask for pattern match function of slice A. - * RW - */ - volatile uint32_t MASK_A; - /* Slice H mask register. Mask for pattern match function of slice H. - * RW - */ - volatile uint32_t MASK_H; - /* Slice I mask register. Mask for pattern match function of slice I. - * RW - */ - volatile uint32_t MASK_I; - /* Slice P mask register. Mask for pattern match function of slice P. - * RW - */ - volatile uint32_t MASK_P; - /* GPIO input status register. R */ - volatile uint32_t GPIO_INREG; - /* GPIO output control register. RW */ - volatile uint32_t GPIO_OUTREG; - /* GPIO output enable register. RW */ - volatile uint32_t GPIO_OENREG; - /* Slice count enable register. RW */ - volatile uint32_t CTRL_ENABLE; - /* Slice count disable register. RW */ - volatile uint32_t CTRL_DISABLE; - volatile uint32_t RES0[823]; - /* Shift clock interrupt clear mask register. W */ - volatile uint32_t CLR_EN_0; - /* Shift clock interrupt set mask register. W */ - volatile uint32_t SET_EN_0; - /* Shift clock interrupt enable register. R */ - volatile uint32_t ENABLE_0; - /* Shift clock interrupt status register. R */ - volatile uint32_t STATUS_0; - /* Shift clock interrupt clear status register. W */ - volatile uint32_t CLR_STATUS_0; - /* Shift clock interrupt set status register. W */ - volatile uint32_t SET_STATUS_0; - volatile uint32_t RES1[2]; - /* Exchange clock interrupt clear mask register. W */ - volatile uint32_t CLR_EN_1; - /* Exchange clock interrupt set mask register. W */ - volatile uint32_t SET_EN_1; - /* Exchange clock interrupt enable. R */ - volatile uint32_t ENABLE_1; - /* Exchange clock interrupt status register. R */ - volatile uint32_t STATUS_1; - /* Exchange clock interrupt clear status register. W */ - volatile uint32_t CLR_STATUS_1; - /* Exchange clock interrupt set status register. W */ - volatile uint32_t SET_STATUS_1; - volatile uint32_t RES2[2]; - /* Pattern match interrupt clear mask register. W */ - volatile uint32_t CLR_EN_2; - /* Pattern match interrupt set mask register. W */ - volatile uint32_t SET_EN_2; - /* Pattern match interrupt enable register. R */ - volatile uint32_t ENABLE_2; - /* Pattern match interrupt status register. R */ - volatile uint32_t STATUS_2; - /* Pattern match interrupt clear status register. W */ - volatile uint32_t CLR_STATUS_2; - /* Pattern match interrupt set status register. W */ - volatile uint32_t SET_STATUS_2; - volatile uint32_t RES3[2]; - /* Input interrupt clear mask register. W */ - volatile uint32_t CLR_EN_3; - /* Input bit match interrupt set mask register. W */ - volatile uint32_t SET_EN_3; - /* Input bit match interrupt enable register. R */ - volatile uint32_t ENABLE_3; - /* Input bit match interrupt status register. R */ - volatile uint32_t STATUS_3; - /* Input bit match interrupt clear status register. W */ - volatile uint32_t CLR_STATUS_3; - /* Input bit match interrupt set status register. W */ - volatile uint32_t SET_STATUS_3; -} sgpio_t; - -/* Global access to SGPIO structure */ -#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ssp.h b/libopencm3/include/libopencm3/lpc43xx/ssp.h deleted file mode 100644 index 554f707..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/ssp.h +++ /dev/null @@ -1,209 +0,0 @@ -/** @defgroup ssp_defines Synchronous Serial Port - -@brief Defined Constants and Types for the LPC43xx Synchronous Serial -Port - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* -* This file is part of the libopencm3 project. -* -* Copyright (C) 2012 Michael Ossmann -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published by -* the Free Software Foundation, either version 3 of the License, or -* (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -*/ - -#ifndef LPC43XX_SSP_H -#define LPC43XX_SSP_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* SSP port base addresses (for convenience) */ -#define SSP0 SSP0_BASE -#define SSP1 SSP1_BASE - - -/* --- SSP registers ------------------------------------------------------- */ - -/* Control Register 0 */ -#define SSP_CR0(port) MMIO32((port) + 0x000) -#define SSP0_CR0 SSP_CR0(SSP0) -#define SSP1_CR0 SSP_CR0(SSP1) - -/* Control Register 1 */ -#define SSP_CR1(port) MMIO32((port) + 0x004) -#define SSP0_CR1 SSP_CR1(SSP0) -#define SSP1_CR1 SSP_CR1(SSP1) - -/* Data Register */ -#define SSP_DR(port) MMIO32((port) + 0x008) -#define SSP0_DR SSP_DR(SSP0) -#define SSP1_DR SSP_DR(SSP1) - -/* Status Register */ -#define SSP_SR(port) MMIO32((port) + 0x00C) -#define SSP0_SR SSP_SR(SSP0) -#define SSP1_SR SSP_SR(SSP1) - -#define SSP_SR_TFE BIT0 -#define SSP_SR_TNF BIT1 -#define SSP_SR_RNE BIT2 -#define SSP_SR_RFF BIT3 -#define SSP_SR_BSY BIT4 - -/* Clock Prescale Register */ -#define SSP_CPSR(port) MMIO32((port) + 0x010) -#define SSP0_CPSR SSP_CPSR(SSP0) -#define SSP1_CPSR SSP_CPSR(SSP1) - -/* Interrupt Mask Set and Clear Register */ -#define SSP_IMSC(port) MMIO32((port) + 0x014) -#define SSP0_IMSC SSP_IMSC(SSP0) -#define SSP1_IMSC SSP_IMSC(SSP1) - -/* Raw Interrupt Status Register */ -#define SSP_RIS(port) MMIO32((port) + 0x018) -#define SSP0_RIS SSP_RIS(SSP0) -#define SSP1_RIS SSP_RIS(SSP1) - -/* Masked Interrupt Status Register */ -#define SSP_MIS(port) MMIO32((port) + 0x01C) -#define SSP0_MIS SSP_MIS(SSP0) -#define SSP1_MIS SSP_MIS(SSP1) - -/* SSPICR Interrupt Clear Register */ -#define SSP_ICR(port) MMIO32((port) + 0x020) -#define SSP0_ICR SSP_ICR(SSP0) -#define SSP1_ICR SSP_ICR(SSP1) - -/* SSP1 DMA control register */ -#define SSP_DMACR(port) MMIO32((port) + 0x024) -#define SSP0_DMACR SSP_DMACR(SSP0) -#define SSP1_DMACR SSP_DMACR(SSP1) - -/* RXDMAE: Receive DMA enable */ -#define SSP_DMACR_RXDMAE 0x1 - -/* RXDMAE: Transmit DMA enable */ -#define SSP_DMACR_TXDMAE 0x2 - -typedef enum { - SSP0_NUM = 0x0, - SSP1_NUM = 0x1 -} ssp_num_t; - -/* - * SSP Control Register 0 - */ -/* SSP Data Size Bits 0 to 3 */ -typedef enum { - SSP_DATA_4BITS = 0x3, - SSP_DATA_5BITS = 0x4, - SSP_DATA_6BITS = 0x5, - SSP_DATA_7BITS = 0x6, - SSP_DATA_8BITS = 0x7, - SSP_DATA_9BITS = 0x8, - SSP_DATA_10BITS = 0x9, - SSP_DATA_11BITS = 0xA, - SSP_DATA_12BITS = 0xB, - SSP_DATA_13BITS = 0xC, - SSP_DATA_14BITS = 0xD, - SSP_DATA_15BITS = 0xE, - SSP_DATA_16BITS = 0xF -} ssp_datasize_t; - -/* SSP Frame Format/Type Bits 4 & 5 */ -typedef enum { - SSP_FRAME_SPI = 0x00, - SSP_FRAME_TI = BIT4, - SSP_FRAM_MICROWIRE = BIT5 -} ssp_frame_format_t; - -/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ -typedef enum { - SSP_CPOL_0_CPHA_0 = 0x0, - SSP_CPOL_1_CPHA_0 = BIT6, - SSP_CPOL_0_CPHA_1 = BIT7, - SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) -} ssp_cpol_cpha_t; - -/* - * SSP Control Register 1 - */ -/* SSP Mode Bit0 */ -typedef enum { - SSP_MODE_NORMAL = 0x0, - SSP_MODE_LOOPBACK = BIT0 -} ssp_mode_t; - -/* SSP Enable Bit1 */ -#define SSP_ENABLE BIT1 - -/* SSP Master/Slave Mode Bit2 */ -typedef enum { - SSP_MASTER = 0x0, - SSP_SLAVE = BIT2 -} ssp_master_slave_t; - -/* -* SSP Slave Output Disable Bit3 -* Slave Output Disable. This bit is relevant only in slave mode -* (MS = 1). If it is 1, this blocks this SSP controller from driving the -* transmit data line (MISO). -*/ -typedef enum { - SSP_SLAVE_OUT_ENABLE = 0x0, - SSP_SLAVE_OUT_DISABLE = BIT3 -} ssp_slave_option_t; /* This option is relevant only in slave mode */ - -BEGIN_DECLS - -void ssp_disable(ssp_num_t ssp_num); - -/* - * SSP Init - * clk_prescale shall be in range 2 to 254 (even number only). - * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, - * SCR=serial_clock_rate - */ -void ssp_init(ssp_num_t ssp_num, - ssp_datasize_t data_size, - ssp_frame_format_t frame_format, - ssp_cpol_cpha_t cpol_cpha_format, - uint8_t serial_clock_rate, - uint8_t clk_prescale, - ssp_mode_t mode, - ssp_master_slave_t master_slave, - ssp_slave_option_t slave_option); - -uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/timer.h b/libopencm3/include/libopencm3/lpc43xx/timer.h deleted file mode 100644 index 660c618..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/timer.h +++ /dev/null @@ -1,270 +0,0 @@ -/** @defgroup timer_defines Timer - -@brief Defined Constants and Types for the LPC43xx timer - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_TIMER_H -#define LPC43XX_TIMER_H - -/**@{*/ - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* Timer base addresses */ -#define TIMER0 TIMER0_BASE -#define TIMER1 TIMER1_BASE -#define TIMER2 TIMER2_BASE -#define TIMER3 TIMER3_BASE - - -/* --- Timer registers ----------------------------------------------------- */ - -/* Interrupt Register */ -#define TIMER_IR(timer) MMIO32((timer) + 0x000) -#define TIMER0_IR TIMER_IR(TIMER0) -#define TIMER1_IR TIMER_IR(TIMER1) -#define TIMER2_IR TIMER_IR(TIMER2) -#define TIMER3_IR TIMER_IR(TIMER3) - -/* Timer Control Register */ -#define TIMER_TCR(timer) MMIO32((timer) + 0x004) -#define TIMER0_TCR TIMER_TCR(TIMER0) -#define TIMER1_TCR TIMER_TCR(TIMER1) -#define TIMER2_TCR TIMER_TCR(TIMER2) -#define TIMER3_TCR TIMER_TCR(TIMER3) - -/* Timer Counter */ -#define TIMER_TC(timer) MMIO32((timer) + 0x008) -#define TIMER0_TC TIMER_TC(TIMER0) -#define TIMER1_TC TIMER_TC(TIMER1) -#define TIMER2_TC TIMER_TC(TIMER2) -#define TIMER3_TC TIMER_TC(TIMER3) - -/* Prescale Register */ -#define TIMER_PR(timer) MMIO32((timer) + 0x00C) -#define TIMER0_PR TIMER_PR(TIMER0) -#define TIMER1_PR TIMER_PR(TIMER1) -#define TIMER2_PR TIMER_PR(TIMER2) -#define TIMER3_PR TIMER_PR(TIMER3) - -/* Prescale Counter */ -#define TIMER_PC(timer) MMIO32((timer) + 0x010) -#define TIMER0_PC TIMER_PC(TIMER0) -#define TIMER1_PC TIMER_PC(TIMER1) -#define TIMER2_PC TIMER_PC(TIMER2) -#define TIMER3_PC TIMER_PC(TIMER3) - -/* Match Control Register */ -#define TIMER_MCR(timer) MMIO32((timer) + 0x014) -#define TIMER0_MCR TIMER_MCR(TIMER0) -#define TIMER1_MCR TIMER_MCR(TIMER1) -#define TIMER2_MCR TIMER_MCR(TIMER2) -#define TIMER3_MCR TIMER_MCR(TIMER3) - -/* Match Register 0 */ -#define TIMER_MR0(timer) MMIO32((timer) + 0x018) -#define TIMER0_MR0 TIMER_MR0(TIMER0) -#define TIMER1_MR0 TIMER_MR0(TIMER1) -#define TIMER2_MR0 TIMER_MR0(TIMER2) -#define TIMER3_MR0 TIMER_MR0(TIMER3) - -/* Match Register 1 */ -#define TIMER_MR1(timer) MMIO32((timer) + 0x01C) -#define TIMER0_MR1 TIMER_MR1(TIMER0) -#define TIMER1_MR1 TIMER_MR1(TIMER1) -#define TIMER2_MR1 TIMER_MR1(TIMER2) -#define TIMER3_MR1 TIMER_MR1(TIMER3) - -/* Match Register 2 */ -#define TIMER_MR2(timer) MMIO32((timer) + 0x020) -#define TIMER0_MR2 TIMER_MR2(TIMER0) -#define TIMER1_MR2 TIMER_MR2(TIMER1) -#define TIMER2_MR2 TIMER_MR2(TIMER2) -#define TIMER3_MR2 TIMER_MR2(TIMER3) - -/* Match Register 3 */ -#define TIMER_MR3(timer) MMIO32((timer) + 0x024) -#define TIMER0_MR3 TIMER_MR3(TIMER0) -#define TIMER1_MR3 TIMER_MR3(TIMER1) -#define TIMER2_MR3 TIMER_MR3(TIMER2) -#define TIMER3_MR3 TIMER_MR3(TIMER3) - -/* Capture Control Register */ -#define TIMER_CCR(timer) MMIO32((timer) + 0x028) -#define TIMER0_CCR TIMER_CCR(TIMER0) -#define TIMER1_CCR TIMER_CCR(TIMER1) -#define TIMER2_CCR TIMER_CCR(TIMER2) -#define TIMER3_CCR TIMER_CCR(TIMER3) - -/* Capture Register 0 */ -#define TIMER_CR0(timer) MMIO32((timer) + 0x02C) -#define TIMER0_CR0 TIMER_CR0(TIMER0) -#define TIMER1_CR0 TIMER_CR0(TIMER1) -#define TIMER2_CR0 TIMER_CR0(TIMER2) -#define TIMER3_CR0 TIMER_CR0(TIMER3) - -/* Capture Register 1 */ -#define TIMER_CR1(timer) MMIO32((timer) + 0x030) -#define TIMER0_CR1 TIMER_CR1(TIMER0) -#define TIMER1_CR1 TIMER_CR1(TIMER1) -#define TIMER2_CR1 TIMER_CR1(TIMER2) -#define TIMER3_CR1 TIMER_CR1(TIMER3) - -/* Capture Register 2 */ -#define TIMER_CR2(timer) MMIO32((timer) + 0x034) -#define TIMER0_CR2 TIMER_CR2(TIMER0) -#define TIMER1_CR2 TIMER_CR2(TIMER1) -#define TIMER2_CR2 TIMER_CR2(TIMER2) -#define TIMER3_CR2 TIMER_CR2(TIMER3) - -/* Capture Register 3 */ -#define TIMER_CR3(timer) MMIO32((timer) + 0x038) -#define TIMER0_CR3 TIMER_CR3(TIMER0) -#define TIMER1_CR3 TIMER_CR3(TIMER1) -#define TIMER2_CR3 TIMER_CR3(TIMER2) -#define TIMER3_CR3 TIMER_CR3(TIMER3) - -/* External Match Register */ -#define TIMER_EMR(timer) MMIO32((timer) + 0x03C) -#define TIMER0_EMR TIMER_EMR(TIMER0) -#define TIMER1_EMR TIMER_EMR(TIMER1) -#define TIMER2_EMR TIMER_EMR(TIMER2) -#define TIMER3_EMR TIMER_EMR(TIMER3) - -/* Count Control Register */ -#define TIMER_CTCR(timer) MMIO32((timer) + 0x070) -#define TIMER0_CTCR TIMER_CTCR(TIMER0) -#define TIMER1_CTCR TIMER_CTCR(TIMER1) -#define TIMER2_CTCR TIMER_CTCR(TIMER2) -#define TIMER3_CTCR TIMER_CTCR(TIMER3) - -/* --- TIMERx_IR values ----------------------------------------------------- */ - -#define TIMER_IR_MR0INT (1 << 0) -#define TIMER_IR_MR1INT (1 << 1) -#define TIMER_IR_MR2INT (1 << 2) -#define TIMER_IR_MR3INT (1 << 3) -#define TIMER_IR_CR0INT (1 << 4) -#define TIMER_IR_CR1INT (1 << 5) -#define TIMER_IR_CR2INT (1 << 6) -#define TIMER_IR_CR3INT (1 << 7) - -/* --- TIMERx_TCR values --------------------------------------------------- */ - -#define TIMER_TCR_CEN (1 << 0) -#define TIMER_TCR_CRST (1 << 1) - -/* --- TIMERx_MCR values --------------------------------------------------- */ - -#define TIMER_MCR_MR0I (1 << 0) -#define TIMER_MCR_MR0R (1 << 1) -#define TIMER_MCR_MR0S (1 << 2) -#define TIMER_MCR_MR1I (1 << 3) -#define TIMER_MCR_MR1R (1 << 4) -#define TIMER_MCR_MR1S (1 << 5) -#define TIMER_MCR_MR2I (1 << 6) -#define TIMER_MCR_MR2R (1 << 7) -#define TIMER_MCR_MR2S (1 << 8) -#define TIMER_MCR_MR3I (1 << 9) -#define TIMER_MCR_MR3R (1 << 10) -#define TIMER_MCR_MR3S (1 << 11) - -/* --- TIMERx_MCR values --------------------------------------------------- */ - -#define TIMER_CCR_CAP0RE (1 << 0) -#define TIMER_CCR_CAP0FE (1 << 1) -#define TIMER_CCR_CAP0I (1 << 2) -#define TIMER_CCR_CAP1RE (1 << 3) -#define TIMER_CCR_CAP1FE (1 << 4) -#define TIMER_CCR_CAP1I (1 << 5) -#define TIMER_CCR_CAP2RE (1 << 6) -#define TIMER_CCR_CAP2FE (1 << 7) -#define TIMER_CCR_CAP2I (1 << 8) -#define TIMER_CCR_CAP3RE (1 << 9) -#define TIMER_CCR_CAP3FE (1 << 10) -#define TIMER_CCR_CAP3I (1 << 11) - -/* --- TIMERx_EMR values --------------------------------------------------- */ - -#define TIMER_EMR_EM0 (1 << 0) -#define TIMER_EMR_EM1 (1 << 1) -#define TIMER_EMR_EM2 (1 << 2) -#define TIMER_EMR_EM3 (1 << 3) -#define TIMER_EMR_EMC0_SHIFT 4 -#define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT) -#define TIMER_EMR_EMC1_SHIFT 6 -#define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT) -#define TIMER_EMR_EMC2_SHIFT 8 -#define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT) -#define TIMER_EMR_EMC3_SHIFT 10 -#define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT) - -#define TIMER_EMR_EMC_NOTHING 0x0 -#define TIMER_EMR_EMC_CLEAR 0x1 -#define TIMER_EMR_EMC_SET 0x2 -#define TIMER_EMR_EMC_TOGGLE 0x3 - -/* --- TIMERx_CTCR values -------------------------------------------------- */ - -#define TIMER_CTCR_MODE_TIMER (0x0 << 0) -#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) -#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) -#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) -#define TIMER_CTCR_MODE_MASK (0x3 << 0) - -#define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2) -#define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2) -#define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2) -#define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2) -#define TIMER_CTCR_CINSEL_MASK (0x3 << 2) - -/* --- TIMER function prototypes ------------------------------------------- */ - -BEGIN_DECLS - -void timer_reset(uint32_t timer_peripheral); -void timer_enable_counter(uint32_t timer_peripheral); -void timer_disable_counter(uint32_t timer_peripheral); -uint32_t timer_get_counter(uint32_t timer_peripheral); -void timer_set_counter(uint32_t timer_peripheral, uint32_t count); -uint32_t timer_get_prescaler(uint32_t timer_peripheral); -void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); -void timer_set_mode(uint32_t timer_peripheral, uint32_t mode); -void timer_set_count_input(uint32_t timer_peripheral, uint32_t input); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/uart.h b/libopencm3/include/libopencm3/lpc43xx/uart.h deleted file mode 100644 index 5ec4533..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/uart.h +++ /dev/null @@ -1,438 +0,0 @@ -/* -* This file is part of the libopencm3 project. -* -* Copyright (C) 2012 Benjamin Vernoux -* -* This library is free software: you can redistribute it and/or modify -* it under the terms of the GNU Lesser General Public License as published by -* the Free Software Foundation, either version 3 of the License, or -* (at your option) any later version. -* -* This library is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU Lesser General Public License for more details. -* -* You should have received a copy of the GNU Lesser General Public License -* along with this library. If not, see . -*/ - -#ifndef LPC43XX_UART_H -#define LPC43XX_UART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* UART port base addresses (for convenience) */ -#define UART0 USART0_BASE /* APB0 */ -#define UART1 UART1_BASE /* APB0 */ -#define UART2 USART2_BASE /* APB2 */ -#define UART3 USART3_BASE /* APB2 */ - -/* --- UART registers ------------------------------------------------------- */ - -/* Receiver Buffer Register (DLAB=0) Read Only */ -#define UART_RBR(port) MMIO32((port) + 0x000) /* 8bits */ - -/* Transmitter Holding Register (DLAB=0) Write Only */ -#define UART_THR(port) MMIO32((port) + 0x000) /* 8bits */ - -/* Divisor Latch LSB Register (DLAB=1) */ -#define UART_DLL(port) MMIO32((port) + 0x000) /* 8bits */ - -/* Divisor Latch MSB Register (DLAB=1) */ -#define UART_DLM(port) MMIO32((port) + 0x004) /* 8bits */ - -/* Interrupt Enable Register (DLAB=0) */ -#define UART_IER(port) MMIO32((port) + 0x004) - -/* Interrupt ID Register Read Only */ -#define UART_IIR(port) MMIO32((port) + 0x008) - -/* FIFO Control Register Write Only */ -#define UART_FCR(port) MMIO32((port) + 0x008) - -/* Line Control Register */ -#define UART_LCR(port) MMIO32((port) + 0x00C) - -/* MCR only for UART1 */ - -/* Line Status Register */ -#define UART_LSR(port) MMIO32((port) + 0x014) - -/* Auto Baud Control Register */ -#define UART_ACR(port) MMIO32((port) + 0x020) - -/* IrDA Control Register only for UART0/2/3 */ -#define UART_ICR(port) MMIO32((port) + 0x024) - -/* Fractional Divider Register */ -#define UART_FDR(port) MMIO32((port) + 0x028) - -/* Oversampling Register only for UART0/2/3 */ -#define UART_OSR(port) MMIO32((port) + 0x02C) - -/* Half-Duplex enable Register only for UART0/2/3 */ -#define UART_HDEN(port) MMIO32((port) + 0x040) - -/* Smart card Interface Register Only for UART0/2/3 */ -#define UART_SCICTRL(port) MMIO32((port) + 0x048) - -/* RS-485/EIA-485 Control Register */ -#define UART_RS485CTRL(port) MMIO32((port) + 0x04C) - -/* RS-485/EIA-485 Address Match Register */ -#define UART_RS485ADRMATCH(port) MMIO32((port) + 0x050) - -/* RS-485/EIA-485 Direction Control Delay Register */ -#define UART_RS485DLY(port) MMIO32((port) + 0x054) - -/* Synchronous Mode Control Register only for UART0/2/3 */ -#define UART_SYNCCTRL(port) MMIO32((port) + 0x058) - -/* Transmit Enable Register */ -#define UART_TER(port) MMIO32((port) + 0x05C) - -/* --------------------- BIT DEFINITIONS ----------------------------------- */ -/*********************************************************************** -* Macro defines for Macro defines for UARTn Receiver Buffer Register -**********************************************************************/ -/* UART Received Buffer mask bit (8 bits) */ -#define UART_RBR_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************** -* Macro defines for Macro defines for UARTn Transmit Holding Register -**********************************************************************/ -/* UART Transmit Holding mask bit (8 bits) */ -#define UART_THR_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************** -* Macro defines for Macro defines for UARTn Divisor Latch LSB register -**********************************************************************/ -/* Macro for loading least significant halfs of divisors */ -#define UART_LOAD_DLL(div) ((div) & 0xFF) - -/* Divisor latch LSB bit mask */ -#define UART_DLL_MASKBIT ((uint8_t)0xFF) - -/*********************************************************************** -* Macro defines for Macro defines for UARTn Divisor Latch MSB register -**********************************************************************/ -/* Divisor latch MSB bit mask */ -#define UART_DLM_MASKBIT ((uint8_t)0xFF) - -/* Macro for loading most significant halfs of divisors */ -#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) - -/*********************************************************************** -* Macro defines for Macro defines for UART interrupt enable register -**********************************************************************/ -/* RBR Interrupt enable*/ -#define UART_IER_RBRINT_EN (1 << 0) -/* THR Interrupt enable*/ -#define UART_IER_THREINT_EN (1 << 1) -/* RX line status interrupt enable*/ -#define UART_IER_RLSINT_EN (1 << 2) -/* Modem status interrupt enable */ -#define UART1_IER_MSINT_EN (1 << 3) -/* CTS1 signal transition interrupt enable */ -#define UART1_IER_CTSINT_EN (1 << 7) -/* Enables the end of auto-baud interrupt */ -#define UART_IER_ABEOINT_EN (1 << 8) -/* Enables the auto-baud time-out interrupt */ -#define UART_IER_ABTOINT_EN (1 << 9) -/* UART interrupt enable register bit mask */ -#define UART_IER_BITMASK ((uint32_t)(0x307)) -/* UART1 interrupt enable register bit mask */ -#define UART1_IER_BITMASK ((uint32_t)(0x38F)) - -/********************************************************************** -* Macro defines for Macro defines for UART interrupt identification register -**********************************************************************/ - -/* Interrupt Status - Active low */ -#define UART_IIR_INTSTAT_PEND (1 << 0) -/* Interrupt identification: Modem interrupt*/ -#define UART1_IIR_INTID_MODEM (0 << 1) -/* Interrupt identification: THRE interrupt*/ -#define UART_IIR_INTID_THRE (1 << 1) -/* Interrupt identification: Receive data available*/ -#define UART_IIR_INTID_RDA (2 << 1) -/* Interrupt identification: Receive line status*/ -#define UART_IIR_INTID_RLS (3 << 1) -/* Interrupt identification: Character time-out indicator*/ -#define UART_IIR_INTID_CTI (6 << 1) -/* Interrupt identification: Interrupt ID mask */ -#define UART_IIR_INTID_MASK (7 << 1) -/* These bits are equivalent to UnFCR[0] */ -#define UART_IIR_FIFO_EN (3 << 6) -/* End of auto-baud interrupt */ -#define UART_IIR_ABEO_INT (1 << 8) -/* Auto-baud time-out interrupt */ -#define UART_IIR_ABTO_INT (1 << 9) -/* UART interrupt identification register bit mask */ -#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) - -/********************************************************************** -* Macro defines for Macro defines for UART FIFO control register -**********************************************************************/ -/* UART FIFO enable */ -#define UART_FCR_FIFO_EN (1 << 0) -/* UART FIFO RX reset */ -#define UART_FCR_RX_RS (1 << 1) -/* UART FIFO TX reset */ -#define UART_FCR_TX_RS (1 << 2) -/* UART DMA mode selection */ -#define UART_FCR_DMAMODE_SEL (1 << 3) -/* UART FIFO trigger level 0: 1 character */ -#define UART_FCR_TRG_LEV0 (0 << 6) -/* UART FIFO trigger level 1: 4 character */ -#define UART_FCR_TRG_LEV1 (1 << 6) -/* UART FIFO trigger level 2: 8 character */ -#define UART_FCR_TRG_LEV2 (2 << 6) -/* UART FIFO trigger level 3: 14 character */ -#define UART_FCR_TRG_LEV3 (3 << 6) -/* UART FIFO control bit mask */ -#define UART_FCR_BITMASK ((uint8_t)(0xCF)) -#define UART_TX_FIFO_SIZE (16) - -/********************************************************************** -* Macro defines for Macro defines for UART line control register -**********************************************************************/ -/* UART 5 bit data mode */ -#define UART_LCR_WLEN5 (0 << 0) -/* UART 6 bit data mode */ -#define UART_LCR_WLEN6 (1 << 0) -/* UART 7 bit data mode */ -#define UART_LCR_WLEN7 (2 << 0) -/* UART 8 bit data mode */ -#define UART_LCR_WLEN8 (3 << 0) -/* UART One Stop Bits */ -#define UART_LCR_ONE_STOPBIT (0 << 2) -/* UART Two Stop Bits */ -#define UART_LCR_TWO_STOPBIT (1 << 2) - -/* UART Parity Disabled / No Parity */ -#define UART_LCR_NO_PARITY (0 << 3) -/* UART Parity Enable */ -#define UART_LCR_PARITY_EN (1 << 3) -/* UART Odd Parity Select */ -#define UART_LCR_PARITY_ODD (0 << 4) -/* UART Even Parity Select */ -#define UART_LCR_PARITY_EVEN (1 << 4) -/* UART force 1 stick parity */ -#define UART_LCR_PARITY_SP_1 (1 << 5) -/* UART force 0 stick parity */ -#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4)) -/* UART Transmission Break enable */ -#define UART_LCR_BREAK_EN (1 << 6) -/* UART Divisor Latches Access bit enable */ -#define UART_LCR_DLAB_EN (1 << 7) -/* UART line control bit mask */ -#define UART_LCR_BITMASK ((uint8_t)(0xFF)) - -/********************************************************************** -* Macro defines for Macro defines for UART line status register -**********************************************************************/ -/* Line status register: Receive data ready */ -#define UART_LSR_RDR (1 << 0) -/* Line status register: Overrun error */ -#define UART_LSR_OE (1 << 1) -/* Line status register: Parity error */ -#define UART_LSR_PE (1 << 2) -/* Line status register: Framing error */ -#define UART_LSR_FE (1 << 3) -/* Line status register: Break interrupt */ -#define UART_LSR_BI (1 << 4) -/* Line status register: Transmit holding register empty */ -#define UART_LSR_THRE (1 << 5) -/* Line status register: Transmitter empty */ -#define UART_LSR_TEMT (1 << 6) -/* Error in RX FIFO */ -#define UART_LSR_RXFE (1 << 7) -/* UART Line status bit mask */ -#define UART_LSR_BITMASK ((uint8_t)(0xFF)) -#define UART_LSR_ERROR_MASK \ - (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE) - -/********************************************************************** -* Macro defines for Macro defines for UART Scratch Pad Register -**********************************************************************/ - -/* UART Scratch Pad bit mask */ -#define UART_SCR_BIMASK ((uint8_t)(0xFF)) - -/*********************************************************************** -* Macro defines for Macro defines for UART Auto baudrate control register -**********************************************************************/ - -/* UART Auto-baud start */ -#define UART_ACR_START (1 << 0) -/* UART Auto baudrate Mode 1 */ -#define UART_ACR_MODE (1 << 1) -/* UART Auto baudrate restart */ -#define UART_ACR_AUTO_RESTART (1 << 2) -/* UART End of auto-baud interrupt clear */ -#define UART_ACR_ABEOINT_CLR (1 << 8) -/* UART Auto-baud time-out interrupt clear */ -#define UART_ACR_ABTOINT_CLR (1 << 9) -/* UART Auto Baudrate register bit mask */ -#define UART_ACR_BITMASK ((uint32_t)(0x307)) - -/********************************************************************* -* Macro defines for Macro defines for UART IrDA control register -**********************************************************************/ -/* IrDA mode enable */ -#define UART_ICR_IRDAEN (1 << 0) -/* IrDA serial input inverted */ -#define UART_ICR_IRDAINV (1 << 1) -/* IrDA fixed pulse width mode */ -#define UART_ICR_FIXPULSE_EN (1 << 2) -/* PulseDiv - Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV(n) ((uint32_t)(((n)&0x07)<<3)) -/* UART IRDA bit mask */ -#define UART_ICR_BITMASK ((uint32_t)(0x3F)) - -/********************************************************************** -* Macro defines for Macro defines for UART half duplex register -**********************************************************************/ -/* enable half-duplex mode*/ -#define UART_HDEN_HDEN (1 << 0) - -/********************************************************************** -* Macro defines for Macro defines for UART smart card interface control register -**********************************************************************/ -/* enable asynchronous half-duplex smart card interface*/ -#define UART_SCICTRL_SCIEN (1 << 0) -/* NACK response is inhibited*/ -#define UART_SCICTRL_NACKDIS (1 << 1) -/* ISO7816-3 protocol T1 is selected*/ -#define UART_SCICTRL_PROTSEL_T1 (1 << 2) -/* number of retransmission*/ -#define UART_SCICTRL_TXRETRY(n) ((uint32_t)(((n)&0x07)<<5)) -/* Extra guard time*/ -#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)(((n)&0xFF)<<8)) - -/********************************************************************* -* Macro defines for Macro defines for UART synchronous control register -**********************************************************************/ -/* enable synchronous mode*/ -#define UART_SYNCCTRL_SYNC (1 << 0) -/* synchronous master mode*/ -#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) -/* sample on falling edge*/ -#define UART_SYNCCTRL_FES (1 << 2) -/* to be defined*/ -#define UART_SYNCCTRL_TSBYPASS (1 << 3) -/* continuous running clock enable (master mode only) */ -#define UART_SYNCCTRL_CSCEN (1 << 4) -/* Do not send start/stop bit */ -#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5) -/* stop continuous clock */ -#define UART_SYNCCTRL_CCCLR (1 << 6) - -/********************************************************************* -* Macro defines for Macro defines for UART Fractional divider register -**********************************************************************/ - -/* Baud-rate generation pre-scaler divisor */ -#define UART_FDR_DIVADDVAL(n) ((uint32_t)((n)&0x0F)) -/* Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL(n) ((uint32_t)(((n)<<4)&0xF0)) -/* UART Fractional Divider register bit mask */ -#define UART_FDR_BITMASK ((uint32_t)(0xFF)) - -/********************************************************************* -* Macro defines for Macro defines for UART Tx Enable register -**********************************************************************/ - -#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */ - -/********************************************************************** -* Macro defines for Macro defines for UART FIFO Level register -**********************************************************************/ -/* Reflects the current level of the UART receiver FIFO */ -#define UART_FIFOLVL_RX(n) ((uint32_t)((n)&0x0F)) -/* Reflects the current level of the UART transmitter FIFO */ -#define UART_FIFOLVL_TX(n) ((uint32_t)(((n)>>8)&0x0F)) -/* UART FIFO Level Register bit mask */ -#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) - -/********************************************************************* -* UART enum -**********************************************************************/ - -/* -* UART Databit type definitions -*/ -typedef enum { - UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */ - UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */ - UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */ - UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */ -} uart_databit_t; - -/* -* UART Stop bit type definitions -*/ -typedef enum { - /* UART 1 Stop Bits Select */ - UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, - /* UART 2 Stop Bits Select */ - UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT -} uart_stopbit_t; - -/* -* UART Parity type definitions -*/ -typedef enum { - /* No parity */ - UART_PARITY_NONE = UART_LCR_NO_PARITY, - /* Odd parity */ - UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), - /* Even parity */ - UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), - /* Forced 1 stick parity */ - UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), - /* Forced 0 stick parity */ - UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) -} uart_parity_t; - -typedef enum { - UART0_NUM = UART0, - UART1_NUM = UART1, - UART2_NUM = UART2, - UART3_NUM = UART3 -} uart_num_t; - -typedef enum { - UART_NO_ERROR = 0, - UART_TIMEOUT_ERROR = 1 -} uart_error_t; - -typedef enum { - UART_RX_NO_DATA = 0, - UART_RX_DATA_READY = 1, - UART_RX_DATA_ERROR = 2 -} uart_rx_data_ready_t; - -/* function prototypes */ - -BEGIN_DECLS - -/* Init UART and set PLL1 as clock source (PCLK) */ -void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, - uart_stopbit_t data_nb_stop, uart_parity_t data_parity, - uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval); - -uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); -uint8_t uart_read(uart_num_t uart_num); -uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, - uart_error_t *error); -void uart_write(uart_num_t uart_num, uint8_t data); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/usb.h b/libopencm3/include/libopencm3/lpc43xx/usb.h deleted file mode 100644 index 9132fb7..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/usb.h +++ /dev/null @@ -1,1337 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_USB_H -#define LPC43XX_USB_H - -#include -#include - -#define BIT_MASK(base_name) \ - (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) -#define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT) - -/* USB device data structures */ - -/* "The software must ensure that no interface data structure reachable - * by the Device controller crosses a 4kB-page boundary." - */ - -/* --- Endpoint Transfer Descriptor (dTD) ---------------------------------- */ - -typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t; -struct usb_transfer_descriptor_t { - volatile usb_transfer_descriptor_t *next_dtd_pointer; - volatile uint32_t total_bytes; - volatile uint32_t buffer_pointer_page[5]; - volatile uint32_t _reserved; -}; - -#define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0) -#define USB_TD_NEXT_DTD_POINTER_TERMINATE \ - ((volatile usb_transfer_descriptor_t *) \ - (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) - -#define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) -#define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) -#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) -#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, (x)) - -#define USB_TD_DTD_TOKEN_IOC_SHIFT (15) -#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) - -#define USB_TD_DTD_TOKEN_MULTO_SHIFT (10) -#define USB_TD_DTD_TOKEN_MULTO_WIDTH (2) -#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) -#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, (x)) - -#define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) -#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ - (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) - -#define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6) -#define USB_TD_DTD_TOKEN_STATUS_HALTED \ - (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) - -#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5) -#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \ - (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) - -#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3) -#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \ - (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) - -/* --- Endpoint Queue Head (dQH) ------------------------------------------- */ - -/* - must be aligned on 64-byte boundaries. */ -typedef struct { - volatile uint32_t capabilities; - volatile usb_transfer_descriptor_t *current_dtd_pointer; - volatile usb_transfer_descriptor_t *next_dtd_pointer; - volatile uint32_t total_bytes; - volatile uint32_t buffer_pointer_page[5]; - volatile uint32_t _reserved_0; - volatile uint8_t setup[8]; - volatile uint32_t _reserved_1[4]; -} usb_queue_head_t; - -#define USB_QH_CAPABILITIES_IOS_SHIFT (15) -#define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) - -#define USB_QH_CAPABILITIES_MPL_SHIFT (16) -#define USB_QH_CAPABILITIES_MPL_WIDTH (11) -#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) -#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, (x)) - -#define USB_QH_CAPABILITIES_ZLT_SHIFT (29) -#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) - -#define USB_QH_CAPABILITIES_MULT_SHIFT (30) -#define USB_QH_CAPABILITIES_MULT_WIDTH (2) -#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) -#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, (x)) - -/* --- USB0 registers ------------------------------------------------------ */ - -/* Device/host capability registers */ - -/* Capability register length */ -#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100) - -/* Host controller structural parameters */ -#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104) - -/* Host controller capability parameters */ -#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108) - -/* Device interface version number */ -#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120) - -/* Device controller capability parameters */ -#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124) - - -/* Device/host operational registers */ - -/* USB command (device mode) */ -#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140) - -/* USB command (host mode) */ -#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140) - -/* USB status (device mode) */ -#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144) - -/* USB status (host mode) */ -#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144) - -/* USB interrupt enable (device mode) */ -#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148) - -/* USB interrupt enable (host mode) */ -#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148) - -/* USB frame index (device mode) */ -#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C) - -/* USB frame index (host mode) */ -#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C) - -/* USB device address (device mode) */ -#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154) - -/* Frame list base address (host mode) */ -#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154) - -/* Address of endpoint list in memory */ -#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158) - -/* Asynchronous list address */ -#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158) - -/* Asynchronous buffer status for embedded TT (host mode) */ -#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C) - -/* Programmable burst size */ -#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160) - -/* Host transmit pre-buffer packet tuning (host mode) */ -#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164) - -/* Length of virtual frame */ -#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174) - -/* Endpoint NAK (device mode) */ -#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178) - -/* Endpoint NAK Enable (device mode) */ -#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C) - -/* Port 1 status/control (device mode) */ -#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184) - -/* Port 1 status/control (host mode) */ -#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184) - -/* OTG status and control */ -#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4) - -/* USB device mode (device mode) */ -#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8) - -/* USB device mode (host mode) */ -#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8) - - -/* Device endpoint registers */ - -/* Endpoint setup status */ -#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC) - -/* Endpoint initialization */ -#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0) - -/* Endpoint de-initialization */ -#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4) - -/* Endpoint status */ -#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8) - -/* Endpoint complete */ -#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) - -/* Endpoint control */ -#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ - ((logical_ep) * 4)) - -/* Endpoint control 0 */ -#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) - -/* Endpoint control 1 */ -#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) - -/* Endpoint control 2 */ -#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) - -/* Endpoint control 3 */ -#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) - -/* Endpoint control 4 */ -#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) - -/* Endpoint control 5 */ -#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) - -/* --- USB0_CAPLENGTH values ------------------------------------ */ - -/* CAPLENGTH: Indicates offset to add to the register base address at the - beginning of the Operational Register */ -#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) -#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) -#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) - -/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host - controller */ -#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) -#define USB0_CAPLENGTH_HCIVERSION_MASK \ - (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) -#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) - -/* --- USB0_HCSPARAMS values ------------------------------------ */ - -/* N_PORTS: Number of downstream ports */ -#define USB0_HCSPARAMS_N_PORTS_SHIFT (0) -#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) -#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) - -/* PPC: Port Power Control */ -#define USB0_HCSPARAMS_PPC_SHIFT (4) -#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) - -/* N_PCC: Number of Ports per Companion Controller */ -#define USB0_HCSPARAMS_N_PCC_SHIFT (8) -#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) -#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) - -/* N_CC: Number of Companion Controller */ -#define USB0_HCSPARAMS_N_CC_SHIFT (12) -#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) -#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT) - -/* PI: Port indicators */ -#define USB0_HCSPARAMS_PI_SHIFT (16) -#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) - -/* N_PTT: Number of Ports per Transaction Translator */ -#define USB0_HCSPARAMS_N_PTT_SHIFT (20) -#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) -#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) - -/* N_TT: Number of Transaction Translators */ -#define USB0_HCSPARAMS_N_TT_SHIFT (24) -#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) -#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT) - -/* --- USB0_HCCPARAMS values ------------------------------------ */ - -/* ADC: 64-bit Addressing Capability */ -#define USB0_HCCPARAMS_ADC_SHIFT (0) -#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) - -/* PFL: Programmable Frame List Flag */ -#define USB0_HCCPARAMS_PFL_SHIFT (1) -#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) - -/* ASP: Asynchronous Schedule Park Capability */ -#define USB0_HCCPARAMS_ASP_SHIFT (2) -#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) - -/* IST: Isochronous Scheduling Threshold */ -#define USB0_HCCPARAMS_IST_SHIFT (4) -#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) -#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT) - -/* EECP: EHCI Extended Capabilities Pointer */ -#define USB0_HCCPARAMS_EECP_SHIFT (8) -#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) -#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT) - -/* --- USB0_DCCPARAMS values ------------------------------------ */ - -/* DEN: Device Endpoint Number */ -#define USB0_DCCPARAMS_DEN_SHIFT (0) -#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) -#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT) - -/* DC: Device Capable */ -#define USB0_DCCPARAMS_DC_SHIFT (7) -#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) - -/* HC: Host Capable */ -#define USB0_DCCPARAMS_HC_SHIFT (8) -#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) - -/* --- USB0_USBCMD_D values ------------------------------------- */ - -/* RS: Run/Stop */ -#define USB0_USBCMD_D_RS_SHIFT (0) -#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) - -/* RST: Controller reset */ -#define USB0_USBCMD_D_RST_SHIFT (1) -#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) - -/* SUTW: Setup trip wire */ -#define USB0_USBCMD_D_SUTW_SHIFT (13) -#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) - -/* ATDTW: Add dTD trip wire */ -#define USB0_USBCMD_D_ATDTW_SHIFT (14) -#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) - -/* ITC: Interrupt threshold control */ -#define USB0_USBCMD_D_ITC_SHIFT (16) -#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) -#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT) - -/* --- USB0_USBCMD_H values ------------------------------------- */ - -/* RS: Run/Stop */ -#define USB0_USBCMD_H_RS_SHIFT (0) -#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) - -/* RST: Controller reset */ -#define USB0_USBCMD_H_RST_SHIFT (1) -#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) - -/* FS0: Bit 0 of the Frame List Size bits */ -#define USB0_USBCMD_H_FS0_SHIFT (2) -#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) - -/* FS1: Bit 1 of the Frame List Size bits */ -#define USB0_USBCMD_H_FS1_SHIFT (3) -#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) - -/* PSE: This bit controls whether the host controller skips processing the -periodic schedule */ -#define USB0_USBCMD_H_PSE_SHIFT (4) -#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) - -/* ASE: This bit controls whether the host controller skips processing the -asynchronous schedule */ -#define USB0_USBCMD_H_ASE_SHIFT (5) -#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) - -/* IAA: This bit is used as a doorbell by software to tell the host controller -to issue an interrupt the next time it advances asynchronous schedule */ -#define USB0_USBCMD_H_IAA_SHIFT (6) -#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) - -/* ASP1_0: Asynchronous schedule park mode */ -#define USB0_USBCMD_H_ASP1_0_SHIFT (8) -#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) -#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) - -/* ASPE: Asynchronous Schedule Park Mode Enable */ -#define USB0_USBCMD_H_ASPE_SHIFT (11) -#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) - -/* FS2: Bit 2 of the Frame List Size bits */ -#define USB0_USBCMD_H_FS2_SHIFT (15) -#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) - -/* ITC: Interrupt threshold control */ -#define USB0_USBCMD_H_ITC_SHIFT (16) -#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) -#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT) - -/* --- USB0_USBSTS_D values ------------------------------------- */ - -/* UI: USB interrupt */ -#define USB0_USBSTS_D_UI_SHIFT (0) -#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) - -/* UEI: USB error interrupt */ -#define USB0_USBSTS_D_UEI_SHIFT (1) -#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) - -/* PCI: Port change detect */ -#define USB0_USBSTS_D_PCI_SHIFT (2) -#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) - -/* URI: USB reset received */ -#define USB0_USBSTS_D_URI_SHIFT (6) -#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) - -/* SRI: SOF received */ -#define USB0_USBSTS_D_SRI_SHIFT (7) -#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) - -/* SLI: DCSuspend */ -#define USB0_USBSTS_D_SLI_SHIFT (8) -#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) - -/* NAKI: NAK interrupt bit */ -#define USB0_USBSTS_D_NAKI_SHIFT (16) -#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) - -/* --- USB0_USBSTS_H values ------------------------------------- */ - -/* UI: USB interrupt */ -#define USB0_USBSTS_H_UI_SHIFT (0) -#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) - -/* UEI: USB error interrupt */ -#define USB0_USBSTS_H_UEI_SHIFT (1) -#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) - -/* PCI: Port change detect */ -#define USB0_USBSTS_H_PCI_SHIFT (2) -#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) - -/* FRI: Frame list roll-over */ -#define USB0_USBSTS_H_FRI_SHIFT (3) -#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) - -/* AAI: Interrupt on async advance */ -#define USB0_USBSTS_H_AAI_SHIFT (5) -#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) - -/* SRI: SOF received */ -#define USB0_USBSTS_H_SRI_SHIFT (7) -#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) - -/* HCH: HCHalted */ -#define USB0_USBSTS_H_HCH_SHIFT (12) -#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) - -/* RCL: Reclamation */ -#define USB0_USBSTS_H_RCL_SHIFT (13) -#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) - -/* PS: Periodic schedule status */ -#define USB0_USBSTS_H_PS_SHIFT (14) -#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) - -/* AS: Asynchronous schedule status */ -#define USB0_USBSTS_H_AS_SHIFT (15) -#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) - -/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ -#define USB0_USBSTS_H_UAI_SHIFT (18) -#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) - -/* UPI: USB host periodic interrupt (USBHSTPERINT) */ -#define USB0_USBSTS_H_UPI_SHIFT (19) -#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) - -/* --- USB0_USBINTR_D values ------------------------------------ */ - -/* UE: USB interrupt enable */ -#define USB0_USBINTR_D_UE_SHIFT (0) -#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) - -/* UEE: USB error interrupt enable */ -#define USB0_USBINTR_D_UEE_SHIFT (1) -#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) - -/* PCE: Port change detect enable */ -#define USB0_USBINTR_D_PCE_SHIFT (2) -#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) - -/* URE: USB reset enable */ -#define USB0_USBINTR_D_URE_SHIFT (6) -#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) - -/* SRE: SOF received enable */ -#define USB0_USBINTR_D_SRE_SHIFT (7) -#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) - -/* SLE: Sleep enable */ -#define USB0_USBINTR_D_SLE_SHIFT (8) -#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) - -/* NAKE: NAK interrupt enable */ -#define USB0_USBINTR_D_NAKE_SHIFT (16) -#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) - -/* --- USB0_USBINTR_H values ------------------------------------ */ - -/* UE: USB interrupt enable */ -#define USB0_USBINTR_H_UE_SHIFT (0) -#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) - -/* UEE: USB error interrupt enable */ -#define USB0_USBINTR_H_UEE_SHIFT (1) -#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) - -/* PCE: Port change detect enable */ -#define USB0_USBINTR_H_PCE_SHIFT (2) -#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) - -/* FRE: Frame list rollover enable */ -#define USB0_USBINTR_H_FRE_SHIFT (3) -#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) - -/* AAE: Interrupt on asynchronous advance enable */ -#define USB0_USBINTR_H_AAE_SHIFT (5) -#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) - -/* SRE: SOF received enable */ -#define USB0_USBINTR_H_SRE_SHIFT (7) -#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) - -/* UAIE: USB host asynchronous interrupt enable */ -#define USB0_USBINTR_H_UAIE_SHIFT (18) -#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) - -/* UPIA: USB host periodic interrupt enable */ -#define USB0_USBINTR_H_UPIA_SHIFT (19) -#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) - -/* --- USB0_FRINDEX_D values ------------------------------------ */ - -/* FRINDEX2_0: Current micro frame number */ -#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0) -#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) -#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) - -/* FRINDEX13_3: Current frame number of the last frame transmitted */ -#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) -#define USB0_FRINDEX_D_FRINDEX13_3_MASK \ - (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) -#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) - -/* --- USB0_FRINDEX_H values ------------------------------------ */ - -/* FRINDEX2_0: Current micro frame number */ -#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0) -#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) -#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) - -/* FRINDEX12_3: Frame list current index */ -#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) -#define USB0_FRINDEX_H_FRINDEX12_3_MASK \ - (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) -#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) - -/* --- USB0_DEVICEADDR values ----------------------------------- */ - -/* USBADRA: Device address advance */ -#define USB0_DEVICEADDR_USBADRA_SHIFT (24) -#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) - -/* USBADR: USB device address */ -#define USB0_DEVICEADDR_USBADR_SHIFT (25) -#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) -#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT) - -/* --- USB0_PERIODICLISTBASE values ----------------------------- */ - -/* PERBASE31_12: Base Address (Low) */ -#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) -#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \ - (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) -#define USB0_PERIODICLISTBASE_PERBASE31_12(x) \ - ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) - -/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ - -/* EPBASE31_11: Endpoint list pointer (low) */ -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \ - (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) -#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \ - ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) - -/* --- USB0_ASYNCLISTADDR values -------------------------------- */ - -/* ASYBASE31_5: Link pointer (Low) LPL */ -#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) -#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \ - (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) -#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \ - ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) - -/* --- USB0_TTCTRL values --------------------------------------- */ - -/* TTHA: Hub address when FS or LS device are connected directly */ -#define USB0_TTCTRL_TTHA_SHIFT (24) -#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) -#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT) - -/* --- USB0_BURSTSIZE values ------------------------------------ */ - -/* RXPBURST: Programmable RX burst length */ -#define USB0_BURSTSIZE_RXPBURST_SHIFT (0) -#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) -#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) - -/* TXPBURST: Programmable TX burst length */ -#define USB0_BURSTSIZE_TXPBURST_SHIFT (8) -#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) -#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) - -/* --- USB0_TXFILLTUNING values --------------------------------- */ - -/* TXSCHOH: FIFO burst threshold */ -#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0) -#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) -#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) - -/* TXSCHEATLTH: Scheduler health counter */ -#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) -#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \ - (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) -#define USB0_TXFILLTUNING_TXSCHEATLTH(x) \ - ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) - -/* TXFIFOTHRES: Scheduler overhead */ -#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) -#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \ - (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) -#define USB0_TXFILLTUNING_TXFIFOTHRES(x) \ - ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* --- USB0_BINTERVAL values ------------------------------------ */ - -/* BINT: bInterval value */ -#define USB0_BINTERVAL_BINT_SHIFT (0) -#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) -#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT) - -/* --- USB0_ENDPTNAK values ------------------------------------- */ - -/* EPRN: Rx endpoint NAK */ -#define USB0_ENDPTNAK_EPRN_SHIFT (0) -#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) -#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT) - -/* EPTN: Tx endpoint NAK */ -#define USB0_ENDPTNAK_EPTN_SHIFT (16) -#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) -#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT) - -/* --- USB0_ENDPTNAKEN values ----------------------------------- */ - -/* EPRNE: Rx endpoint NAK enable */ -#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0) -#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) -#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) - -/* EPTNE: Tx endpoint NAK */ -#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16) -#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) -#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) - -/* --- USB0_PORTSC1_D values ------------------------------------ */ - -/* CCS: Current connect status */ -#define USB0_PORTSC1_D_CCS_SHIFT (0) -#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) - -/* PE: Port enable */ -#define USB0_PORTSC1_D_PE_SHIFT (2) -#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) - -/* PEC: Port enable/disable change */ -#define USB0_PORTSC1_D_PEC_SHIFT (3) -#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) - -/* FPR: Force port resume */ -#define USB0_PORTSC1_D_FPR_SHIFT (6) -#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) - -/* SUSP: Suspend */ -#define USB0_PORTSC1_D_SUSP_SHIFT (7) -#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) - -/* PR: Port reset */ -#define USB0_PORTSC1_D_PR_SHIFT (8) -#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) - -/* HSP: High-speed status */ -#define USB0_PORTSC1_D_HSP_SHIFT (9) -#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) - -/* PIC1_0: Port indicator control */ -#define USB0_PORTSC1_D_PIC1_0_SHIFT (14) -#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) -#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) - -/* PTC3_0: Port test control */ -#define USB0_PORTSC1_D_PTC3_0_SHIFT (16) -#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) -#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) - -/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ -#define USB0_PORTSC1_D_PHCD_SHIFT (23) -#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) - -/* PFSC: Port force full speed connect */ -#define USB0_PORTSC1_D_PFSC_SHIFT (24) -#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) - -/* PSPD: Port speed */ -#define USB0_PORTSC1_D_PSPD_SHIFT (26) -#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) -#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT) - -/* --- USB0_PORTSC1_H values ------------------------------------ */ - -/* CCS: Current connect status */ -#define USB0_PORTSC1_H_CCS_SHIFT (0) -#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) - -/* CSC: Connect status change */ -#define USB0_PORTSC1_H_CSC_SHIFT (1) -#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) - -/* PE: Port enable */ -#define USB0_PORTSC1_H_PE_SHIFT (2) -#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) - -/* PEC: Port disable/enable change */ -#define USB0_PORTSC1_H_PEC_SHIFT (3) -#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) - -/* OCA: Over-current active */ -#define USB0_PORTSC1_H_OCA_SHIFT (4) -#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) - -/* OCC: Over-current change */ -#define USB0_PORTSC1_H_OCC_SHIFT (5) -#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) - -/* FPR: Force port resume */ -#define USB0_PORTSC1_H_FPR_SHIFT (6) -#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) - -/* SUSP: Suspend */ -#define USB0_PORTSC1_H_SUSP_SHIFT (7) -#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) - -/* PR: Port reset */ -#define USB0_PORTSC1_H_PR_SHIFT (8) -#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) - -/* HSP: High-speed status */ -#define USB0_PORTSC1_H_HSP_SHIFT (9) -#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) - -/* LS: Line status */ -#define USB0_PORTSC1_H_LS_SHIFT (10) -#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) -#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT) - -/* PP: Port power control */ -#define USB0_PORTSC1_H_PP_SHIFT (12) -#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) - -/* PIC1_0: Port indicator control */ -#define USB0_PORTSC1_H_PIC1_0_SHIFT (14) -#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) -#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) - -/* PTC3_0: Port test control */ -#define USB0_PORTSC1_H_PTC3_0_SHIFT (16) -#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) -#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) - -/* WKCN: Wake on connect enable (WKCNNT_E) */ -#define USB0_PORTSC1_H_WKCN_SHIFT (20) -#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) - -/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ -#define USB0_PORTSC1_H_WKDC_SHIFT (21) -#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) - -/* WKOC: Wake on over-current enable (WKOC_E) */ -#define USB0_PORTSC1_H_WKOC_SHIFT (22) -#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) - -/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ -#define USB0_PORTSC1_H_PHCD_SHIFT (23) -#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) - -/* PFSC: Port force full speed connect */ -#define USB0_PORTSC1_H_PFSC_SHIFT (24) -#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) - -/* PSPD: Port speed */ -#define USB0_PORTSC1_H_PSPD_SHIFT (26) -#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) -#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT) - -/* --- USB0_OTGSC values ---------------------------------------- */ - -/* VD: VBUS_Discharge */ -#define USB0_OTGSC_VD_SHIFT (0) -#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) - -/* VC: VBUS_Charge */ -#define USB0_OTGSC_VC_SHIFT (1) -#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) - -/* HAAR: Hardware assist auto_reset */ -#define USB0_OTGSC_HAAR_SHIFT (2) -#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) - -/* OT: OTG termination */ -#define USB0_OTGSC_OT_SHIFT (3) -#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) - -/* DP: Data pulsing */ -#define USB0_OTGSC_DP_SHIFT (4) -#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) - -/* IDPU: ID pull-up */ -#define USB0_OTGSC_IDPU_SHIFT (5) -#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) - -/* HADP: Hardware assist data pulse */ -#define USB0_OTGSC_HADP_SHIFT (6) -#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) - -/* HABA: Hardware assist B-disconnect to A-connect */ -#define USB0_OTGSC_HABA_SHIFT (7) -#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) - -/* ID: USB ID */ -#define USB0_OTGSC_ID_SHIFT (8) -#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) - -/* AVV: A-VBUS valid */ -#define USB0_OTGSC_AVV_SHIFT (9) -#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) - -/* ASV: A-session valid */ -#define USB0_OTGSC_ASV_SHIFT (10) -#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) - -/* BSV: B-session valid */ -#define USB0_OTGSC_BSV_SHIFT (11) -#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) - -/* BSE: B-session end */ -#define USB0_OTGSC_BSE_SHIFT (12) -#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) - -/* MS1T: 1 millisecond timer toggle */ -#define USB0_OTGSC_MS1T_SHIFT (13) -#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) - -/* DPS: Data bus pulsing status */ -#define USB0_OTGSC_DPS_SHIFT (14) -#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) - -/* IDIS: USB ID interrupt status */ -#define USB0_OTGSC_IDIS_SHIFT (16) -#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) - -/* AVVIS: A-VBUS valid interrupt status */ -#define USB0_OTGSC_AVVIS_SHIFT (17) -#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) - -/* ASVIS: A-Session valid interrupt status */ -#define USB0_OTGSC_ASVIS_SHIFT (18) -#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) - -/* BSVIS: B-Session valid interrupt status */ -#define USB0_OTGSC_BSVIS_SHIFT (19) -#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) - -/* BSEIS: B-Session end interrupt status */ -#define USB0_OTGSC_BSEIS_SHIFT (20) -#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) - -/* MS1S: 1 millisecond timer interrupt status */ -#define USB0_OTGSC_MS1S_SHIFT (21) -#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) - -/* DPIS: Data pulse interrupt status */ -#define USB0_OTGSC_DPIS_SHIFT (22) -#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) - -/* IDIE: USB ID interrupt enable */ -#define USB0_OTGSC_IDIE_SHIFT (24) -#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) - -/* AVVIE: A-VBUS valid interrupt enable */ -#define USB0_OTGSC_AVVIE_SHIFT (25) -#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) - -/* ASVIE: A-session valid interrupt enable */ -#define USB0_OTGSC_ASVIE_SHIFT (26) -#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) - -/* BSVIE: B-session valid interrupt enable */ -#define USB0_OTGSC_BSVIE_SHIFT (27) -#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) - -/* BSEIE: B-session end interrupt enable */ -#define USB0_OTGSC_BSEIE_SHIFT (28) -#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) - -/* MS1E: 1 millisecond timer interrupt enable */ -#define USB0_OTGSC_MS1E_SHIFT (29) -#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) - -/* DPIE: Data pulse interrupt enable */ -#define USB0_OTGSC_DPIE_SHIFT (30) -#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) - -/* --- USB0_USBMODE_D values ------------------------------------ */ - -/* CM1_0: Controller mode */ -#define USB0_USBMODE_D_CM1_0_SHIFT (0) -#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) -#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT) - -/* ES: Endian select */ -#define USB0_USBMODE_D_ES_SHIFT (2) -#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) - -/* SLOM: Setup Lockout mode */ -#define USB0_USBMODE_D_SLOM_SHIFT (3) -#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) - -/* SDIS: Setup Lockout mode */ -#define USB0_USBMODE_D_SDIS_SHIFT (4) -#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) - -/* --- USB0_USBMODE_H values ------------------------------------ */ - -/* CM: Controller mode */ -#define USB0_USBMODE_H_CM_SHIFT (0) -#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) -#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT) - -/* ES: Endian select */ -#define USB0_USBMODE_H_ES_SHIFT (2) -#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) - -/* SDIS: Stream disable mode */ -#define USB0_USBMODE_H_SDIS_SHIFT (4) -#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) - -/* VBPS: VBUS power select */ -#define USB0_USBMODE_H_VBPS_SHIFT (5) -#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) - -/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */ - -/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ - (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ - ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* --- USB0_ENDPTPRIME values ----------------------------------- */ - -/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */ -#define USB0_ENDPTPRIME_PERB_SHIFT (0) -#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) -#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT) - -/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */ -#define USB0_ENDPTPRIME_PETB_SHIFT (16) -#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) -#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT) - -/* --- USB0_ENDPTFLUSH values ----------------------------------- */ - -/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */ -#define USB0_ENDPTFLUSH_FERB_SHIFT (0) -#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) -#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) - -/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */ -#define USB0_ENDPTFLUSH_FETB_SHIFT (16) -#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) -#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) - -/* --- USB0_ENDPTSTAT values ------------------------------------ */ - -/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */ -#define USB0_ENDPTSTAT_ERBR_SHIFT (0) -#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) -#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) - -/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ -#define USB0_ENDPTSTAT_ETBR_SHIFT (16) -#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) -#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) - -/* --- USB0_ENDPTCOMPLETE values -------------------------------- */ - -/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */ -#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0) -#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) -#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) - -/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */ -#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16) -#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) -#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) - -/* --- USB0_ENDPTCTRL0 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL0_RXS_SHIFT (0) -#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) - -/* RXT1_0: Endpoint type */ -#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2) -#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) -#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL0_RXE_SHIFT (7) -#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL0_TXS_SHIFT (16) -#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) - -/* TXT1_0: Endpoint type */ -#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL0_TXE_SHIFT (23) -#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) - -/* --- USB0_ENDPTCTRL1 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL1_RXS_SHIFT (0) -#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL1_RXT_SHIFT (2) -#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) -#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL1_RXI_SHIFT (5) -#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL1_RXR_SHIFT (6) -#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL1_RXE_SHIFT (7) -#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL1_TXS_SHIFT (16) -#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL1_TXI_SHIFT (21) -#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL1_TXR_SHIFT (22) -#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL1_TXE_SHIFT (23) -#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) - -/* --- USB0_ENDPTCTRL2 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL2_RXS_SHIFT (0) -#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL2_RXT_SHIFT (2) -#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) -#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL2_RXI_SHIFT (5) -#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL2_RXR_SHIFT (6) -#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL2_RXE_SHIFT (7) -#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL2_TXS_SHIFT (16) -#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL2_TXI_SHIFT (21) -#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL2_TXR_SHIFT (22) -#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL2_TXE_SHIFT (23) -#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) - -/* --- USB0_ENDPTCTRL3 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL3_RXS_SHIFT (0) -#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL3_RXT_SHIFT (2) -#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) -#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL3_RXI_SHIFT (5) -#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL3_RXR_SHIFT (6) -#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL3_RXE_SHIFT (7) -#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL3_TXS_SHIFT (16) -#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL3_TXI_SHIFT (21) -#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL3_TXR_SHIFT (22) -#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL3_TXE_SHIFT (23) -#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) - -/* --- USB0_ENDPTCTRL4 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL4_RXS_SHIFT (0) -#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL4_RXT_SHIFT (2) -#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) -#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL4_RXI_SHIFT (5) -#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL4_RXR_SHIFT (6) -#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL4_RXE_SHIFT (7) -#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL4_TXS_SHIFT (16) -#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL4_TXI_SHIFT (21) -#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL4_TXR_SHIFT (22) -#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL4_TXE_SHIFT (23) -#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) - -/* --- USB0_ENDPTCTRL5 values ----------------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL5_RXS_SHIFT (0) -#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL5_RXT_SHIFT (2) -#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) -#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL5_RXI_SHIFT (5) -#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL5_RXR_SHIFT (6) -#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL5_RXE_SHIFT (7) -#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL5_TXS_SHIFT (16) -#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL5_TXI_SHIFT (21) -#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL5_TXR_SHIFT (22) -#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL5_TXE_SHIFT (23) -#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) - -/* -------------------------------------------------------------- */ - - -/* --- USB0_ENDPTCTRL common values ----------------------------- */ - -/* RXS: Rx endpoint stall */ -#define USB0_ENDPTCTRL_RXS_SHIFT (0) -#define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT) - -/* RXT: Endpoint type */ -#define USB0_ENDPTCTRL_RXT_SHIFT (2) -#define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT) -#define USB0_ENDPTCTRL_RXT(x) ((x) << USB0_ENDPTCTRL_RXT_SHIFT) - -/* RXI: Rx data toggle inhibit */ -#define USB0_ENDPTCTRL_RXI_SHIFT (5) -#define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT) - -/* RXR: Rx data toggle reset */ -#define USB0_ENDPTCTRL_RXR_SHIFT (6) -#define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT) - -/* RXE: Rx endpoint enable */ -#define USB0_ENDPTCTRL_RXE_SHIFT (7) -#define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT) - -/* TXS: Tx endpoint stall */ -#define USB0_ENDPTCTRL_TXS_SHIFT (16) -#define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT) - -/* TXT1_0: Tx Endpoint type */ -#define USB0_ENDPTCTRL_TXT1_0_SHIFT (18) -#define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT) -#define USB0_ENDPTCTRL_TXT1_0(x) ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT) - -/* TXI: Tx data toggle inhibit */ -#define USB0_ENDPTCTRL_TXI_SHIFT (21) -#define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT) - -/* TXR: Tx data toggle reset */ -#define USB0_ENDPTCTRL_TXR_SHIFT (22) -#define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT) - -/* TXE: Tx endpoint enable */ -#define USB0_ENDPTCTRL_TXE_SHIFT (23) -#define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT) - - - - - -/* --- USB1 registers ------------------------------------------------------ */ -/* TODO */ - -#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/wwdt.h b/libopencm3/include/libopencm3/lpc43xx/wwdt.h deleted file mode 100644 index 30ff6a7..0000000 --- a/libopencm3/include/libopencm3/lpc43xx/wwdt.h +++ /dev/null @@ -1,65 +0,0 @@ -/** @defgroup wwdt_defines Windowed Watchdog Timer - -@brief Defined Constants and Types for the LPC43xx Windowed Watchdog -Timer - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_WWDT_H -#define LPC43XX_WWDT_H - -/**@{*/ - -#include -#include - -/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */ - -/* Watchdog mode register */ -#define WWDT_MOD MMIO32(WWDT_BASE + 0x000) - -/* Watchdog timer constant register */ -#define WWDT_TC MMIO32(WWDT_BASE + 0x004) - -/* Watchdog feed sequence register */ -#define WWDT_FEED MMIO32(WWDT_BASE + 0x008) - -/* Watchdog timer value register */ -#define WWDT_TV MMIO32(WWDT_BASE + 0x00C) - -/* Watchdog warning interrupt register */ -#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014) - -/* Watchdog timer window register */ -#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/msp432/e4/doc-msp432e4.h b/libopencm3/include/libopencm3/msp432/e4/doc-msp432e4.h deleted file mode 100644 index 6383ac1..0000000 --- a/libopencm3/include/libopencm3/msp432/e4/doc-msp432e4.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @page libopencm3 MSP432E4 - -@version 1.0.0 - -@date 29 July 2018 - -API documentation for Texas Instruments MSP432E4xx Cortex M4F series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup MSP432E4xx MSP432E4xx -Libraries for Texas Instruments MSP432E4xx series. - -@version 1.0.0 - -@date 29 July 2018 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup MSP432E4xx_defines MSP432E4xx Defines - * -@brief Defined Constants and Types for the MSP432E4xx series. - -@version 1.0.0 - -@date 29 July 2018 - -LGPL License Terms @ref lgpl_license -*/ diff --git a/libopencm3/include/libopencm3/msp432/e4/gpio.h b/libopencm3/include/libopencm3/msp432/e4/gpio.h deleted file mode 100644 index 9ad39ff..0000000 --- a/libopencm3/include/libopencm3/msp432/e4/gpio.h +++ /dev/null @@ -1,2524 +0,0 @@ -/** @defgroup gpio_defines General Purpose I/O Defines - * - * @ingroup MSP432E4xx_defines - * - * @brief Defined Constants and Types for the MSP432E4 General Purpose I/O - * - * @version 1.0.0 - * - * @date 23 September 2018 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2013 Alexandru Gagniuc - * Copyright (C) 2018 Dmitry Rezvanov - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef MSP432E4_GPIO_H -#define MSP432E4_GPIO_H - -/**@{*/ - -#include -#include -#include - -/** @defgroup gpio_reg_base GPIO Register Base Addresses - * @brief GPIO Register Base Addresses -@{*/ -/** GPIOA Base Address */ -#define GPIOA GPIOA_BASE -/** GPIOB Base Address */ -#define GPIOB GPIOB_BASE -/** GPIOC Base Address */ -#define GPIOC GPIOC_BASE -/** GPIOD Base Address */ -#define GPIOD GPIOD_BASE -/** GPIOE Base Address */ -#define GPIOE GPIOE_BASE -/** GPIOF Base Address */ -#define GPIOF GPIOF_BASE -/** GPIOG Base Address */ -#define GPIOG GPIOG_BASE -/** GPIOH Base Address */ -#define GPIOH GPIOH_BASE -/** GPIOJ Base Address */ -#define GPIOJ GPIOJ_BASE -/** GPIOK Base Address */ -#define GPIOK GPIOK_BASE -/** GPIOL Base Address */ -#define GPIOL GPIOL_BASE -/** GPIOM Base Address */ -#define GPIOM GPIOM_BASE -/** GPION Base Address */ -#define GPION GPION_BASE -/** GPIOP Base Address */ -#define GPIOP GPIOP_BASE -/** GPIOQ Base Address */ -#define GPIOQ GPIOQ_BASE -/**@}*/ - -/** @defgroup gpio_pin_id GPIO Pin Identifiers - * @brief GPIO Pin Identifiers -@{*/ -/** GPIO Pin 0 Identifier */ -#define GPIO0 (1 << 0) -/** GPIO Pin 1 Identifier */ -#define GPIO1 (1 << 1) -/** GPIO Pin 2 Identifier */ -#define GPIO2 (1 << 2) -/** GPIO Pin 3 Identifier */ -#define GPIO3 (1 << 3) -/** GPIO Pin 4 Identifier */ -#define GPIO4 (1 << 4) -/** GPIO Pin 5 Identifier */ -#define GPIO5 (1 << 5) -/** GPIO Pin 6 Identifier */ -#define GPIO6 (1 << 6) -/** GPIO Pin 7 Identifier */ -#define GPIO7 (1 << 7) -/** GPIO All Pins Identifier */ -#define GPIO_ALL (0xFF) -/**@}*/ - -/** @defgroup gpio_af_id GPIO Alternate Functions Identifiers - * @brief GPIO Alternate Functions Identifiers -@{*/ -/** GPIO Alternate Function 1 Identifier */ -#define GPIO_AF1 0x1 -/** GPIO Alternate Function 2 Identifier */ -#define GPIO_AF2 0x2 -/** GPIO Alternate Function 3 Identifier */ -#define GPIO_AF3 0x3 -/** GPIO Alternate Function 4 Identifier */ -#define GPIO_AF4 0x4 -/** GPIO Alternate Function 5 Identifier */ -#define GPIO_AF5 0x5 -/** GPIO Alternate Function 6 Identifier */ -#define GPIO_AF6 0x6 -/** GPIO Alternate Function 7 Identifier */ -#define GPIO_AF7 0x7 -/** GPIO Alternate Function 8 Identifier */ -#define GPIO_AF8 0x8 -/** GPIO Alternate Function 11 Identifier */ -#define GPIO_AF11 0xB -/** GPIO Alternate Function 13 Identifier */ -#define GPIO_AF13 0xD -/** GPIO Alternate Function 14 Identifier */ -#define GPIO_AF14 0xE -/** GPIO Alternate Function 15 Identifier */ -#define GPIO_AF15 0xF -/** GPIO Alternate Function Disable */ -#define GPIO_AF_DISABLE 0x0 -/**@}*/ - -/** @defgroup gpio_registers GPIO Registers - * @brief GPIO Registers -@{*/ -/** GPIO Data */ -#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) -/** GPIO Direction */ -#define GPIO_DIR(port) MMIO32((port) + 0x400) -/** GPIO Interrupt Sense */ -#define GPIO_IS(port) MMIO32((port) + 0x404) -/** GPIO Interrupt Both Edges */ -#define GPIO_IBE(port) MMIO32((port) + 0x408) -/** GPIO Interrupt Event */ -#define GPIO_IEV(port) MMIO32((port) + 0x40C) -/** GPIO Interrupt Mask */ -#define GPIO_IM(port) MMIO32((port) + 0x410) -/** GPIO Raw Interrupt Status */ -#define GPIO_RIS(port) MMIO32((port) + 0x414) -/** GPIO Masked Interrupt Status */ -#define GPIO_MIS(port) MMIO32((port) + 0x418) -/** GPIO Interrupt Clear */ -#define GPIO_ICR(port) MMIO32((port) + 0x41C) -/** GPIO Alternate Function Select */ -#define GPIO_AFSEL(port) MMIO32((port) + 0x420) -/** GPIO 2-mA Drive Select */ -#define GPIO_DR2R(port) MMIO32((port) + 0x500) -/** GPIO 4-mA Drive Select */ -#define GPIO_DR4R(port) MMIO32((port) + 0x504) -/** GPIO 8-mA Drive Select */ -#define GPIO_DR8R(port) MMIO32((port) + 0x508) -/** GPIO Open Drain Select */ -#define GPIO_ODR(port) MMIO32((port) + 0x50C) -/** GPIO Pull-Up Select */ -#define GPIO_PUR(port) MMIO32((port) + 0x510) -/** GPIO Pull-Down Select */ -#define GPIO_PDR(port) MMIO32((port) + 0x514) -/** GPIO Slew Rate Control Select */ -#define GPIO_SLR(port) MMIO32((port) + 0x518) -/** GPIO Digital Enable */ -#define GPIO_DEN(port) MMIO32((port) + 0x51C) -/** GPIO Lock */ -#define GPIO_LOCK(port) MMIO32((port) + 0x520) -/** GPIO Commit */ -#define GPIO_CR(port) MMIO32((port) + 0x524) -/** GPIO Analog Mode Select */ -#define GPIO_AMSEL(port) MMIO32((port) + 0x528) -/** GPIO Port Control */ -#define GPIO_PCTL(port) MMIO32((port) + 0x52C) -/** GPIO ADC Control */ -#define GPIO_ADCCTL(port) MMIO32((port) + 0x530) -/** GPIO DMA Control */ -#define GPIO_DMACTL(port) MMIO32((port) + 0x534) -/** GPIO Select Interrupt */ -#define GPIO_SI(port) MMIO32((port) + 0x538) -/** GPIO 12-mA Drive Select */ -#define GPIO_DR12R(port) MMIO32((port) + 0x53C) -/** GPIO Wake Pin Enable - * @note This register is only available on Port K */ -#define GPIO_WAKEPEN(port) MMIO32((port) + 0x540) -/** GPIO Wake Level - * @note This register is only available on Port K */ -#define GPIO_WAKELVL(port) MMIO32((port) + 0x544) -/** GPIO Wake Status - * @note This register is only available on Port K */ -#define GPIO_WAKESTAT(port) MMIO32((port) + 0x548) -/** GPIO Peripheral Property */ -#define GPIO_PP(port) MMIO32((port) + 0xFC0) -/** GPIO Peripheral Configuration */ -#define GPIO_PC(port) MMIO32((port) + 0xFC4) - -/** GPIO Peripheral Identification 0 */ -#define GPIO_PERIPH_ID0(port) MMIO32((port) + 0xFE0) -/** GPIO Peripheral Identification 1 */ -#define GPIO_PERIPH_ID1(port) MMIO32((port) + 0xFE4) -/** GPIO Peripheral Identification 2 */ -#define GPIO_PERIPH_ID2(port) MMIO32((port) + 0xFE8) -/** GPIO Peripheral Identification 3 */ -#define GPIO_PERIPH_ID3(port) MMIO32((port) + 0xFEC) -/** GPIO Peripheral Identification 4 */ -#define GPIO_PERIPH_ID4(port) MMIO32((port) + 0xFD0) -/** GPIO Peripheral Identification 5 */ -#define GPIO_PERIPH_ID5(port) MMIO32((port) + 0xFD4) -/** GPIO Peripheral Identification 6 */ -#define GPIO_PERIPH_ID6(port) MMIO32((port) + 0xFD8) -/** GPIO Peripheral Identification 7 */ -#define GPIO_PERIPH_ID7(port) MMIO32((port) + 0xFDC) - -/** GPIO PrimeCell Identification 0 */ -#define GPIO_PCELL_ID0(port) MMIO32((port) + 0xFF0) -/** GPIO PrimeCell Identification 1 */ -#define GPIO_PCELL_ID1(port) MMIO32((port) + 0xFF4) -/** GPIO PrimeCell Identification 2 */ -#define GPIO_PCELL_ID2(port) MMIO32((port) + 0xFF8) -/** GPIO PrimeCell Identification 3 */ -#define GPIO_PCELL_ID3(port) MMIO32((port) + 0xFFC) -/**@}*/ - -/** @defgroup gpio_im_values GPIO_IM Values - * @brief GPIO Interrupt Mask Register Values -@{*/ -/** GPIO Micro Direct Memory Access Done Interrupt Mask Enable */ -#define GPIO_IM_DMAIME (1 << 8) -/**@}*/ - -/** @defgroup gpio_ris_values GPIO_RIS Values - * @brief GPIO Raw Interrupt Status Register Values -@{*/ -/** GPIO Micro Direct Memory Access Done Interrupt Raw Status */ -#define GPIO_RIS_DMARIS (1 << 8) -/**@}*/ - -/** @defgroup gpio_mis_values GPIO_MIS Values - * @brief GPIO Masked Interrupt Status Register Values -@{*/ -/** GPIO Micro Direct Memory Access Done Masked Interrupt Status */ -#define GPIO_MIS_DMAMIS (1 << 8) -/**@}*/ - -/** @defgroup gpio_icr_values GPIO_RIS Values - * @brief GPIO Interrupt Clear Register Values -@{*/ -/** GPIO Micro Direct Memory Access Interrupt Clear */ -#define GPIO_ICR_DMAIC (1 << 8) -/**@}*/ - -/** @defgroup gpio_lock_values GPIO_LOCK Values - * @brief GPIO Lock Register Values -@{*/ -/* Value we need to write to unlock the GPIO commit register */ -#define GPIO_LOCK_UNLOCK_CODE (0x4C4F434B) -/** GPIO Lock Status */ -#define GPIO_LOCK_STATUS (1 << 0) -/**@}*/ - -/** @defgroup gpio_pctl_values GPIO_PCTL Values - * @brief GPIO Port Control Register Values -@{*/ -/** GPIO Port Control Set AF for Pin */ -#define GPIO_PCTL_AF(pin, af) ((af) << ((pin) * 4)) -/* GPIO Port Control Mask for Pin */ -#define GPIO_PCTL_MASK(pin) GPIO_PCTL_AF((pin), 0xf) -/**@}*/ - -/** @defgroup gpio_si_values GPIO_SI Values - * @brief GPIO Select Interrupt Register Values -@{*/ -/** Summary Interrupt */ -#define GPIO_SI_SUM (1 << 0) -/**@}*/ - -/** @defgroup gpio_wakepen_values GPIO_WAKEPEN Values - * @brief GPIO Wake Pin Enable Register Values - * @note This register is only available on Port K -@{*/ -/** PK7 Wake Enable */ -#define GPIO_WAKEPEN_WAKEP7 (1 << 7) -/** PK6 Wake Enable */ -#define GPIO_WAKEPEN_WAKEP6 (1 << 6) -/** PK5 Wake Enable */ -#define GPIO_WAKEPEN_WAKEP5 (1 << 5) -/** PK4 Wake Enable */ -#define GPIO_WAKEPEN_WAKEP4 (1 << 4) -/**@}*/ - -/** @defgroup gpio_wakelvl_values GPIO_WAKELVL Values - * @brief GPIO Wake Level Register Values -@{*/ -/** PK7 Wake Level */ -#define GPIO_WAKELVL_WAKELVL7 (1 << 7) -/** PK6 Wake Level */ -#define GPIO_WAKELVL_WAKELVL6 (1 << 6) -/** PK5 Wake Level */ -#define GPIO_WAKELVL_WAKELVL5 (1 << 5) -/** PK4 Wake Level */ -#define GPIO_WAKELVL_WAKELVL4 (1 << 4) -/**@}*/ - -/** @defgroup gpio_wakestat_values GPIO_WAKESTAT Values - * @brief GPIO Wake Status Register Values -@{*/ -/** PK7 Wake Status */ -#define GPIO_WAKESTAT_STAT7 (1 << 7) -/** PK6 Wake Status */ -#define GPIO_WAKESTAT_STAT6 (1 << 6) -/** PK5 Wake Status */ -#define GPIO_WAKESTAT_STAT5 (1 << 5) -/** PK4 Wake Status */ -#define GPIO_WAKESTAT_STAT4 (1 << 4) -/**@}*/ - -/** @defgroup gpio_pp_values GPIO_PP Values - * @brief GPIO Peripheral Property Register Values -@{*/ -/** Extended Drive Enable */ -#define GPIO_PP_EDE (1 << 0) -/**@}*/ - -/** @defgroup gpio_pc_values GPIO_PC Values - * @brief GPIO Peripheral Configuration Register Values -@{*/ -/** Extended Drive Mode Bit N */ -#define GPIO_PC_EDM(n, mode) ((mode) << (2 * (n))) -/** Extended Drive Mode Bit N Mask */ -#define GPIO_PC_EDM_MASK(n) (0x3 << (2 * (n))) -/** Normal behavior, 2, 4 and 8 mA are available */ -#define GPIO_PC_EDM_NORMAL 0x0 -/** An additional 6 mA option is provided. - * Set one, clear other behavior is disabled */ -#define GPIO_PC_EDM_ADD_6MA 0x1 -/** Full range, 2, 4, 6, 8, 10 and 12 mA are available. - * Set one, clear other behavior is disabled */ -#define GPIO_PC_EDM_FULL_RANGE 0x3 -/**@}*/ - -/** @defgroup gpio_af_pa0_values GPIO_AF_PA0 Values - * @brief GPIO PA0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 33 | - * NFBGA-212 | V3 | -@{*/ -/** UART module 0 receive */ -#define GPIO_AF_PA0_U0RX GPIO_AF1 -/** I2C module 9 clock */ -#define GPIO_AF_PA0_I2C9SCL GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ -#define GPIO_AF_PA0_T0CCP0 GPIO_AF3 -/** CAN module 0 receive */ -#define GPIO_AF_PA0_CAN0RX GPIO_AF7 -/**@}*/ - -/** @defgroup gpio_af_pa1_values GPIO_AF_PA1 Values - * @brief GPIO PA1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 34 | - * NFBGA-212 | W3 | -@{*/ -/** UART module 0 transmit */ -#define GPIO_AF_PA1_U0TX GPIO_AF1 -/** I2C module 9 data */ -#define GPIO_AF_PA1_I2C9SDA GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ -#define GPIO_AF_PA1_T0CCP1 GPIO_AF3 -/** CAN module 0 transmit */ -#define GPIO_AF_PA1_CAN0TX GPIO_AF7 -/**@}*/ - -/** @defgroup gpio_af_pa2_values GPIO_AF_PA2 Values - * @brief GPIO PA2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 35 | - * NFBGA-212 | T6 | -@{*/ -/** UART module 4 receive */ -#define GPIO_AF_PA2_U4RX GPIO_AF1 -/** I2C module 8 clock */ -#define GPIO_AF_PA2_I2C8SCL GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ -#define GPIO_AF_PA2_T1CCP0 GPIO_AF3 -/** SSI module 0 clock */ -#define GPIO_AF_PA2_SSI0CLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pa3_values GPIO_AF_PA3 Values - * @brief GPIO PA3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 36 | - * NFBGA-212 | U5 | -@{*/ -/** UART module 4 transmit */ -#define GPIO_AF_PA3_U4TX GPIO_AF1 -/** I2C module 8 data */ -#define GPIO_AF_PA3_I2C8SDA GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ -#define GPIO_AF_PA3_T1CCP1 GPIO_AF3 -/** SSI module 0 frame signal */ -#define GPIO_AF_PA3_SSI0FSS GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pa4_values GPIO_AF_PA4 Values - * @brief GPIO PA4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 37 | - * NFBGA-212 | V4 | -@{*/ -/** UART module 3 receive */ -#define GPIO_AF_PA4_U3RX GPIO_AF1 -/** I2C module 7 clock */ -#define GPIO_AF_PA4_I2C7SCL GPIO_AF2 -/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ -#define GPIO_AF_PA4_T2CCP0 GPIO_AF3 -/** SSI Module 0 bidirectional data pin 0 */ -#define GPIO_AF_PA4_SSI0XDAT0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pa5_values GPIO_AF_PA5 Values - * @brief GPIO PA5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 38 | - * NFBGA-212 | W4 | -@{*/ -/** UART module 3 transmit */ -#define GPIO_AF_PA5_U3TX GPIO_AF1 -/** I2C module 7 data */ -#define GPIO_AF_PA5_I2C7SDA GPIO_AF2 -/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ -#define GPIO_AF_PA5_T2CCP1 GPIO_AF3 -/** SSI Module 0 bidirectional data pin 1 */ -#define GPIO_AF_PA5_SSI0XDAT1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pa6_values GPIO_AF_PA6 Values - * @brief GPIO PA6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 40 | - * NFBGA-212 | V5 | -@{*/ -/** UART module 2 receive */ -#define GPIO_AF_PA6_U2RX GPIO_AF1 -/** I2C module 6 clock */ -#define GPIO_AF_PA6_I2C6SCL GPIO_AF2 -/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ -#define GPIO_AF_PA6_T3CCP0 GPIO_AF3 -/** USB Control an external power source in host mode */ -#define GPIO_AF_PA6_USB0EPEN GPIO_AF5 -/** SSI Module 0 bidirectional data pin 2 */ -#define GPIO_AF_PA6_SSI0XDAT2 GPIO_AF13 -/** Ethernet 0 receive clock */ -#define GPIO_AF_PA6_EN0RXCK GPIO_AF14 -/** EPI module 0 signal 8 */ -#define GPIO_AF_PA6_EPI0S8 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pa7_values GPIO_AF_PA7 Values - * @brief GPIO PA7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 41 | - * NFBGA-212 | R7 | -@{*/ -/** UART module 2 transmit */ -#define GPIO_AF_PA7_U2TX GPIO_AF1 -/** I2C module 6 data */ -#define GPIO_AF_PA7_I2C6SDA GPIO_AF2 -/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ -#define GPIO_AF_PA7_T3CCP1 GPIO_AF3 -/** USB Power Fault input in host mode */ -#define GPIO_AF_PA7_USB0PFLT GPIO_AF5 -/** USB Control an external power source in host mode */ -#define GPIO_AF_PA7_USB0EPEN GPIO_AF11 -/** SSI Module 0 bidirectional data pin 3 */ -#define GPIO_AF_PA7_SSI0XDAT3 GPIO_AF13 -/** EPI module 0 signal 9 */ -#define GPIO_AF_PA7_EPI0S9 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pb0_values GPIO_AF_PB0 Values - * @brief GPIO PB0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 95 | - * NFBGA-212 | A16 | -@{*/ -/** UART module 1 receive */ -#define GPIO_AF_PB0_U1RX GPIO_AF1 -/** I2C module 5 clock */ -#define GPIO_AF_PB0_I2C5SCL GPIO_AF2 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ -#define GPIO_AF_PB0_T4CCP0 GPIO_AF3 -/** CAN module 1 receive */ -#define GPIO_AF_PB0_CAN1RX GPIO_AF7 -/**@}*/ - -/** @defgroup gpio_af_pb1_values GPIO_AF_PB1 Values - * @brief GPIO PB1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 96 | - * NFBGA-212 | B16 | -@{*/ -/** UART module 1 transmit */ -#define GPIO_AF_PB1_U1TX GPIO_AF1 -/** I2C module 5 data */ -#define GPIO_AF_PB1_I2C5SDA GPIO_AF2 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ -#define GPIO_AF_PB1_T4CCP1 GPIO_AF3 -/** CAN module 1 transmit */ -#define GPIO_AF_PB1_CAN1TX GPIO_AF7 -/**@}*/ - -/** @defgroup gpio_af_pb2_values GPIO_AF_PB2 Values - * @brief GPIO PB2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 91 | - * NFBGA-212 | A17 | -@{*/ -/** I2C module 0 clock */ -#define GPIO_AF_PB2_I2C0SCL GPIO_AF2 -/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ -#define GPIO_AF_PB2_T5CCP0 GPIO_AF3 -/** Ethernet 0 management data clock */ -#define GPIO_AF_PB2_EN0MDC GPIO_AF5 -/** USB Asserted by the USB controller to signal the end of a USB transmit - * packet or register write operation */ -#define GPIO_AF_PB2_USB0STP GPIO_AF14 -/** EPI module 0 signal 27 */ -#define GPIO_AF_PB2_EPI0S27 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pb3_values GPIO_AF_PB3 Values - * @brief GPIO PB3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 92 | - * NFBGA-212 | B17 | -@{*/ -/** I2C module 0 data */ -#define GPIO_AF_PB3_I2C0SDA GPIO_AF2 -/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ -#define GPIO_AF_PB3_T5CCP1 GPIO_AF3 -/** Ethernet 0 management data input/output signal */ -#define GPIO_AF_PB3_EN0MDIO GPIO_AF5 -/** USB 60-MHz clock to the external PHY */ -#define GPIO_AF_PB3_USB0CLK GPIO_AF14 -/** EPI module 0 signal 28 */ -#define GPIO_AF_PB3_EPI0S28 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pb4_values GPIO_AF_PB4 Values - * @brief GPIO PB4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 121 | - * NFBGA-212 | C6 | -@{*/ -/** UART module 0 clear to send modem flow control input signal */ -#define GPIO_AF_PB4_U0CTS GPIO_AF1 -/** I2C module 5 clock */ -#define GPIO_AF_PB4_I2C5SCL GPIO_AF2 -/** SSI module 1 frame signal */ -#define GPIO_AF_PB4_SSI1FSS GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pb5_values GPIO_AF_PB5 Values - * @brief GPIO PB5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 120 | - * NFBGA-212 | B6 | -@{*/ -/** UART module 0 request to send modem flow control output signal */ -#define GPIO_AF_PB5_U0RTS GPIO_AF1 -/** I2C module 5 data */ -#define GPIO_AF_PB5_I2C5SDA GPIO_AF2 -/** SSI module 1 clock */ -#define GPIO_AF_PB5_SSI1CLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pb6_values GPIO_AF_PB6 Values - * @brief GPIO PB6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | F2 | -@{*/ -/** I2C module 6 clock */ -#define GPIO_AF_PB6_I2C6SCL GPIO_AF1 -/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ -#define GPIO_AF_PB6_T6CCP0 GPIO_AF3 -/**@}*/ - -/** @defgroup gpio_af_pb7_values GPIO_AF_PB7 Values - * @brief GPIO PB7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | F1 | -@{*/ -/** I2C module 6 data */ -#define GPIO_AF_PB7_I2C6SDA GPIO_AF1 -/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ -#define GPIO_AF_PB7_T6CCP1 GPIO_AF3 -/**@}*/ - -/** @defgroup gpio_af_pc0_values GPIO_AF_PC0 Values - * @brief GPIO PC0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 100 | - * NFBGA-212 | B15 | -@{*/ -/** JTAG and SWD clock */ -#define GPIO_AF_PC0_TCK GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pc1_values GPIO_AF_PC1 Values - * @brief GPIO PC1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 99 | - * NFBGA-212 | C15 | -@{*/ -/** JTAG TMS and SWDIO */ -#define GPIO_AF_PC1_TMS GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pc2_values GPIO_AF_PC2 Values - * @brief GPIO PC2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 98 | - * NFBGA-212 | D14 | -@{*/ -/** JTAG TDI */ -#define GPIO_AF_PC2_TDI GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pc3_values GPIO_AF_PC3 Values - * @brief GPIO PC3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 97 | - * NFBGA-212 | C14 | -@{*/ -/** JTAG TDO and SWO */ -#define GPIO_AF_PC3_TDO GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pc4_values GPIO_AF_PC4 Values - * @brief GPIO PC4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 25 | - * NFBGA-212 | M2 | -@{*/ -/** UART module 7 receive */ -#define GPIO_AF_PC4_U7RX GPIO_AF1 -/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ -#define GPIO_AF_PC4_T7CCP0 GPIO_AF3 -/** EPI module 0 signal 7 */ -#define GPIO_AF_PC4_EPI0S7 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pc5_values GPIO_AF_PC5 Values - * @brief GPIO PC5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 24 | - * NFBGA-212 | M1 | -@{*/ -/** UART module 7 transmit */ -#define GPIO_AF_PC5_U7TX GPIO_AF1 -/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ -#define GPIO_AF_PC5_T7CCP1 GPIO_AF3 -/** Buffered version of the 32.768-kHz clock of the Hibernation module */ -#define GPIO_AF_PC5_RTCCLK GPIO_AF7 -/** EPI module 0 signal 6 */ -#define GPIO_AF_PC5_EPI0S6 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pc6_values GPIO_AF_PC6 Values - * @brief GPIO PC6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 22 | - * NFBGA-212 | L2 | -@{*/ -/** UART module 5 receive */ -#define GPIO_AF_PC6_U5RX GPIO_AF1 -/** EPI module 0 signal 5 */ -#define GPIO_AF_PC6_EPI0S5 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pc7_values GPIO_AF_PC7 Values - * @brief GPIO PC7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 22 | - * NFBGA-212 | K3 | -@{*/ -/** UART module 5 transmit */ -#define GPIO_AF_PC7_U5TX GPIO_AF1 -/** EPI module 0 signal 4 */ -#define GPIO_AF_PC7_EPI0S4 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd0_values GPIO_AF_PD0 Values - * @brief GPIO PD0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 1 | - * NFBGA-212 | C2 | -@{*/ -/** I2C module 7 clock */ -#define GPIO_AF_PD0_I2C7SCL GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ -#define GPIO_AF_PD0_T0CCP0 GPIO_AF3 -/** Analog comparator 0 output */ -#define GPIO_AF_PD0_C0O GPIO_AF5 -/** SSI Module 2 bidirectional data pin 1 */ -#define GPIO_AF_PD0_SSI2XDAT1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd1_values GPIO_AF_PD1 Values - * @brief GPIO PD1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 2 | - * NFBGA-212 | C1 | -@{*/ -/** I2C module 7 data */ -#define GPIO_AF_PD1_I2C7SDA GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ -#define GPIO_AF_PD1_T0CCP1 GPIO_AF3 -/** Analog comparator 1 output */ -#define GPIO_AF_PD1_C1O GPIO_AF5 -/** SSI Module 2 bidirectional data pin 0 */ -#define GPIO_AF_PD1_SSI2XDAT0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd2_values GPIO_AF_PD2 Values - * @brief GPIO PD2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 3 | - * NFBGA-212 | D2 | -@{*/ -/** I2C module 8 clock */ -#define GPIO_AF_PD2_I2C8SCL GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ -#define GPIO_AF_PD2_T1CCP0 GPIO_AF3 -/** Analog comparator 2 output */ -#define GPIO_AF_PD2_C2O GPIO_AF5 -/** SSI module 2 frame signal */ -#define GPIO_AF_PD2_SSI2FSS GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd3_values GPIO_AF_PD3 Values - * @brief GPIO PD3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 4 | - * NFBGA-212 | D1 | -@{*/ -/** I2C module 8 data */ -#define GPIO_AF_PD3_I2C8SDA GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ -#define GPIO_AF_PD3_T1CCP1 GPIO_AF3 -/** SSI module 2 clock */ -#define GPIO_AF_PD3_SSI2CLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd4_values GPIO_AF_PD4 Values - * @brief GPIO PD4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 125 | - * NFBGA-212 | A4 | -@{*/ -/** UART module 2 receive */ -#define GPIO_AF_PD4_U2RX GPIO_AF1 -/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ -#define GPIO_AF_PD4_T3CCP0 GPIO_AF3 -/** SSI Module 1 bidirectional data pin 2 */ -#define GPIO_AF_PD4_SSI1XDAT2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd5_values GPIO_AF_PD5 Values - * @brief GPIO PD5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 126 | - * NFBGA-212 | B4 | -@{*/ -/** UART module 2 transmit */ -#define GPIO_AF_PD5_U2TX GPIO_AF1 -/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ -#define GPIO_AF_PD5_T3CCP1 GPIO_AF3 -/** SSI Module 1 bidirectional data pin 3 */ -#define GPIO_AF_PD5_SSI1XDAT3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd6_values GPIO_AF_PD6 Values - * @brief GPIO PD6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 127 | - * NFBGA-212 | B3 | -@{*/ -/** UART module 2 request to send modem flow control output line */ -#define GPIO_AF_PD6_U2RTS GPIO_AF1 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ -#define GPIO_AF_PD6_T4CCP0 GPIO_AF3 -/** USB Control an external power source in host mode */ -#define GPIO_AF_PD6_USB0EPEN GPIO_AF5 -/** SSI Module 2 bidirectional data pin 3 */ -#define GPIO_AF_PD6_SSI2XDAT3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pd7_values GPIO_AF_PD7 Values - * @brief GPIO PD7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 128 | - * NFBGA-212 | B2 | -@{*/ -/** UART module 2 clear to send modem flow control input signal */ -#define GPIO_AF_PD7_U2CTS GPIO_AF1 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ -#define GPIO_AF_PD7_T4CCP1 GPIO_AF3 -/** USB Power Fault input in host mode */ -#define GPIO_AF_PD7_USB0PFLT GPIO_AF5 -/** Nonmaskable interrupt */ -#define GPIO_AF_PD7_NMI GPIO_AF8 -/** SSI Module 2 bidirectional data pin 2 */ -#define GPIO_AF_PD7_SSI2XDAT2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pe0_values GPIO_AF_PE0 Values - * @brief GPIO PE0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 15 | - * NFBGA-212 | H3 | -@{*/ -/** UART module 1 request to send modem flow control output line */ -#define GPIO_AF_PE0_U1RTS GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pe1_values GPIO_AF_PE1 Values - * @brief GPIO PE1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 14 | - * NFBGA-212 | H2 | -@{*/ -/** UART module 1 data set ready modem output control line */ -#define GPIO_AF_PE1_U1DSR GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pe2_values GPIO_AF_PE2 Values - * @brief GPIO PE2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 13 | - * NFBGA-212 | G1 | -@{*/ -/** UART module 1 data carrier detect modem status input signal */ -#define GPIO_AF_PE2_U1DCD GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pe3_values GPIO_AF_PE3 Values - * @brief GPIO PE3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 12 | - * NFBGA-212 | G2 | -@{*/ -/** UART module 1 data terminal ready modem status input signal */ -#define GPIO_AF_PE3_U1DTR GPIO_AF1 -/** 1-Wire single bus pin */ -#define GPIO_AF_PE3_OWIRE GPIO_AF5 -/**@}*/ - -/** @defgroup gpio_af_pe4_values GPIO_AF_PE4 Values - * @brief GPIO PE4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 123 | - * NFBGA-212 | A5 | -@{*/ -/** UART module 1 ring indicator modem status input signal */ -#define GPIO_AF_PE4_U1RI GPIO_AF1 -/** SSI Module 1 bidirectional data pin 0 */ -#define GPIO_AF_PE4_SSI1XDAT0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pe5_values GPIO_AF_PE5 Values - * @brief GPIO PE5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 124 | - * NFBGA-212 | B5 | -@{*/ -/** SSI Module 1 bidirectional data pin 1 */ -#define GPIO_AF_PE5_SSI1XDAT1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pe6_values GPIO_AF_PE6 Values - * @brief GPIO PE6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | A7 | -@{*/ -/** UART module 0 clear to send modem flow control input signal */ -#define GPIO_AF_PE6_U0CTS GPIO_AF1 -/** I2C module 9 clock */ -#define GPIO_AF_PE6_I2C9SCL GPIO_AF2 -/**@}*/ - -/** @defgroup gpio_af_pe7_values GPIO_AF_PE7 Values - * @brief GPIO PE7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | B7 | -@{*/ -/** UART module 0 request to send modem flow control output signal */ -#define GPIO_AF_PE7_U0RTS GPIO_AF1 -/** I2C module 9 data */ -#define GPIO_AF_PE7_I2C9SDA GPIO_AF2 -/** Nonmaskable interrupt */ -#define GPIO_AF_PE7_NMI GPIO_AF8 -/**@}*/ - -/** @defgroup gpio_af_pf0_values GPIO_AF_PF0 Values - * @brief GPIO PF0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 42 | - * NFBGA-212 | U6 | -@{*/ -/** Ethernet 0 LED 0 */ -#define GPIO_AF_PF0_EN0LED0 GPIO_AF5 -/** Motion control module 0 PWM 0 */ -#define GPIO_AF_PF0_M0PWM0 GPIO_AF6 -/** SSI Module 3 bidirectional data pin 1 */ -#define GPIO_AF_PF0_SSI3XDAT1 GPIO_AF14 -/** Trace data 2 */ -#define GPIO_AF_PF0_TRD2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf1_values GPIO_AF_PF1 Values - * @brief GPIO PF1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 43 | - * NFBGA-212 | V6 | -@{*/ -/** Ethernet 0 LED 2 */ -#define GPIO_AF_PF1_EN0LED2 GPIO_AF5 -/** Motion control module 0 PWM 1 */ -#define GPIO_AF_PF1_M0PWM1 GPIO_AF6 -/** SSI Module 3 bidirectional data pin 0 */ -#define GPIO_AF_PF1_SSI3XDAT0 GPIO_AF14 -/** Trace data 1 */ -#define GPIO_AF_PF1_TRD1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf2_values GPIO_AF_PF2 Values - * @brief GPIO PF2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 44 | - * NFBGA-212 | W6 | -@{*/ -/** Ethernet 0 management data clock */ -#define GPIO_AF_PF2_EN0MDC GPIO_AF5 -/** Motion control module 0 PWM 2 */ -#define GPIO_AF_PF2_M0PWM2 GPIO_AF6 -/** SSI module 3 frame signal */ -#define GPIO_AF_PF2_SSI3FSS GPIO_AF14 -/** Trace data 0 */ -#define GPIO_AF_PF2_TRD0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf3_values GPIO_AF_PF3 Values - * @brief GPIO PF3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 45 | - * NFBGA-212 | T7 | -@{*/ -/** Ethernet 0 management data input/output signal */ -#define GPIO_AF_PF3_EN0MDIO GPIO_AF5 -/** Motion control module 0 PWM 3 */ -#define GPIO_AF_PF3_M0PWM3 GPIO_AF6 -/** SSI module 3 clock */ -#define GPIO_AF_PF3_SSI3CLK GPIO_AF14 -/** Trace clock */ -#define GPIO_AF_PF3_TRCLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf4_values GPIO_AF_PF4 Values - * @brief GPIO PF4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 46 | - * NFBGA-212 | V7 | -@{*/ -/** Ethernet 0 LED 1 */ -#define GPIO_AF_PF4_EN0LED1 GPIO_AF5 -/** Motion control module 0 PWM fault 0 */ -#define GPIO_AF_PF4_M0FAULT0 GPIO_AF6 -/** SSI Module 3 bidirectional data pin 2 */ -#define GPIO_AF_PF4_SSI3XDAT2 GPIO_AF14 -/** Trace data 3 */ -#define GPIO_AF_PF4_TRD3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf5_values GPIO_AF_PF5 Values - * @brief GPIO PF5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | W7 | -@{*/ -/** SSI Module 3 bidirectional data pin 3 */ -#define GPIO_AF_PF5_SSI3XDAT3 GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pf6_values GPIO_AF_PF6 Values - * @brief GPIO PF6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | T8 | -@{*/ -/** LCD memory clock, secondary chip select (CS1), or secondary enable (E1) */ -#define GPIO_AF_PF6_LCDMCLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pf7_values GPIO_AF_PF7 Values - * @brief GPIO PF7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U8 | -@{*/ -/** LCD data pin 2 input/output */ -#define GPIO_AF_PF7_LCDDATA02 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg0_values GPIO_AF_PG0 Values - * @brief GPIO PG0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 49 | - * NFBGA-212 | N15 | -@{*/ -/** I2C module 1 clock */ -#define GPIO_AF_PG0_I2C1SCL GPIO_AF2 -/** Ethernet 0 pulse-per-second (PPS) output */ -#define GPIO_AF_PG0_EN0PPS GPIO_AF5 -/** Motion control module 0 PWM 4 */ -#define GPIO_AF_PG0_M0PWM4 GPIO_AF6 -/** EPI module 0 signal 11 */ -#define GPIO_AF_PG0_EPI0S11 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg1_values GPIO_AF_PG1 Values - * @brief GPIO PG1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 50 | - * NFBGA-212 | T14 | -@{*/ -/** I2C module 1 data */ -#define GPIO_AF_PG1_I2C1SDA GPIO_AF2 -/** Motion control module 0 PWM 5 */ -#define GPIO_AF_PG1_M0PWM5 GPIO_AF6 -/** EPI module 0 signal 10 */ -#define GPIO_AF_PG1_EPI0S10 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg2_values GPIO_AF_PG2 Values - * @brief GPIO PG2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V11 | -@{*/ -/** I2C module 2 clock */ -#define GPIO_AF_PG2_I2C2SCL GPIO_AF2 -/** Ethernet 0 transmit clock */ -#define GPIO_AF_PG2_EN0TXCK GPIO_AF14 -/** SSI Module 2 bidirectional data pin 3 */ -#define GPIO_AF_PG2_SSI2XDAT3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg3_values GPIO_AF_PG3 Values - * @brief GPIO PG3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | M16 | -@{*/ -/** I2C module 2 data */ -#define GPIO_AF_PG3_I2C2SDA GPIO_AF2 -/** Ethernet 0 transmit enable */ -#define GPIO_AF_PG3_EN0TXEN GPIO_AF14 -/** SSI Module 2 bidirectional data pin 2 */ -#define GPIO_AF_PG3_SSI2XDAT2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg4_values GPIO_AF_PG4 Values - * @brief GPIO PG4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | K17 | -@{*/ -/** UART module 0 clear to send modem flow control input signal */ -#define GPIO_AF_PG4_U0CTS GPIO_AF1 -/** I2C module 3 clock */ -#define GPIO_AF_PG4_I2C3SCL GPIO_AF2 -/** 1-Wire single bus pin */ -#define GPIO_AF_PG4_OWIRE GPIO_AF5 -/** Ethernet 0 transmit data 0 */ -#define GPIO_AF_PG4_EN0TXD0 GPIO_AF14 -/** SSI Module 2 bidirectional data pin 1 */ -#define GPIO_AF_PG4_SSI2XDAT1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg5_values GPIO_AF_PG5 Values - * @brief GPIO PG5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | K15 | -@{*/ -/** UART module 0 request to send modem flow control output signal */ -#define GPIO_AF_PG5_U0RTS GPIO_AF1 -/** I2C module 3 data */ -#define GPIO_AF_PG5_I2C3SDA GPIO_AF2 -/** 1-Wire optional second signal to be used as output */ -#define GPIO_AF_PG5_OWALT GPIO_AF5 -/** Ethernet 0 transmit data 1 */ -#define GPIO_AF_PG5_EN0TXD1 GPIO_AF14 -/** SSI Module 2 bidirectional data pin 0 */ -#define GPIO_AF_PG5_SSI2XDAT0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg6_values GPIO_AF_PG6 Values - * @brief GPIO PG6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V12 | -@{*/ -/** I2C module 4 clock */ -#define GPIO_AF_PG6_I2C4SCL GPIO_AF2 -/** 1-Wire single bus pin */ -#define GPIO_AF_PG6_OWIRE GPIO_AF5 -/** Ethernet 0 receive error */ -#define GPIO_AF_PG6_EN0RXER GPIO_AF14 -/** SSI module 2 frame signal */ -#define GPIO_AF_PG6_SSI2FSS GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pg7_values GPIO_AF_PG7 Values - * @brief GPIO PG7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U14 | -@{*/ -/** I2C module 4 data */ -#define GPIO_AF_PG7_I2C4SDA GPIO_AF2 -/** 1-Wire single bus pin */ -#define GPIO_AF_PG7_OWIRE GPIO_AF5 -/** Ethernet 0 receive data valid */ -#define GPIO_AF_PG7_EN0RXDV GPIO_AF14 -/** SSI module 2 clock */ -#define GPIO_AF_PG7_SSI2CLK GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph0_values GPIO_AF_PH0 Values - * @brief GPIO PH0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 29 | - * NFBGA-212 | P4 | -@{*/ -/** UART module 0 request to send modem flow control output signal */ -#define GPIO_AF_PH0_U0RTS GPIO_AF1 -/** EPI module 0 signal 0 */ -#define GPIO_AF_PH0_EPI0S0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph1_values GPIO_AF_PH1 Values - * @brief GPIO PH1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 30 | - * NFBGA-212 | R2 | -@{*/ -/** UART module 0 clear to send modem flow control input signal */ -#define GPIO_AF_PH1_U0CTS GPIO_AF1 -/** EPI module 0 signal 1 */ -#define GPIO_AF_PH1_EPI0S1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph2_values GPIO_AF_PH2 Values - * @brief GPIO PH2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 31 | - * NFBGA-212 | R1 | -@{*/ -/** UART module 0 data carrier detect modem status input signal */ -#define GPIO_AF_PH2_U0DCD GPIO_AF1 -/** EPI module 0 signal 2 */ -#define GPIO_AF_PH2_EPI0S2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph3_values GPIO_AF_PH3 Values - * @brief GPIO PH3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 32 | - * NFBGA-212 | T1 | -@{*/ -/** UART module 0 data set ready modem output control line */ -#define GPIO_AF_PH3_U0DSR GPIO_AF1 -/** EPI module 0 signal 3 */ -#define GPIO_AF_PH3_EPI0S3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph4_values GPIO_AF_PH4 Values - * @brief GPIO PH4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | R3 | -@{*/ -/** UART module 0 data terminal ready modem status input signal */ -#define GPIO_AF_PH4_U0DTR GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_ph5_values GPIO_AF_PH5 Values - * @brief GPIO PH5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | T2 | -@{*/ -/** UART module 0 ring indicator modem status input signal */ -#define GPIO_AF_PH5_U0RI GPIO_AF1 -/** Ethernet 0 pulse-per-second (PPS) output */ -#define GPIO_AF_PH5_EN0PPS GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ph6_values GPIO_AF_PH6 Values - * @brief GPIO PH6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U2 | -@{*/ -/** UART module 5 receive */ -#define GPIO_AF_PH6_U5RX GPIO_AF1 -/** UART module 7 receive */ -#define GPIO_AF_PH6_U7RX GPIO_AF2 -/**@}*/ - -/** @defgroup gpio_af_ph7_values GPIO_AF_PH7 Values - * @brief GPIO PH7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V2 | -@{*/ -/** UART module 5 transmit */ -#define GPIO_AF_PH7_U5TX GPIO_AF1 -/** UART module 7 transmit */ -#define GPIO_AF_PH7_U7TX GPIO_AF2 -/**@}*/ - -/** @defgroup gpio_af_pj0_values GPIO_AF_PJ0 Values - * @brief GPIO PJ0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 116 | - * NFBGA-212 | C8 | -@{*/ -/** UART module 3 receive */ -#define GPIO_AF_PJ0_U3RX GPIO_AF1 -/** Ethernet 0 pulse-per-second (PPS) output */ -#define GPIO_AF_PJ0_EN0PPS GPIO_AF5 -/**@}*/ - -/** @defgroup gpio_af_pj1_values GPIO_AF_PJ1 Values - * @brief GPIO PJ1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 117 | - * NFBGA-212 | E7 | -@{*/ -/** UART module 3 transmit */ -#define GPIO_AF_PJ1_U3TX GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pj2_values GPIO_AF_PJ2 Values - * @brief GPIO PJ2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | H17 | -@{*/ -/** UART module 2 request to send modem flow control output line */ -#define GPIO_AF_PJ2_U2RTS GPIO_AF1 -/** LCD data pin 14 input/output */ -#define GPIO_AF_PJ2_LCDDATA14 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pj3_values GPIO_AF_PJ3 Values - * @brief GPIO PJ3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | F16 | -@{*/ -/** UART module 2 clear to send modem flow control input signal */ -#define GPIO_AF_PJ3_U2CTS GPIO_AF1 -/** LCD data pin 15 input/output */ -#define GPIO_AF_PJ3_LCDDATA15 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pj4_values GPIO_AF_PJ4 Values - * @brief GPIO PJ4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | F18 | -@{*/ -/** UART module 3 request to send modem flow control output line */ -#define GPIO_AF_PJ4_U3RTS GPIO_AF1 -/** LCD data pin 16 output */ -#define GPIO_AF_PJ4_LCDDATA16 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pj5_values GPIO_AF_PJ5 Values - * @brief GPIO PJ5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | E17 | -@{*/ -/** UART module 3 clear to send modem flow control input signal */ -#define GPIO_AF_PJ5_U3CTS GPIO_AF1 -/** LCD data pin 17 output */ -#define GPIO_AF_PJ5_LCDDATA17 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pj6_values GPIO_AF_PJ6 Values - * @brief GPIO PJ6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | N1 | -@{*/ -/** UART module 4 request to send modem flow control output line */ -#define GPIO_AF_PJ6_U4RTS GPIO_AF1 -/** LCD AC bias or latch enable in raster mode */ -#define GPIO_AF_PJ6_LCDAC GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pj7_values GPIO_AF_PJ7 Values - * @brief GPIO PJ7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | K5 | -@{*/ -/** UART module 4 clear to send modem flow control input signal */ -#define GPIO_AF_PJ7_U4CTS GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pk0_values GPIO_AF_PK0 Values - * @brief GPIO PK0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 18 | - * NFBGA-212 | J1 | -@{*/ -/** UART module 4 receive */ -#define GPIO_AF_PK0_U4RX GPIO_AF1 -/** EPI module 0 signal 0 */ -#define GPIO_AF_PK0_EPI0S0 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk1_values GPIO_AF_PK1 Values - * @brief GPIO PK1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 19 | - * NFBGA-212 | J2 | -@{*/ -/** UART module 4 transmit */ -#define GPIO_AF_PK1_U4TX GPIO_AF1 -/** EPI module 0 signal 1 */ -#define GPIO_AF_PK1_EPI0S1 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk2_values GPIO_AF_PK2 Values - * @brief GPIO PK2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 20 | - * NFBGA-212 | K1 | -@{*/ -/** UART module 4 request to send modem flow control output line */ -#define GPIO_AF_PK2_U4RTS GPIO_AF1 -/** EPI module 0 signal 2 */ -#define GPIO_AF_PK2_EPI0S2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk3_values GPIO_AF_PK3 Values - * @brief GPIO PK3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 21 | - * NFBGA-212 | K2 | -@{*/ -/** UART module 4 clear to send modem flow control input signal */ -#define GPIO_AF_PK3_U4CTS GPIO_AF1 -/** EPI module 0 signal 3 */ -#define GPIO_AF_PK3_EPI0S3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk4_values GPIO_AF_PK4 Values - * @brief GPIO PK4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 63 | - * NFBGA-212 | U19 | -@{*/ -/** I2C module 3 clock */ -#define GPIO_AF_PK4_I2C3SCL GPIO_AF2 -/** Ethernet 0 LED 0 */ -#define GPIO_AF_PK4_EN0LED0 GPIO_AF5 -/** Motion control module 0 PWM 6 */ -#define GPIO_AF_PK4_M0PWM6 GPIO_AF6 -/** Ethernet 0 interrupt from the Ethernet PHY */ -#define GPIO_AF_PK4_EN0INTRN GPIO_AF7 -/** Ethernet 0 receive data 3 */ -#define GPIO_AF_PK4_EN0RXD3 GPIO_AF14 -/** EPI module 0 signal 32 */ -#define GPIO_AF_PK4_EPI0S32 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk5_values GPIO_AF_PK5 Values - * @brief GPIO PK5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 62 | - * NFBGA-212 | V17 | -@{*/ -/** I2C module 3 data */ -#define GPIO_AF_PK5_I2C3SDA GPIO_AF2 -/** Ethernet 0 LED 2 */ -#define GPIO_AF_PK5_EN0LED2 GPIO_AF5 -/** Motion control module 0 PWM 7 */ -#define GPIO_AF_PK5_M0PWM7 GPIO_AF6 -/** Ethernet 0 receive data 2 */ -#define GPIO_AF_PK5_EN0RXD2 GPIO_AF14 -/** EPI module 0 signal 31 */ -#define GPIO_AF_PK5_EPI0S31 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk6_values GPIO_AF_PK6 Values - * @brief GPIO PK6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 61 | - * NFBGA-212 | V16 | -@{*/ -/** I2C module 4 clock */ -#define GPIO_AF_PK6_I2C4SCL GPIO_AF2 -/** Ethernet 0 LED 1 */ -#define GPIO_AF_PK6_EN0LED1 GPIO_AF5 -/** Motion control module 0 PWM fault 1 */ -#define GPIO_AF_PK6_M0FAULT1 GPIO_AF6 -/** Ethernet 0 transmit data 2 */ -#define GPIO_AF_PK6_EN0TXD2 GPIO_AF14 -/** EPI module 0 signal 25 */ -#define GPIO_AF_PK6_EPI0S25 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pk7_values GPIO_AF_PK7 Values - * @brief GPIO PK7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 60 | - * NFBGA-212 | W16 | -@{*/ -/** UART module 0 ring indicator modem status input signal */ -#define GPIO_AF_PK7_U0RI GPIO_AF1 -/** I2C module 4 data */ -#define GPIO_AF_PK7_I2C4SDA GPIO_AF2 -/** Buffered version of the 32.768-kHz clock of the Hibernation module */ -#define GPIO_AF_PK7_RTCCLK GPIO_AF5 -/** Motion control module 0 PWM fault 2 */ -#define GPIO_AF_PK7_M0FAULT2 GPIO_AF6 -/** Ethernet 0 transmit data 3 */ -#define GPIO_AF_PK7_EN0TXD3 GPIO_AF14 -/** EPI module 0 signal 24 */ -#define GPIO_AF_PK7_EPI0S24 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl0_values GPIO_AF_PL0 Values - * @brief GPIO PL0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 81 | - * NFBGA-212 | G16 | -@{*/ -/** I2C module 2 data */ -#define GPIO_AF_PL0_I2C2SDA GPIO_AF2 -/** Motion control module 0 PWM fault 3 */ -#define GPIO_AF_PL0_M0FAULT3 GPIO_AF6 -/** USB data 0 */ -#define GPIO_AF_PL0_USB0D0 GPIO_AF14 -/** EPI module 0 signal 16 */ -#define GPIO_AF_PL0_EPI0S16 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl1_values GPIO_AF_PL1 Values - * @brief GPIO PL1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 82 | - * NFBGA-212 | H19 | -@{*/ -/** I2C module 2 clock */ -#define GPIO_AF_PL1_I2C2SCL GPIO_AF2 -/** QEI module 0 phase A */ -#define GPIO_AF_PL1_PHA0 GPIO_AF6 -/** USB data 1 */ -#define GPIO_AF_PL1_USB0D1 GPIO_AF14 -/** EPI module 0 signal 17 */ -#define GPIO_AF_PL1_EPI0S17 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl2_values GPIO_AF_PL2 Values - * @brief GPIO PL2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 83 | - * NFBGA-212 | G18 | -@{*/ -/** Analog comparator 0 output */ -#define GPIO_AF_PL2_C0O GPIO_AF5 -/** QEI module 0 phase B */ -#define GPIO_AF_PL2_PHB0 GPIO_AF6 -/** USB data 2 */ -#define GPIO_AF_PL2_USB0D2 GPIO_AF14 -/** EPI module 0 signal 18 */ -#define GPIO_AF_PL2_EPI0S18 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl3_values GPIO_AF_PL3 Values - * @brief GPIO PL3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 84 | - * NFBGA-212 | J18 | -@{*/ -/** Analog comparator 1 output */ -#define GPIO_AF_PL3_C1O GPIO_AF5 -/** QEI module 0 index */ -#define GPIO_AF_PL3_IDX0 GPIO_AF6 -/** USB data 3 */ -#define GPIO_AF_PL3_USB0D3 GPIO_AF14 -/** EPI module 0 signal 19 */ -#define GPIO_AF_PL3_EPI0S19 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl4_values GPIO_AF_PL4 Values - * @brief GPIO PL4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 85 | - * NFBGA-212 | H18 | -@{*/ -/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ -#define GPIO_AF_PL4_T0CCP0 GPIO_AF3 -/** USB data 4 */ -#define GPIO_AF_PL4_USB0D4 GPIO_AF14 -/** EPI module 0 signal 26 */ -#define GPIO_AF_PL4_EPI0S26 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl5_values GPIO_AF_PL5 Values - * @brief GPIO PL5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 86 | - * NFBGA-212 | G19 | -@{*/ -/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ -#define GPIO_AF_PL5_T0CCP1 GPIO_AF3 -/** USB data 5 */ -#define GPIO_AF_PL5_USB0D5 GPIO_AF14 -/** EPI module 0 signal 33 */ -#define GPIO_AF_PL5_EPI0S33 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pl6_values GPIO_AF_PL6 Values - * @brief GPIO PL6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 94 | - * NFBGA-212 | C18 | -@{*/ -/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ -#define GPIO_AF_PL6_T1CCP0 GPIO_AF3 -/**@}*/ - -/** @defgroup gpio_af_pl7_values GPIO_AF_PL7 Values - * @brief GPIO PL7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 93 | - * NFBGA-212 | B18 | -@{*/ -/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ -#define GPIO_AF_PL7_T1CCP1 GPIO_AF3 -/**@}*/ - -/** @defgroup gpio_af_pm0_values GPIO_AF_PM0 Values - * @brief GPIO PM0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 78 | - * NFBGA-212 | K18 | -@{*/ -/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ -#define GPIO_AF_PM0_T2CCP0 GPIO_AF3 -/** EPI module 0 signal 15 */ -#define GPIO_AF_PM0_EPI0S15 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pm1_values GPIO_AF_PM1 Values - * @brief GPIO PM1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 77 | - * NFBGA-212 | K19 | -@{*/ -/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ -#define GPIO_AF_PM1_T2CCP1 GPIO_AF3 -/** EPI module 0 signal 14 */ -#define GPIO_AF_PM1_EPI0S14 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pm2_values GPIO_AF_PM2 Values - * @brief GPIO PM2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 76 | - * NFBGA-212 | L18 | -@{*/ -/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ -#define GPIO_AF_PM2_T3CCP0 GPIO_AF3 -/** EPI module 0 signal 13 */ -#define GPIO_AF_PM2_EPI0S13 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pm3_values GPIO_AF_PM3 Values - * @brief GPIO PM3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 75 | - * NFBGA-212 | L19 | -@{*/ -/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ -#define GPIO_AF_PM3_T3CCP1 GPIO_AF3 -/** EPI module 0 signal 12 */ -#define GPIO_AF_PM3_EPI0S12 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pm4_values GPIO_AF_PM4 Values - * @brief GPIO PM4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 74 | - * NFBGA-212 | M18 | -@{*/ -/** UART module 0 clear to send modem flow control input signal */ -#define GPIO_AF_PM4_U0CTS GPIO_AF1 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ -#define GPIO_AF_PM4_T4CCP0 GPIO_AF3 -/** Ethernet 0 reference clock */ -#define GPIO_AF_PM4_EN0RREF_CLK GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pm5_values GPIO_AF_PM5 Values - * @brief GPIO PM5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 73 | - * NFBGA-212 | G15 | -@{*/ -/** UART module 0 data carrier detect modem status input signal */ -#define GPIO_AF_PM5_U0DCD GPIO_AF1 -/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ -#define GPIO_AF_PM5_T4CCP1 GPIO_AF3 -/**@}*/ - -/** @defgroup gpio_af_pm6_values GPIO_AF_PM6 Values - * @brief GPIO PM6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 72 | - * NFBGA-212 | N19 | -@{*/ -/** UART module 0 data set ready modem output control line */ -#define GPIO_AF_PM6_U0DSR GPIO_AF1 -/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ -#define GPIO_AF_PM6_T5CCP0 GPIO_AF3 -/** Ethernet 0 carrier sense */ -#define GPIO_AF_PM6_EN0CRS GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pm7_values GPIO_AF_PM7 Values - * @brief GPIO PM7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 71 | - * NFBGA-212 | N18 | -@{*/ -/** UART module 0 ring indicator modem status input signal */ -#define GPIO_AF_PM7_U0RI GPIO_AF1 -/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ -#define GPIO_AF_PM7_T5CCP1 GPIO_AF3 -/** Ethernet 0 collision detect */ -#define GPIO_AF_PM7_EN0COL GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pn0_values GPIO_AF_PN0 Values - * @brief GPIO PN0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 107 | - * NFBGA-212 | C10 | -@{*/ -/** UART module 1 request to send modem flow control output line */ -#define GPIO_AF_PN0_U1RTS GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pn1_values GPIO_AF_PN1 Values - * @brief GPIO PN1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 108 | - * NFBGA-212 | B11 | -@{*/ -/** UART module 1 clear to send modem flow control input signal */ -#define GPIO_AF_PN1_U1CTS GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pn2_values GPIO_AF_PN2 Values - * @brief GPIO PN2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 109 | - * NFBGA-212 | A11 | -@{*/ -/** UART module 1 data carrier detect modem status input signal */ -#define GPIO_AF_PN2_U1DCD GPIO_AF1 -/** UART module 2 request to send modem flow control output line */ -#define GPIO_AF_PN2_U2RTS GPIO_AF2 -/** EPI module 0 signal 29 */ -#define GPIO_AF_PN2_EPI0S29 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pn3_values GPIO_AF_PN3 Values - * @brief GPIO PN3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 110 | - * NFBGA-212 | B10 | -@{*/ -/** UART module 1 data set ready modem output control line */ -#define GPIO_AF_PN3_U1DSR GPIO_AF1 -/** UART module 2 clear to send modem flow control input signal */ -#define GPIO_AF_PN3_U2CTS GPIO_AF2 -/** EPI module 0 signal 30 */ -#define GPIO_AF_PN3_EPI0S30 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pn4_values GPIO_AF_PN4 Values - * @brief GPIO PN4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 111 | - * NFBGA-212 | A10 | -@{*/ -/** UART module 1 data terminal ready modem status input signal */ -#define GPIO_AF_PN4_U1DTR GPIO_AF1 -/** UART module 3 request to send modem flow control output line */ -#define GPIO_AF_PN4_U3RTS GPIO_AF2 -/** I2C module 2 data */ -#define GPIO_AF_PN4_I2C2SDA GPIO_AF3 -/** EPI module 0 signal 34 */ -#define GPIO_AF_PN4_EPI0S34 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pn5_values GPIO_AF_PN5 Values - * @brief GPIO PN5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 112 | - * NFBGA-212 | B9 | -@{*/ -/** UART module 1 ring indicator modem status input signal */ -#define GPIO_AF_PN5_U1RI GPIO_AF1 -/** UART module 3 clear to send modem flow control input signal */ -#define GPIO_AF_PN5_U3CTS GPIO_AF2 -/** I2C module 2 clock */ -#define GPIO_AF_PN5_I2C2SCL GPIO_AF3 -/** EPI module 0 signal 35 */ -#define GPIO_AF_PN5_EPI0S35 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pn6_values GPIO_AF_PN7 Values - * @brief GPIO PN6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | T12 | -@{*/ -/** UART module 4 request to send modem flow control output line */ -#define GPIO_AF_PN6_U4RTS GPIO_AF2 -/** Ethernet 0 transmit error */ -#define GPIO_AF_PN6_EN0TXER GPIO_AF14 -/** LCD data pin 13 input/output */ -#define GPIO_AF_PN6_LCDDATA13 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pn7_values GPIO_AF_PN7 Values - * @brief GPIO PN7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U12 | -@{*/ -/** UART module 1 request to send modem flow control output line */ -#define GPIO_AF_PN7_U1RTS GPIO_AF1 -/** UART module 4 clear to send modem flow control input signal */ -#define GPIO_AF_PN7_U4CTS GPIO_AF2 -/** LCD data pin 12 input/output */ -#define GPIO_AF_PN7_LCDDATA12 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pp0_values GPIO_AF_PP0 Values - * @brief GPIO PP0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 118 | - * NFBGA-212 | D6 | -@{*/ -/** UART module 6 receive */ -#define GPIO_AF_PP0_U6RX GPIO_AF1 -/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ -#define GPIO_AF_PP0_T6CCP0 GPIO_AF5 -/** Ethernet 0 interrupt from the Ethernet PHY */ -#define GPIO_AF_PP0_EN0INTRN GPIO_AF7 -/** SSI Module 3 bidirectional data pin 2 */ -#define GPIO_AF_PP0_SSI3XDAT2 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pp1_values GPIO_AF_PP1 Values - * @brief GPIO PP1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 119 | - * NFBGA-212 | D7 | -@{*/ -/** UART module 6 transmit */ -#define GPIO_AF_PP1_U6TX GPIO_AF1 -/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ -#define GPIO_AF_PP1_T6CCP1 GPIO_AF5 -/** SSI Module 3 bidirectional data pin 3 */ -#define GPIO_AF_PP1_SSI3XDAT3 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pp2_values GPIO_AF_PP2 Values - * @brief GPIO PP2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 103 | - * NFBGA-212 | B13 | -@{*/ -/** UART module 0 data terminal ready modem status input signal */ -#define GPIO_AF_PP2_U0DTR GPIO_AF1 -/** USB Asserted by the external PHY to throttle all data types */ -#define GPIO_AF_PP2_USB0NXT GPIO_AF14 -/** EPI module 0 signal 29 */ -#define GPIO_AF_PP2_EPI0S29 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pp3_values GPIO_AF_PP3 Values - * @brief GPIO PP3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 104 | - * NFBGA-212 | C12 | -@{*/ -/** UART module 1 clear to send modem flow control input signal */ -#define GPIO_AF_PP3_U1CTS GPIO_AF1 -/** UART module 0 data carrier detect modem status input signal */ -#define GPIO_AF_PP3_U0DCD GPIO_AF2 -/** Buffered version of the 32.768-kHz clock of the Hibernation module */ -#define GPIO_AF_PP3_RTCCLK GPIO_AF7 -/** USB Indicates that the external PHY is able to accept data - * from the USB controller */ -#define GPIO_AF_PP3_USB0DIR GPIO_AF14 -/** EPI module 0 signal 30 */ -#define GPIO_AF_PP3_EPI0S30 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pp4_values GPIO_AF_PP4 Values - * @brief GPIO PP4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 105 | - * NFBGA-212 | D8 | -@{*/ -/** UART module 3 request to send modem flow control output line */ -#define GPIO_AF_PP4_U3RTS GPIO_AF1 -/** UART module 0 data set ready modem output control line */ -#define GPIO_AF_PP4_U0DSR GPIO_AF2 -/** 1-Wire single bus pin */ -#define GPIO_AF_PP4_OWIRE GPIO_AF4 -/** USB data 7 */ -#define GPIO_AF_PP4_USB0D7 GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pp5_values GPIO_AF_PP5 Values - * @brief GPIO PP5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 106 | - * NFBGA-212 | B12 | -@{*/ -/** UART module 3 clear to send modem flow control input signal */ -#define GPIO_AF_PP5_U3CTS GPIO_AF1 -/** I2C module 2 clock */ -#define GPIO_AF_PP5_I2C2SCL GPIO_AF2 -/** 1-Wire optional second signal to be used as output */ -#define GPIO_AF_PP5_OWALT GPIO_AF4 -/** USB data 6 */ -#define GPIO_AF_PP5_USB0D6 GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pp6_values GPIO_AF_PP6 Values - * @brief GPIO PP6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | B8 | -@{*/ -/** UART module 1 data carrier detect modem status input signal */ -#define GPIO_AF_PP6_U1DCD GPIO_AF1 -/** I2C module 2 data */ -#define GPIO_AF_PP6_I2C2SDA GPIO_AF2 -/**@}*/ - -/** @defgroup gpio_af_pp7_values GPIO_AF_PP7 Values - * @brief GPIO PP7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | A8 | -@{*/ -/** 1-Wire single bus pin */ -#define GPIO_AF_PP7_OWIRE GPIO_AF5 -/**@}*/ - -/** @defgroup gpio_af_pq0_values GPIO_AF_PQ0 Values - * @brief GPIO PQ0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 5 | - * NFBGA-212 | E3 | -@{*/ -/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ -#define GPIO_AF_PQ0_T6CCP0 GPIO_AF3 -/** SSI module 3 clock */ -#define GPIO_AF_PQ0_SSI3CLK GPIO_AF14 -/** EPI module 0 signal 20 */ -#define GPIO_AF_PQ0_EPI0S20 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pq1_values GPIO_AF_PQ1 Values - * @brief GPIO PQ1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 6 | - * NFBGA-212 | E2 | -@{*/ -/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ -#define GPIO_AF_PQ1_T6CCP1 GPIO_AF3 -/** SSI module 3 frame signal */ -#define GPIO_AF_PQ1_SSI3FSS GPIO_AF14 -/** EPI module 0 signal 21 */ -#define GPIO_AF_PQ1_EPI0S21 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pq2_values GPIO_AF_PQ2 Values - * @brief GPIO PQ2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 11 | - * NFBGA-212 | H4 | -@{*/ -/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ -#define GPIO_AF_PQ2_T7CCP0 GPIO_AF3 -/** SSI Module 3 bidirectional data pin 0 */ -#define GPIO_AF_PQ2_SSI3XDAT0 GPIO_AF14 -/** EPI module 0 signal 22 */ -#define GPIO_AF_PQ2_EPI0S22 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pq3_values GPIO_AF_PQ3 Values - * @brief GPIO PQ3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 27 | - * NFBGA-212 | M4 | -@{*/ -/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ -#define GPIO_AF_PQ3_T7CCP1 GPIO_AF3 -/** SSI Module 3 bidirectional data pin 1 */ -#define GPIO_AF_PQ3_SSI3XDAT1 GPIO_AF14 -/** EPI module 0 signal 23 */ -#define GPIO_AF_PQ3_EPI0S23 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pq4_values GPIO_AF_PQ4 Values - * @brief GPIO PQ4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | 102 | - * NFBGA-212 | A13 | -@{*/ -/** UART module 1 receive */ -#define GPIO_AF_PQ4_U1RX GPIO_AF1 -/** Divided reference clock output */ -#define GPIO_AF_PQ4_DIVSCLK GPIO_AF7 -/**@}*/ - -/** @defgroup gpio_af_pq5_values GPIO_AF_PQ5 Values - * @brief GPIO PQ5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | W12 | -@{*/ -/** UART module 1 transmit */ -#define GPIO_AF_PQ5_U1TX GPIO_AF1 -/** Ethernet 0 receive data 0 */ -#define GPIO_AF_PQ5_EN0RXD0 GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pq6_values GPIO_AF_PQ6 Values - * @brief GPIO PQ6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U15 | -@{*/ -/** UART module 1 data terminal ready modem status input signal */ -#define GPIO_AF_PQ6_U1DTR GPIO_AF1 -/** Ethernet 0 receive data 1 */ -#define GPIO_AF_PQ6_EN0RXD1 GPIO_AF14 -/**@}*/ - -/** @defgroup gpio_af_pq7_values GPIO_AF_PQ7 Values - * @brief GPIO PQ7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | M3 | -@{*/ -/** UART module 1 ring indicator modem status input signal */ -#define GPIO_AF_PQ7_U1RI GPIO_AF1 -/**@}*/ - -/** @defgroup gpio_af_pr0_values GPIO_AF_PR0 Values - * @brief GPIO PR0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | N5 | -@{*/ -/** UART module 4 transmit */ -#define GPIO_AF_PR0_U4TX GPIO_AF1 -/** I2C module 1 clock */ -#define GPIO_AF_PR0_I2C1SCL GPIO_AF2 -/** Motion control module 0 PWM 0 */ -#define GPIO_AF_PR0_M0PWM0 GPIO_AF6 -/** LCD pixel clock in raster mode */ -#define GPIO_AF_PR0_LCDCP GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr1_values GPIO_AF_PR1 Values - * @brief GPIO PR1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | N4 | -@{*/ -/** UART module 4 receive */ -#define GPIO_AF_PR1_U4RX GPIO_AF1 -/** I2C module 1 data */ -#define GPIO_AF_PR1_I2C1SDA GPIO_AF2 -/** Motion control module 0 PWM 1 */ -#define GPIO_AF_PR1_M0PWM1 GPIO_AF6 -/** LCD frame clock or VSYNC in raster mode */ -#define GPIO_AF_PR1_LCDFP GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr2_values GPIO_AF_PR2 Values - * @brief GPIO PR2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | N2 | -@{*/ -/** I2C module 2 clock */ -#define GPIO_AF_PR2_I2C2SCL GPIO_AF2 -/** Motion control module 0 PWM 2 */ -#define GPIO_AF_PR2_M0PWM2 GPIO_AF6 -/** LCD line clock or HSYNC in raster mode */ -#define GPIO_AF_PR2_LCDLP GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr3_values GPIO_AF_PR3 Values - * @brief GPIO PR3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V8 | -@{*/ -/** I2C module 2 data */ -#define GPIO_AF_PR3_I2C2SDA GPIO_AF2 -/** Motion control module 0 PWM 3 */ -#define GPIO_AF_PR3_M0PWM3 GPIO_AF6 -/** LCD data pin 3 input/output */ -#define GPIO_AF_PR3_LCDDATA03 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr4_values GPIO_AF_PR4 Values - * @brief GPIO PR4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | P3 | -@{*/ -/** I2C module 3 clock */ -#define GPIO_AF_PR4_I2C3SCL GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ -#define GPIO_AF_PR4_T0CCP0 GPIO_AF3 -/** Motion control module 0 PWM 4 */ -#define GPIO_AF_PR4_M0PWM4 GPIO_AF6 -/** LCD data pin 0 input/output */ -#define GPIO_AF_PR4_LCDDATA00 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr5_values GPIO_AF_PR5 Values - * @brief GPIO PR5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | P2 | -@{*/ -/** UART module 1 receive */ -#define GPIO_AF_PR5_U1RX GPIO_AF1 -/** I2C module 3 data */ -#define GPIO_AF_PR5_I2C3SDA GPIO_AF2 -/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ -#define GPIO_AF_PR5_T0CCP1 GPIO_AF3 -/** Motion control module 0 PWM 5 */ -#define GPIO_AF_PR5_M0PWM5 GPIO_AF6 -/** LCD data pin 1 input/output */ -#define GPIO_AF_PR5_LCDDATA01 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr6_values GPIO_AF_PR6 Values - * @brief GPIO PR6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | W9 | -@{*/ -/** UART module 1 transmit */ -#define GPIO_AF_PR6_U1TX GPIO_AF1 -/** I2C module 4 clock */ -#define GPIO_AF_PR6_I2C4SCL GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ -#define GPIO_AF_PR6_T1CCP0 GPIO_AF3 -/** Motion control module 0 PWM 6 */ -#define GPIO_AF_PR6_M0PWM6 GPIO_AF6 -/** LCD data pin 4 input/output */ -#define GPIO_AF_PR6_LCDDATA04 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pr7_values GPIO_AF_PR7 Values - * @brief GPIO PR7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | R10 | -@{*/ -/** I2C module 4 data */ -#define GPIO_AF_PR7_I2C4SDA GPIO_AF2 -/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ -#define GPIO_AF_PR7_T1CCP1 GPIO_AF3 -/** Motion control module 0 PWM 7 */ -#define GPIO_AF_PR7_M0PWM7 GPIO_AF6 -/** Ethernet 0 transmit enable */ -#define GPIO_AF_PR7_EN0TXEN GPIO_AF14 -/** LCD data pin 5 input/output */ -#define GPIO_AF_PR7_LCDDATA05 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps0_values GPIO_AF_PS0 Values - * @brief GPIO PS0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | D12 | -@{*/ -/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ -#define GPIO_AF_PS0_T2CCP0 GPIO_AF3 -/** Motion control module 0 PWM fault 0 */ -#define GPIO_AF_PS0_M0FAULT0 GPIO_AF6 -/** LCD data pin 20 output */ -#define GPIO_AF_PS0_LCDDATA20 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps1_values GPIO_AF_PS1 Values - * @brief GPIO PS1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | D13 | -@{*/ -/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ -#define GPIO_AF_PS1_T2CCP1 GPIO_AF3 -/** Motion control module 0 PWM fault 1 */ -#define GPIO_AF_PS1_M0FAULT1 GPIO_AF6 -/** LCD data pin 21 output */ -#define GPIO_AF_PS1_LCDDATA21 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps2_values GPIO_AF_PS2 Values - * @brief GPIO PS2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | B14 | -@{*/ -/** UART module 1 data set ready modem output control line */ -#define GPIO_AF_PS2_U1DSR GPIO_AF1 -/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ -#define GPIO_AF_PS2_T3CCP0 GPIO_AF3 -/** Motion control module 0 PWM fault 2 */ -#define GPIO_AF_PS2_M0FAULT2 GPIO_AF6 -/** LCD data pin 22 output */ -#define GPIO_AF_PS2_LCDDATA22 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps3_values GPIO_AF_PS3 Values - * @brief GPIO PS3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | A14 | -@{*/ -/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ -#define GPIO_AF_PS3_T3CCP1 GPIO_AF3 -/** Motion control module 0 PWM fault 3 */ -#define GPIO_AF_PS3_M0FAULT3 GPIO_AF6 -/** LCD data pin 23 output */ -#define GPIO_AF_PS3_LCDDATA23 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps4_values GPIO_AF_PS4 Values - * @brief GPIO PS4 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V9 | -@{*/ -/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ -#define GPIO_AF_PS4_T4CCP0 GPIO_AF3 -/** QEI module 0 phase A */ -#define GPIO_AF_PS4_PHA0 GPIO_AF6 -/** Ethernet 0 transmit data 0 */ -#define GPIO_AF_PS4_EN0TXD0 GPIO_AF14 -/** LCD data pin 6 input/output */ -#define GPIO_AF_PS4_LCDDATA06 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps5_values GPIO_AF_PS5 Values - * @brief GPIO PS5 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | T13 | -@{*/ -/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ -#define GPIO_AF_PS5_T4CCP1 GPIO_AF3 -/** QEI module 0 phase B */ -#define GPIO_AF_PS5_PHB0 GPIO_AF6 -/** Ethernet 0 transmit data 1 */ -#define GPIO_AF_PS5_EN0TXD1 GPIO_AF14 -/** LCD data pin 7 input/output */ -#define GPIO_AF_PS5_LCDDATA07 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps6_values GPIO_AF_PS6 Values - * @brief GPIO PS6 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | U10 | -@{*/ -/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ -#define GPIO_AF_PS6_T5CCP0 GPIO_AF3 -/** QEI module 0 index */ -#define GPIO_AF_PS6_IDX0 GPIO_AF6 -/** Ethernet 0 receive error */ -#define GPIO_AF_PS6_EN0RXER GPIO_AF14 -/** LCD data pin 8 input/output */ -#define GPIO_AF_PS6_LCDDATA08 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_ps7_values GPIO_AF_PS7 Values - * @brief GPIO PS7 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | R13 | -@{*/ -/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ -#define GPIO_AF_PS7_T5CCP1 GPIO_AF3 -/** Ethernet 0 receive data valid */ -#define GPIO_AF_PS7_EN0RXDV GPIO_AF14 -/** LCD data pin 9 input/output */ -#define GPIO_AF_PS7_LCDDATA09 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pt0_values GPIO_AF_PT0 Values - * @brief GPIO PT0 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | W10 | -@{*/ -/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ -#define GPIO_AF_PT0_T6CCP0 GPIO_AF3 -/** CAN module 0 receive */ -#define GPIO_AF_PT0_CAN0RX GPIO_AF7 -/** Ethernet 0 receive data 0 */ -#define GPIO_AF_PT0_EN0RXD0 GPIO_AF14 -/** LCD data pin 10 input/output */ -#define GPIO_AF_PT0_LCDDATA10 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pt1_values GPIO_AF_PT1 Values - * @brief GPIO PT1 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | V10 | -@{*/ -/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ -#define GPIO_AF_PT1_T6CCP1 GPIO_AF3 -/** CAN module 0 transmit */ -#define GPIO_AF_PT1_CAN0TX GPIO_AF7 -/** Ethernet 0 receive data 1 */ -#define GPIO_AF_PT1_EN0RXD1 GPIO_AF14 -/** LCD data pin 11 input/output */ -#define GPIO_AF_PT1_LCDDATA11 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pt2_values GPIO_AF_PT2 Values - * @brief GPIO PT2 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | E18 | -@{*/ -/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ -#define GPIO_AF_PT2_T7CCP0 GPIO_AF3 -/** CAN module 1 receive */ -#define GPIO_AF_PT2_CAN1RX GPIO_AF7 -/** LCD data pin 18 output */ -#define GPIO_AF_PT2_LCDDATA18 GPIO_AF15 -/**@}*/ - -/** @defgroup gpio_af_pt3_values GPIO_AF_PT3 Values - * @brief GPIO PT3 Alternate Functions Values - * Package | Pin number | - * ----------- | -------------- | - * TQFP-128 | Not available | - * NFBGA-212 | F17 | -@{*/ -/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ -#define GPIO_AF_PT3_T7CCP1 GPIO_AF3 -/** CAN module 1 transmit */ -#define GPIO_AF_PT3_CAN1TX GPIO_AF7 -/** LCD data pin 19 output */ -#define GPIO_AF_PT3_LCDDATA19 GPIO_AF15 -/**@}*/ - -/** @brief GPIO Mode Definitions */ -enum gpio_mode { - GPIO_MODE_OUTPUT, /**< Configure pin as output */ - GPIO_MODE_INPUT, /**< Configure pin as input */ - GPIO_MODE_ANALOG /**< Configure pin as analog function */ -}; - -/** @brief GPIO Pull-Up/Pull-Down Definitions */ -enum gpio_pull_up_down { - GPIO_PUPD_NONE, /**< Do not pull the pin high or low */ - GPIO_PUPD_PULLUP, /**< Pull the pin high */ - GPIO_PUPD_PULLDOWN, /**< Pull the pin low */ -}; - -/** @brief GPIO Output Type Definitions */ -enum gpio_output_type { - GPIO_OTYPE_PP, /**< Push-pull configuration */ - GPIO_OTYPE_OD, /**< Open drain configuration */ -}; - -/** @brief GPIO Drive Strength Definitions */ -enum gpio_drive_strength { - GPIO_DRIVE_2MA, /**< 2mA drive */ - GPIO_DRIVE_4MA, /**< 4mA drive */ - GPIO_DRIVE_6MA, /**< 6mA drive */ - GPIO_DRIVE_8MA, /**< 8mA drive */ - GPIO_DRIVE_10MA, /**< 10mA drive */ - GPIO_DRIVE_12MA /**< 12mA drive */ -}; - -/** @brief GPIO Slew Control Definitions */ -enum gpio_slew_ctl { - GPIO_SLEW_CTL_ENABLE, /**< Slew rate control enable */ - GPIO_SLEW_CTL_DISABLE /**< Slew rate control disable */ -}; - -/** @brief GPIO Trigger Level/Edge Definitions */ -enum gpio_trigger { - GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */ - GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */ - GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */ - GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger */ - GPIO_TRIG_EDGE_BOTH /**< Both edges trigger */ -}; - -BEGIN_DECLS - -void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, - enum gpio_pull_up_down pull_up_down, uint8_t gpios); -void gpio_set_output_options(uint32_t gpioport, enum gpio_output_type otype, - enum gpio_drive_strength drive, - enum gpio_slew_ctl slewctl, - uint8_t gpios); -void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios); -void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, - uint8_t gpios); -void gpio_set(uint32_t gpioport, uint8_t gpios); -void gpio_clear(uint32_t gpioport, uint8_t gpios); -uint8_t gpio_get(uint32_t gpioport, uint8_t gpios); -void gpio_toggle(uint32_t gpioport, uint8_t gpios); -uint8_t gpio_port_read(uint32_t gpioport); -void gpio_port_write(uint32_t gpioport, uint8_t data); -void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios); -void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios); -void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios); -uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios); -void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios); - -END_DECLS - -/**@}*/ - -#endif /* MSP432E4_GPIO_H */ diff --git a/libopencm3/include/libopencm3/msp432/e4/irq.json b/libopencm3/include/libopencm3/msp432/e4/irq.json deleted file mode 100644 index b8c03fc..0000000 --- a/libopencm3/include/libopencm3/msp432/e4/irq.json +++ /dev/null @@ -1,102 +0,0 @@ -{ - "irqs": [ - "gpioa", - "gpiob", - "gpioc", - "gpiod", - "gpioe", - "uart0", - "uart1", - "ssi0", - "i2c0", - "pwm0_fault", - "pwm0_0", - "pwm0_1", - "pwm0_2", - "qei0", - "adc0ss0", - "adc0ss1", - "adc0ss2", - "adc0ss3", - "watchdog0", - "timer0a", - "timer0b", - "timer1a", - "timer1b", - "timer2a", - "timer2b", - "comp0", - "comp1", - "comp2", - "sysctl", - "flash_ctrl", - "gpiof", - "gpiog", - "gpioh", - "uart2", - "ssi1", - "timer3a", - "timer3b", - "i2c1", - "can0", - "can1", - "emac0", - "hib", - "usb0", - "pwm0_3", - "udma", - "udmaerr", - "adc1ss0", - "adc1ss1", - "adc1ss2", - "adc1ss3", - "epi0", - "gpioj", - "gpiok", - "gpiol", - "ssi2", - "ssi3", - "uart3", - "uart4", - "uart5", - "uart6", - "uart7", - "i2c2", - "i2c3", - "timer4a", - "timer4b", - "timer5a", - "timer5b", - "sysexc", - "i2c4", - "i2c5", - "gpiom", - "gpion", - "gpiop0", - "gpiop1", - "gpiop3", - "gpiop4", - "gpiop5", - "gpiop6", - "gpiop7", - "gpioq0", - "gpioq1", - "gpioq2", - "gpioq3", - "gpioq4", - "gpioq5", - "gpioq6", - "gpioq7", - "timer6a", - "timer6b", - "timer7a", - "timer7b", - "i2c6", - "i2c7", - "i2c8", - "i2c9" - ], - "partname_humanreadable": "MSP432 E4 series", - "partname_doxygen": "MSP432E4", - "includeguard": "LIBOPENCM3_MSP432_E4_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/msp432/e4/memorymap.h b/libopencm3/include/libopencm3/msp432/e4/memorymap.h deleted file mode 100644 index a2c864a..0000000 --- a/libopencm3/include/libopencm3/msp432/e4/memorymap.h +++ /dev/null @@ -1,174 +0,0 @@ -/** @defgroup msp432e4_memorymap MSP432E4xx Memory Map - * - * @ingroup MSP432E4xx_defines - * - * @brief Memory map for the MSP432E4xx devices - * - * @version 1.0.0 - * - * @date 22 July 2018 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2018 Dmitry Rezvanov - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef MSP432E4_MEMORYMAP_H -#define MSP432E4_MEMORYMAP_H - -#include - -/* --- MSP432E4xx specific peripheral definitions --------------------------- */ - -/** System Control Base Address */ -#define SYSCTL_BASE (0x400FE000U) - -/** Hibernation Module Base Address */ -#define HIB_BASE (0x400FC000U) - -/** Flash Controller Base Address */ -#define FLASH_CTRL_BASE (0x400FD000U) - -/** EEPROM Controller Base Address */ -#define EEPROM_BASE (0x400AF000U) - -/** Micro Direct Memory Access Base Address */ -#define DMA_BASE (0x400FF000U) - -/** Advance Encryption Standard Accelerator Base Address */ -#define AES_BASE (0x44036000U) - -/** Analog-to-Digital Converter Base Address */ -#define ADC0_BASE (0x40038000U) -#define ADC1_BASE (0x40039000U) - -/** Controller Area Network Base Address */ -#define CAN0_BASE (0x40040000U) -#define CAN1_BASE (0x40041000U) - -/** Analog Comparator Base Address */ -#define ACMP_BASE (0x4003C000U) - -/** Cyclical Redundancy Check Base Address */ -#define CRC_BASE (0x44030000U) - -/** Data Encryption Standard Accelerator Base Address */ -#define DES_BASE (0x44038000U) - -/** Ethernet Controller Base Address */ -#define EMAC_BASE (0x400EC000U) - -/** External Peripheral Interface Base Address */ -#define EPI0_BASE (0x400D0000U) - -/** General-Purpose Input/Outputs Base Address */ -#define GPIOA_APB_BASE (0x40004000U) -#define GPIOB_APB_BASE (0x40005000U) -#define GPIOC_APB_BASE (0x40006000U) -#define GPIOD_APB_BASE (0x40007000U) -#define GPIOE_APB_BASE (0x40024000U) -#define GPIOF_APB_BASE (0x40025000U) -#define GPIOG_APB_BASE (0x40026000U) -#define GPIOH_APB_BASE (0x40027000U) -#define GPIOJ_APB_BASE (0x4003D000U) - -/** General-Purpose Input/Outputs (AHB) Base Address */ -#define GPIOA_BASE (0x40058000U) -#define GPIOB_BASE (0x40059000U) -#define GPIOC_BASE (0x4005A000U) -#define GPIOD_BASE (0x4005B000U) -#define GPIOE_BASE (0x4005C000U) -#define GPIOF_BASE (0x4005D000U) -#define GPIOG_BASE (0x4005E000U) -#define GPIOH_BASE (0x4005F000U) -#define GPIOJ_BASE (0x40060000U) -#define GPIOK_BASE (0x40061000U) -#define GPIOL_BASE (0x40062000U) -#define GPIOM_BASE (0x40063000U) -#define GPION_BASE (0x40064000U) -#define GPIOP_BASE (0x40065000U) -#define GPIOQ_BASE (0x40066000U) - -/** General-Purpose Timers Base Address */ -#define TIM0_BASE (0x40030000U) -#define TIM1_BASE (0x40031000U) -#define TIM2_BASE (0x40032000U) -#define TIM3_BASE (0x40033000U) -#define TIM4_BASE (0x40034000U) -#define TIM5_BASE (0x40035000U) -#define TIM6_BASE (0x400E0000U) -#define TIM7_BASE (0x400E1000U) - -/** Inter-Integrated Circuit Base Address */ -#define I2C0_BASE (0x40020000U) -#define I2C1_BASE (0x40021000U) -#define I2C2_BASE (0x40022000U) -#define I2C3_BASE (0x40023000U) -#define I2C4_BASE (0x400C0000U) -#define I2C5_BASE (0x400C1000U) -#define I2C6_BASE (0x400C2000U) -#define I2C7_BASE (0x400C3000U) -#define I2C8_BASE (0x400B8000U) -#define I2C9_BASE (0x400B9000U) - -/** LCD Controller Base Address */ -#define LCD_BASE (0x44050000U) - -/** Pulse Width Modulator Base Address */ -#define PWM0_BASE (0x40028000U) - -/** 1-Wire Master Module Base Address */ -#define ONEWIRE_BASE (0x400B6000U) - -/** Quad Synchronous Serial Interface Base Address */ -#define SSI0_BASE (0x40008000U) -#define SSI1_BASE (0x40009000U) -#define SSI2_BASE (0x4000A000U) -#define SSI3_BASE (0x4000B000U) - -/** Quadrature Encoder Interface Base Address */ -#define QEI0_BASE (0x4002C000U) - -/** SHA/MD5 Accelerator Base Address */ -#define SHA_BASE (0x44034000U) - -/** Universal Asynchronous Receiver/Transmitter Base Address */ -#define UART0_BASE (0x4000C000U) -#define UART1_BASE (0x4000D000U) -#define UART2_BASE (0x4000E000U) -#define UART3_BASE (0x4000F000U) -#define UART4_BASE (0x40010000U) -#define UART5_BASE (0x40011000U) -#define UART6_BASE (0x40012000U) -#define UART7_BASE (0x40013000U) - -/** Universal Serial Bus Controller Base Address */ -#define USB_BASE (0x40050000U) - -/** Watchdog Timers Base Address */ -#define WDT0_BASE (0x40000000U) -#define WDT1_BASE (0x40001000U) - -#endif /* MSP432E4_MEMORYMAP_H */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/msp432/e4/systemcontrol.h b/libopencm3/include/libopencm3/msp432/e4/systemcontrol.h deleted file mode 100644 index 628c6c2..0000000 --- a/libopencm3/include/libopencm3/msp432/e4/systemcontrol.h +++ /dev/null @@ -1,1471 +0,0 @@ -/** @defgroup systemcontrol_defines System Control Defines - * - * @ingroup MSP432E4xx_defines - * - * @brief Defined Constants and Types for the MSP432E4xx System Control - * - * @version 1.0.0 - * - * @date 22 July 2018 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Alexandru Gagniuc - * Copyright (C) 2018 Dmitry Rezvanov - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef MSP432E4_SYSTEMCONTROL_H -#define MSP432E4_SYSTEMCONTROL_H - -/**@{*/ - -#include -#include -#include - -/** @defgroup sysctl_registers SYSCTL Registers - * @brief System Control Registers -@{*/ -/** Device Identification 0 */ -#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) -/** Device Identification 1 */ -#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) -/** Power-Temp Brownout Control */ -#define SYSCTL_PTBOCTL MMIO32(SYSCTL_BASE + 0x038) -/** Raw Interrupt Status */ -#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) -/** Interrupt Mask Control */ -#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) -/** RW1C Masked Interrupt Status and Clear */ -#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) -/** Reset Cause */ -#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) -/** RW1C Power-Temperature Cause */ -#define SYSCTL_PWRTC MMIO32(SYSCTL_BASE + 0x060) -/** NMI Cause Register */ -#define SYSCTL_NMIC MMIO32(SYSCTL_BASE + 0x064) -/** Main Oscillator Control */ -#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) -/** Run and Sleep Mode Configuration Register */ -#define SYSCTL_RSCLKCFG MMIO32(SYSCTL_BASE + 0x0B0) -/** Memory Timing Parameter Register 0 for Main Flash and EEPROM */ -#define SYSCTL_MEMTIM0 MMIO32(SYSCTL_BASE + 0x0C0) -/** Alternate Clock Configuration */ -#define SYSCTL_ALTCLKCFG MMIO32(SYSCTL_BASE + 0x138) -/** Deep Sleep Clock Configuration Register */ -#define SYSCTL_DSCLKCFG MMIO32(SYSCTL_BASE + 0x144) -/** Divisor and Source Clock Configuration */ -#define SYSCTL_DIVSCLK MMIO32(SYSCTL_BASE + 0x148) -/** System Properties */ -#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) -/** Precision Internal Oscillator Calibration */ -#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) -/** Precision Internal Oscillator Statistics */ -#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) -/** PLL Frequency 0 */ -#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) -/** PLL Frequency 1 */ -#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) -/** PLL Status */ -#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) -/** Sleep Power Configuration */ -#define SYSCTL_SLPPWRCFG MMIO32(SYSCTL_BASE + 0x188) -/** Deep-Sleep Power Configuration */ -#define SYSCTL_DSLPPWRCFG MMIO32(SYSCTL_BASE + 0x18C) -/** Non-Volatile Memory Information */ -#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) -/** LDO Sleep Power Control */ -#define SYSCTL_LDOSPCTL MMIO32(SYSCTL_BASE + 0x1B4) -/** LDO Sleep Power Calibration */ -#define SYSCTL_LDOSPCAL MMIO32(SYSCTL_BASE + 0x1B8) -/** LDO Deep-Sleep Power Control */ -#define SYSCTL_LDODPCTL MMIO32(SYSCTL_BASE + 0x1BC) -/** LDO Deep-Sleep Power Calibration */ -#define SYSCTL_LDODPCAL MMIO32(SYSCTL_BASE + 0x1C0) -/** Sleep / Deep-Sleep Power Mode Status */ -#define SYSCTL_SDPMST MMIO32(SYSCTL_BASE + 0x1CC) -/** Reset Behavior Control Register */ -#define SYSCTL_RESBEHAVCTL MMIO32(SYSCTL_BASE + 0x1D8) -/** Hardware System Service Request */ -#define SYSCTL_HSSR MMIO32(SYSCTL_BASE + 0x1F4) -/** USB Power Domain Status */ -#define SYSCTL_USBPDS MMIO32(SYSCTL_BASE + 0x280) -/** USB Memory Power Control */ -#define SYSCTL_USBMPC MMIO32(SYSCTL_BASE + 0x284) -/** Ethernet MAC Power Domain Status */ -#define SYSCTL_EMACPDS MMIO32(SYSCTL_BASE + 0x288) -/** Ethernet MAC Memory Power Control */ -#define SYSCTL_EMACMPC MMIO32(SYSCTL_BASE + 0x28C) -/** LCD Power Domain Status */ -#define SYSCTL_LCDPDS MMIO32(SYSCTL_BASE + 0x290) -/** LCD Memory Power Control */ -#define SYSCTL_LCDMPC MMIO32(SYSCTL_BASE + 0x294) -/** CAN 0 Power Domain Status */ -#define SYSCTL_CAN0PDS MMIO32(SYSCTL_BASE + 0x298) -/** CAN 0 Memory Power Control */ -#define SYSCTL_CAN0MPC MMIO32(SYSCTL_BASE + 0x29C) -/** CAN 1 Power Domain Status */ -#define SYSCTL_CAN1PDS MMIO32(SYSCTL_BASE + 0x2A0) -/** CAN 1 Memory Power Control */ -#define SYSCTL_CAN1MPC MMIO32(SYSCTL_BASE + 0x2A4) - -/** Watchdog Timer Peripheral Present */ -#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) -/** 16/32-Bit General-Purpose Timer Peripheral Present */ -#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) -/** General-Purpose Input/Output Peripheral Present */ -#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) -/** Micro Direct Memory Access Peripheral Present */ -#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) -/** EPI Peripheral Present */ -#define SYSCTL_PPEPI MMIO32(SYSCTL_BASE + 0x310) -/** Hibernation Peripheral Present */ -#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) -/** Universal Asynchronous Receiver/Transmitter Peripheral Present */ -#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) -/** Synchronous Serial Interface Peripheral Present */ -#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) -/** Inter-Integrated Circuit Peripheral Present */ -#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) -/** Universal Serial Bus Peripheral Present */ -#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) -/** Ethernet PHY Peripheral Present */ -#define SYSCTL_PPEPHY MMIO32(SYSCTL_BASE + 0x330) -/** Controller Area Network Peripheral Present */ -#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) -/** Analog-to-Digital Converter Peripheral Present */ -#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) -/** Analog Comparator Peripheral Present */ -#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) -/** Pulse Width Modulator Peripheral Present */ -#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) -/** Quadrature Encoder Interface Peripheral Present */ -#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) -/** EEPROM Peripheral Present */ -#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) -/** CRC and Cryptographic Modules Peripheral Present */ -#define SYSCTL_PPCCM MMIO32(SYSCTL_BASE + 0x374) -/** LCD Peripheral Present */ -#define SYSCTL_PPLCD MMIO32(SYSCTL_BASE + 0x390) -/** 1-Wire Peripheral Present */ -#define SYSCTL_PPOWIRE MMIO32(SYSCTL_BASE + 0x398) -/** Ethernet MAC Peripheral Present */ -#define SYSCTL_PPEMAC MMIO32(SYSCTL_BASE + 0x39C) -/** Power Regulator Bus Peripheral Present */ -#define SYSCTL_PPPRB MMIO32(SYSCTL_BASE + 0x3A0) - -/** Watchdog Timer Software Reset */ -#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) -/** 16/32-Bit General-Purpose Timer Software Reset */ -#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) -/** General-Purpose Input/Output Software Reset */ -#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) -/** Micro Direct Memory Access Software Reset */ -#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) -/** EPI Software Reset */ -#define SYSCTL_SREPI MMIO32(SYSCTL_BASE + 0x510) -/** Hibernation Software Reset */ -#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) -/** Universal Asynchronous Receiver/Transmitter Software Reset */ -#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) -/** Synchronous Serial Interface Software Reset */ -#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) -/** Inter-Integrated Circuit Software Reset */ -#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) -/** Universal Serial Bus Software Reset */ -#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) -/** Ethernet PHY Software Reset */ -#define SYSCTL_SREPHY MMIO32(SYSCTL_BASE + 0x530) -/** Controller Area Network Software Reset */ -#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) -/** Analog-to-Digital Converter Software Reset */ -#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) -/** Analog Comparator Software Reset */ -#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) -/** Pulse Width Modulator Software Reset */ -#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) -/** Quadrature Encoder Interface Software Reset */ -#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) -/** EEPROM Software Reset */ -#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) -/** CRC and Cryptographic Modules Software Reset */ -#define SYSCTL_SRCCM MMIO32(SYSCTL_BASE + 0x574) -/** LCD Controller Software Reset */ -#define SYSCTL_SRLCD MMIO32(SYSCTL_BASE + 0x590) -/** 1-Wire Software Reset */ -#define SYSCTL_SROWIRE MMIO32(SYSCTL_BASE + 0x598) -/** Ethernet MAC Software Reset */ -#define SYSCTL_SREMAC MMIO32(SYSCTL_BASE + 0x59C) - -/** Watchdog Timer Run Mode Clock Gating Control */ -#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) -/** 16/32-BitGeneral-Purpose Timer RunMode Clock Gating Control */ -#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) -/** General-Purpose Input/Output Run Mode Clock Gating Control */ -#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) -/** Micro Direct Memory Access Run Mode Clock Gating Control */ -#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) -/** EPI Run Mode Clock Gating Control */ -#define SYSCTL_RCGCEPI MMIO32(SYSCTL_BASE + 0x610) -/** Hibernation Run Mode Clock Gating Control */ -#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) -/** Universal Asynchronous Receiver/Transmitter RunMode Clock Gating Control */ -#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) -/** Synchronous Serial Interface Run Mode Clock Gating Control */ -#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) -/** Inter-Integrated Circuit Run Mode Clock Gating Control */ -#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) -/** Universal Serial Bus Run Mode Clock Gating Control */ -#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) -/** Ethernet PHY Run Mode Clock Gating Control */ -#define SYSCTL_RCGCEPHY MMIO32(SYSCTL_BASE + 0x630) -/** Controller Area Network RunMode Clock Gating Control */ -#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) -/** Analog-to-Digital Converter Run Mode Clock Gating Control */ -#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) -/** Analog Comparator Run Mode Clock Gating Control */ -#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) -/** Pulse Width Modulator Run Mode Clock Gating Control */ -#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) -/** Quadrature Encoder Interface Run Mode Clock Gating Control */ -#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) -/** EEPROM Run Mode Clock Gating Control */ -#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) -/** CRC and CryptographicModules RunMode ClockGating Control */ -#define SYSCTL_RCGCCCM MMIO32(SYSCTL_BASE + 0x674) -/** LCD Controller Run Mode Clock Gating Control */ -#define SYSCTL_RCGCLCD MMIO32(SYSCTL_BASE + 0x690) -/** 1-Wire Run Mode Clock Gating Control */ -#define SYSCTL_RCGCOWIRE MMIO32(SYSCTL_BASE + 0x698) -/** Ethernet MAC Run Mode Clock Gating Control */ -#define SYSCTL_RCGCEMAC MMIO32(SYSCTL_BASE + 0x69C) - -/** Watchdog Timer Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) -/** 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) -/** General-Purpose Input/Output Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) -/** Micro Direct Memory Access Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) -/** EPI Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCEPI MMIO32(SYSCTL_BASE + 0x710) -/** Hibernation Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) -/** Universal Asynchronous Receiver/Transmitter S Mode Clock Gating Control */ -#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) -/** Synchronous Serial Interface Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) -/** Inter-Integrated Circuit Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) -/** Universal Serial Bus Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) -/** Ethernet PHY Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCEPHY MMIO32(SYSCTL_BASE + 0x730) -/** Controller Area Network Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) -/** Analog-to-Digital Converter Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) -/** Analog Comparator Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) -/** PulseWidthModulator Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) -/** Quadrature Encoder Interface Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) -/** EEPROM Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) -/** CRC and Cryptographic Modules Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCCCM MMIO32(SYSCTL_BASE + 0x774) -/** LCD Controller Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCLCD MMIO32(SYSCTL_BASE + 0x790) -/** 1-Wire Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCOWIRE MMIO32(SYSCTL_BASE + 0x798) -/** Ethernet MAC Sleep Mode Clock Gating Control */ -#define SYSCTL_SCGCEMAC MMIO32(SYSCTL_BASE + 0x79C) - -/** Watchdog Timer Deep-SleepMode Clock Gating Control */ -#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) -/** Clock 16/32-Bit General-Purpose Timer Deep-Sleep Mode Gating Control */ -#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) -/** General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) -/** Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) -/** EPI Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCEPI MMIO32(SYSCTL_BASE + 0x810) -/** Hibernation Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) -/** Universal Asynchronous Receiver/Transmitter D-S Mode Clock Gating Control*/ -#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) -/** Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) -/** Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) -/** Universal Serial Bus Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) -/** Ethernet PHY Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCEPHY MMIO32(SYSCTL_BASE + 0x830) -/** Controller Area Network Deep-SleepMode Clock Gating Control */ -#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) -/** Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) -/** Analog Comparator Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) -/** Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) -/** Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) -/** EEPROM Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) -/** CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCCCM MMIO32(SYSCTL_BASE + 0x874) -/** LCD Controller Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCLCD MMIO32(SYSCTL_BASE + 0x890) -/** 1-Wire Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCOWIRE MMIO32(SYSCTL_BASE + 0x898) -/** Ethernet MAC Deep-Sleep Mode Clock Gating Control */ -#define SYSCTL_DCGCEMAC MMIO32(SYSCTL_BASE + 0x89C) - -/** Watchdog Timer Power Control */ -#define SYSCTL_PCWD MMIO32(SYSCTL_BASE + 0x900) -/** 16/32-Bit General-Purpose Timer Power Control */ -#define SYSCTL_PCTIMER MMIO32(SYSCTL_BASE + 0x904) -/** General-Purpose Input/Output Power Control */ -#define SYSCTL_PCGPIO MMIO32(SYSCTL_BASE + 0x908) -/** Micro Direct Memory Access Power Control */ -#define SYSCTL_PCDMA MMIO32(SYSCTL_BASE + 0x90C) -/** External Peripheral Interface Power Control */ -#define SYSCTL_PCEPI MMIO32(SYSCTL_BASE + 0x910) -/** Hibernation Power Control */ -#define SYSCTL_PCHIB MMIO32(SYSCTL_BASE + 0x914) -/** Universal Asynchronous Receiver/Transmitter Power Control */ -#define SYSCTL_PCUART MMIO32(SYSCTL_BASE + 0x918) -/** Synchronous Serial Interface Power Control */ -#define SYSCTL_PCSSI MMIO32(SYSCTL_BASE + 0x91C) -/** Inter-Integrated Circuit Power Control */ -#define SYSCTL_PCI2C MMIO32(SYSCTL_BASE + 0x920) -/** Universal Serial Bus Power Control */ -#define SYSCTL_PCUSB MMIO32(SYSCTL_BASE + 0x928) -/** Ethernet PHY Power Control */ -#define SYSCTL_PCEPHY MMIO32(SYSCTL_BASE + 0x930) -/** Controller Area Network Power Control */ -#define SYSCTL_PCCAN MMIO32(SYSCTL_BASE + 0x934) -/** Analog-to-Digital Converter Power Control */ -#define SYSCTL_PCADC MMIO32(SYSCTL_BASE + 0x938) -/** Analog Comparator Power Control */ -#define SYSCTL_PCACMP MMIO32(SYSCTL_BASE + 0x93C) -/** Pulse Width Modulator Power Control */ -#define SYSCTL_PCPWM MMIO32(SYSCTL_BASE + 0x940) -/** Quadrature Encoder Interface Power Control */ -#define SYSCTL_PCQEI MMIO32(SYSCTL_BASE + 0x944) -/** EEPROM Power Control */ -#define SYSCTL_PCEEPROM MMIO32(SYSCTL_BASE + 0x958) -/** CRC and Cryptographic Modules Power Control */ -#define SYSCTL_PCCCM MMIO32(SYSCTL_BASE + 0x974) -/** LCD Controller Power Control */ -#define SYSCTL_PCLCD MMIO32(SYSCTL_BASE + 0x990) -/** 1-Wire Power Control */ -#define SYSCTL_PCOWIRE MMIO32(SYSCTL_BASE + 0x998) -/** Ethernet MAC Power Control */ -#define SYSCTL_PCEMAC MMIO32(SYSCTL_BASE + 0x99C) - -/** Watchdog Timer Peripheral Ready */ -#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) -/** 16/32-Bit General-Purpose Timer Peripheral Ready */ -#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) -/** General-Purpose Input/Output Peripheral Ready */ -#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) -/** Micro Direct Memory Access Peripheral Ready */ -#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) -/** EPI Peripheral Ready */ -#define SYSCTL_PREPI MMIO32(SYSCTL_BASE + 0xA10) -/** Hibernation Peripheral Ready */ -#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) -/** Universal Asynchronous Receiver/Transmitter Peripheral Ready */ -#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) -/** Synchronous Serial Interface Peripheral Ready */ -#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) -/** Inter-Integrated Circuit Peripheral Ready */ -#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) -/** Universal Serial Bus Peripheral Ready */ -#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) -/** Ethernet PHY Peripheral Ready */ -#define SYSCTL_PREPHY MMIO32(SYSCTL_BASE + 0xA30) -/** Controller Area Network Peripheral Ready */ -#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) -/** Analog-to-Digital Converter Peripheral Ready */ -#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) -/** Analog Comparator Peripheral Ready */ -#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) -/** Pulse Width Modulator Peripheral Ready */ -#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) -/** Quadrature Encoder Interface Peripheral Ready */ -#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) -/** EEPROM Peripheral Ready */ -#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) -/** CRC and Cryptographic Modules Peripheral Ready */ -#define SYSCTL_PRCCM MMIO32(SYSCTL_BASE + 0xA74) -/** LCD Controller Peripheral Ready */ -#define SYSCTL_PRLCD MMIO32(SYSCTL_BASE + 0xA90) -/** 1-Wire Peripheral Ready */ -#define SYSCTL_PROWIRE MMIO32(SYSCTL_BASE + 0xA98) -/** Ethernet MAC Peripheral Ready */ -#define SYSCTL_PREMAC MMIO32(SYSCTL_BASE + 0xA9C) - -/** Unique ID 0 */ -#define SYSCTL_UNIQUEID0 MMIO32(SYSCTL_BASE + 0xF20) -/** Unique ID 1 */ -#define SYSCTL_UNIQUEID1 MMIO32(SYSCTL_BASE + 0xF24) -/** Unique ID 2 */ -#define SYSCTL_UNIQUEID2 MMIO32(SYSCTL_BASE + 0xF28) -/** Unique ID 3 */ -#define SYSCTL_UNIQUEID3 MMIO32(SYSCTL_BASE + 0xF2C) -/**@}*/ - -/** @defgroup sysctl_did0_values SYSCTL_DID0 Values - * @brief System Control Device Identification 0 Register Values -@{*/ -/** DID0 Version Shift */ -#define SYSCTL_DID0_VER_SHIFT (28) -/** DID0 Version Mask */ -#define SYSCTL_DID0_VER_MASK (0x7) -/** Device Class Shift */ -#define SYSCTL_DID0_CLASS_SHIFT (16) -/** Device Class Mask */ -#define SYSCTL_DID0_CLASS_MASK (0xFF) -/** Major Revision Shift */ -#define SYSCTL_DID0_MAJOR_SHIFT (8) -/** Major Revision Mask */ -#define SYSCTL_DID0_MAJOR_MASK (0xFF) -/** Minor Revision Shift */ -#define SYSCTL_DID0_MINOR_SHIFT (0) -/** Minor Revision Mask */ -#define SYSCTL_DID0_MINOR_MASK (0xFF) -/**@}*/ - -/** @defgroup sysctl_did1_values SYSCTL_DID1 Values - * @brief System Control Device Identification 1 Register Values -@{*/ -/** DID1 Version Shift */ -#define SYSCTL_DID1_VER_SHIFT (28) -/** DID1 Version Mask */ -#define SYSCTL_DID1_VER_MASK (0xF) -/** Family Shift */ -#define SYSCTL_DID1_FAM_SHIFT (24) -/** Family Mask */ -#define SYSCTL_DID1_FAM_MASK (0xF) -/** Part Number Shift */ -#define SYSCTL_DID1_PARTNO_SHIFT (16) -/** Part Number Mask */ -#define SYSCTL_DID1_PARTNO_MASK (0xFF) -/** Package Pin Count Shift */ -#define SYSCTL_DID1_PINCOUNT_SHIFT (13) -/** Package Pin Count Mask */ -#define SYSCTL_DID1_PINCOUNT_MASK (0x7) -/** 128-pin package */ -#define SYSCTL_DID1_PINCOUNT_128P (0x6) -/** 212-pin package */ -#define SYSCTL_DID1_PINCOUNT_212P (0x7) -/** Temperature Range Shift */ -#define SYSCTL_DID1_TEMP_SHIFT (5) -/** Temperature Range Mask */ -#define SYSCTL_DID1_TEMP_MASK (0x7) -/** 0°C to +70°C */ -#define SYSCTL_DID1_TEMP_COMMERCIAL (0x0) -/** -40°C to +85°C */ -#define SYSCTL_DID1_TEMP_INDUSTRIAL (0x1) -/** -40°C to +105°C */ -#define SYSCTL_DID1_TEMP_EXTENDED (0x2) -/** Package Type Shift */ -#define SYSCTL_DID1_PKG_SHIFT (3) -/** Package Type Mask */ -#define SYSCTL_DID1_PKG_MASK (0x3) -/** QFP package */ -#define SYSCTL_DID1_PKG_QFP (0x1) -/** BGA package */ -#define SYSCTL_DID1_PKG_BGA (0x2) -/** RoHS-compliance */ -#define SYSCTL_DID1_ROHS (1 << 2) -/** Qualification Status Shift */ -#define SYSCTL_DID1_QUAL_SHIFT (0) -/** Qualification Status Mask */ -#define SYSCTL_DID1_QUAL_MASK (0x3) -/** Engineering Sample */ -#define SYSCTL_DID1_QUAL_SAMPLE (0x0) -/** Pilot Production */ -#define SYSCTL_DID1_QUAL_PILOT (0x1) -/** Fully Qualified */ -#define SYSCTL_DID1_QUAL_QUALIFIED (0x2) -/**@}*/ - -/** @defgroup sysctl_ptboctl_values SYSCTL_PTBOCTL0 Values - * @brief System Control Power-Temp Brownout Control Register Values -@{*/ -/** VDDA Under BOR Event Action Shift */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_SHIFT (8) -/** VDDA Under BOR Event Action Mask */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_MASK (0x3) -/** VDDA Under BOR Event Action - No action */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_NO (0x0) -/** VDDA Under BOR Event Action - System Control Interrupt */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_INT (0x1) -/** VDDA Under BOR Event Action - Non-maskable interrupt */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI (0x2) -/** VDDA Under BOR Event Action - Reset */ -#define SYSCTL_PTBOCTL_VDDA_UBOR_RESET (0x3) -/** VDD Under BOR Event Action Shift */ -#define SYSCTL_PTBOCTL_VDD_UBOR_SHIFT (1) -/** VDD Under BOR Event Action Mask */ -#define SYSCTL_PTBOCTL_VDD_UBOR_MASK (0x3) -/** VDD Under BOR Event Action - No action */ -#define SYSCTL_PTBOCTL_VDD_UBOR_NO (0x0) -/** VDD Under BOR Event Action - System Control Interrupt */ -#define SYSCTL_PTBOCTL_VDD_UBOR_INT (0x1) -/** VDD Under BOR Event Action - Non-maskable interrupt */ -#define SYSCTL_PTBOCTL_VDD_UBOR_NMI (0x2) -/** VDD Under BOR Event Action - Reset */ -#define SYSCTL_PTBOCTL_VDD_UBOR_RESET (0x3) -/**@}*/ - -/** @defgroup sysctl_ric_values SYSCTL_RIS Values - * @brief System Control Raw Interrupt Status Register Values -@{*/ -/** MOSC Power Up Raw Interrupt Status */ -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) -/** PLL Lock Raw Interrupt Status */ -#define SYSCTL_RIS_PLLLRIS (1 << 6) -/** Main Oscillator Failure Raw Interrupt Status */ -#define SYSCTL_RIS_MOFRIS (1 << 3) -/** Brown-Out Reset Raw Interrupt Status */ -#define SYSCTL_RIS_BORRIS (1 << 1) -/**@}*/ - -/** @defgroup sysctl_imc_values SYSCTL_IMC Values - * @brief System Control Interrupt Mask Control Register Values -@{*/ -/** MOSC Power Up Raw Interrupt Mask */ -#define SYSCTL_IMC_MOSCPUPIM (1 << 8) -/** PLL Lock Raw Interrupt Mask */ -#define SYSCTL_IMC_PLLLIM (1 << 6) -/** Main Oscillator Failure Raw Interrupt Mask */ -#define SYSCTL_IMC_MOFIM (1 << 3) -/** Brown-Out Reset Raw Interrupt Mask */ -#define SYSCTL_IMC_BORIM (1 << 1) -/**@}*/ - -/** @defgroup sysctl_misc_values SYSCTL_MISC Values - * @brief System Control Masked Interrupt Status and Clear Register Values -@{*/ -/** MOSC Power Up Raw Interrupt Status*/ -#define SYSCTL_MISC_MOSCPUPMIS (1 << 8) -/** PLL Lock Raw Interrupt Status */ -#define SYSCTL_MISC_PLLLMIS (1 << 6) -/** Main Oscillator Failure Raw Interrupt Status */ -#define SYSCTL_MISC_MOFMIS (1 << 3) -/** Brown-Out Reset Raw Interrupt Status */ -#define SYSCTL_MISC_BORMIS (1 << 1) -/**@}*/ - -/** @defgroup sysctl_resc_values SYSCTL_RESC Values - * @brief System Control Reset Cause Register Values -@{*/ -/** MOSC Failure Reset */ -#define SYSCTL_RESC_MOSCFAIL (1 << 16) -/** HSSR Reset */ -#define SYSCTL_RESC_HSSR (1 << 12) -/** Watchdog Timer 1 Reset */ -#define SYSCTL_RESC_WDT1 (1 << 5) -/** Software Reset */ -#define SYSCTL_RESC_SW (1 << 4) -/** Watchdog Timer 0 Reset */ -#define SYSCTL_RESC_WDT0 (1 << 3) -/** Brown-Out Reset */ -#define SYSCTL_RESC_BOR (1 << 2) -/** Power-On Reset */ -#define SYSCTL_RESC_POR (1 << 1) -/** External Reset */ -#define SYSCTL_RESC_EXT (1 << 0) -/**@}*/ - -/** @defgroup sysctl_pwrtc_values SYSCTL_PWRTC Values - * @brief System Control Power-Temperature Cause Register Values -@{*/ -/** VDDA Under BOR Status */ -#define SYSCTL_PWRTC_VDDA_UBOR (1 << 4) -/** VDD Under BOR Status */ -#define SYSCTL_PWRTC_VDD_UBOR (1 << 0) -/**@}*/ - -/** @defgroup sysctl_nmic_values SYSCTL_NMIC Values - * @brief System Control NMI Cause Register Values -@{*/ -/** MOSC Failure NMI */ -#define SYSCTL_NMIC_MOSCFAIL (1 << 16) -/** Tamper Event NMI */ -#define SYSCTL_NMIC_TAMPER (1 << 9) -/** WDT1 NMI */ -#define SYSCTL_NMIC_WDT1 (1 << 5) -/** WDT0 NMI */ -#define SYSCTL_NMIC_WDT0 (1 << 3) -/** Power/Brownout Event NMI */ -#define SYSCTL_NMIC_POWER (1 << 2) -/** External Pin NMI */ -#define SYSCTL_NMIC_EXTERNAL (1 << 0) -/**@}*/ - -/** @defgroup sysctl_moscctl_values SYSCTL_MOSCCTL Values - * @brief System Control Main Oscillator Control Register Values -@{*/ -/** Oscillator Range */ -#define SYSCTL_MOSCCTL_OSCRNG (1 << 4) -/** Power Down */ -#define SYSCTL_MOSCCTL_PWRDN (1 << 3) -/** No MOSC or Crystal Connected */ -#define SYSCTL_MOSCCTL_NOXTAL (1 << 2) -/** MOSC Failure Action */ -#define SYSCTL_MOSCCTL_MOSCIM (1 << 1) -/** Clock Validation for MOSC */ -#define SYSCTL_MOSCCTL_CVAL (1 << 0) -/**@}*/ - -/** @defgroup sysctl_rsclkcfg_values SYSCTL_RSCLKCFG Values - * @brief System Control Run and Sleep Mode Configuration Register Values -@{*/ -/** Memory Timing Register Update */ -#define SYSCTL_RSCLKCFG_MEMTIMU (1 << 31) -/** New PLLFREQ Accept */ -#define SYSCTL_RSCLKCFG_NEWFREQ (1 << 30) -/** Auto Clock Gating */ -#define SYSCTL_RSCLKCFG_ACG (1 << 29) -/** Use PLL */ -#define SYSCTL_RSCLKCFG_USEPLL (1 << 28) -/** PLL Source Shift */ -#define SYSCTL_RSCLKCFG_PLLSRC_SHIFT (24) -/** PLL Source Mask */ -#define SYSCTL_RSCLKCFG_PLLSRC_MASK (0xF) -/** PLL Source - MOSC */ -#define SYSCTL_RSCLKCFG_PLLSRC_MOSC (0x3) -/** Oscillator Source Shift */ -#define SYSCTL_RSCLKCFG_OSCSRC_SHIFT (20) -/** Oscillator Source Mask */ -#define SYSCTL_RSCLKCFG_OSCSRC_MASK (0xF) -/** Oscillator Source - LFIOSC */ -#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC (0x2) -/** Oscillator Source - MOSC */ -#define SYSCTL_RSCLKCFG_OSCSRC_MOSC (0x3) -/** Oscillator Source - RTCOSC */ -#define SYSCTL_RSCLKCFG_OSCSRC_RTCOSC (0x4) -/** Oscillator System Clock Divisor Shift */ -#define SYSCTL_RSCLKCFG_OSYSDIV_SHIFT (10) -/** Oscillator System Clock Divisor Mask */ -#define SYSCTL_RSCLKCFG_OSYSDIV_MASK (0x3FF) -/** PLL System Clock Divisor Shift */ -#define SYSCTL_RSCLKCFG_PSYSDIV_SHIFT (0) -/** PLL System Clock Divisor Mask */ -#define SYSCTL_RSCLKCFG_PSYSDIV_MASK (0x3FF) -/**@}*/ - -/** @defgroup sysctl_memtim0_values SYSCTL_MEMTIM0 Values - * @brief System Control Memory Timing Parameter Register 0 for Main Flash - * and EEPROM Register Values - * - * CPU Frequency Range (f) in MHZ |FBCHT and EBCHT|FBCE and EBCE| FWS and EWS| - * -------------------------------| ------------- | ----------- | ---------- | - * 16 | 0x0 (1/2) | 0x1 | 0x0 | - * 16 < f <= 40 | 0x2 (1.5) | 0x0 | 0x1 | - * 40 < f <= 60 | 0x3 (2) | 0x0 | 0x2 | - * 60 < f <= 80 | 0x4 (2.5) | 0x0 | 0x3 | - * 80 < f <= 100 | 0x5 (3) | 0x0 | 0x4 | - * 100 < f <= 120 | 0x6 (3.5) | 0x0 | 0x5 | - * -@{*/ -/** EEPROM Clock High Time Shift */ -#define SYSCTL_MEMTIM0_EBCHT_SHIFT (22) -/** EEPROM Clock High Time Mask */ -#define SYSCTL_MEMTIM0_EBCHT_MASK (0xF) -/** EBCHT - 0.5 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_0_POINT_5 (0x0) -/** EBCHT - 1 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_1 (0x1) -/** EBCHT - 1.5 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_1_POINT_5 (0x2) -/** EBCHT - 2 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_2 (0x3) -/** EBCHT - 2.5 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_2_POINT_5 (0x4) -/** EBCHT - 3 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_3 (0x5) -/** EBCHT - 3.5 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_3_POINT_5 (0x6) -/** EBCHT - 4 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_4 (0x7) -/** EBCHT - 4.5 sys clock period */ -#define SYSCTL_MEMTIM0_EBCHT_4_POINT_5 (0x8) -/** EEPROM Bank Clock Edge */ -#define SYSCTL_MEMTIM0_EBCE (1 << 21) -/** EEPROM Wait States Shift */ -#define SYSCTL_MEMTIM0_EWS_SHIFT (16) -/** EEPROM Wait States Mask */ -#define SYSCTL_MEMTIM0_EWS_MASK (0xF) -/** EWS - 1 wait state */ -#define SYSCTL_MEMTIM0_EWS_1 (0x1) -/** EWS - 2 wait state */ -#define SYSCTL_MEMTIM0_EWS_2 (0x2) -/** EWS - 3 wait state */ -#define SYSCTL_MEMTIM0_EWS_3 (0x3) -/** EWS - 4 wait state */ -#define SYSCTL_MEMTIM0_EWS_4 (0x4) -/** EWS - 5 wait state */ -#define SYSCTL_MEMTIM0_EWS_5 (0x5) -/** EWS - 6 wait state */ -#define SYSCTL_MEMTIM0_EWS_6 (0x6) -/** EWS - 7 wait state */ -#define SYSCTL_MEMTIM0_EWS_7 (0x7) -/** Flash Clock High Time Shift */ -#define SYSCTL_MEMTIM0_FBCHT_SHIFT (6) -/** Flash Clock High Time Mask */ -#define SYSCTL_MEMTIM0_FBCHT_MASK (0xF) -/** FBCHT - 0.5 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_0_POINT_5 (0x0) -/** FBCHT - 1 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_1 (0x1) -/** FBCHT - 1.5 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_1_POINT_5 (0x2) -/** FBCHT - 2 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_2 (0x3) -/** FBCHT - 2.5 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_2_POINT_5 (0x4) -/** FBCHT - 3 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_3 (0x5) -/** FBCHT - 3.5 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_3_POINT_5 (0x6) -/** FBCHT - 4 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_4 (0x7) -/** FBCHT - 4.5 sys clock period */ -#define SYSCTL_MEMTIM0_FBCHT_4_POINT_5 (0x8) -/** Flash Bank Clock Edge */ -#define SYSCTL_MEMTIM0_FBCE (1 << 5) -/** Flash Wait States Shift */ -#define SYSCTL_MEMTIM0_FWS_SHIFT (0) -/** Flash Wait States Mask */ -#define SYSCTL_MEMTIM0_FWS_MASK (0xF) -/** FWS - 1 wait state */ -#define SYSCTL_MEMTIM0_FWS_1 (0x1) -/** FWS - 2 wait state */ -#define SYSCTL_MEMTIM0_FWS_2 (0x2) -/** FWS - 3 wait state */ -#define SYSCTL_MEMTIM0_FWS_3 (0x3) -/** FWS - 4 wait state */ -#define SYSCTL_MEMTIM0_FWS_4 (0x4) -/** FWS - 5 wait state */ -#define SYSCTL_MEMTIM0_FWS_5 (0x5) -/** FWS - 6 wait state */ -#define SYSCTL_MEMTIM0_FWS_6 (0x6) -/** FWS - 7 wait state */ -#define SYSCTL_MEMTIM0_FWS_7 (0x7) -/**@}*/ - -/** @defgroup sysctl_altclkcfg_values SYSCTL_ALTCLKCFG Values - * @brief System Control Alternate Clock Configuration Register Values -@{*/ -/** Alternate Clock Source Shift */ -#define SYSCTL_ALTCLKCFG_ALTCLK_SHIFT (0) -/** Alternate Clock Source Mask */ -#define SYSCTL_ALTCLKCFG_ALTCLK_MASK (0xF) -/** Alternate Clock Source - RTCOSC */ -#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC (0x3) -/** Alternate Clock Source - LFIOSC */ -#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC (0x4) -/**@}*/ - -/** @defgroup sysctl_dsclkcfg_values SYSCTL_DSCLKCFG Values - * @brief System Control Deep Sleep Clock Configuration Register Values -@{*/ -/** PIOSC Power Down */ -#define SYSCTL_DSCLKCFG_PIOSCPD (1 << 31) -/** MOSC Disable Power Down */ -#define SYSCTL_DSCLKCFG_MOSCDPD (1 << 30) -/** Deep Sleep Oscillator Source Shift */ -#define SYSCTL_DSCLKCFG_DSOSCSRC_SHIFT (20) -/** Deep Sleep Oscillator Source Mask */ -#define SYSCTL_DSCLKCFG_DSOSCSRC_MASK (0xF) -/** Deep Sleep Oscillator Source - LFIOSC */ -#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC (0x2) -/** Deep Sleep Oscillator Source - MOSC */ -#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC (0x3) -/** Deep Sleep Oscillator Source - RTCOSC */ -#define SYSCTL_DSCLKCFG_DSOSCSRC_RTCOSC (0x4) -/** Deep Sleep Clock Divisor Shift */ -#define SYSCTL_DSCLKCFG_DSSYSDIV_SHIFT (0) -/** Deep Sleep Clock Divisor Mask */ -#define SYSCTL_DSCLKCFG_DSSYSDIV_MASK (0x3FF) -/**@}*/ - -/** @defgroup sysctl_divsclk_values SYSCTL_DIVSCLK Values - * @brief System Control Divisor and Source Clock Configuration Register Values -@{*/ -/** DIVSCLK Enable */ -#define SYSCTL_DIVSCLK_EN (1 << 31) -/** Clock Source Shift */ -#define SYSCTL_DIVSCLK_SRC_SHIFT (16) -/** Clock Source Mask */ -#define SYSCTL_DIVSCLK_SRC_MASK (0x3) -/** Clock Source - PIOSCK */ -#define SYSCTL_DIVSCLK_SRC_PIOSC (0x1) -/** Clock Source - MOSC */ -#define SYSCTL_DIVSCLK_SRC_MOSC (0x2) -/** Divisor Value Shift */ -#define SYSCTL_DIVSCLK_DIV_SHIFT (0) -/** Divisor Value Mask */ -#define SYSCTL_DIVSCLK_DIV_MASK (0xF) -/** Divisor Value - 1 */ -#define SYSCTL_DIVSCLK_DIV_1 (0x0) -/** Divisor Value - 2 */ -#define SYSCTL_DIVSCLK_DIV_2 (0x1) -/**@}*/ - -/** @defgroup sysctl_sysprop_values SYSCTL_SYSPROP Values - * @brief System Control System Properties Register Values -@{*/ -/** LDO Sleep Mode Enable */ -#define SYSCTL_SYSPROP_LDOSME (1 << 17) -/** Temp Sense Power Down Enable */ -#define SYSCTL_SYSPROP_TSPDE (1 << 16) -/** PIOSC Power Down Present */ -#define SYSCTL_SYSPROP_PIOSCPDE (1 << 12) -/** SRAM Sleep/Deep-Sleep Standby Mode Present */ -#define SYSCTL_SYSPROP_SRAMSM (1 << 11) -/** SRAM Sleep/Deep-Sleep Low Power Mode Present */ -#define SYSCTL_SYSPROP_SRAMLPM (1 << 10) -/** Flash Memory Sleep/Deep-Sleep Low Power Mode Present */ -#define SYSCTL_SYSPROP_FLASHLPM (1 << 8) -/** Automatic LDO Sequence Control Present */ -#define SYSCTL_SYSPROP_LDOSEQ (1 << 5) -/** FPU Present */ -#define SYSCTL_SYSPROP_FPU (1 << 0) -/**@}*/ - -/** @defgroup sysctl_piosccal_values SYSCTL_PIOSCCAL Values - * @brief System Control Precision Internal Oscillator - * Calibration Register Values -@{*/ -/** Use User Trim Value */ -#define SYSCTL_PIOSCCAL_UTEN (1 << 31) -/** Start Calibration */ -#define SYSCTL_PIOSCCAL_CAL (1 << 9) -/** Update Trim */ -#define SYSCTL_PIOSCCAL_UPDATE (1 << 8) -/** User Trim Value Shift */ -#define SYSCTL_PIOSCCAL_UT_SHIFT (0) -/** User Trim Value Mask */ -#define SYSCTL_PIOSCCAL_UT_MASK (0x7F) -/**@}*/ - -/** @defgroup sysctl_pioscstat_values SYSCTL_PIOSCSTAT Values - * @brief System Control Precision Internal Oscillator - * Statistics Register Values -@{*/ -/** Default Trim Value Shift */ -#define SYSCTL_PIOSCSTAT_DT_SHIFT (16) -/** Default Trim Value Mask */ -#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F) -/** Calibration Result Shift */ -#define SYSCTL_PIOSCSTAT_RESULT_SHIFT (8) -/** Calibration Result Mask */ -#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3) -/** Calibration Not Attempted */ -#define SYSCTL_PIOSCSTAT_RESULT_NOT_ATTEMPT (0x0) -/** Calibration Completed */ -#define SYSCTL_PIOSCSTAT_RESULT_COMPLETE (0x1) -/** Calibration Failed */ -#define SYSCTL_PIOSCSTAT_RESULT_FAIL (0x2) -/** Calibration Value Shift */ -#define SYSCTL_PIOSCSTAT_CT_SHIFT (0) -/** Calibration Value Mask */ -#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F) -/**@}*/ - -/** @defgroup sysctl_pllfreq0_values SYSCTL_PLLFREQ0 Values - * @brief System Control PLL Frequency 0 Register Values -@{*/ -/** PLL Power */ -#define SYSCTL_PLLFREQ0_PLLPWR (1 << 23) -/** PLL M Fractional Value Shift */ -#define SYSCTL_PLLFREQ0_MFRAC_SHIFT (10) -/** PLL M Fractional Value Mask */ -#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF) -/** PLL M Integer Value Shift */ -#define SYSCTL_PLLFREQ0_MINT_SHIFT (0) -/** PLL M Integer Value Mask */ -#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF) -/**@}*/ - -/** @defgroup sysctl_pllfreq1_values SYSCTL_PLLFREQ1 Values - * @brief System Control PLL Frequency 1 Register Values -@{*/ -/** PLL Q Value Shift */ -#define SYSCTL_PLLFREQ1_Q_SHIFT (8) -/** PLL Q Value Mask */ -#define SYSCTL_PLLFREQ1_Q_MASK (0x1F) -/** PLL N Value Shift */ -#define SYSCTL_PLLFREQ1_N_SHIFT (0) -/** PLL N Value Mask */ -#define SYSCTL_PLLFREQ1_N_MASK (0x1F) -/**@}*/ - -/** @defgroup sysctl_pllstat_values SYSCTL_PLLSTAT Values - * @brief System Control PLL Status Register Values -@{*/ -/** PLL Lock */ -#define SYSCTL_PLLSTAT_LOCK (1 << 0) -/**@}*/ - -/** @defgroup sysctl_slppwrcfg_values SYSCTL_SLPPWRCFG Values - * @brief System Control Sleep Power Configuration Register Values -@{*/ -/** Flash Power Modes Shift */ -#define SYSCTL_SLPPWRCFG_FLASHPM_SHIFT (4) -/** Flash Power Modes Mask */ -#define SYSCTL_SLPPWRCFG_FLASHPM_MASK (0x3) -/** Flash Power Mode - Active mode */ -#define SYSCTL_SLPPWRCFG_FLASHPM_ACTIVE (0x0) -/** Flash Power Mode - Low-Power Mode */ -#define SYSCTL_SLPPWRCFG_FLASHPM_LP (0x2) -/** SRAM Power Modes Shift */ -#define SYSCTL_SLPPWRCFG_SRAMPM_SHIFT (0) -/** SRAM Power Modes Mask */ -#define SYSCTL_SLPPWRCFG_SRAMPM_MASK (0x3) -/** SRAM Power Mode - Active mode */ -#define SYSCTL_SLPPWRCFG_SRAMPM_ACTIVE (0x0) -/** SRAM Power Mode - Standby mode */ -#define SYSCTL_SLPPWRCFG_SRAMPM_STANDBY (0x1) -/** SRAM Power Mode - Low-Power Mode */ -#define SYSCTL_SLPPWRCFG_SRAMPM_LP (0x3) -/**@}*/ - -/** @defgroup sysctl_dslppwrcfg_values SYSCTL_DSLPPWRCFG Values - * @brief System Control Deep-Sleep Power Configuration Register Values -@{*/ -/** LDO Sleep Mode */ -#define SYSCTL_DSLPPWRCFG_LDOSM (1 << 9) -/** Temp Sense Power Down */ -#define SYSCTL_DSLPPWRCFG_TSPD (1 << 8) -/** Flash Power Modes Shift */ -#define SYSCTL_DSLPPWRCFG_FLASHPM_SHIFT (4) -/** Flash Power Modes Mask */ -#define SYSCTL_DSLPPWRCFG_FLASHPM_MASK (0x3) -/** Flash Power Mode - Active mode */ -#define SYSCTL_DSLPPWRCFG_FLASHPM_ACTIVE (0x0) -/** Flash Power Mode - Low-Power Mode */ -#define SYSCTL_DSLPPWRCFG_FLASHPM_LP (0x2) -/** SRAM Power Modes Shift */ -#define SYSCTL_DSLPPWRCFG_SRAMPM_SHIFT (0) -/** SRAM Power Modes Mask */ -#define SYSCTL_DSLPPWRCFG_SRAMPM_MASK (0x3) -/** SRAM Power Mode - Active mode */ -#define SYSCTL_DSLPPWRCFG_SRAMPM_ACTIVE (0x0) -/** SRAM Power Mode - Standby mode */ -#define SYSCTL_DSLPPWRCFG_SRAMPM_STANDBY (0x1) -/** SRAM Power Mode - Low-Power Mode */ -#define SYSCTL_DSLPPWRCFG_SRAMPM_LP (0x3) -/**@}*/ - -/** @defgroup sysctl_nvmstat_values SYSCTL_NVMSTAT Values - * @brief System Control Non-Volatile Memory Information Register Values -@{*/ -/** 32 Word Flash Write Buffer Available */ -#define SYSCTL_NVMSTAT_FWB (1 << 0) -/**@}*/ - -/** @defgroup sysctl_ldospctl_values SYSCTL_LDOSPCTL Values - * @brief System Control LDO Sleep Power Control Register Values -@{*/ -/** Voltage Adjust Enable */ -#define SYSCTL_LDOSPCTL_VADJEN (1 << 31) -/** LDO Out Voltage Shift */ -#define SYSCTL_LDOSPCTL_VLDO_SHIFT (0) -/** LDO Out Voltage Mask */ -#define SYSCTL_LDOSPCTL_VLDO_MASK (0xFF) -/** LDO Out Voltage - 0.90V */ -#define SYSCTL_LDOSPCTL_VLDO_0_POINT_90 (0x12) -/** LDO Out Voltage - 0.95V */ -#define SYSCTL_LDOSPCTL_VLDO_0_POINT_95 (0x13) -/** LDO Out Voltage - 1.00V */ -#define SYSCTL_LDOSPCTL_VLDO_1_POINT_00 (0x14) -/** LDO Out Voltage - 1.05V */ -#define SYSCTL_LDOSPCTL_VLDO_1_POINT_05 (0x15) -/** LDO Out Voltage - 1.10V */ -#define SYSCTL_LDOSPCTL_VLDO_1_POINT_10 (0x16) -/** LDO Out Voltage - 1.15V */ -#define SYSCTL_LDOSPCTL_VLDO_1_POINT_15 (0x17) -/** LDO Out Voltage - 1.20V */ -#define SYSCTL_LDOSPCTL_VLDO_1_POINT_20 (0x18) -/**@}*/ - -/** @defgroup sysctl_ldospcal_values SYSCTL_LDOSPCAL Values - * @brief System Control LDO Sleep Power Calibration Register Values -@{*/ -/** Sleep With PLL Shift */ -#define SYSCTL_LDOSPCAL_WITHPLL_SHIFT (8) -/** Sleep With PLL Mask */ -#define SYSCTL_LDOSPCAL_WITHPLL_MASK (0xFF) -/** Sleep Without PLL Shift */ -#define SYSCTL_LDOSPCAL_NOPLL_SHIFT (0) -/** Sleep Without PLL Mask */ -#define SYSCTL_LDOSPCAL_NOPLL_MASK (0xFF) -/**@}*/ - -/** @defgroup sysctl_ldodpctl_values SYSCTL_LDODPCTL Values - * @brief System Control LDO Deep-Sleep Power Control Register Values -@{*/ -/** Voltage Adjust Enable */ -#define SYSCTL_LDODPCTL_VADJEN (1 << 31) -/** LDO Out Voltage Shift */ -#define SYSCTL_LDODPCTL_VLDO_SHIFT (0) -/** LDO Out Voltage Mask */ -#define SYSCTL_LDODPCTL_VLDO_MASK (0xFF) -/** LDO Out Voltage - 0.90V */ -#define SYSCTL_LDODPCTL_VLDO_0_POINT_90 (0x12) -/** LDO Out Voltage - 0.95V */ -#define SYSCTL_LDODPCTL_VLDO_0_POINT_95 (0x13) -/** LDO Out Voltage - 1.00V */ -#define SYSCTL_LDODPCTL_VLDO_1_POINT_00 (0x14) -/** LDO Out Voltage - 1.05V */ -#define SYSCTL_LDODPCTL_VLDO_1_POINT_05 (0x15) -/** LDO Out Voltage - 1.10V */ -#define SYSCTL_LDODPCTL_VLDO_1_POINT_10 (0x16) -/** LDO Out Voltage - 1.15V */ -#define SYSCTL_LDODPCTL_VLDO_1_POINT_15 (0x17) -/** LDO Out Voltage - 1.20V */ -#define SYSCTL_LDODPCTL_VLDO_1_POINT_20 (0x18) -/**@}*/ - -/** @defgroup sysctl_ldodpcal_values SYSCTL_LDODPCAL Values - * @brief System Control LDO Deep-Sleep Power Calibration Register Values -@{*/ -/** Deep-Sleep Without PLL Shift */ -#define SYSCTL_LDODPCAL_NOPLL_SHIFT (8) -/** Deep-Sleep Without PLL Mask */ -#define SYSCTL_LDODPCAL_NOPLL_MASK (0xFF) -/** Deep-Sleep With IOSC Shift */ -#define SYSCTL_LDODPCAL_30KHZ_SHIFT (0) -/** Deep-Sleep With IOSC Mask */ -#define SYSCTL_LDODPCAL_30KHZ_MASK (0xFF) -/**@}*/ - -/** @defgroup sysctl_sdpmst_values SYSCTL_SDPMST Values - * @brief System Control Sleep/Deep-Sleep Power Mode Status Register Values -@{*/ -/** LDO Update Active */ -#define SYSCTL_SDPMST_LDOUA (1 << 19) -/** Flash Memory in Low Power State */ -#define SYSCTL_SDPMST_FLASHLP (1 << 18) -/** Sleep or Deep-Sleep Mode */ -#define SYSCTL_SDPMST_LOWPWR (1 << 17) -/** Sleep or Deep-Sleep Power Request Active */ -#define SYSCTL_SDPMST_PRACT (1 << 16) -/** PIOSC Power Down Request Warning */ -#define SYSCTL_SDPMST_PPDW (1 << 7) -/** VLDO Value Above Max Error */ -#define SYSCTL_SDPMST_LMAXERR (1 << 6) -/** VLDO Value Below Minimum Error in Sleep Mode */ -#define SYSCTL_SDPMST_LSMINERR (1 << 4) -/** VLDO Value Below Minimum Error in Deep-Sleep Mode */ -#define SYSCTL_SDPMST_LDMINERR (1 << 3) -/** PIOSC Power Down Request Error */ -#define SYSCTL_SDPMST_PPDERR (1 << 2) -/** Flash Memory Power Down Request Error */ -#define SYSCTL_SDPMST_FPDERR (1 << 1) -/** SRAM Power Down Request Error */ -#define SYSCTL_SDPMST_SPDERR (1 << 0) -/**@}*/ - -/** @defgroup sysctl_resbehavctl_values SYSCTL_RESBEHAVCTL Values - * @brief System Control Reset Behavior Control Register Values -@{*/ -/** Reset Operation - System Reset */ -#define SYSCTL_RESBEHAVCTL_SYSRES (0x2) -/** Reset Operation - Power-On-Reset */ -#define SYSCTL_RESBEHAVCTL_POR (0x3) -/** Watchdog 1 Reset Operation Shift */ -#define SYSCTL_RESBEHAVCTL_WDOG1_SHIFT (6) -/** Watchdog 1 Reset Operation Mask */ -#define SYSCTL_RESBEHAVCTL_WDOG1_MASK (0x3) -/** Watchdog 0 Reset Operation Shift */ -#define SYSCTL_RESBEHAVCTL_WDOG0_SHIFT (4) -/** Watchdog 0 Reset Operation Mask */ -#define SYSCTL_RESBEHAVCTL_WDOG0_MASK (0x3) -/** BOR Reset Operation Shift */ -#define SYSCTL_RESBEHAVCTL_BOR_SHIFT (2) -/** BOR Reset Operation Shift */ -#define SYSCTL_RESBEHAVCTL_BOR_MASK (0x3) -/** EXT Reset Operation Shift */ -#define SYSCTL_RESBEHAVCTL_EXTRES_SHIFT (2) -/** EXT Reset Operation Mask */ -#define SYSCTL_RESBEHAVCTL_EXTRES_MASK (0x3) -/**@}*/ - -/** @defgroup sysctl_hssr_values SYSCTL_HSSR Values - * @brief System Control Hardware System Service Request Register Values -@{*/ -/** Write Key Shift */ -#define SYSCTL_HSSR_KEY_SHIFT (24) -/** Write Key Mask */ -#define SYSCTL_HSSR_KEY_MASK (0xFF) -/** Key Value for initiate request */ -#define SYSCTL_HSSR_KEY_VALUE (0xCA) -/** Command Descriptor Pointer Shift */ -#define SYSCTL_HSSR_CDOFF_SHIFT (0) -/** Command Descriptor Pointer Mask */ -#define SYSCTL_HSSR_CDOFF_MASK (0xFFFFFF) -/** Command Descriptor - No Request */ -#define SYSCTL_HSSR_CDOFF_NO_REQUEST (0x000000) -/** Command Descriptor - Error Or Incomplete Request */ -#define SYSCTL_HSSR_CDOFF_ERROR (0xFFFFFF) -/**@}*/ - -/** @defgroup sysctl_usbpds_values SYSCTL_USBPDS Values - * @brief System Control USB Power Domain Status Register Values -@{*/ -/** Memory Array Power Status Shift */ -#define SYSCTL_USBPDS_MEMSTAT_SHIFT (2) -/** Memory Array Power Status Mask */ -#define SYSCTL_USBPDS_MEMSTAT_MASK (0x3) -/** Memory Array Power Status - Off */ -#define SYSCTL_USBPDS_MEMSTAT_ARR_OFF (0x0) -/** Memory Array Power Status - SRAM Retention */ -#define SYSCTL_USBPDS_MEMSTAT_SRAM_RET (0x1) -/** Memory Array Power Status - On */ -#define SYSCTL_USBPDS_MEMSTAT_ARR_ON (0x3) -/** Power Domain Status Shift */ -#define SYSCTL_USBPDS_PWRSTAT_SHIFT (0) -/** Power Domain Status Mask */ -#define SYSCTL_USBPDS_PWRSTAT_MASK (0x3) -/** Power Domain Status - Off */ -#define SYSCTL_USBPDS_PWRSTAT_OFF (0x0) -/** Power Domain Status - On */ -#define SYSCTL_USBPDS_PWRSTAT_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_usbmpc_values SYSCTL_USBMPC Values - * @brief System Control USB Memory Power Control Register Values -@{*/ -/** Memory Array Power Control Shift */ -#define SYSCTL_USBMPC_PWRCTL_SHIFT (0) -/** Memory Array Power Control Mask */ -#define SYSCTL_USBMPC_PWRCTL_MASK (0x3) -/** Memory Array Power Control - Off */ -#define SYSCTL_USBMPC_PWRCTL_ARR_OFF (0x0) -/** Memory Array Power Control - SRAM Retention */ -#define SYSCTL_USBMPC_PWRCTL_SRAM_RET (0x1) -/** Memory Array Power Control - On */ -#define SYSCTL_USBMPC_PWRCTL_ARR_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_emacpds_values SYSCTL_EMACPDS Values - * @brief System Control Ethernet MAC Power Domain Status Register Values -@{*/ -/** Memory Array Power Status Shift */ -#define SYSCTL_EMACPDS_MEMSTAT_SHIFT (2) -/** Memory Array Power Status Mask */ -#define SYSCTL_EMACPDS_MEMSTAT_MASK (0x3) -/** Memory Array Power Status - Off */ -#define SYSCTL_EMACPDS_MEMSTAT_ARR_OFF (0x0) -/** Memory Array Power Status - On */ -#define SYSCTL_EMACPDS_MEMSTAT_ARR_ON (0x3) -/** Power Domain Status Shift*/ -#define SYSCTL_EMACPDS_PWRSTAT_SHIFT (0) -/** Power Domain Status Mask */ -#define SYSCTL_EMACPDS_PWRSTAT_MASK (0x3) -/** Power Domain Status - Off */ -#define SYSCTL_EMACPDS_PWRSTAT_OFF (0x0) -/** Power Domain Status - On */ -#define SYSCTL_EMACPDS_PWRSTAT_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_emacmpc_values SYSCTL_EMACMPC Values - * @brief System Control Ethernet MAC Memory Power Control Register Values -@{*/ -/** Memory Array Power Control Shift */ -#define SYSCTL_EMACMPC_PWRCTL_SHIFT (0) -/** Memory Array Power Control Mask */ -#define SYSCTL_EMACMPC_PWRCTL_MASK (0x3) -/** Memory Array Power Control - Off */ -#define SYSCTL_EMACMPC_PWRCTL_ARR_OFF (0x0) -/** Memory Array Power Control - On */ -#define SYSCTL_EMACMPC_PWRCTL_ARR_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_lcdpds_values SYSCTL_LCDPDS Values - * @brief System Control LCD Power Domain Status Register Values -@{*/ -/** Memory Array Power Status Shift */ -#define SYSCTL_LCDPDS_MEMSTAT_SHIFT (2) -/** Memory Array Power Status Mask */ -#define SYSCTL_LCDPDS_MEMSTAT_MASK (0x3) -/** Memory Array Power Status - Off */ -#define SYSCTL_LCDPDS_MEMSTAT_ARR_OFF (0x0) -/** Memory Array Power Status - On */ -#define SYSCTL_LCDPDS_MEMSTAT_ARR_ON (0x3) -/** Power Domain Status Shift*/ -#define SYSCTL_LCDPDS_PWRSTAT_SHIFT (0) -/** Power Domain Status Mask */ -#define SYSCTL_LCDPDS_PWRSTAT_MASK (0x3) -/** Power Domain Status - Off */ -#define SYSCTL_LCDPDS_PWRSTAT_OFF (0x0) -/** Power Domain Status - On */ -#define SYSCTL_LCDPDS_PWRSTAT_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_lcdmpc_values SYSCTL_LCDMPC Values - * @brief System Control LCD Memory Power Control Register Values -@{*/ -/** Memory Array Power Control Shift */ -#define SYSCTL_LCDMPC_PWRCTL_SHIFT (0) -/** Memory Array Power Control Mask */ -#define SYSCTL_LCDMPC_PWRCTL_MASK (0x3) -/** Memory Array Power Control - Off */ -#define SYSCTL_LCDMPC_PWRCTL_ARR_OFF (0x0) -/** Memory Array Power Control - On */ -#define SYSCTL_LCDMPC_PWRCTL_ARR_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_can0pds_values SYSCTL_CAN0PDS Values - * @brief System Control CAN 0 Power Domain Status Register Values -@{*/ -/** Memory Array Power Status Shift */ -#define SYSCTL_CAN0PDS_MEMSTAT_SHIFT (2) -/** Memory Array Power Status Mask */ -#define SYSCTL_CAN0PDS_MEMSTAT_MASK (0x3) -/** Memory Array Power Status - Off */ -#define SYSCTL_CAN0PDS_MEMSTAT_ARR_OFF (0x0) -/** Memory Array Power Status - On */ -#define SYSCTL_CAN0PDS_MEMSTAT_ARR_ON (0x3) -/** Power Domain Status Shift*/ -#define SYSCTL_CAN0PDS_PWRSTAT_SHIFT (0) -/** Power Domain Status Mask */ -#define SYSCTL_CAN0PDS_PWRSTAT_MASK (0x3) -/** Power Domain Status - Off */ -#define SYSCTL_CAN0PDS_PWRSTAT_OFF (0x0) -/** Power Domain Status - On */ -#define SYSCTL_CAN0PDS_PWRSTAT_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_can0mpc_values SYSCTL_CAN0MPC Values - * @brief System Control CAN 0 Memory Power Control Register Values -@{*/ -/** Memory Array Power Control Shift */ -#define SYSCTL_CAN0MPC_PWRCTL_SHIFT (0) -/** Memory Array Power Control Mask */ -#define SYSCTL_CAN0MPC_PWRCTL_MASK (0x3) -/** Memory Array Power Control - Off */ -#define SYSCTL_CAN0MPC_PWRCTL_ARR_OFF (0x0) -/** Memory Array Power Control - On */ -#define SYSCTL_CAN0MPC_PWRCTL_ARR_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_can1pds_values SYSCTL_CAN1PDS Values - * @brief System Control CAN 1 Power Domain Status Register Values -@{*/ -/** Memory Array Power Status Shift */ -#define SYSCTL_CAN1PDS_MEMSTAT_SHIFT (2) -/** Memory Array Power Status Mask */ -#define SYSCTL_CAN1PDS_MEMSTAT_MASK (0x3) -/** Memory Array Power Status - Off */ -#define SYSCTL_CAN1PDS_MEMSTAT_ARR_OFF (0x0) -/** Memory Array Power Status - On */ -#define SYSCTL_CAN1PDS_MEMSTAT_ARR_ON (0x3) -/** Power Domain Status Shift*/ -#define SYSCTL_CAN1PDS_PWRSTAT_SHIFT (0) -/** Power Domain Status Mask */ -#define SYSCTL_CAN1PDS_PWRSTAT_MASK (0x3) -/** Power Domain Status - Off */ -#define SYSCTL_CAN1PDS_PWRSTAT_OFF (0x0) -/** Power Domain Status - On */ -#define SYSCTL_CAN1PDS_PWRSTAT_ON (0x3) -/**@}*/ - -/** @defgroup sysctl_can1mpc_values SYSCTL_CAN1MPC Values - * @brief System Control CAN 1 Memory Power Control Register Values -@{*/ -/** Memory Array Power Control Shift */ -#define SYSCTL_CAN1MPC_PWRCTL_SHIFT (0) -/** Memory Array Power Control Mask */ -#define SYSCTL_CAN1MPC_PWRCTL_MASK (0x3) -/** Memory Array Power Control - Off */ -#define SYSCTL_CAN1MPC_PWRCTL_ARR_OFF (0x0) -/** Memory Array Power Control - On */ -#define SYSCTL_CAN1MPC_PWRCTL_ARR_ON (0x3) -/**@}*/ - -/** - * @brief Clock mode definitions - * The definitions are specified in the form offset from - * SYSCTL_BASE - * @li CLOCK_RUN - Run mode - * @li CLOCK_SLEEP - Sleep mode - * @li CLOCK_DEEP_SLEEP - Deep-Sleep Mode - */ -enum msp432_clock_mode { - CLOCK_RUN = 0x600, - CLOCK_SLEEP = 0x700, - CLOCK_DEEP_SLEEP = 0x800 -}; - -/** - * @brief Power mode definitions - * - * @li POWER_DISABLE - Module is not powered and does not receive a clock - * @li POWER_ENABLE - Module is powered but does not receive a clock - * - * @note If the module is in run, sleep or deep-sleep mode - the module - * is powered and receives a clock regardless of the value of power mode. - */ -enum msp432_power_mode { - POWER_DISABLE = false, - POWER_ENABLE = true -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -/** - * @brief Peripheral list definitions - * The definitions are specified in the form - * 31:5 register offset from first register for SR, PP, RCGC, - * SCGC, DCGC, PC, PR - * 4:0 bit offset for the given peripheral - */ -enum msp432_periph { - - PERIPH_WD0 = _REG_BIT(0x00, 0), - PERIPH_WD1, - - PERIPH_TIMER0 = _REG_BIT(0x04, 0), - PERIPH_TIMER1, - PERIPH_TIMER2, - PERIPH_TIMER3, - PERIPH_TIMER4, - PERIPH_TIMER5, - PERIPH_TIMER6, - PERIPH_TIMER7, - - PERIPH_GPIOA = _REG_BIT(0x08, 0), - PERIPH_GPIOB, - PERIPH_GPIOC, - PERIPH_GPIOD, - PERIPH_GPIOE, - PERIPH_GPIOF, - PERIPH_GPIOG, - PERIPH_GPIOH, - PERIPH_GPIOJ, - PERIPH_GPIOK, - PERIPH_GPIOL, - PERIPH_GPIOM, - PERIPH_GPION, - PERIPH_GPIOP, - PERIPH_GPIOQ, - PERIPH_GPIOR, - PERIPH_GPIOS, - PERIPH_GPIOT, - - PERIPH_DMA = _REG_BIT(0x0C, 0), - - PERIPH_EPI = _REG_BIT(0x10, 0), - - PERIPH_HIB = _REG_BIT(0x14, 0), - - PERIPH_UART0 = _REG_BIT(0x18, 0), - PERIPH_UART1, - PERIPH_UART2, - PERIPH_UART3, - PERIPH_UART4, - PERIPH_UART5, - PERIPH_UART6, - PERIPH_UART7, - - PERIPH_SSI0 = _REG_BIT(0x1C, 0), - PERIPH_SSI1, - PERIPH_SSI2, - PERIPH_SSI3, - - PERIPH_I2C0 = _REG_BIT(0x20, 0), - PERIPH_I2C1, - PERIPH_I2C2, - PERIPH_I2C3, - PERIPH_I2C4, - PERIPH_I2C5, - PERIPH_I2C6, - PERIPH_I2C7, - PERIPH_I2C8, - PERIPH_I2C9, - - PERIPH_USB0 = _REG_BIT(0x28, 0), - - PERIPH_EPHY = _REG_BIT(0x30, 0), - - PERIPH_CAN0 = _REG_BIT(0x34, 0), - PERIPH_CAN1, - - PERIPH_ADC0 = _REG_BIT(0x38, 0), - PERIPH_ADC1, - - PERIPH_ACMP = _REG_BIT(0x3C, 0), - - PERIPH_PWM = _REG_BIT(0x40, 0), - - PERIPH_QEI = _REG_BIT(0x44, 0), - - PERIPH_EEPROM = _REG_BIT(0x58, 0), - - PERIPH_CCM = _REG_BIT(0x74, 0), - - PERIPH_LCD = _REG_BIT(0x90, 0), - - PERIPH_OWIRE = _REG_BIT(0x98, 0), - - PERIPH_EMAC = _REG_BIT(0x9C, 0), - - PERIPH_PRB = _REG_BIT(0xA0, 0) -}; - -#undef _REG_BIT - -/* Function prototypes ------------------------------------------------------ */ - -BEGIN_DECLS - -void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph); -void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph); - -void sysctl_periph_reset(enum msp432_periph periph); -void sysctl_periph_clear_reset(enum msp432_periph periph); - -bool sysctl_periph_is_present(enum msp432_periph periph); -bool sysctl_periph_is_ready(enum msp432_periph periph); -void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, - enum msp432_periph periph); - -END_DECLS - -/**@}*/ - -#endif /* MSP432E4_SYSTEMCONTROL_H */ diff --git a/libopencm3/include/libopencm3/pac55xx/ccs.h b/libopencm3/include/libopencm3/pac55xx/ccs.h deleted file mode 100644 index b3054f1..0000000 --- a/libopencm3/include/libopencm3/pac55xx/ccs.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @brief Clock Control and System Defines for the Qorvo PAC55xx series of microcontrollers. - * - * @defgroup system_defines Clock Config and System Defines - * @ingroup PAC55xx_defines - * @author Brian Viele - * LGPL License Terms @ref lgpl_license - * @date 1 Dec 2019 - * - * Definitions in this file come from the PAC55XX Family User Guide Rev 1.21 - * by Active-Semi dated August 26, 2019. - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#ifndef INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ -#define INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ - -#include - -/**@{*/ - -/** Clock Control Registers - * @defgroup clock_config_regs Clock Config Registers. - * @{*/ -#define CCSCTL MMIO32(SCC_BASE) -#define CCSPLLCTL MMIO32(SCC_BASE + 0x04) -#define CCSROSCTRIM MMIO32(SCC_BASE + 0x08) -/**@}*/ - -/** Port Pin Config Addresses - * @defgroup port_pin_addresses Port Pinmux Register Base. - * @{*/ -#define CCS_PORTA (SCC_BASE + 0x0C) -#define CCS_PORTB (SCC_BASE + 0x10) -#define CCS_PORTC (SCC_BASE + 0x14) -#define CCS_PORTD (SCC_BASE + 0x18) -#define CCS_PORTE (SCC_BASE + 0x1C) -#define CCS_PORTF (SCC_BASE + 0x20) -#define CCS_PORTG (SCC_BASE + 0x24) -/**@}*/ - -/** Port Pin Mux Select Registers - * @defgroup pmux_sel_regs PMUXSEL register mapping. - * @{*/ -#define CCS_MUXSELR(base) MMIO32(base) -#define CCS_PAMUXSELR CCS_MUXSELR(CCS_PORTA) -#define CCS_PBMUXSELR CCS_MUXSELR(CCS_PORTB) -#define CCS_PCMUXSELR CCS_MUXSELR(CCS_PORTC) -#define CCS_PDMUXSELR CCS_MUXSELR(CCS_PORTD) -#define CCS_PEMUXSELR CCS_MUXSELR(CCS_PORTE) -#define CCS_PFMUXSELR CCS_MUXSELR(CCS_PORTF) -#define CCS_PGMUXSELR CCS_MUXSELR(CCS_PORTG) -#define CCS_MUXSELR_MASK 0x7 -#define CCS_MUXSELR_MASK_PIN(pin) (CCS_MUXSELR_MASK << ((pin) * 4)) -#define CCS_MUXSELR_VAL(pin, muxsel) (((muxsel) & CCS_MUXSELR_MASK) << ((pin) * 4)) - -/* Enum type for port function setting for type specificity. */ -typedef enum { - CCS_MUXSEL_GPIO = 0, - CCS_MUXSEL_AF1 = 1, - CCS_MUXSEL_AF2 = 2, - CCS_MUXSEL_AF3 = 3, - CCS_MUXSEL_AF4 = 4, - CCS_MUXSEL_AF5 = 5, - CCS_MUXSEL_AF6 = 6, - CCS_MUXSEL_AF7 = 7, -} ccs_muxsel_func_t; -/**@}*/ - -/** Port Pull-Up/Down Enable Registers. - * @defgroup pden_regs PUEN PDEN register mapping. - * @{*/ -#define CCS_PUENR(base) MMIO32(base + 0x1C) -#define CCS_PAPUENR CCS_PUENR(CCS_PORTA) -#define CCS_PBPUENR CCS_PUENR(CCS_PORTB) -#define CCS_PCPUENR CCS_PUENR(CCS_PORTC) -#define CCS_PDPUENR CCS_PUENR(CCS_PORTD) -#define CCS_PEPUENR CCS_PUENR(CCS_PORTE) -#define CCS_PFPUENR CCS_PUENR(CCS_PORTF) -#define CCS_PGPUENR CCS_PUENR(CCS_PORTG) -#define CCS_PDENR(base) MMIO32(base + 0x38) -#define CCS_PAPDENR CCS_PDENR(CCS_PORTA) -#define CCS_PBPDENR CCS_PDENR(CCS_PORTB) -#define CCS_PCPDENR CCS_PDENR(CCS_PORTC) -#define CCS_PDPDENR CCS_PDENR(CCS_PORTD) -#define CCS_PEPDENR CCS_PDENR(CCS_PORTE) -#define CCS_PFPDENR CCS_PDENR(CCS_PORTF) -#define CCS_PGPDENR CCS_PDENR(CCS_PORTG) -/** Pull Up/Down enum for type specificity. */ -typedef enum { - CCS_IO_PULL_NONE = 0, - CCS_IO_PULL_UP = 1, - CCS_IO_PULL_DOWN = 2 -} ccs_pull_updown_t; -/**@}*/ - -/** Port Drive Strength Enable Registers. - * @defgroup dsr_regs DSR register mapping. - * @{*/ -#define CCS_DSR(base) MMIO32(base + 0x54) -#define CCS_PADSR CCS_DSR(CCS_PORTA) -#define CCS_PBDSR CCS_DSR(CCS_PORTB) -#define CCS_PCDSR CCS_DSR(CCS_PORTC) -#define CCS_PDDSR CCS_DSR(CCS_PORTD) -#define CCS_PEDSR CCS_DSR(CCS_PORTE) -#define CCS_PFDSR CCS_DSR(CCS_PORTF) -#define CCS_PGDSR CCS_DSR(CCS_PORTG) -#define CCS_DSR_MASK 0x7 -#define CCS_DSR_MASK_PIN(pin) (CCS_DSR_MASK << ((pin) * 4)) -#define CCS_DSR_DS_VAL(pin, ds) (((ds)&CCS_DSR_MASK) << ((pin)*4)) -#define CCS_DSR_SCHMIDT_PIN(pin) (BIT0 << (((pin)*4) + 3)) - -/** Drive strength enumeration for type specificity. */ -typedef enum { - CCS_DSR_DS_6MA = 0x00, - CCS_DSR_DS_8MA = 0x01, - CCS_DSR_DS_11MA = 0x02, - CCS_DSR_DS_14MA = 0x03, - CCS_DSR_DS_17MA = 0x04, - CCS_DSR_DS_20MA = 0x05, - CCS_DSR_DS_22MA = 0x06, - CCS_DSR_DS_25MA = 0x07, -} ccs_drive_strength_t; -/**@}*/ -/**@}*/ - -#endif /* INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ */ diff --git a/libopencm3/include/libopencm3/pac55xx/doc-pac55xx.h b/libopencm3/include/libopencm3/pac55xx/doc-pac55xx.h deleted file mode 100644 index 4b218dd..0000000 --- a/libopencm3/include/libopencm3/pac55xx/doc-pac55xx.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @page libopencm3 PAC55xx - -@version 1.0.0 - -API documentation for Qorvo PAC55xx series MCUs. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup PAC55xx_defines PAC55xx Defines - -@brief Defined Constants and Types for the PAC55xx series - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/pac55xx/gpio.h b/libopencm3/include/libopencm3/pac55xx/gpio.h deleted file mode 100644 index 0d73c63..0000000 --- a/libopencm3/include/libopencm3/pac55xx/gpio.h +++ /dev/null @@ -1,320 +0,0 @@ -/** - * @brief GPIO definitions for the Qorvo PAC55xx series of microcontrollers. - * - * @addtogroup PAC55xx_gpio GPIO - * @ingroup PAC55xx_defines - * @author Brian Viele - * LGPL License Terms @ref lgpl_license - * @date 1 Dec 2019 - * - * Definitions in this file come from the PAC55XX Family User Guide Rev 1.21 - * by Active-Semi dated August 26, 2019. - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#ifndef INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_ -#define INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_ - -#include - -/* Note: CCS include file defines pinmux, drive strength, pull-up/pull-down, etc. */ -#include -#include - -/**@{*/ - -/** GPIO port base addresses (for convenience) - * @defgroup gpio_port_id GPIO Port IDs - * @{*/ -#define GPIOA GPIOA_BASE -#define GPIOB GPIOB_BASE -#define GPIOC GPIOC_BASE -#define GPIOD GPIOD_BASE -#define GPIOE GPIOE_BASE -#define GPIOF GPIOF_BASE -#define GPIOG GPIOG_BASE -/**@}*/ - -/** GPIO number definitions (for convenience) - * @defgroup gpio_pin_id GPIO Pin Identifiers - * @{*/ -#define GPIO_MAX_PIN (7U) -#define GPIO0 BIT0 -#define GPIO1 BIT1 -#define GPIO2 BIT2 -#define GPIO3 BIT3 -#define GPIO4 BIT4 -#define GPIO5 BIT5 -#define GPIO6 BIT6 -#define GPIO7 BIT7 -#define GPIO_ALL 0xff -/**@}*/ - -/** GPIO Mode Register Definitions - * @defgroup gpio_mode_regs GPIO MODE register mapping. - * @{*/ -/* Enum definitions for at least minimal type safety. */ -typedef enum { - GPIO_ANALOG_INPUT = 0, - GPIO_PUSH_PULL_OUTPUT = 1, - GPIO_OPEN_DRAIN_OUTPUT = 2, - GPIO_HIGH_IMPEDENCE_INPUT = 3, -} gpio_mode_t; -#define GPIO_MODER(base) MMIO32((base) + 0x00) -#define GPIOA_MODER GPIO_MODER(GPIOA) -#define GPIOB_MODER GPIO_MODER(GPIOB) -#define GPIOC_MODER GPIO_MODER(GPIOC) -#define GPIOD_MODER GPIO_MODER(GPIOD) -#define GPIOE_MODER GPIO_MODER(GPIOE) -#define GPIOF_MODER GPIO_MODER(GPIOF) -#define GPIOG_MODER GPIO_MODER(GPIOG) -#define GPIO_MODER_MASK 0x3 -#define GPIO_MODER_MASK_PIN(pin) (GPIO_MODER_MASK << ((pin)*2)) -#define GPIO_MODER_MODE(pin, mode) (((mode)&GPIO_MODER_MASK) << ((pin)*2)) -/**@}*/ - -/** GPIO Output Mask Register Definitions. This register may be used to lock the output value of - * a pin as changes to masked pins will have no effect. - * @defgroup gpio_outmask_regs GPIO OUTMASK register mapping. - * @{*/ -#define GPIO_OUTMASKR(base) MMIO32((base) + 0x04) -#define GPIOA_OUTMASKR GPIO_OUTMASKR(GPIOA) -#define GPIOB_OUTMASKR GPIO_OUTMASKR(GPIOB) -#define GPIOC_OUTMASKR GPIO_OUTMASKR(GPIOC) -#define GPIOD_OUTMASKR GPIO_OUTMASKR(GPIOD) -#define GPIOE_OUTMASKR GPIO_OUTMASKR(GPIOE) -#define GPIOF_OUTMASKR GPIO_OUTMASKR(GPIOF) -#define GPIOG_OUTMASKR GPIO_OUTMASKR(GPIOG) -/**@}*/ - -/** GPIO Output Register Definitions. - * @defgroup gpio_out_regs GPIO OUT register mapping. - * @{*/ -#define GPIO_OUTR(base) MMIO32((base) + 0x08) -#define GPIOA_OUTR GPIO_OUTR(GPIOA) -#define GPIOB_OUTR GPIO_OUTR(GPIOB) -#define GPIOC_OUTR GPIO_OUTR(GPIOC) -#define GPIOD_OUTR GPIO_OUTR(GPIOD) -#define GPIOE_OUTR GPIO_OUTR(GPIOE) -#define GPIOF_OUTR GPIO_OUTR(GPIOF) -#define GPIOG_OUTR GPIO_OUTR(GPIOG) -/**@}*/ - -/** GPIO Input Register Definitions. - * @defgroup gpio_in_regs GPIO IN register mapping. - * @{*/ -#define GPIO_INR(base) MMIO32((base) + 0x0C) -#define GPIOA_INR GPIO_INR(GPIOA) -#define GPIOB_INR GPIO_INR(GPIOB) -#define GPIOC_INR GPIO_INR(GPIOC) -#define GPIOD_INR GPIO_INR(GPIOD) -#define GPIOE_INR GPIO_INR(GPIOE) -#define GPIOF_INR GPIO_INR(GPIOF) -#define GPIOG_INR GPIO_INR(GPIOG) -/**@}*/ - -/** GPIO Interrupt Enable Register Definitions. - * @defgroup gpio_inten_regs GPIO INTEN register mapping. - * @{*/ -#define GPIO_INTENR(base) MMIO32((base) + 0x10) -#define GPIOA_INTENR GPIO_INTENR(GPIOA) -#define GPIOB_INTENR GPIO_INTENR(GPIOB) -#define GPIOC_INTENR GPIO_INTENR(GPIOC) -#define GPIOD_INTENR GPIO_INTENR(GPIOD) -#define GPIOE_INTENR GPIO_INTENR(GPIOE) -#define GPIOF_INTENR GPIO_INTENR(GPIOF) -#define GPIOG_INTENR GPIO_INTENR(GPIOG) -/**@}*/ - -/** GPIO Interrupt Flag Register Definitions. - * @defgroup gpio_intflag_regs GPIO INTFLAG register mapping. - * @{*/ -#define GPIO_INTFLAGR(base) MMIO32((base) + 0x14) -#define GPIOA_INTFLAGR GPIO_INTFLAGR(GPIOA) -#define GPIOB_INTFLAGR GPIO_INTFLAGR(GPIOB) -#define GPIOC_INTFLAGR GPIO_INTFLAGR(GPIOC) -#define GPIOD_INTFLAGR GPIO_INTFLAGR(GPIOD) -#define GPIOE_INTFLAGR GPIO_INTFLAGR(GPIOE) -#define GPIOF_INTFLAGR GPIO_INTFLAGR(GPIOF) -#define GPIOG_INTFLAGR GPIO_INTFLAGR(GPIOG) -/**@}*/ - -/** GPIO Interrupt Clear Register Definitions. - * @defgroup gpio_intclear_regs GPIO INTCLEAR register mapping. - * @{*/ -#define GPIO_INTCLEARR(base) MMIO32((base) + 0x1C) -#define GPIOA_INTCLEARR GPIO_INTCLEARR(GPIOA) -#define GPIOB_INTCLEARR GPIO_INTCLEARR(GPIOB) -#define GPIOC_INTCLEARR GPIO_INTCLEARR(GPIOC) -#define GPIOD_INTCLEARR GPIO_INTCLEARR(GPIOD) -#define GPIOE_INTCLEARR GPIO_INTCLEARR(GPIOE) -#define GPIOF_INTCLEARR GPIO_INTCLEARR(GPIOF) -#define GPIOG_INTCLEARR GPIO_INTCLEARR(GPIOG) -/**@}*/ - -/** GPIO Interrupt Type Register Definitions. - * @defgroup gpio_inttype_regs GPIO INTTYPE register mapping. - * @{*/ -#define GPIO_INTTYPE_EDGE 0U -#define GPIO_INTTYPE_LEVEL 1U -#define GPIO_INTTYPER(base) MMIO32((base) + 0x20) -#define GPIOA_INTTYPER GPIO_INTTYPER(GPIOA) -#define GPIOB_INTTYPER GPIO_INTTYPER(GPIOB) -#define GPIOC_INTTYPER GPIO_INTTYPER(GPIOC) -#define GPIOD_INTTYPER GPIO_INTTYPER(GPIOD) -#define GPIOE_INTTYPER GPIO_INTTYPER(GPIOE) -#define GPIOF_INTTYPER GPIO_INTTYPER(GPIOF) -#define GPIOG_INTTYPER GPIO_INTTYPER(GPIOG) -/**@}*/ - -/** GPIO Interrupt Config Register Definitions. - * @defgroup gpio_intcfg_regs GPIO INTCFG register mapping. - * @{*/ -#define GPIO_INTCFG_FALLING_LOW 0U -#define GPIO_INTCFG_RISING_HIGH 1U -#define GPIO_INTCFGR(base) MMIO32((base) + 0x24) -#define GPIOA_INTCFGR GPIO_INTCFGR(GPIOA) -#define GPIOB_INTCFGR GPIO_INTCFGR(GPIOB) -#define GPIOC_INTCFGR GPIO_INTCFGR(GPIOC) -#define GPIOD_INTCFGR GPIO_INTCFGR(GPIOD) -#define GPIOE_INTCFGR GPIO_INTCFGR(GPIOE) -#define GPIOF_INTCFGR GPIO_INTCFGR(GPIOF) -#define GPIOG_INTCFGR GPIO_INTCFGR(GPIOG) -/**@}*/ - -/** GPIO Interrupt Edge Both Definitions. This overrides the config if set. - * @defgroup gpio_intedgeboth_regs GPIO INTEDGEBOTH register mapping. - * @{*/ -#define GPIO_INTEDGEBOTHR(base) MMIO32((base) + 0x28) -#define GPIOA_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOA) -#define GPIOB_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOB) -#define GPIOC_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOC) -#define GPIOD_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOD) -#define GPIOE_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOE) -#define GPIOF_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOF) -#define GPIOG_INTEDGEBOTHR GPIO_INTEDGEBOTHR(GPIOG) -/**@}*/ - -/** GPIO Clock Synchronization Settings. When set, this enables 3-clock synchronizer on pins. - * @defgroup gpio_clksync_regs GPIO CLKSYNC register mapping. - * @{*/ -#define GPIO_CLKSYNCR(base) MMIO32((base) + 0x2C) -#define GPIOA_CLKSYNCR GPIO_CLKSYNCR(GPIOA) -#define GPIOB_CLKSYNCR GPIO_CLKSYNCR(GPIOB) -#define GPIOC_CLKSYNCR GPIO_CLKSYNCR(GPIOC) -#define GPIOD_CLKSYNCR GPIO_CLKSYNCR(GPIOD) -#define GPIOE_CLKSYNCR GPIO_CLKSYNCR(GPIOE) -#define GPIOF_CLKSYNCR GPIO_CLKSYNCR(GPIOF) -#define GPIOG_CLKSYNCR GPIO_CLKSYNCR(GPIOG) -/**@}*/ - -/** GPIO Set Register. This register can be used for atomic setting of outputs. - * @defgroup gpio_doset_regs GPIO DOSET register mapping. - * @{*/ -#define GPIO_DOSETR(base) MMIO32((base) + 0x30) -#define GPIOA_DOSETR GPIO_DOSETR(GPIOA) -#define GPIOB_DOSETR GPIO_DOSETR(GPIOB) -#define GPIOC_DOSETR GPIO_DOSETR(GPIOC) -#define GPIOD_DOSETR GPIO_DOSETR(GPIOD) -#define GPIOE_DOSETR GPIO_DOSETR(GPIOE) -#define GPIOF_DOSETR GPIO_DOSETR(GPIOF) -#define GPIOG_DOSETR GPIO_DOSETR(GPIOG) -/**@}*/ - -/** GPIO Set Register. This register can be used for atomic setting of outputs. - * @defgroup gpio_doclear_regs GPIO DOCLEAR register mapping. - * @{*/ -#define GPIO_DOCLEARR(base) MMIO32((base) + 0x34) -#define GPIOA_DOCLEARR GPIO_DOCLEARR(GPIOA) -#define GPIOB_DOCLEARR GPIO_DOCLEARR(GPIOB) -#define GPIOC_DOCLEARR GPIO_DOCLEARR(GPIOC) -#define GPIOD_DOCLEARR GPIO_DOCLEARR(GPIOD) -#define GPIOE_DOCLEARR GPIO_DOCLEARR(GPIOE) -#define GPIOF_DOCLEARR GPIO_DOCLEARR(GPIOF) -#define GPIOG_DOCLEARR GPIO_DOCLEARR(GPIOG) -/**@}*/ - -/**@}*/ - -BEGIN_DECLS -/** GPIO Application Programming Interface. - * @defgroup gpio_api GPIO Peripheral API - * @ingroup peripheral_apis -@{*/ -/** - * Set the IO mode and pull-up/down configuration for the pins. - * @param[in] gpioport Port to configure the alternate function on. - * @param[in] mode IO Mode to configure (analog, input, output). - * @param[in] pull_up_down Pull configuration (up/down/none) to set for the pins.. - * @param[in] gpios Pins to set with the mode and pull config specified. - */ -void gpio_mode_setup(uint32_t gpioport, gpio_mode_t mode, - ccs_pull_updown_t pull_up_down, uint16_t gpios); -/** - * Set the output mask (disable changes) to the output pins specified. - * @param[in] gpioport Port to set output mask on. - * @param[in] enable Whether to enable or disable output masking. - * @param[in] gpios bitfield of pins to set. - */ -void gpio_set_outmask(uint32_t gpioport, bool enable, uint16_t gpios); -/** - * Set the port pins specified to the true state. - * @param[in] gpioport Port to set bits on. - * @param[in] gpios bitfield of pins to set. - */ -void gpio_set(uint32_t gpioport, uint16_t gpios); -/** - * Clear the port pins specified to the false state. - * @param[in] gpioport Port to clear bits on. - * @param[in] gpios bitfield of pins to clear. - */ -void gpio_clear(uint32_t gpioport, uint16_t gpios); -/** - * Return a masked bitfield of the port specified. - * @param[in] gpioport Port to read the bits from. - * @param[in] gpios bitfield mask to apply to the port read. - * @return masked bitfield of the port. - */ -uint16_t gpio_get(uint32_t gpioport, uint16_t gpios); -/** - * Set the function of the pin for this port. This will modify the pinmux, - * @param[in] gpioport Port to configure the alternate function on. - * @param[in] muxsel Mux select mode to configure on the port and pins. - * @param[in] gpios Pins to set with the function specified. - */ -void gpio_set_af(uint32_t gpioport, ccs_muxsel_func_t muxsel, uint16_t gpios); - -/** - * Set special output options for the gpio pin. For this MCU, this is only the drive strength. - * @param[in] gpioport Port to configure the alternate function on. - * @param[in] strength Drive strength (DS_XXMA from ccs.h). - * @param[in] gpios Pins to set with the drive strength specified. - */ -void gpio_set_output_options(uint32_t gpioport, ccs_drive_strength_t strength, - uint16_t gpios); -/** - * Set input schmidt trigger for glitch rejection on the input pin. - * @param[in] gpioport Port to configure the alternate function on. - * @param[in] enable True to enable, false to disable the schmidt trigger. - * @param[in] gpios Pins to set with the schmidt trigger setting specified. - */ -void gpio_set_schmidt_trigger(uint32_t gpioport, bool enable, uint16_t gpios); -/**@}*/ - -END_DECLS - -#endif /* INCLUDE_LIBOPENCM3_PAC55XX_GPIO_H_ */ diff --git a/libopencm3/include/libopencm3/pac55xx/irq.json b/libopencm3/include/libopencm3/pac55xx/irq.json deleted file mode 100644 index a141d80..0000000 --- a/libopencm3/include/libopencm3/pac55xx/irq.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "irqs": [ - "memctl", - "wdt", - "rtc", - "adc0", - "adc1", - "adc2", - "adc3", - "timera", - "timerb", - "timerc", - "timerd", - "timera_qep", - "timerb_qep", - "timerc_qep", - "timerd_qep", - "gpioa", - "gpiob", - "gpioc", - "gpiod", - "gpioe", - "gpiof", - "gpiog", - "i2c", - "usarta", - "usartb", - "usartc", - "usartd", - "can", - "gptimera", - "gptimerb", - "scc" - ], - "partname_humanreadable": "PAC55XX Series", - "partname_doxygen": "PAC55XX", - "includeguard": "LIBOPENCM3_PAC55XX_H_" -} diff --git a/libopencm3/include/libopencm3/pac55xx/memorymap.h b/libopencm3/include/libopencm3/pac55xx/memorymap.h deleted file mode 100644 index bebd132..0000000 --- a/libopencm3/include/libopencm3/pac55xx/memorymap.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @defgroup memorymap Peripheral Memory Map - * - * @ingroup PAC55xx_defines - * @author Brian Viele - * LGPL License Terms @ref lgpl_license - * @date 1 Dec 2019 - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#ifndef INCLUDE_LIBOPENCM3_PAC55XX_MEMORYMAP_H_ -#define INCLUDE_LIBOPENCM3_PAC55XX_MEMORYMAP_H_ - -/**@{*/ - -/** @defgroup address_memory Address Memory Map. -@{*/ -#define FLASH_BASE (0x00000000UL) -#define INFO1_FLASH_BASE (0x00100000UL) -#define INFO2_FLASH_BASE (0x00100400UL) -#define INFO3_FLASH_BASE (0x00100800UL) -#define SRAM_BASE (0x20000000UL) -#define PERIPH_BASE (0x40000000UL) -/**@}*/ -/** @defgroup peripheral_addresses Core Peripheral Memory Map. -@{*/ -#define ADC_BASE (PERIPH_BASE + 0x00000) -#define I2C_BASE (PERIPH_BASE + 0x10000) -#define USARTA_BASE (PERIPH_BASE + 0x20000) -#define USARTB_BASE (PERIPH_BASE + 0x30000) -#define USARTC_BASE (PERIPH_BASE + 0x40000) -#define USARTD_BASE (PERIPH_BASE + 0x50000) -#define TIMERA_BASE (PERIPH_BASE + 0x60000) -#define TIMERB_BASE (PERIPH_BASE + 0x70000) -#define TIMERC_BASE (PERIPH_BASE + 0x80000) -#define TIMERD_BASE (PERIPH_BASE + 0x90000) -#define CAN_BASE (PERIPH_BASE + 0xA0000) -#define GPTIMERA_BASE (PERIPH_BASE + 0xB0000) -#define GPTIMERB_BASE (PERIPH_BASE + 0xC0000) -#define SYS_PERIPH_BASE (PERIPH_BASE + 0xD0000) -/**@}*/ -/** @defgroup system_peripheral_addresses System Peripheral Memory Map. -@{*/ -#define MEMCTL_BASE (SYS_PERIPH_BASE + 0x0000) -#define SCC_BASE (SYS_PERIPH_BASE + 0x0400) -#define WWDT_BASE (SYS_PERIPH_BASE + 0x0800) -#define RTC_BASE (SYS_PERIPH_BASE + 0x0C00) -#define CRC_BASE (SYS_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (SYS_PERIPH_BASE + 0x1400) -#define GPIOB_BASE (SYS_PERIPH_BASE + 0x1800) -#define GPIOC_BASE (SYS_PERIPH_BASE + 0x1C00) -#define GPIOD_BASE (SYS_PERIPH_BASE + 0x2000) -#define GPIOE_BASE (SYS_PERIPH_BASE + 0x2400) -#define GPIOF_BASE (SYS_PERIPH_BASE + 0x2800) -#define GPIOG_BASE (SYS_PERIPH_BASE + 0x2C00) -/**@}*/ -/**@}*/ - -#endif /* INCLUDE_LIBOPENCM3_PAC55XX_MEMORYMAP_H_ */ diff --git a/libopencm3/include/libopencm3/sam/3a/gpio.h b/libopencm3/include/libopencm3/sam/3a/gpio.h deleted file mode 100644 index 852085e..0000000 --- a/libopencm3/include/libopencm3/sam/3a/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3a/irq.json b/libopencm3/include/libopencm3/sam/3a/irq.json deleted file mode 100644 index c3d8c10..0000000 --- a/libopencm3/include/libopencm3/sam/3a/irq.json +++ /dev/null @@ -1,52 +0,0 @@ -{ - "irqs": [ - "supc", - "rstc", - "rtc", - "rtt", - "wdt", - "pmc", - "eefc0", - "eefc1", - "uart", - "smc_sdramc", - "sdramc", - "pioa", - "piob", - "pioc", - "piod", - "pioe", - "piof", - "usart0", - "usart1", - "usart2", - "usart3", - "hsmci", - "twi0", - "twi1", - "spi0", - "spi1", - "ssc", - "tc0", - "tc1", - "tc2", - "tc3", - "tc4", - "tc5", - "tc6", - "tc7", - "tc8", - "pwm", - "adc", - "dacc", - "dmac", - "uotghs", - "trng", - "reserved0", - "can0", - "can1" - ], - "partname_humanreadable": "Atmel SAM3A series", - "partname_doxygen": "SAM3A", - "includeguard": "LIBOPENCM3_SAM3A_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3a/memorymap.h b/libopencm3/include/libopencm3/sam/3a/memorymap.h deleted file mode 100644 index 90d97c6..0000000 --- a/libopencm3/include/libopencm3/sam/3a/memorymap.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3A_MEMORYMAP_H -#define SAM3A_MEMORYMAP_H - -#include - -/* --- SAM3A peripheral space -------------------------------------------- */ -#define HSMCI_BASE (0x40000000U) -#define SSC_BASE (0x40004000U) -#define SPI0_BASE (0x40008000U) -#define SPI1_BASE (0x4000C000U) -#define TC0_BASE (0x40080000U) -#define TC1_BASE (0x40080040U) -#define TC2_BASE (0x40080080U) -#define TC3_BASE (0x40084000U) -#define TC4_BASE (0x40084040U) -#define TC5_BASE (0x40084080U) -#define TC6_BASE (0x40088000U) -#define TC7_BASE (0x40088040U) -#define TC8_BASE (0x40088080U) -#define TWI0_BASE (0x4008C000U) -#define TWI1_BASE (0x40090000U) -#define PWM_BASE (0x40094000U) -#define USART0_BASE (0x40098000U) -#define USART1_BASE (0x4009C000U) -#define USART2_BASE (0x400A0000U) -#define USART3_BASE (0x400A4000U) -#define UOTGHS_BASE (0x400AC000U) -#define CAN0_BASE (0x400B4000U) -#define CAN1_BASE (0x400B8000U) -#define TRNG_BASE (0x400BC000U) -#define ADC_BASE (0x400C0000U) -#define DMAC_BASE (0x400C4000U) -#define DACC_BASE (0x400C8000U) - -/* --- SAM3A system controller space ------------------------------------- */ -#define SMC_BASE (0x400E0000U) -#define SDRAM_BASE (0x400E0200U) -#define MATRIX_BASE (0x400E0400U) -#define PMC_BASE (0x400E0600U) -#define UART_BASE (0x400E0800U) -#define CHIPID_BASE (0x400E0940U) -#define EEFC0_BASE (0x400E0A00U) -#define EEFC1_BASE (0x400E0C00U) -#define PIOA_BASE (0x400E0E00U) -#define PIOB_BASE (0x400E1000U) -#define PIOC_BASE (0x400E1200U) -#define PIOD_BASE (0x400E1400U) -#define PIOE_BASE (0x400E1600U) -#define PIOF_BASE (0x400E1800U) -#define RSTC_BASE (0x400E1A00U) -#define SUPC_BASE (0x400E1A10U) -#define RTT_BASE (0x400E1A30U) -#define WDT_BASE (0x400E1A50U) -#define RTC_BASE (0x400E1A60U) -#define GPBR_BASE (0x400E1A90U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/3a/pio.h b/libopencm3/include/libopencm3/sam/3a/pio.h deleted file mode 100644 index 10fafae..0000000 --- a/libopencm3/include/libopencm3/sam/3a/pio.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PIO_H -#define LIBOPENCM3_PIO_H - -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3a/pmc.h b/libopencm3/include/libopencm3/sam/3a/pmc.h deleted file mode 100644 index 1db09bb..0000000 --- a/libopencm3/include/libopencm3/sam/3a/pmc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PMC_H -#define LIBOPENCM3_PMC_H - -#include -#include -#include -#include - -/* --- Power Management Controller (PMC) registers ------------------------- */ - -/* Peripheral Control Register */ -#define PMC_PCR MMIO32(PMC_BASE + 0x010C) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* PLLA Divide by 2 */ -#define PMC_MCKR_PLLADIV2 (0x01 << 12) - - -/* --- PMC Peripheral Control Register (PMC_PCR) --------------------------- */ - -/* Enable */ -#define PMC_PCR_EN (0x01 << 28) - -/* Divisor Value */ -#define PMC_PCR_DIV_SHIFT 16 -#define PMC_PCR_DIV_MASK (0x03 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x00 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x01 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x02 << PMC_PCR_DIV_SHIFT) - -/* Command */ -#define PMC_PCR_CMD (0x01 << 12) - -/* Peripheral ID */ -#define PMC_PCR_PID_SHIFT 0 -#define PMC_PCR_PID_MASK (0x3F << PMC_PCR_PID_SHIFT) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3n/gpio.h b/libopencm3/include/libopencm3/sam/3n/gpio.h deleted file mode 100644 index bb00ac4..0000000 --- a/libopencm3/include/libopencm3/sam/3n/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3n/irq.json b/libopencm3/include/libopencm3/sam/3n/irq.json deleted file mode 100644 index 9d1d39e..0000000 --- a/libopencm3/include/libopencm3/sam/3n/irq.json +++ /dev/null @@ -1,39 +0,0 @@ -{ - "irqs": [ - "supc", - "rstc", - "rtc", - "rtt", - "wdt", - "pmc", - "eefc", - "reserved0", - "uart0", - "uart1", - "reserved1", - "pioa", - "piob", - "pioc", - "usart0", - "usart1", - "reserved2", - "reserved3", - "reserved4", - "twi0", - "twi1", - "spi", - "reserved5", - "tc0", - "tc1", - "tc2", - "tc3", - "tc4", - "tc5", - "adc", - "dacc", - "pwm" - ], - "partname_humanreadable": "Atmel SAM3N series", - "partname_doxygen": "SAM3N", - "includeguard": "LIBOPENCM3_SAM3N_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3n/memorymap.h b/libopencm3/include/libopencm3/sam/3n/memorymap.h deleted file mode 100644 index 34c193f..0000000 --- a/libopencm3/include/libopencm3/sam/3n/memorymap.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3N_MEMORYMAP_H -#define SAM3N_MEMORYMAP_H - -#include - -/* --- SAM3N peripheral space -------------------------------------------- */ - -#define SPI_BASE (0x40008000U) -#define TC0_BASE (0x40010000U) -#define TC1_BASE (0x40010040U) -#define TC2_BASE (0x40010080U) -#define TC3_BASE (0x40014000U) -#define TC4_BASE (0x40014040U) -#define TC5_BASE (0x40014080U) -#define TWI0_BASE (0x40018000U) -#define TWI1_BASE (0x4001C000U) -#define PWM_BASE (0x40020000U) -#define USART0_BASE (0x40024000U) -#define USART1_BASE (0x40028000U) -#define ADC_BASE (0x40038000U) -#define DACC_BASE (0x4003C000U) - -/* --- SAM3N system controller space ------------------------------------- */ -#define SMC_BASE (0x400E0000U) -#define MATRIX_BASE (0x400E0200U) -#define PMC_BASE (0x400E0400U) -#define UART0_BASE (0x400E0600U) -#define CHIPID_BASE (0x400E0740U) -#define UART1_BASE (0x400E0800U) -#define EEFC_BASE (0x400E0A00U) -#define PIOA_BASE (0x400E0E00U) -#define PIOB_BASE (0x400E1000U) -#define PIOC_BASE (0x400E1200U) -#define RSTC_BASE (0x400E1400U) -#define SUPC_BASE (0x400E1410U) -#define RTT_BASE (0x400E1430U) -#define WDT_BASE (0x400E1450U) -#define RTC_BASE (0x400E1460U) -#define GPBR_BASE (0x400E1490U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/3n/periph.h b/libopencm3/include/libopencm3/sam/3n/periph.h deleted file mode 100644 index ca14059..0000000 --- a/libopencm3/include/libopencm3/sam/3n/periph.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PERIPH_H -#define LIBOPENCM3_PERIPH_H - -/* --- Peripheral Identifiers ---------------------------------------------- */ -#define PERIPH_SUPC 0 -#define PERIPH_RSTC 1 -#define PERIPH_RTC 2 -#define PERIPH_RTT 3 -#define PERIPH_WDG 4 -#define PERIPH_PMC 5 -#define PERIPH_EEFC 6 -#define PERIPH_UART0 8 -#define PERIPH_UART1 9 -#define PERIPH_PIOA 11 -#define PERIPH_PIOB 12 -#define PERIPH_PIOC 13 -#define PERIPH_USART0 14 -#define PERIPH_USART1 15 -#define PERIPH_TWI0 19 -#define PERIPH_TWI1 20 -#define PERIPH_SPI 21 -#define PERIPH_TC0 23 -#define PERIPH_TC1 24 -#define PERIPH_TC2 25 -#define PERIPH_TC3 26 -#define PERIPH_TC4 27 -#define PERIPH_TC5 28 -#define PERIPH_ADC 29 -#define PERIPH_DACC 30 -#define PERIPH_PWM 31 - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3n/pio.h b/libopencm3/include/libopencm3/sam/3n/pio.h deleted file mode 100644 index cf06243..0000000 --- a/libopencm3/include/libopencm3/sam/3n/pio.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PIO_H -#define LIBOPENCM3_PIO_H - -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3n/pmc.h b/libopencm3/include/libopencm3/sam/3n/pmc.h deleted file mode 100644 index bd03e5d..0000000 --- a/libopencm3/include/libopencm3/sam/3n/pmc.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PMC_H -#define LIBOPENCM3_PMC_H - -#include -#include -#include - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* PMC Clock Generator PLL Register */ -#define CKGR_PLLR CKGR_PLLAR - -/* Oscillator Calibration Register */ -#define PMC_OCR MMIO32(PMC_BASE + 0x0110) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */ - -/* Wait Mode Command */ -#define CKGR_MOR_WAITMODE (0x01 << 2) - - -/* --- PMC Clock Generator PLL Register (CKGR_PLLR) ---------------------- */ -/* CKGR_PLLAR on all other device subfamilies */ - -/* must be set to program CKGR_PLLR */ -#define CKGR_PLLR_ONE CKGR_PLLAR_ONE - -/* PLLA Multiplier */ -#define CKGR_PLLR_MUL_SHIFT CKGR_PLLAR_MULA_SHIFT -#define CKGR_PLLR_MUL_MASK CKGR_PLLAR_MULA_MASK - -/* PLLA Counter */ -#define CKGR_PLLR_PLLCOUNT_SHIFT CKGR_PLLAR_PLLACOUNT_SHIFT -#define CKGR_PLLR_PLLCOUNT_MASK CKGR_PLLAR_PLLACOUNT_MASK - -/* Divider */ -#define CKGR_PLLR_DIV_SHIFT CKGR_PLLAR_DIVA_SHIFT -#define CKGR_PLLR_DIV_MASK CKGR_PLLAR_DIVA_MASK - - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* PLL Divide by 2 */ -#define PMC_MCKR_PLLDIV2 (0x01 << 12) - -/* Master Clock Source Selection */ -#define PMC_MCKR_CSS_PLL_CLK (2 << PMC_MCKR_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK0_CSS_PLL_CLK (2 << PMC_PCK0_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK1_CSS_PLL_CLK (2 << PMC_PCK1_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK2_CSS_PLL_CLK (2 << PMC_PCK2_CSS_SHIFT) - - -/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */ - -/* PLL Lock Interrupt Enable */ -#define PMC_IER_LOCK PMC_IER_LOCKA - - -/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */ - -/* PLL Lock Interrupt Disable */ -#define PMC_IDR_LOCK PMC_IDR_LOCKA - - -/* --- PMC Status Register (PMC_SR) ---------------------------------------- */ - -/* PLL Lock Status */ -#define PMC_SR_LOCK PMC_SR_LOCKA - - -/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */ - -/* PLL Lock Interrupt Mask */ -#define PMC_IMR_LOCK PMC_IMR_LOCKA - - -/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */ - -/* Selection of RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x01 << 23) - -/* RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_CAL12_SHIFT 16 -#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT) - -/* Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x01 << 15) - -/* RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL8_SHIFT 8 -#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT) - -/* Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x01 << 7) - -/* RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL4_SHIFT 0 -#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/gpio.h b/libopencm3/include/libopencm3/sam/3s/gpio.h deleted file mode 100644 index bb00ac4..0000000 --- a/libopencm3/include/libopencm3/sam/3s/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/irq.json b/libopencm3/include/libopencm3/sam/3s/irq.json deleted file mode 100644 index ddf76f6..0000000 --- a/libopencm3/include/libopencm3/sam/3s/irq.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "irqs": [ - "supc", - "rstc", - "rtc", - "rtt", - "wdt", - "pmc", - "eefc", - "reserved0", - "uart0", - "uart1", - "smc", - "pioa", - "piob", - "pioc", - "usart0", - "usart1", - "usart2", - "reserved1", - "hsmci", - "twi0", - "twi1", - "spi", - "ssc", - "tc0", - "tc1", - "tc2", - "tc3", - "tc4", - "tc5", - "adc", - "dacc", - "pwm", - "crccu", - "acc", - "udp" - ], - "partname_humanreadable": "Atmel SAM3S series", - "partname_doxygen": "SAM3S", - "includeguard": "LIBOPENCM3_SAM3S_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3s/memorymap.h b/libopencm3/include/libopencm3/sam/3s/memorymap.h deleted file mode 100644 index 0ce7200..0000000 --- a/libopencm3/include/libopencm3/sam/3s/memorymap.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3S_MEMORYMAP_H -#define SAM3S_MEMORYMAP_H - -#include - -/* --- SAM3S peripheral space -------------------------------------------- */ -#define HSMCI_BASE (0x40000000U) -#define SSC_BASE (0x40004000U) -#define SPI_BASE (0x40008000U) -#define TC0_BASE (0x40010000U) -#define TC1_BASE (0x40010040U) -#define TC2_BASE (0x40010080U) -#define TC3_BASE (0x40014000U) -#define TC4_BASE (0x40014040U) -#define TC5_BASE (0x40014080U) -#define TWI0_BASE (0x40018000U) -#define TWI1_BASE (0x4001C000U) -#define PWM_BASE (0x40020000U) -#define USART0_BASE (0x40024000U) -#define USART1_BASE (0x40028000U) -#define USART2_BASE (0x4002C000U) -#define UDP_BASE (0x40034000U) -#define ADC_BASE (0x40038000U) -#define DACC_BASE (0x4003C000U) -#define ACC_BASE (0x40040000U) -#define CRCCU_BASE (0x40044000U) - -/* --- SAM3S system controller space ------------------------------------- */ -#define SMC_BASE (0x400E0000U) -#define MATRIX_BASE (0x400E0200U) -#define PMC_BASE (0x400E0400U) -#define UART0_BASE (0x400E0600U) -#define CHIPID_BASE (0x400E0740U) -#define UART1_BASE (0x400E0800U) -#define EEFC_BASE (0x400E0A00U) -#define PIOA_BASE (0x400E0E00U) -#define PIOB_BASE (0x400E1000U) -#define PIOC_BASE (0x400E1200U) -#define RSTC_BASE (0x400E1400U) -#define SUPC_BASE (0x400E1410U) -#define RTT_BASE (0x400E1430U) -#define WDT_BASE (0x400E1450U) -#define RTC_BASE (0x400E1460U) -#define GPBR_BASE (0x400E1490U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/periph.h b/libopencm3/include/libopencm3/sam/3s/periph.h deleted file mode 100644 index fb0ee5c..0000000 --- a/libopencm3/include/libopencm3/sam/3s/periph.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PERIPH_H -#define LIBOPENCM3_PERIPH_H - -/* --- Peripheral Identifiers ---------------------------------------------- */ -#define PERIPH_SUPC 0 -#define PERIPH_RSTC 1 -#define PERIPH_RTC 2 -#define PERIPH_RTT 3 -#define PERIPH_WDG 4 -#define PERIPH_PMC 5 -#define PERIPH_EEFC 6 -#define PERIPH_UART0 8 -#define PERIPH_UART1 9 -#define PERIPH_SMC 10 -#define PERIPH_PIOA 11 -#define PERIPH_PIOB 12 -#define PERIPH_PIOC 13 -#define PERIPH_USART0 14 -#define PERIPH_USART1 15 -#define PERIPH_USART2 16 -#define PERIPH_HSMCI 18 -#define PERIPH_TWI0 19 -#define PERIPH_TWI1 20 -#define PERIPH_SPI 21 -#define PERIPH_SSC 22 -#define PERIPH_TC0 23 -#define PERIPH_TC1 24 -#define PERIPH_TC2 25 -#define PERIPH_TC3 26 -#define PERIPH_TC4 27 -#define PERIPH_TC5 28 -#define PERIPH_ADC 29 -#define PERIPH_DACC 30 -#define PERIPH_PWM 31 -#define PERIPH_CRCCU 32 -#define PERIPH_ACC 33 -#define PERIPH_UDP 34 - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/pio.h b/libopencm3/include/libopencm3/sam/3s/pio.h deleted file mode 100644 index a559f50..0000000 --- a/libopencm3/include/libopencm3/sam/3s/pio.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PIO_H -#define LIBOPENCM3_PIO_H - -#include -#include - -/* --- PIO registers ----------------------------------------------------- */ - -/* Parallel Capture Mode Register */ -#define PIO_PCMR(port) MMIO32((port) + 0x0150) - -/* Parallel Capture Interrupt Enable Register */ -#define PIO_PCIER(port) MMIO32((port) + 0x0154) - -/* Parallel Capture Interrupt Disable Register */ -#define PIO_PCIDR(port) MMIO32((port) + 0x0158) - -/* Parallel Capture Interrupt Mask Register */ -#define PIO_PCIMR(port) MMIO32((port) + 0x015C) - -/* Parallel Capture Interrupt Status Register */ -#define PIO_PCISR(port) MMIO32((port) + 0x0160) - -/* Parallel Capture Reception Holding Register */ -#define PIO_PCRHR(port) MMIO32((port) + 0x0164) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/pmc.h b/libopencm3/include/libopencm3/sam/3s/pmc.h deleted file mode 100644 index 5f0e061..0000000 --- a/libopencm3/include/libopencm3/sam/3s/pmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PMC_H -#define LIBOPENCM3_PMC_H - -#include -#include -#include - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* PLLB Register */ -#define CKGR_PLLBR MMIO32(PMC_BASE + 0x002C) - -/* Oscillator Calibration Register */ -#define PMC_OCR MMIO32(PMC_BASE + 0x0110) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */ - -/* RC Oscillator Frequency Measure (write-only, only on atsam3s8) */ -#define CKGR_MCFR_RCMEAS (0x01 << 20) - - -/* --- PMC Clock Generator PLLB Register (CKGR_PLLBR) ---------------------- */ - -/* PLLB Multiplier */ -#define CKGR_PLLBR_MULB_SHIFT 16 -#define CKGR_PLLBR_MULB_MASK (0x7FF << CKGR_PLLBR_MULB_SHIFT) - -/* PLLA Counter */ -#define CKGR_PLLBR_PLLBCOUNT_SHIFT 8 -#define CKGR_PLLBR_PLLBCOUNT_MASK (0x3F << CKGR_PLLBR_PLLBCOUNT_SHIFT) - -/* Divider */ -#define CKGR_PLLBR_DIVB_SHIFT 0 -#define CKGR_PLLBR_DIVB_MASK (0xFF << CKGR_PLLBR_DIVB_SHIFT) - - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* PLLB Divide by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x01 << 13) - -/* PLLA Divide by 2 */ -#define PMC_MCKR_PLLADIV2 (0x01 << 12) - -/* Master Clock Source Selection */ -#define PMC_MCKR_CSS_PLLB_CLK (3 << PMC_MCKR_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK0_CSS_PLLB_CLK (3 << PMC_PCK0_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK1_CSS_PLLB_CLK (3 << PMC_PCK1_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK2_CSS_PLLB_CLK (3 << PMC_PCK2_CSS_SHIFT) - - -/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */ - -/* PLLB Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x01 << 2) - - -/* --- PMC Interrupt Disable Register (PMC_IDR) ---------------------------- */ - -/* PLLB Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x01 << 2) - - -/* --- PMC Status Register (PMC_SR) ---------------------------------------- */ - -/* PLLB Lock Status */ -#define PMC_SR_LOCKB (0x01 << 2) - - -/* --- PMC Interrupt Mask Register (PMC_IDR) ------------------------------- */ - -/* PLLB Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x01 << 2) - - -/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */ - -/* Selection of RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x01 << 23) - -/* RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_CAL12_SHIFT 16 -#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT) - -/* Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x01 << 15) - -/* RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL8_SHIFT 8 -#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT) - -/* Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x01 << 7) - -/* RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL4_SHIFT 0 -#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3s/smc.h b/libopencm3/include/libopencm3/sam/3s/smc.h deleted file mode 100644 index 53cbeae..0000000 --- a/libopencm3/include/libopencm3/sam/3s/smc.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SMC_H -#define LIBOPENCM3_SMC_H - -#include - - -/* Chip Select Defines */ -#define SMC_CS_0 0 -#define SMC_CS_1 1 -#define SMC_CS_2 2 -#define SMC_CS_3 3 - - -/* --- Static Memory Controller (SMC) registers ---------------------------- */ - -/* Setup Register */ -#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \ - + 0x00) - -/* Pulse Register */ -#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \ - + 0x04) - -/* Cycle Register */ -#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \ - + 0x08) - -/* Mode Register */ -#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \ - + 0x0C) - -/* Off Chip Memory Scrambling Mode Register */ -#define SMC_OCMS MMIO32(SMC_BASE + 0x80) - -/* Off Chip Memory Scrambling KEY1 Register */ -#define SMC_KEY1 MMIO32(SMC_BASE + 0x84) - -/* Off Chip Memory Scrambling KEY2 Register */ -#define SMC_KEY2 MMIO32(SMC_BASE + 0x88) - -/* Write Protect Mode Register */ -#define SMC_WPMR MMIO32(SMC_BASE + 0xE4) - -/* Write Protect Status Register */ -#define SMC_WPSR MMIO32(SMC_BASE + 0xE8) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- SMC Setup Register (SMC_SETUPx) ------------------------------------- */ - -/* NCS Setup length in Read access */ -#define SMC_SETUP_NCS_RD_SETUP_SHIFT 24 -#define SMC_SETUP_NCS_RD_SETUP_MASK (0x3F << SMC_SETUP_NCS_RD_SETUP_SHIFT) - -/* NRD Setup length */ -#define SMC_SETUP_NRD_SETUP_SHIFT 16 -#define SMC_SETUP_NRD_SETUP_MASK (0x3F << SMC_SETUP_NRD_SETUP_SHIFT) - -/* NCS Setup length in Write access */ -#define SMC_SETUP_NCS_WR_SETUP_SHIFT 8 -#define SMC_SETUP_NCS_WR_SETUP_MASK (0x3F << SMC_SETUP_NCS_WR_SETUP_SHIFT) - -/* NWE Setup Length */ -#define SMC_SETUP_NWE_SETUP_SHIFT 0 -#define SMC_SETUP_NWE_SETUP_MASK (0x3F << SMC_SETUP_NWE_SETUP_SHIFT) - - -/* --- SMC Pulse Register (SMC_PULSEx) ------------------------------------- */ - -/* NCS Pulse Length in READ Access */ -#define SMC_PULSE_NCS_RD_PULSE_SHIFT 24 -#define SMC_PULSE_NCS_RD_PULSE_MASK (0x7F << SMC_PULSE_NCS_RD_PULSE_SHIFT) - -/* NRD Pulse Length */ -#define SMC_PULSE_NRD_PULSE_SHIFT 16 -#define SMC_PULSE_NRD_PULSE_MASK (0x7F << SMC_PULSE_NRD_PULSE_SHIFT) - -/* NCS Pulse Length in WRITE Access */ -#define SMC_PULSE_NCS_WR_PULSE_SHIFT 8 -#define SMC_PULSE_NCS_WR_PULSE_MASK (0x7F << SMC_PULSE_NCS_WR_PULSE_SHIFT) - -/* NWE Pulse Length */ -#define SMC_PULSE_NWE_PULSE_SHIFT 0 -#define SMC_PULSE_NWE_PULSE_MASK (0x7F << SMC_PULSE_NWE_PULSE_SHIFT) - - -/* --- SMC Cycle Register (SMC_CYCLEx) ------------------------------------- */ - -/* Total Read Cycle Length */ -#define SMC_CYCLE_NRD_CYCLE_SHIFT 16 -#define SMC_CYCLE_NRD_CYCLE_MASK (0x1FF << SMC_CYCLE_NRD_CYCLE_SHIFT) - -/* Total Write Cycle Length */ -#define SMC_CYCLE_NWE_CYCLE_SHIFT 0 -#define SMC_CYCLE_NWE_CYCLE_MASK (0x1FF << SMC_CYCLE_NWE_CYCLE_SHIFT) - - -/* --- SMC MODE Register (SMC_MODEx) --------------------------------------- */ - -/* Page Size */ -#define SMC_MODE_PS_SHIFT 28 -#define SMC_MODE_PS_MASK (0x03 << SMC_MODE_PS_SHIFT) - -/* Page Size Values */ -#define SMC_MODE_PS_4_BYTE (0x00 << SMC_MODE_PS_SHIFT) -#define SMC_MODE_PS_8_BYTE (0x01 << SMC_MODE_PS_SHIFT) -#define SMC_MODE_PS_16_BYTE (0x02 << SMC_MODE_PS_SHIFT) -#define SMC_MODE_PS_32_BYTE (0x03 << SMC_MODE_PS_SHIFT) - -/* Page Mode Enabled */ -#define SMC_MODE_PMEN (1 << 24) - -/* TDF Optimization */ -#define SMC_MODE_TDF_MODE (1 << 20) - -/* Data Float Time */ -#define SMC_MODE_TDF_CYCLES_SHIFT 16 -#define SMC_MODE_TDF_CYCLES_MASK (0x0F << SMC_MODE_TDF_CYCLES_SHIFT) - -/* Data Bus Width */ -#define SMC_MODE_DBW_SHIFT 12 -#define SMC_MODE_DBW_MASK (0x03 << SMC_MODE_DBW_SHIFT) - -/* Data Bus Width Values */ -#define SMC_MODE_DBW_8_BIT (0x00 << SMC_MODE_DBW_SHIFT) -#define SMC_MODE_DBW_16_BIT (0x01 << SMC_MODE_DBW_SHIFT) -#define SMC_MODE_DBW_32_BIT (0x02 << SMC_MODE_DBW_SHIFT) - -/* NWAIT Mode */ -#define SMC_MODE_EXNW_MODE_SHIFT 4 -#define SMC_MODE_EXNW_MODE_MASK (0x03 << SMC_MODE_EXNW_MODE_SHIFT) - -/* NWAIT Mode Values */ -#define SMC_MODE_EXNW_MODE_DISABLED (0x00 << SMC_MODE_EXNW_MODE_SHIFT) -#define SMC_MODE_EXNW_MODE_FROZEN (0x02 << SMC_MODE_EXNW_MODE_SHIFT) -#define SMC_MODE_EXNW_MODE_READY (0x03 << SMC_MODE_EXNW_MODE_SHIFT) - -/* Write Mode */ -#define SMC_MODE_WRITE_MODE (1 << 1) - -/* Read Mode */ -#define SMC_MODE_READ_MODE (1 << 0) - - -/* --- SMC OCMS Mode Register (SMC_OCMS) ----------------------------------- */ - -/* Chip Select 3 Scrambling Enable */ -#define SMC_OCMS_CS3SE (1 << 19) - -/* Chip Select 2 Scrambling Enable */ -#define SMC_OCMS_CS2SE (1 << 18) - -/* Chip Select 1 Scrambling Enable */ -#define SMC_OCMS_CS1SE (1 << 17) - -/* Chip Select 0 Scrambling Enable */ -#define SMC_OCMS_CS0SE (1 << 16) - -/* Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SMSE (1 << 0) - - -/* --- SMC Write Protect Mode Register (SMC_WPMR) -------------------------- */ - -/* Write Protect Key */ -#define SMC_WPMR_WPKEY_SHIFT 8 -#define SMC_WPMR_WPKEY_KEY (0x534D43 << SMC_WPMR_WPKEY_SHIFT) - -/* Write Protect Enable */ -#define SMC_WPMR_WPEN (1 << 0) - - -/* --- SMC Write Protect Status Register (SMC_WPSR) ------------------------ */ - -/* Write Protection Violation Source */ -#define SMC_WPSR_WP_VSRC_SHIFT 8 -#define SMC_WPSR_WP_VSRC_MASK (0xFFFF << SMC_WPSR_WP_VSRC_SHIFT) - -/* Write Protect Enable */ -#define SMC_WPSR_WPVS (1 << 0) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3u/gpio.h b/libopencm3/include/libopencm3/sam/3u/gpio.h deleted file mode 100644 index 852085e..0000000 --- a/libopencm3/include/libopencm3/sam/3u/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3u/irq.json b/libopencm3/include/libopencm3/sam/3u/irq.json deleted file mode 100644 index c52f183..0000000 --- a/libopencm3/include/libopencm3/sam/3u/irq.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "irqs": [ - "supc", - "rstc", - "rtc", - "rtt", - "wdt", - "pmc", - "eefc0", - "eefc1", - "uart", - "smc", - "pioa", - "piob", - "pioc", - "usart0", - "usart1", - "usart2", - "usart3", - "hsmci", - "twi0", - "twi1", - "spi", - "ssc", - "tc0", - "tc1", - "tc2", - "pwm", - "adc12b", - "adc", - "dmac", - "udphs" - ], - "partname_humanreadable": "Atmel SAM3U series", - "partname_doxygen": "SAM3U", - "includeguard": "LIBOPENCM3_SAM3U_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3u/memorymap.h b/libopencm3/include/libopencm3/sam/3u/memorymap.h deleted file mode 100644 index edd2f29..0000000 --- a/libopencm3/include/libopencm3/sam/3u/memorymap.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3U_MEMORYMAP_H -#define SAM3U_MEMORYMAP_H - -#include - -/* --- SAM3U peripheral space -------------------------------------------- */ -#define HSMCI_BASE (0x40000000U) -#define SSC_BASE (0x40004000U) -#define SPI_BASE (0x40008000U) -#define TC0_BASE (0x40080000U) -#define TC1_BASE (0x40080040U) -#define TC2_BASE (0x40080080U) -#define TWI0_BASE (0x40084000U) -#define TWI1_BASE (0x40088000U) -#define PWM_BASE (0x4008C000U) -#define USART0_BASE (0x40090000U) -#define USART1_BASE (0x40094000U) -#define USART2_BASE (0x40098000U) -#define USART3_BASE (0x4009C000U) -#define UDPHS_BASE (0x400A4000U) -#define ADC12B_BASE (0x400A8000U) -#define ADC_BASE (0x400AC000U) -#define DMAC_BASE (0x400B0000U) - -/* --- SAM3U system controller space ------------------------------------- */ -#define SMC_BASE (0x400E0000U) -#define MATRIX_BASE (0x400E0200U) -#define PMC_BASE (0x400E0400U) -#define UART_BASE (0x400E0600U) -#define CHIPID_BASE (0x400E0740U) -#define EEFC0_BASE (0x400E0800U) -#define EEFC1_BASE (0x400E0A00U) -#define PIOA_BASE (0x400E0C00U) -#define PIOB_BASE (0x400E0E00U) -#define PIOC_BASE (0x400E1000U) -#define RSTC_BASE (0x400E1200U) -#define SUPC_BASE (0x400E1210U) -#define RTT_BASE (0x400E1230U) -#define WDT_BASE (0x400E1250U) -#define RTC_BASE (0x400E1260U) -#define GPBR_BASE (0x400E1290U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/3u/periph.h b/libopencm3/include/libopencm3/sam/3u/periph.h deleted file mode 100644 index 507f18b..0000000 --- a/libopencm3/include/libopencm3/sam/3u/periph.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PERIPH_H -#define LIBOPENCM3_PERIPH_H - -/* --- Peripheral Identifiers ---------------------------------------------- */ -#define PERIPH_SUPC 0 -#define PERIPH_RSTC 1 -#define PERIPH_RTC 2 -#define PERIPH_RTT 3 -#define PERIPH_WDG 4 -#define PERIPH_PMC 5 -#define PERIPH_EEFC0 6 -#define PERIPH_EEFC1 7 -#define PERIPH_UART 8 -#define PERIPH_SMC 9 -#define PERIPH_PIOA 10 -#define PERIPH_PIOB 11 -#define PERIPH_PIOC 12 -#define PERIPH_USART0 13 -#define PERIPH_USART1 14 -#define PERIPH_USART2 15 -#define PERIPH_USART3 16 -#define PERIPH_HSMCI 17 -#define PERIPH_TWI0 18 -#define PERIPH_TWI1 19 -#define PERIPH_SPI 20 -#define PERIPH_SSC 21 -#define PERIPH_TC0 22 -#define PERIPH_TC1 23 -#define PERIPH_TC2 24 -#define PERIPH_PWM 25 -#define PERIPH_ADC12B 26 -#define PERIPH_ADC 27 -#define PERIPH_DMAC 28 -#define PERIPH_UDPHS 29 - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3u/pio.h b/libopencm3/include/libopencm3/sam/3u/pio.h deleted file mode 100644 index 10fafae..0000000 --- a/libopencm3/include/libopencm3/sam/3u/pio.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PIO_H -#define LIBOPENCM3_PIO_H - -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3u/pmc.h b/libopencm3/include/libopencm3/sam/3u/pmc.h deleted file mode 100644 index 888bfb1..0000000 --- a/libopencm3/include/libopencm3/sam/3u/pmc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PMC_H -#define LIBOPENCM3_PMC_H - -#include -#include -#include -#include - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */ - -/* Wait Mode Command */ -#define CKGR_MOR_WAITMODE (0x01 << 2) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3x/gpio.h b/libopencm3/include/libopencm3/sam/3x/gpio.h deleted file mode 100644 index 852085e..0000000 --- a/libopencm3/include/libopencm3/sam/3x/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3x/irq.json b/libopencm3/include/libopencm3/sam/3x/irq.json deleted file mode 100644 index c53d63c..0000000 --- a/libopencm3/include/libopencm3/sam/3x/irq.json +++ /dev/null @@ -1,52 +0,0 @@ -{ - "irqs": [ - "supc", - "rstc", - "rtc", - "rtt", - "wdt", - "pmc", - "eefc0", - "eefc1", - "uart", - "smc_sdramc", - "sdramc", - "pioa", - "piob", - "pioc", - "piod", - "pioe", - "piof", - "usart0", - "usart1", - "usart2", - "usart3", - "hsmci", - "twi0", - "twi1", - "spi0", - "spi1", - "ssc", - "tc0", - "tc1", - "tc2", - "tc3", - "tc4", - "tc5", - "tc6", - "tc7", - "tc8", - "pwm", - "adc", - "dacc", - "dmac", - "uotghs", - "trng", - "emac", - "can0", - "can1" - ], - "partname_humanreadable": "Atmel SAM3X series", - "partname_doxygen": "SAM3X", - "includeguard": "LIBOPENCM3_SAM3X_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3x/memorymap.h b/libopencm3/include/libopencm3/sam/3x/memorymap.h deleted file mode 100644 index dea04bb..0000000 --- a/libopencm3/include/libopencm3/sam/3x/memorymap.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_MEMORYMAP_H -#define SAM3X_MEMORYMAP_H - -#include - -/* --- SAM3X peripheral space -------------------------------------------- */ - -#define HSMCI_BASE (0x40000000U) -#define SSC_BASE (0x40004000U) -#define SPI0_BASE (0x40008000U) -#define SPI1_BASE (0x4000C000U) -#define TC0_BASE (0x40080000U) -#define TC1_BASE (0x40080040U) -#define TC2_BASE (0x40080080U) -#define TC3_BASE (0x40084000U) -#define TC4_BASE (0x40084040U) -#define TC5_BASE (0x40084080U) -#define TC6_BASE (0x40088000U) -#define TC7_BASE (0x40088040U) -#define TC8_BASE (0x40088080U) -#define TWI0_BASE (0x4008C000U) -#define TWI1_BASE (0x40090000U) -#define PWM_BASE (0x40094000U) -#define USART0_BASE (0x40098000U) -#define USART1_BASE (0x4009C000U) -#define USART2_BASE (0x400A0000U) -#define USART3_BASE (0x400A4000U) -#define UOTGHS_BASE (0x400AC000U) -#define EMAC_BASE (0x400B0000U) -#define CAN0_BASE (0x400B4000U) -#define CAN1_BASE (0x400B8000U) -#define TRNG_BASE (0x400BC000U) -#define ADC_BASE (0x400C0000U) -#define DMAC_BASE (0x400C4000U) -#define DACC_BASE (0x400C8000U) - -/* --- SAM3X system controller space ------------------------------------- */ -#define SMC_BASE (0x400E0000U) -#define SDRAM_BASE (0x400E0200U) -#define MATRIX_BASE (0x400E0400U) -#define PMC_BASE (0x400E0600U) -#define UART_BASE (0x400E0800U) -#define CHIPID_BASE (0x400E0940U) -#define EEFC0_BASE (0x400E0A00U) -#define EEFC1_BASE (0x400E0C00U) -#define PIOA_BASE (0x400E0E00U) -#define PIOB_BASE (0x400E1000U) -#define PIOC_BASE (0x400E1200U) -#define PIOD_BASE (0x400E1400U) -#define PIOE_BASE (0x400E1600U) -#define PIOF_BASE (0x400E1800U) -#define RSTC_BASE (0x400E1A00U) -#define SUPC_BASE (0x400E1A10U) -#define RTT_BASE (0x400E1A30U) -#define WDT_BASE (0x400E1A50U) -#define RTC_BASE (0x400E1A60U) -#define GPBR_BASE (0x400E1A90U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/3x/pio.h b/libopencm3/include/libopencm3/sam/3x/pio.h deleted file mode 100644 index 10fafae..0000000 --- a/libopencm3/include/libopencm3/sam/3x/pio.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PIO_H -#define LIBOPENCM3_PIO_H - -#include -#include - - -#endif diff --git a/libopencm3/include/libopencm3/sam/3x/pmc.h b/libopencm3/include/libopencm3/sam/3x/pmc.h deleted file mode 100644 index e11b554..0000000 --- a/libopencm3/include/libopencm3/sam/3x/pmc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PMC_H -#define LIBOPENCM3_PMC_H - -#include -#include -#include -#include - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* Peripheral Control Register */ -#define PMC_PCR MMIO32(PMC_BASE + 0x010C) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* PLLA Divide by 2 */ -#define PMC_MCKR_PLLADIV2 (0x01 << 12) - - -/* --- PMC Peripheral Control Register (PMC_PCR) --------------------------- */ - -/* Enable */ -#define PMC_PCR_EN (0x01 << 28) - -/* Divisor Value */ -#define PMC_PCR_DIV_SHIFT 16 -#define PMC_PCR_DIV_MASK (0x03 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x00 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x01 << PMC_PCR_DIV_SHIFT) -#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x02 << PMC_PCR_DIV_SHIFT) - -/* Command */ -#define PMC_PCR_CMD (0x01 << 12) - -/* Peripheral ID */ -#define PMC_PCR_PID_SHIFT 0 -#define PMC_PCR_PID_MASK (0x3F << PMC_PCR_PID_SHIFT) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/4l/adcife.h b/libopencm3/include/libopencm3/sam/4l/adcife.h deleted file mode 100644 index c0cfb5d..0000000 --- a/libopencm3/include/libopencm3/sam/4l/adcife.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SAM4L_ADCIFE_H -#define LIBOPENCM3_SAM4L_ADCIFE_H - -#include - - -/* Analog to Digital Converter Interface (ADCIFE) registers. */ - -/* 0x0000 Control Register CR Write-Only 0x00000000 */ -#define ADCIFE_CR MMIO32(ADCIFE_BASE + 0x0000) - -/* 0x0004 Configuration Register CFG Read/Write 0x00000000 */ -#define ADCIFE_CFG MMIO32(ADCIFE_BASE + 0x0004) - -/* 0x0008 Status Register SR Read-Only 0x00000000 */ -#define ADCIFE_SR MMIO32(ADCIFE_BASE + 0x008) - -/* 0x000C Status Clear Register SCR Write-Only 0x00000000 */ -#define ADCIFE_SCR MMIO32(ADCIFE_BASE + 0x000C) - -/* 0x0014 Sequencer Configuration Register SEQCFG Read/Write 0x00000000 */ -#define ADCIFE_SEQCFG MMIO32(ADCIFE_BASE + 0x0014) - -/* 0x0018 Configuration Direct Memory Access Register CDMA Write-Only 0x00000000 */ -#define ADCIFE_CDMA MMIO32(ADCIFE_BASE + 0x0018) - -/* 0x001C Timing Configuration Register TIM Read/Write 0x00000000 */ -#define ADCIFE_TIM MMIO32(ADCIFE_BASE + 0x001C) - -/* 0x0020 Internal Timer Register ITIMER Read/Write 0x00000000 */ -#define ADCIFE_ITIMER MMIO32(ADCIFE_BASE + 0x0020) - -/* 0x0024 Window Monitor Configuration Register WCFG Read/Write 0x00000000 */ -#define ADCIFE_WCFG MMIO32(ADCIFE_BASE + 0x0024) - -/* 0x0028 Window Monitor Threshold Configuration Register WTH Read/Write 0x00000000 */ -#define ADCIFE_WTH MMIO32(ADCIFE_BASE + 0x0028) - -/* 0x002C Sequencer Last Converted Value Register LCV Read-Only 0x00000000 */ -#define ADCIFE_LCV MMIO32(ADCIFE_BASE + 0x002C) - -/* 0x0030 Interrupt Enable Register IER Write-Only 0x00000000 */ -#define ADCIFE_IER MMIO32(ADCIFE_BASE + 0x0030) - -/* 0x0034 Interrupt Disable Register IDR Write-Only 0x00000000 */ -#define ADCIFE_IDR MMIO32(ADCIFE_BASE + 0x0034) - -/* 0x0038 Interrupt Mask Register IMR Read-Only 0x00000000 */ -#define ADCIFE_IMR MMIO32(ADCIFE_BASE + 0x0038) - -/* 0x003C Calibration Register CALIB Read/Write 0x00000000 */ -#define ADCIFE_CALIB MMIO32(ADCIFE_BASE + 0x003C) - -/* 0x0040 Version Register VERSION Read-Only - */ -#define ADCIFE_VERSION MMIO32(ADCIFE_BASE + 0x0040) - -/* 0x0044 Parameter Register PARAMETER Read-Only - */ -#define ADCIFE_PARAMETER MMIO32(ADCIFE_BASE + 0x0044) - - -/* --------- Register Contents --------------------------- */ -#define ADCIFE_CR_SWRST (1 << 0) -#define ADCIFE_CR_TSTOP (1 << 1) -#define ADCIFE_CR_TSTART (1 << 2) -#define ADCIFE_CR_STRIG (1 << 3) -#define ADCIFE_CR_REFBUFEN (1 << 4) -#define ADCIFE_CR_REFBUFDIS (1 << 5) -#define ADCIFE_CR_EN (1 << 8) -#define ADCIFE_CR_DIS (1 << 9) -#define ADCIFE_CR_BGREQEN (1 << 10) -#define ADCIFE_CR_BGREQDIS (1 << 11) - -#define _MASKED_VALUE(V, S, M) (((V) << (S)) & (M)) - -#define ADCIFE_CFG_REFSEL_SHIFT (1) -#define ADCIFE_CFG_REFSEL_MASK (7 << ADCIFE_CFG_REFSEL_SHIFT) -#define ADCIFE_CFG_REFSEL_MASKED(V) _MASKED_VALUE((V), ADCIFE_CFG_REFSEL_SHIFT, ADCIFE_CFG_REFSEL_MASK) -#define ADCIFE_CFG_SPEED_SHIFT (4) -#define ADCIFE_CFG_SPEED_MASK (3 << ADCIFE_CFG_SPEED_SHIFT) -#define ADCIFE_CFG_SPEED_MASKED(V) _MASKED_VALUE((V), ADCIFE_CFG_SPEED_SHIFT, ADCIFE_CFG_SPEED_MASK) -#define ADCIFE_CFG_CLKSEL (1 << 6) -#define ADCIFE_CFG_PRESCAL_SHIFT (8) -#define ADCIFE_CFG_PRESCAL_MASK (3 << ADCIFE_CFG_PRESCAL_SHIFT) -#define ADCIFE_CFG_PRESCAL_MASKED(V) _MASKED_VALUE((V), ADCIFE_CFG_PRESCAL_SHIFT, ADCIFE_CFG_PRESCAL_MASK) - -#define ADCIFE_SR_SEOC (1 << 0) -#define ADCIFE_SR_LOVR (1 << 1) -#define ADCIFE_SR_WM (1 << 2) -#define ADCIFE_SR_SMTRG (1 << 3) -#define ADCIFE_SR_TTO (1 << 5) -#define ADCIFE_SR_EN (1 << 24) -#define ADCIFE_SR_TBUSY (1 << 25) -#define ADCIFE_SR_SBUSY (1 << 26) -#define ADCIFE_SR_CBUSY (1 << 27) -#define ADCIFE_SR_REFBUF (1 << 28) -#define ADCIFE_SR_BGREQ (1 << 30) - -#define ADCIFE_IR_SEOC (1 << 0) -#define ADCIFE_IR_LOVR (1 << 1) -#define ADCIFE_IR_WM (1 << 2) -#define ADCIFE_IR_SMTRG (1 << 3) -#define ADCIFE_IR_TTO (1 << 5) - -#define ADCIFE_SEQCFG_HWLA (1 << 0) -#define ADCIFE_SEQCFG_BIPOLAR (1 << 2) -#define ADCIFE_SEQCFG_GAIN_SHIFT (4) -#define ADCIFE_SEQCFG_GAIN_MASK (7 << ADCIFE_SEQCFG_GAIN_SHIFT) -#define ADCIFE_SEQCFG_GAIN_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_GAIN_SHIFT, ADCIFE_SEQCFG_GAIN_MASK) -#define ADCIFE_SEQCFG_GCOMP (1 << 7) -#define ADCIFE_SEQCFG_TRGSEL_SHIFT (8) -#define ADCIFE_SEQCFG_TRGSEL_MASK (7 << ADCIFE_SEQCFG_TRGSEL_SHIFT) -#define ADCIFE_SEQCFG_TRGSEL_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_TRGSEL_SHIFT, ADCIFE_SEQCFG_TRGSEL_MASK) -#define ADCIFE_SEQCFG_RES (1 << 12) -#define ADCIFE_SEQCFG_INTERNAL_SHIFT (14) -#define ADCIFE_SEQCFG_INTERNAL_MASK (3 << ADCIFE_SEQCFG_INTERNAL_SHIFT) -#define ADCIFE_SEQCFG_INTERNAL_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_INTERNAL_SHIFT, ADCIFE_SEQCFG_INTERNAL_MASK) -#define ADCIFE_SEQCFG_MUXPOS_SHIFT (16) -#define ADCIFE_SEQCFG_MUXPOS_MASK (0xf << ADCIFE_SEQCFG_MUXPOS_SHIFT) -#define ADCIFE_SEQCFG_MUXPOS_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_MUXPOS_SHIFT, ADCIFE_SEQCFG_MUXPOS_MASK) -#define ADCIFE_SEQCFG_MUXNEG_SHIFT (20) -#define ADCIFE_SEQCFG_MUXNEG_MASK (7 << ADCIFE_SEQCFG_MUXNEG_SHIFT) -#define ADCIFE_SEQCFG_MUXNEG_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_MUXNEG_SHIFT, ADCIFE_SEQCFG_MUXNEG_MASK) -#define ADCIFE_SEQCFG_ZOOMRANGE_SHIFT (28) -#define ADCIFE_SEQCFG_ZOOMRANGE_MASK (7 << ADCIFE_SEQCFG_ZOOMRANGE_SHIFT) -#define ADCIFE_SEQCFG_ZOOMRANGE_MASKED(V) _MASKED_VALUE((V), ADCIFE_SEQCFG_ZOOMRANGE_SHIFT, ADCIFE_SEQCFG_ZOOMRANGE_MASK) - -/* If x is of type enum adcife_prescal, the prescale value is 2^(x + 2) */ -enum adcife_prescal { - ADCIFE_PRESCAL_DIV4, - ADCIFE_PRESCAL_DIV8, - ADCIFE_PRESCAL_DIV16, - ADCIFE_PRESCAL_DIV32, - ADCIFE_PRESCAL_DIV64, - ADCIFE_PRESCAL_DIV128, - ADCIFE_PRESCAL_DIV256, - ADCIFE_PRESCAL_DIV512, -}; - -enum adcife_speed { - ADCIFE_SPEED_300KSPS, - ADCIFE_SPEED_225KSPS, - ADCIFE_SPEED_150KSPS, - ADCIFE_SPEED_75KSPS, -}; - -enum adcife_refsel { - ADCIFE_REFSEL_INTERNAL1V, - ADCIFE_REFSEL_0_625xVCC, - ADCIFE_REFSEL_EXTERNAL1, - ADCIFE_REFSEL_EXTERNAL2, - ADCIFE_REFSEL_HALF_VCC, -}; - -enum adcife_clk { - ADCIFE_CLK_GENERIC, - ADCIFE_CLK_APB = ADCIFE_CFG_CLKSEL, -}; - -enum adcife_channel { - ADCIFE_CHANNEL_AD0, - ADCIFE_CHANNEL_AD1, - ADCIFE_CHANNEL_AD2, - ADCIFE_CHANNEL_AD3, - ADCIFE_CHANNEL_AD4, - ADCIFE_CHANNEL_AD5, - ADCIFE_CHANNEL_AD6, - ADCIFE_CHANNEL_AD7, - ADCIFE_CHANNEL_AD8, - ADCIFE_CHANNEL_AD9, - ADCIFE_CHANNEL_AD10, - ADCIFE_CHANNEL_AD11, - ADCIFE_CHANNEL_AD12, - ADCIFE_CHANNEL_AD13, - ADCIFE_CHANNEL_AD14, -}; - -enum adcife_resolution { - ADCIFE_RESOLUTION_12BITS, - ADCIFE_RESOLUTION_8BITS, -}; - -enum adcife_trigger { - ADCIFE_TRIGGER_SW, - ADCIFE_TRIGGER_IADC_TMR, - ADCIFE_TRIGGER_ITS, - ADCIFE_TRIGGER_CONT, - ADCIFE_TRIGGER_EXT_RIS, - ADCIFE_TRIGGER_EXT_FALL, - ADCIFE_TRIGGER_EXT_BOTH, -}; - -enum adcife_gain { - ADCIFE_GAIN_1X, - ADCIFE_GAIN_2X, - ADCIFE_GAIN_4X, - ADCIFE_GAIN_8X, - ADCIFE_GAIN_16X, - ADCIFE_GAIN_32X, - ADCIFE_GAIN_64X, - ADCIFE_GAIN_0_5X, -}; - -struct adcife_lcv { - union { - uint32_t lcv; - struct { - uint16_t value; - uint8_t channel; - uint8_t reserved; - } _lc_s; - } _lc_u; -}; - -#define lc_channel _lc_u._lc_s.channel -#define lc_value _lc_u._lc_s.value - -BEGIN_DECLS - -void adcife_enable_sync(void); -void adcife_configure( - enum adcife_refsel ref, - enum adcife_speed speed, - enum adcife_clk clk, - enum adcife_prescal prescal); -void adcife_select_channel(enum adcife_channel ad); -void adcife_set_resolution(enum adcife_resolution res); -void adcife_select_trigger(enum adcife_trigger trig); -void adcife_set_gain(enum adcife_gain gain); -void adcife_set_bipolar(bool enable); -void adcife_set_left_adjust(bool enable); -void adcife_start_conversion(void); -void adcife_wait_conversion(void); -struct adcife_lcv adcife_get_lcv(void); -void adcife_enable_interrupts(uint32_t imask); -void adcife_disable_interrupts(uint32_t imask); -void adcife_timer_start(void); -void adcife_timer_stop(void); -void adcife_timer_set_timeout(uint16_t timeout); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/sam/4l/gpio.h b/libopencm3/include/libopencm3/sam/4l/gpio.h deleted file mode 100644 index 315b802..0000000 --- a/libopencm3/include/libopencm3/sam/4l/gpio.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include -#include - -#define GPIOA (GPIO_BASE) -#define GPIOB (GPIO_BASE + 0x200) -#define GPIOC (GPIO_BASE + 0x400) - -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO16 (1 << 16) -#define GPIO17 (1 << 17) -#define GPIO18 (1 << 18) -#define GPIO19 (1 << 19) -#define GPIO20 (1 << 20) -#define GPIO21 (1 << 21) -#define GPIO22 (1 << 22) -#define GPIO23 (1 << 23) -#define GPIO24 (1 << 24) -#define GPIO25 (1 << 25) -#define GPIO26 (1 << 26) -#define GPIO27 (1 << 27) -#define GPIO28 (1 << 28) -#define GPIO29 (1 << 29) -#define GPIO30 (1 << 30) -#define GPIO31 (1 << 31) - - -#define GPIO_GPER(X) MMIO32(X) -#define GPIO_GPERS(X) MMIO32((X) + 0x004) -#define GPIO_GPERC(X) MMIO32((X) + 0x008) -#define GPIO_GPERT(X) MMIO32((X) + 0x00C) - -#define GPIO_PMR(P, I) MMIO32((P) + (0x10*(1 + (I)))) -#define GPIO_PMR_SETVAL(P, I, S) MMIO32((P) + (0x10*(1 + (I)) + ((S) ? 0x04 : 0x08))) - -#define GPIO_PMR0(X) MMIO32((X) + 0x010) -#define GPIO_PMR0S(X) MMIO32((X) + 0x014) -#define GPIO_PMR0C(X) MMIO32((X) + 0x018) -#define GPIO_PMR0T(X) MMIO32((X) + 0x01C) - -#define GPIO_PMR1(X) MMIO32((X) + 0x020) -#define GPIO_PMR1S(X) MMIO32((X) + 0x024) -#define GPIO_PMR1C(X) MMIO32((X) + 0x028) -#define GPIO_PMR1T(X) MMIO32((X) + 0x02C) - -#define GPIO_PMR2(X) MMIO32((X) + 0x030) -#define GPIO_PMR2S(X) MMIO32((X) + 0x034) -#define GPIO_PMR2C(X) MMIO32((X) + 0x038) -#define GPIO_PMR2T(X) MMIO32((X) + 0x03C) - -#define GPIO_ODER(X) MMIO32((X) + 0x040) -#define GPIO_ODERS(X) MMIO32((X) + 0x044) -#define GPIO_ODERC(X) MMIO32((X) + 0x048) -#define GPIO_ODERT(X) MMIO32((X) + 0x04C) - -#define GPIO_OVR(X) MMIO32((X) + 0x050) -#define GPIO_OVRS(X) MMIO32((X) + 0x054) -#define GPIO_OVRC(X) MMIO32((X) + 0x058) -#define GPIO_OVRT(X) MMIO32((X) + 0x05C) - -#define GPIO_PVR(X) MMIO32((X) + 0x060) - -#define GPIO_PUER(X) MMIO32((X) + 0x070) -#define GPIO_PUERS(X) MMIO32((X) + 0x074) -#define GPIO_PUERC(X) MMIO32((X) + 0x078) -#define GPIO_PUERT(X) MMIO32((X) + 0x07C) - -#define GPIO_PDER(X) MMIO32((X) + 0x080) -#define GPIO_PDERS(X) MMIO32((X) + 0x084) -#define GPIO_PDERC(X) MMIO32((X) + 0x088) -#define GPIO_PDERT(X) MMIO32((X) + 0x08C) - -#define GPIO_IER(X) MMIO32((X) + 0x090) -#define GPIO_IERS(X) MMIO32((X) + 0x094) -#define GPIO_IERC(X) MMIO32((X) + 0x098) -#define GPIO_IERT(X) MMIO32((X) + 0x09C) - -#define GPIO_IMR0(X) MMIO32((X) + 0x0A0) -#define GPIO_IMR0S(X) MMIO32((X) + 0x0A4) -#define GPIO_IMR0C(X) MMIO32((X) + 0x0A8) -#define GPIO_IMR0T(X) MMIO32((X) + 0x0AC) - -#define GPIO_IMR1(X) MMIO32((X) + 0x0B0) -#define GPIO_IMR1S(X) MMIO32((X) + 0x0B4) -#define GPIO_IMR1C(X) MMIO32((X) + 0x0B8) -#define GPIO_IMR1T(X) MMIO32((X) + 0x0BC) - -#define GPIO_GFER(X) MMIO32((X) + 0x0C0) -#define GPIO_GFERS(X) MMIO32((X) + 0x0C4) -#define GPIO_GFERC(X) MMIO32((X) + 0x0C8) -#define GPIO_GFERT(X) MMIO32((X) + 0x0CC) - -#define GPIO_IFR(X) MMIO32((X) + 0x0D0) -#define GPIO_IFRC(X) MMIO32((X) + 0x0D8) - -#define GPIO_ODCR0(X) MMIO32((X) + 0x100) -#define GPIO_ODCR0S(X) MMIO32((X) + 0x104) -#define GPIO_ODCR0C(X) MMIO32((X) + 0x108) -#define GPIO_ODCR0T(X) MMIO32((X) + 0x10C) - -#define GPIO_ODCR1(X) MMIO32((X) + 0x110) -#define GPIO_ODCR1S(X) MMIO32((X) + 0x114) -#define GPIO_ODCR1C(X) MMIO32((X) + 0x118) -#define GPIO_ODCR1T(X) MMIO32((X) + 0x11C) - -#define GPIO_OSRR0(X) MMIO32((X) + 0x130) -#define GPIO_OSRR0S(X) MMIO32((X) + 0x134) -#define GPIO_OSRR0C(X) MMIO32((X) + 0x138) -#define GPIO_OSRR0T(X) MMIO32((X) + 0x13C) - -#define GPIO_STER(X) MMIO32((X) + 0x160) -#define GPIO_STERS(X) MMIO32((X) + 0x164) -#define GPIO_STERC(X) MMIO32((X) + 0x168) -#define GPIO_STERT(X) MMIO32((X) + 0x16C) - -#define GPIO_EVER(X) MMIO32((X) + 0x180) -#define GPIO_EVERS(X) MMIO32((X) + 0x184) -#define GPIO_EVERC(X) MMIO32((X) + 0x188) -#define GPIO_EVERT(X) MMIO32((X) + 0x18C) - -#define GPIO_PARAMETER(X) MMIO32((X) + 0x1f8) -#define GPIO_VERSION(X) MMIO32((X) + 0x1fc) - -enum gpio_mode { - // Peripherals - GPIO_MODE_A = 0, - GPIO_MODE_B, - GPIO_MODE_C, - GPIO_MODE_D, - GPIO_MODE_E, - GPIO_MODE_F, - GPIO_MODE_G, - GPIO_MODE_H, - GPIO_MODE_IN, - GPIO_MODE_OUT, -}; - -BEGIN_DECLS - -void gpio_enable(uint32_t gpioport, uint32_t gpios, enum gpio_mode mode); -void gpio_disable(uint32_t gpioport, uint32_t gpios); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/sam/4l/irq.json b/libopencm3/include/libopencm3/sam/4l/irq.json deleted file mode 100644 index 5bf9534..0000000 --- a/libopencm3/include/libopencm3/sam/4l/irq.json +++ /dev/null @@ -1,87 +0,0 @@ -{ - "irqs": [ - "hflashc", - "pdca0", - "pdca1", - "pdca2", - "pdca3", - "pdca4", - "pdca5", - "pdca6", - "pdca7", - "pdca8", - "pdca9", - "pdca10", - "pdca11", - "pdca12", - "pdca13", - "pdca14", - "pdca15", - "crccu", - "usbc", - "pevc_tr", - "pevc_ov", - "aesa", - "pm", - "scim", - "freqm", - "gpio0", - "gpio1", - "gpio2", - "gpio3", - "gpio4", - "gpio5", - "gpio6", - "gpio7", - "gpio8", - "gpio9", - "gpio10", - "gpio11", - "bpm", - "bscif", - "ast_alarm", - "ast_per", - "ast_ovf", - "ast_ready", - "ast_clkready", - "wdt", - "eic1", - "eic2", - "eic3", - "eic4", - "eic5", - "eic6", - "eic7", - "eic8", - "iisc", - "spi", - "tc00", - "tc01", - "tc02", - "tc10", - "tc11", - "tc12", - "twim0", - "twis0", - "twim1", - "twis1", - "usart0", - "usart1", - "usart2", - "usart3", - "adcife", - "dacc", - "acifc", - "abdacb", - "trng", - "parc", - "catb", - "reserved0", - "twim2", - "twim3", - "lcdca" - ], - "partname_humanreadable": "Atmel SAM4L series", - "partname_doxygen": "SAM4L", - "includeguard": "LIBOPENCM3_SAM4L_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/sam/4l/memorymap.h b/libopencm3/include/libopencm3/sam/4l/memorymap.h deleted file mode 100644 index 807f3f0..0000000 --- a/libopencm3/include/libopencm3/sam/4l/memorymap.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM4L_MEMORYMAP_H -#define SAM4L_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) - -/* --- SAM4L peripheral bridge A -------------------------------------------- */ -#define PERIPH_PBA_BASE PERIPH_BASE -/* (PERIPH_PBA_BASE + 0x4000) RESERVED */ -#define I2SC_BASE (PERIPH_PBA_BASE + 0x04000) -#define SPI_BASE (PERIPH_PBA_BASE + 0x08000) -/* (PERIPH_PBA_BASE + 0x0C000) RESERVED */ -#define TC0_BASE (PERIPH_PBA_BASE + 0x10000) -#define TC1_BASE (PERIPH_PBA_BASE + 0x14000) -#define TWIMS0_BASE (PERIPH_PBA_BASE + 0x18000) -#define TWIMS1_BASE (PERIPH_PBA_BASE + 0x1C000) -/* (PERIPH_PBA_BASE + 0x20000) RESERVED */ -#define USART0_BASE (PERIPH_PBA_BASE + 0x24000) -#define USART1_BASE (PERIPH_PBA_BASE + 0x28000 -#define USART2_BASE (PERIPH_PBA_BASE + 0x2C000) -#define USART3_BASE (PERIPH_PBA_BASE + 0x30000) -/* (PERIPH_PBA_BASE + 0x34000) RESERVED */ -#define ADCIFE_BASE (PERIPH_PBA_BASE + 0x38000) -#define DACC_BASE (PERIPH_PBA_BASE + 0x3C000) -#define ACIFC_BASE (PERIPH_PBA_BASE + 0x40000) -/* (PERIPH_PBA_BASE + 0x44000) to (PERIPH_PBA_BASE + 0x5C000) RESERVED */ -#define GLOC_BASE (PERIPH_PBA_BASE + 0x60000) -#define ABDACB_BASE (PERIPH_PBA_BASE + 0x64000) -#define TRNG_BASE (PERIPH_PBA_BASE + 0x68000) -#define PARC_BASE (PERIPH_PBA_BASE + 0x6C000) -#define CATB_BASE (PERIPH_PBA_BASE + 0x70000) -/* (PERIPH_PBA_BASE + 0x74000) RESERVED */ -#define TWIM2_BASE (PERIPH_PBA_BASE + 0x78000) -#define TWIM3_BASE (PERIPH_PBA_BASE + 0x7C000) -#define LCDCA_BASE (PERIPH_PBA_BASE + 0x80000) - -/* --- SAM4L peripheral bridge B -------------------------------------------- */ -#define PERIPH_PBB_BASE (PERIPH_BASE + 0xA0000U) -#define FLASHCALW_BASE (PERIPH_PBB_BASE) -#define PICOCACHE_BASE (PERIPH_PBB_BASE + 0x400) -#define HMATRIX_BASE (PERIPH_PBB_BASE + 0x1000) -#define PDCA_BASE (PERIPH_PBB_BASE + 0x2000) -#define SMAP_BASE (PERIPH_PBB_BASE + 0x3000) -#define CRCCU_BASE (PERIPH_PBB_BASE + 0x4000) -#define USBC_BASE (PERIPH_PBB_BASE + 0x5000) -#define PEVC_BASE (PERIPH_PBB_BASE + 0x6000) - -/* --------- Advanced Encryption Standard (AESA) ------------- */ -#define AESA_BASE (PERIPH_BASE + 0xB0000) - -/* --- SAM4L peripheral bridge C -------------------------------------------- */ -#define PERIPH_PBC_BASE (PERIPH_BASE + 0xE0000) -#define PM_BASE (PERIPH_PBC_BASE) -#define CHIPID_BASE (PERIPH_PBC_BASE + 0x740) -#define SCIF_BASE (PERIPH_PBC_BASE + 0x800) -#define FREQM_BASE (PERIPH_PBC_BASE + 0xC00) -#define GPIO_BASE (PERIPH_PBC_BASE + 0x1000) - -/* --- SAM4L peripheral bridge D -------------------------------------------- */ -#define PERIPH_PBD_BASE (PERIPH_BASE + 0xF0000U) -#define BPM_BASE (PERIPH_PBD_BASE) -#define BSCIF_BASE (PERIPH_PBD_BASE + 0x400) -#define AST_BASE (PERIPH_PBD_BASE + 0x800) -#define WDT_BASE (PERIPH_PBD_BASE + 0xC00) -#define EIC_BASE (PERIPH_PBD_BASE + 0x1000) -#define PICOUART_BASE (PERIPH_PBD_BASE + 0x1400) - -#endif diff --git a/libopencm3/include/libopencm3/sam/4l/pm.h b/libopencm3/include/libopencm3/sam/4l/pm.h deleted file mode 100644 index fb7224d..0000000 --- a/libopencm3/include/libopencm3/sam/4l/pm.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PM_H -#define LIBOPENCM3_PM_H - -#include - -/* --- Power Manager (PM) registers ----------------------- */ - -/* Main Clock Control MCCTRL Read/Write */ -#define PM_MCCTRL MMIO32(PM_BASE + 0x000) -#define PM_MCCTRL_KEY (PM_UNLOCK_KEY) - -/* CPU & PBx Clock Select, Read/Write */ -#define PM_CKSEL(I) MMIO32(PM_BASE + 0x004 + (0x004 * (I))) -#define PM_CKSEL_KEY(I) (PM_UNLOCK_KEY | (0x004 + (0x004 * (I)))) - -#define PM_MASK(I) MMIO32(PM_BASE + 0x020 + (0x004) * (I)) -#define PM_MASK_KEY(I) (PM_UNLOCK_KEY | (0x020 + (0x004) * (I))) - -/* CPU Mask CPUMASK Read/Write */ -#define PM_CPUMASK MMIO32(PM_BASE + 0x020) - -/* HSB Mask HSBMASK Read/Write */ -#define PM_HSBMASK MMIO32(PM_BASE + 0x024) - -/* PBA Mask PBAMASK Read/Write */ -#define PM_PBAMASK MMIO32(PM_BASE + 0x028) -#define PM_PBAMASK_KEY (PM_UNLOCK_KEY | 0x028) - -/* PBB Mask PBBMASK Read/Write */ -#define PM_PBBMASK MMIO32(PM_BASE + 0x02C) - -/* PBC Mask PBCMASK Read/Write */ -#define PM_PBCMASK MMIO32(PM_BASE + 0x030) - -/* PBD Mask PBDMASK Read/Write */ -#define PM_PBDMASK MMIO32(PM_BASE + 0x034) - -/* PBA Divided Mask PBADIVMASK Read/Write */ -#define PM_PBADIVMASK MMIO32(PM_BASE + 0x040) -#define PM_PBADIVMASK_KEY (PM_UNLOCK_KEY | 0x040) - -/* Clock Failure Detector Control CFDCTRL Read/Write */ -#define PM_CFDCTRL MMIO32(PM_BASE + 0x054) - -/* Unlock Register UNLOCK Write-only */ -#define PM_UNLOCK MMIO32(PM_BASE + 0x058) -#define PM_UNLOCK_KEY (0xAA << 24) - -/* Interrupt Enable Register IER Write-only */ -#define PM_IER MMIO32(PM_BASE + 0x0C0) - -/* Interrupt Disable Register IDR Write-only */ -#define PM_IDR MMIO32(PM_BASE + 0x0C4) - -/* Interrupt Mask Register IMR Read-only */ -#define PM_IMR MMIO32(PM_BASE + 0x0C8) - -/* Interrupt Status Register ISR Read-only */ -#define PM_ISR MMIO32(PM_BASE + 0x0CC) - -/* Interrupt Clear Register ICR Write-only */ -#define PM_ICR MMIO32(PM_BASE + 0x0D0) - -/* Status Register SR Read-only */ -#define PM_SR MMIO32(PM_BASE + 0x0D4) - -/* Peripheral Power Control Register PPCR Read/Write */ -#define PM_PPCR MMIO32(PM_BASE + 0x160) - -/* Reset Cause Register RCAUSE Read-only */ -#define PM_RCAUSE MMIO32(PM_BASE + 0x180) - -/* Wake Cause Register WCAUSE Read-only */ -#define PM_WCAUSE MMIO32(PM_BASE + 0x184) - -/* Asynchronous Wake Enable AWEN Read/Write */ -#define PM_AWEN MMIO32(PM_BASE + 0x188) - -/* Protection Control Register PROTCTRL Read/Write */ -#define PM_PROTCTRL MMIO32(PM_BASE + 0x18C) - -/* Fast Sleep Register FASTSLEEP Read/Write */ -#define PM_FASTSLEEP MMIO32(PM_BASE + 0x194) - -/* Configuration Register CONFIG Read-only */ -#define PM_CONFIG MMIO32(PM_BASE + 0x3F8) - -/* Version Register VERSION Read-only */ -#define PM_VERSION MMIO32(PM_BASE + 0x3FC) - - -/* --- Register contents --------------------------------------------------- */ -#define PM_MCCTRL_MCSEL_SHIFT 0 -#define PM_MCCTRL_MCSEL_MASK 3 - -// Values common for CPUSEL and PBxSEL -#define PM_CKSEL_DIV (1 << 7) -#define PM_CKSEL_MASK (3) - -#define PM_CPUMASK_OSC (1 << 0) - -#define PM_HSBMASK_PDCA (1 << 0) -#define PM_HSBMASK_FLASHCALW (1 << 1) -#define PM_HSBMASK_FLASHCALW_PICO (1 << 2) -#define PM_HSBMASK_USBC (1 << 3) -#define PM_HSBMASK_CRCCU (1 << 4) -#define PM_HSBMASK_APBA (1 << 5) -#define PM_HSBMASK_APBB (1 << 6) -#define PM_HSBMASK_APBC (1 << 7) -#define PM_HSBMASK_APBD (1 << 8) -#define PM_HSBMASK_AESA (1 << 9) - -#define PM_PBAMASK_IISC (1 << 0) -#define PM_PBAMASK_SPI (1 << 1) -#define PM_PBAMASK_TC0 (1 << 2) -#define PM_PBAMASK_TC1 (1 << 3) -#define PM_PBAMASK_TWIM0 (1 << 4) -#define PM_PBAMASK_TWIS0 (1 << 5) -#define PM_PBAMASK_TWIM1 (1 << 6) -#define PM_PBAMASK_TWIS1 (1 << 7) -#define PM_PBAMASK_USART0 (1 << 8) -#define PM_PBAMASK_USART1 (1 << 9) -#define PM_PBAMASK_USART2 (1 << 10) -#define PM_PBAMASK_USART3 (1 << 11) -#define PM_PBAMASK_ADCIFE (1 << 12) -#define PM_PBAMASK_DACC (1 << 13) -#define PM_PBAMASK_ACIFC (1 << 14) -#define PM_PBAMASK_GLOC (1 << 15) -#define PM_PBAMASK_ABDACB (1 << 16) -#define PM_PBAMASK_TRNG (1 << 17) -#define PM_PBAMASK_PARC (1 << 18) -#define PM_PBAMASK_CATB (1 << 19) -/* -- */ -#define PM_PBAMASK_TWIM2 (1 << 21) -#define PM_PBAMASK_TWIM3 (1 << 22) -#define PM_PBAMASK_LCDCA (1 << 23) - -#define PM_PBBMASK_FLASHCALW (1 << 0) -#define PM_PBBMASK_HRAMC1 (1 << 1) -#define PM_PBBMASK_HMATRIX (1 << 2) -#define PM_PBBMASK_PDCA (1 << 3) -#define PM_PBBMASK_CRCCU (1 << 4) -#define PM_PBBMASK_USBC (1 << 5) -#define PM_PBBMASK_PEVC (1 << 6) - -#define PM_PBCMASK_PM (1 << 0) -#define PM_PBCMASK_CHIPID (1 << 1) -#define PM_PBCMASK_SCIF (1 << 2) -#define PM_PBCMASK_FREQM (1 << 3) -#define PM_PBCMASK_GPIO (1 << 4) - -#define PM_PBDMASK_BPM (1 << 0) -#define PM_PBDMASK_BSCIF (1 << 1) -#define PM_PBDMASK_AST (1 << 2) -#define PM_PBDMASK_WDT (1 << 3) -#define PM_PBDMASK_EIC (1 << 4) -#define PM_PBDMASK_PICOUART (1 << 5) - -#define PM_PBADIVMASK_TC2 (1 << 0) -#define PM_PBADIVMASK_USART0 (1 << 2) -#define PM_PBADIVMASK_USART1 (1 << 2) -#define PM_PBADIVMASK_USART2 (1 << 2) -#define PM_PBADIVMASK_USART3 (1 << 2) -#define PM_PBADIVMASK_TC3 (1 << 2) -#define PM_PBADIVMASK_TC4 (1 << 4) -#define PM_PBADIVMASK_TC5 (1 << 6) - -#define PM_SR_CFD (1 << 0) -#define PM_SR_CKRDY (1 << 5) -#define PM_SR_WAKE (1 << 8) - -enum mck_src { - MCK_SRC_RCSYS = 0, - MCK_SRC_OSC0, - MCK_SRC_PLL, - MCK_SRC_DFLL, - MCK_SRC_RC80M, - MCK_SRC_RCFAST, - MCK_SRC_RC1M, -}; - -enum pm_cksel { - PM_CKSEL_CPU = 0, - PM_CKSEL_PBA = 2, - PM_CKSEL_PBB, - PM_CKSEL_PBC, - PM_CKSEL_PBD, -}; - -/* - * Ids are designed such that - * PM_MASK(id/32) = (1 << id % 32) - * would enable the peripheral clock. - */ -enum pm_peripheral { - PM_PERIPHERAL_OCD = 0, - PM_PERIPHERAL_PDCA = 32, - PM_PERIPHERAL_FLASHCALW, - PM_PERIPHERAL_FLASHCALW_PICORAM, - PM_PERIPHERAL_USBC, - PM_PERIPHERAL_CRCCU, - PM_PERIPHERAL_APBA_BRIDGE, - PM_PERIPHERAL_APBB_BRIDGE, - PM_PERIPHERAL_APBC_BRIDGE, - PM_PERIPHERAL_APBD_BRIDGE, - PM_PERIPHERAL_AESA, - PM_PERIPHERAL_IISC = 64, - PM_PERIPHERAL_SPI, - PM_PERIPHERAL_TC0, - PM_PERIPHERAL_TC1, - PM_PERIPHERAL_TWIM0, - PM_PERIPHERAL_TWIS0, - PM_PERIPHERAL_TWIM1, - PM_PERIPHERAL_TWIS1, - PM_PERIPHERAL_USART0, - PM_PERIPHERAL_USART1, - PM_PERIPHERAL_USART2, - PM_PERIPHERAL_USART3, - PM_PERIPHERAL_ADCIFE, - PM_PERIPHERAL_DACC, - PM_PERIPHERAL_ACIFC, - PM_PERIPHERAL_GLOC, - PM_PERIPHERAL_ABDACB, - PM_PERIPHERAL_TRNG, - PM_PERIPHERAL_PARC, - PM_PERIPHERAL_CATB, - PM_PERIPHERAL_RESERVED1, - PM_PERIPHERAL_TWIM2, - PM_PERIPHERAL_TWIM3, - PM_PERIPHERAL_LCDCA, - PM_PERIPHERAL_FLASHCALW_ALT = 96, - PM_PERIPHERAL_HRAMC1, - PM_PERIPHERAL_HMATRIX, - PM_PERIPHERAL_PDCA_ALT, - PM_PERIPHERAL_CRCCU_ALT, - PM_PERIPHERAL_USBC_ALT, - PM_PERIPHERAL_PEVC, - PM_PERIPHERAL_PM = 128, - PM_PERIPHERAL_CHIPID, - PM_PERIPHERAL_SCIF, - PM_PERIPHERAL_FREQM, - PM_PERIPHERAL_GPIO, - PM_PERIPHERAL_BPM = 160, - PM_PERIPHERAL_BSCIF, - PM_PERIPHERAL_AST, - PM_PERIPHERAL_WDT, - PM_PERIPHERAL_EIC, - PM_PERIPHERAL_PICOUART, -}; - -BEGIN_DECLS - -void pm_select_main_clock(enum mck_src source_clock); -void pm_enable_clock_div(enum pm_cksel sel_target, uint8_t div); -void pm_set_divmask_clock(uint8_t mask); -void pm_enable_peripheral_clock(enum pm_peripheral periph); -void pm_disable_peripheral_clock(enum pm_peripheral periph); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/sam/4l/scif.h b/libopencm3/include/libopencm3/sam/4l/scif.h deleted file mode 100644 index 416837b..0000000 --- a/libopencm3/include/libopencm3/sam/4l/scif.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SCIF_H -#define LIBOPENCM3_SCIF_H - -#include -#include - -/* ------------ SCIF Registers ------------------------------ */ - -/* Interrupt Enable Register IER Write Only */ -#define SCIF_IER MMIO32(SCIF_BASE) - -/* Interrupt Disable Register IDR Write Only */ -#define SCIF_IDR MMIO32(SCIF_BASE + 0x0004) - -/* Interrupt Mask Register IMR Read Only */ -#define SCIF_IMR MMIO32(SCIF_BASE + 0x0008) - -/* Interrupt Status Register ISR Read Only */ -#define SCIF_ISR MMIO32(SCIF_BASE + 0x000C) - -/* Interrupt Clear Register ICR Write Only */ -#define SCIF_ICR MMIO32(SCIF_BASE + 0x0010) - -/* Power and Clocks Status Register PCLKSR Read Only */ -#define SCIF_PCLKSR MMIO32(SCIF_BASE + 0x0014) - -/* Unlock Register UNLOCK Write Only */ -#define SCIF_UNLOCK MMIO32(SCIF_BASE + 0x0018) -#define SCIF_UNLOCK_KEY (0xaa << 24) - -/* Chip Specific Configuration Register CSCR Read/Write */ -#define SCIF_CSCR MMIO32(SCIF_BASE + 0x001C) - -/* Oscillator Control Register OSCCTRL0 Read/Write */ -#define SCIF_OSCCTRL0 MMIO32(SCIF_BASE + 0x0020) -#define SCIF_OSCCTRL0_KEY (SCIF_UNLOCK_KEY | 0x0020) - -/* PLL0 Control Register PLL0 Read/Write */ -#define SCIF_PLL0 MMIO32(SCIF_BASE + 0x0024) -#define SCIF_PLL0_KEY (SCIF_UNLOCK_KEY | 0x0024) - -/* DFLL0 Config Register DFLL0CONF Read/Write */ -#define SCIF_DFLL0CONF MMIO32(SCIF_BASE + 0x0028) - -/* DFLL Value Register DFLL0VAL Read/Write */ -#define SCIF_DFLL0VAL MMIO32(SCIF_BASE + 0x002C) - -/* DFLL0 Multiplier Register DFLL0MUL Read/Write */ -#define SCIF_DFLL0MUL MMIO32(SCIF_BASE + 0x0030) - -/* DFLL0 Step Register DFLL0STEP Read/Write */ -#define SCIF_DFLL0STEP MMIO32(SCIF_BASE + 0x0034) - -/* DFLL0 Spread Spectrum Generator Control Register DFLL0SSG Read/Write */ -#define SCIF_DFLL0SSG MMIO32(SCIF_BASE + 0x0038) - -/* DFLL0 Ratio Register DFLL0RATIO Read Only */ -#define SCIF_DFLL0RATIO MMIO32(SCIF_BASE + 0x003C) - -/* DFLL0 Synchronization Register DFLL0SYNC Write Only */ -#define SCIF_DFLL0SYNC MMIO32(SCIF_BASE + 0x0040) - -/* System RC Oscillator Calibration Register RCCR Read/Write */ -#define SCIF_RCCR MMIO32(SCIF_BASE + 0x0044) - -/* 4/8/12MHz RC Oscillator Configuration Register RCFASTCFG Read/Write */ -#define SCIF_RCFASTCFG MMIO32(SCIF_BASE + 0x0048) - -/* 4/8/12MHz RC Oscillator Status Register RCFASTSR Read Only */ -#define SCIF_RCFASTSR MMIO32(SCIF_BASE + 0x004C) - -/* 80MHz RC Oscillator Register RC80MCR Read/Write */ -#define SCIF_RC80MCR MMIO32(SCIF_BASE + 0x0050) - -/* High Resolution Prescaler Control Register HRPCR Read/Write */ -#define SCIF_HPPCR MMIO32(SCIF_BASE + 0x0064) - -/* Fractional Prescaler Control Register FPCR Read/Write */ -#define SCIF_FPCR MMIO32(SCIF_BASE + 0x0068) - -/* Fractional Prescaler Multiplier Register FPMUL Read/Write */ -#define SCIF_FPMUL MMIO32(SCIF_BASE + 0x006C) - -/* Fractional Prescaler DIVIDER Register FPDIV Read/Write */ -#define SCIF_FPDIV MMIO32(SCIF_BASE + 0x006C) - -/* Generic Clock Control1 GCCTRL0 Read/Write */ -#define SCIF_GCCTRL0 MMIO32(SCIF_BASE + 0x0074) - -/* Generic Clock Control1 GCCTRL1 Read/Write */ -#define SCIF_GCCTRL1 MMIO32(SCIF_BASE + 0x0078) - -/* Generic Clock Control2 GCCTRL2 Read/Write */ -#define SCIF_GCCTRL2 MMIO32(SCIF_BASE + 0x007C) - -/* Generic Clock Control3 GCCTRL3 Read/Write */ -#define SCIF_GCCTRL3 MMIO32(SCIF_BASE + 0x0080) - -/* Generic Clock Control4 GCCTRL4 Read/Write */ -#define SCIF_GCCTRL4 MMIO32(SCIF_BASE + 0x0084) - -/* Generic Clock Control5 GCCTRL5 Read/Write */ -#define SCIF_GCCTRL5 MMIO32(SCIF_BASE + 0x0088) - -/* Generic Clock Control6 GCCTRL6 Read/Write */ -#define SCIF_GCCTRL6 MMIO32(SCIF_BASE + 0x008C) - -/* Generic Clock Control7 GCCTRL7 Read/Write */ -#define SCIF_GCCTRL7 MMIO32(SCIF_BASE + 0x0090) - -/* Generic Clock Control8 GCCTRL8 Read/Write */ -#define SCIF_GCCTRL8 MMIO32(SCIF_BASE + 0x0094) - -/* Generic Clock Control9 GCCTRL9 Read/Write */ -#define SCIF_GCCTRL9 MMIO32(SCIF_BASE + 0x0098) - -/* Generic Clock Control10 GCCTRL10 Read/Write */ -#define SCIF_GCCTRL10 MMIO32(SCIF_BASE + 0x009C) - -/* Generic Clock Control11 GCCTRL11 Read/Write */ -#define SCIF_GCCTRL11 MMIO32(SCIF_BASE + 0x00A0) - -#define SCIF_GCTRL(N) MMIO32(SCIF_BASE + 0x0074 + 0x0004 * (N)) -#define SCIF_GCLK_MAX_NUM 11 - -/* 4/8/12MHz RC Oscillator Version Register RCFASTVERSION Read-only */ -#define SCIF_RCFASTVERSION MMIO32(SCIF_BASE + 0x03D8) - -/* Generic Clock Prescaler Version Register GCLKPRESCVERSION Read-only */ -#define SCIF_GCLKPRESCVERSION MMIO32(SCIF_BASE + 0x03DC) - -/* PLL Version Register PLLIFAVERSION Read-only */ -#define SCIF_PLLIFAVERSION MMIO32(SCIF_BASE + 0x03E0) - -/* Oscillator0 Version Register OSCIFAVERSION Read-only */ -#define SCIF_OSCIFAVERSION MMIO32(SCIF_BASE + 0x03E4) - -/* DFLL Version Register DFLLIFBVERSION Read-only */ -#define SCIF_DFLLIFBVERSION MMIO32(SCIF_BASE + 0x03E8) - -/* System RC Oscillator Version Register RCOSCIFAVERSION Read-only */ -#define SCIF_RCOSCIFAVERSION MMIO32(SCIF_BASE + 0x03EC) - -/* 80MHz RC Oscillator Version Register RC80MVERSION Read-only */ -#define SCIF_RC80MVERSION MMIO32(SCIF_BASE + 0x03F4) - -/* Generic Clock Version Register GCLKVERSION Read-only */ -#define SCIF_GCLKVERSION MMIO32(SCIF_BASE + 0x03F8) - -/* SCIF Version Register VERSION Read-Only */ -#define SCIF_VERSION MMIO32(SCIF_BASE + 0x03FC) - - -/* ---------------- SCIF Registers' Contents ------------------- */ - -/* Interrupt Enable/Disable/Mask/Status/Clear registers and PCLKSR - * have the same bit configuration */ -#define SCIF_OSC0RDY (1 << 0) -#define SCIF_DFLL0LOCKC (1 << 1) -#define SCIF_DFLL0LOCKF (1 << 2) -#define SCIF_DFLL0RDY (1 << 3) -#define SCIF_DFLL0RCS (1 << 4) -#define SCIF_PLL0LOCK (1 << 6) -#define SCIF_PLL0LOCKLOST (1 << 7) -#define SCIF_RCFASTLOCK (1 << 13) -#define SCIF_RCFASTLOCKLOST (1 << 14) - -#define SCIF_OSCCTRL_MODE (1 << 0) -#define SCIF_OSCCTRL_GAIN_SHIFT 1 -#define SCIF_OSCCTRL_GAIN_MASK (3 << SCIF_OSCCTRL_GAIN_SHIFT) -#define SCIF_OSCCTRL_AGC (1 << 3) -#define SCIF_OSCCTRL_STARTUP_SHIFT 8 -#define SCIF_OSCCTRL_STARTUP_MASK (0xf << SCIF_OSCCTRL_STARTUP_SHIFT) -#define SCIF_OSCCTRL_OSCEN (1 << 16) - -#define _MASKED_VALUE(V, S, M) (((V) << (S)) & (M)) - -#define SCIF_PLL0_PLLEN (1 << 0) -#define SCIF_PLL0_PLLOSC_SHIFT 1 -#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT) -#define SCIF_PLL0_PLLOSC_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLOSC_SHIFT, SCIF_PLL0_PLLOSC_MASK) - -#define SCIF_PLL0_PLLOPT_SHIFT 3 -#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT) -#define SCIF_PLL0_PLLOPT_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLOPT_SHIFT, SCIF_PLL0_PLLOPT_MASK) - -#define SCIF_PLL0_PLLDIV_SHIFT 8 -#define SCIF_PLL0_PLLDIV_MASK (0xf << SCIF_PLL0_PLLDIV_SHIFT) -#define SCIF_PLL0_PLLDIV_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLDIV_SHIFT, SCIF_PLL0_PLLDIV_MASK) - -#define SCIF_PLL0_PLLMUL_SHIFT 16 -#define SCIF_PLL0_PLLMUL_MASK (0xf << SCIF_PLL0_PLLMUL_SHIFT) -#define SCIF_PLL0_PLLMUL_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLMUL_SHIFT, SCIF_PLL0_PLLMUL_MASK) - -#define SCIF_PLL0_PLLCOUNT_SHIFT 24 -#define SCIF_PLL0_PLLCOUNT_MASK (0x3f << SCIF_PLL0_PLLCOUNT_SHIFT) -#define SCIF_PLL0_PLLCOUNT_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLCOUNT_SHIFT, SCIF_PLL0_PLLCOUNT_MASK) - - -#define SCIF_GCCTRL_CEN (1 << 0) -#define SCIF_GCCTRL_DIVEN (1 << 1) -#define SCIF_GCCTRL_OSCSEL_SHIFT 8 -#define SCIF_GCCTRL_OSCSEL_MASK (0x1f << SCIF_GCCTRL_OSCSEL_SHIFT) -#define SCIF_GCCTRL_OSCSEL_MASKED(V) _MASKED_VALUE(V, SCIF_GCCTRL_OSCSEL_SHIFT, SCIF_GCCTRL_OSCSEL_MASK) -#define SCIF_GCCTRL_DIV_SHIFT 16 -#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT) -#define SCIF_GCCTRL_DIV_MASKED(V) _MASKED_VALUE(V, SCIF_GCCTRL_DIV_SHIFT, SCIF_GCCTRL_DIV_MASK) - - -enum osc_mode { - OSC_MODE_XIN = 0, - OSC_MODE_XIN_XOUT, -}; - -enum osc_startup { - OSC_STARTUP_0 = 0, - OSC_STARTUP_4 = 8, - OSC_STARTUP_8 = 9, - OSC_STARTUP_16 = 10, - OSC_STARTUP_32 = 11, - OSC_STARTUP_64 = 1, - OSC_STARTUP_128 = 2, - OSC_STARTUP_256 = 12, - OSC_STARTUP_512 = 13, - OSC_STARTUP_1K = 14, - OSC_STARTUP_2K = 3, - OSC_STARTUP_4K = 4, - OSC_STARTUP_8K = 5, - OSC_STARTUP_16K = 6, - OSC_STARTUP_32K = 7, -}; - -enum pll_clk_src { - PLL_CLK_SRC_OSC0 = 0, - PLL_CLK_SRC_GCLK9, -}; - -/* Generic Clock Source - * 0 RCSYS System RC oscillator clock - * 1 OSC32K Output clock from OSC32K - * 2 DFLL0 Output clock from DFLL0 - * 3 OSC0 Output clock from Oscillator0 - * 4 RC80M Output from 80MHz RCOSC - * 5 RCFAST Output from 4,8,12MHz RCFAST - * 6 RC1M Output from 1MHz RC1M - * 7 CLK_CPU The clock the CPU runs on - * 8 CLK_HSB High Speed Bus clock - * 9 CLK_PBA Peripheral Bus A clock - * 10 CLK_PBB Peripheral Bus B clock - * 11 CLK_PBC Peripheral Bus C clock - * 12 CLK_PBD Peripheral Bus D clock - * 13 RC32K Output from 32kHz RCOSC - * 14 Reserved - * 15 CLK_1K 1kHz output clock from OSC32K - * 16 PLL0 Output clock from PLL0 - * 17 HRP High Resolution Prescaler Output - * 18 FP Fractionnal Prescaler Output - * 19-20 GCLK_IN[0-1] GCLK_IN[0-1] pins, digital clock input - * 21 GCLK11 Generic Clock 11. Can not be use as input to itself. - */ -enum gclk_src { - GCLK_SRC_RCSYS, - GCLK_SRC_OSC32K, - GCLK_SRC_DFLL0, - GCLK_SRC_OSC0, - GCLK_SRC_RC80M, - GCLK_SRC_RCFAST, - GCLK_SRC_RC1M, - GCLK_SRC_CLK_CPU, - GCLK_SRC_CLK_HSB, - GCLK_SRC_CLK_PBA, - GCLK_SRC_CLK_PBB, - GCLK_SRC_CLK_PBC, - GCLK_SRC_CLK_PBD, - GCLK_SRC_RC32K, - GCLK_SRC_RESERVED_, - GCLK_SRC_CLK_1K, - GCLK_SRC_PLL0, - GCLK_SRC_HRP, - GCLK_SRC_FP, - GCLK_SRC_GCLK_IN0, - GCLK_SRC_GCLK_IN1, - GCLK_SRC_GCLK11, -}; - -enum generic_clock { - GENERIC_CLOCK0, - GENERIC_CLOCK1, - GENERIC_CLOCK2, - GENERIC_CLOCK3, - GENERIC_CLOCK4, - GENERIC_CLOCK5, - GENERIC_CLOCK6, - GENERIC_CLOCK7, - GENERIC_CLOCK8, - GENERIC_CLOCK9, - GENERIC_CLOCK10, - GENERIC_CLOCK_ADCIFE = GENERIC_CLOCK10, - GENERIC_CLOCK11, -}; - -BEGIN_DECLS - -int scif_osc_enable(enum osc_mode mode, uint32_t freq, enum osc_startup startup); -int scif_enable_pll(uint8_t delay, uint8_t mul, uint8_t div, uint8_t pll_opt, enum pll_clk_src source_clock); -void scif_enable_gclk(enum generic_clock gclk, enum gclk_src source_clock, uint16_t div); - -END_DECLS - - -#endif /* LIBOPENCM3_SCIF_H */ diff --git a/libopencm3/include/libopencm3/sam/adcife.h b/libopencm3/include/libopencm3/sam/adcife.h deleted file mode 100644 index 805e5be..0000000 --- a/libopencm3/include/libopencm3/sam/adcife.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM_ADCIFE_H -#define SAM_ADCIFE_H - -#if defined(SAM4L) -# include -#else -# error "ADC interface is not defined for your processor family" -#endif - -#endif diff --git a/libopencm3/include/libopencm3/sam/common/gpio_common_3a3u3x.h b/libopencm3/include/libopencm3/sam/common/gpio_common_3a3u3x.h deleted file mode 100644 index f397d3e..0000000 --- a/libopencm3/include/libopencm3/sam/common/gpio_common_3a3u3x.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * COpyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_GPIO_H) - -#ifndef LIBOPENCM3_GPIO_COMMON_3A3U3X_H -#define LIBOPENCM3_GPIO_COMMON_3A3U3X_H - -#include - - -/* flags may be or'd together, but only contain one of - * GPOUTPUT, PERIPHA and PERIPHB */ -enum gpio_flags { - GPIO_FLAG_GPINPUT = 0, - GPIO_FLAG_GPOUTPUT = 1, - GPIO_FLAG_PERIPHA = 2, - GPIO_FLAG_PERIPHB = 3, - GPIO_FLAG_OPEN_DRAIN = (1 << 3), - GPIO_FLAG_PULL_UP = (1 << 4), -}; - - -void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags); - - -#endif - -#else -#warning "gpio_common_3a3u3x.h should not be included explicitly, only via gpio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/gpio_common_3n3s.h b/libopencm3/include/libopencm3/sam/common/gpio_common_3n3s.h deleted file mode 100644 index 348dd6e..0000000 --- a/libopencm3/include/libopencm3/sam/common/gpio_common_3n3s.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_GPIO_H) - -#ifndef LIBOPENCM3_GPIO_COMMON_3N3S_H -#define LIBOPENCM3_GPIO_COMMON_3N3S_H - -#include - - -/* flags may be or'd together, but only contain one of - * GPOUTPUT, PERIPHA, PERIPHB, PERIPHC and PERIPHD */ -enum gpio_flags { - GPIO_FLAG_GPINPUT = 0, - GPIO_FLAG_GPOUTPUT = 1, - GPIO_FLAG_PERIPHA = 2, - GPIO_FLAG_PERIPHB = 3, - GPIO_FLAG_PERIPHC = 4, - GPIO_FLAG_PERIPHD = 5, - GPIO_FLAG_OPEN_DRAIN = (1 << 3), - GPIO_FLAG_PULL_UP = (1 << 4), -}; - - -void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags); - - -#endif - -#else -#warning "gpio_common_3n3s.h should not be included explicitly, only via gpio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/gpio_common_all.h b/libopencm3/include/libopencm3/sam/common/gpio_common_all.h deleted file mode 100644 index 5873b72..0000000 --- a/libopencm3/include/libopencm3/sam/common/gpio_common_all.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_GPIO_H) - -#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H -#define LIBOPENCM3_GPIO_COMMON_ALL_H - -#include - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint32_t gpios); -void gpio_clear(uint32_t gpioport, uint32_t gpios); -void gpio_toggle(uint32_t gpioport, uint32_t gpios); - -END_DECLS - -#endif - -#else -#warning "gpio_common_all.h should not be included explicitly, only via gpio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/periph_common_3a3x.h b/libopencm3/include/libopencm3/sam/common/periph_common_3a3x.h deleted file mode 100644 index a0dcae2..0000000 --- a/libopencm3/include/libopencm3/sam/common/periph_common_3a3x.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PERIPH_H -#define LIBOPENCM3_PERIPH_H - -/* --- Peripheral Identifiers ---------------------------------------------- */ -#define PERIPH_SUPC 0 -#define PERIPH_RSTC 1 -#define PERIPH_RTC 2 -#define PERIPH_RTT 3 -#define PERIPH_WDG 4 -#define PERIPH_PMC 5 -#define PERIPH_EEFC0 6 -#define PERIPH_EEFC1 7 -#define PERIPH_UART 8 -#define PERIPH_SMC_SDRAMC 9 -#define PERIPH_SDRAMC 10 -#define PERIPH_PIOA 11 -#define PERIPH_PIOB 12 -#define PERIPH_PIOC 13 -#define PERIPH_PIOD 14 -#define PERIPH_PIOE 15 -#define PERIPH_PIOF 16 -#define PERIPH_USART0 17 -#define PERIPH_USART1 18 -#define PERIPH_USART2 19 -#define PERIPH_USART3 20 -#define PERIPH_HSMCI 21 -#define PERIPH_TWI0 22 -#define PERIPH_TWI1 23 -#define PERIPH_SPI0 24 -#define PERIPH_SPI1 25 -#define PERIPH_SSC 26 -#define PERIPH_TC0 27 -#define PERIPH_TC1 28 -#define PERIPH_TC2 29 -#define PERIPH_TC3 30 -#define PERIPH_TC4 31 -#define PERIPH_TC5 32 -#define PERIPH_TC6 33 -#define PERIPH_TC7 34 -#define PERIPH_TC8 35 -#define PERIPH_PWM 36 -#define PERIPH_ADC 37 -#define PERIPH_DACC 38 -#define PERIPH_DMAC 39 -#define PERIPH_UOTGHS 40 -#define PERIPH_TRNG 41 -#define PERIPH_EMAC 42 -#define PERIPH_CAN0 43 -#define PERIPH_CAN1 44 - - -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pio_common_3a3u3x.h b/libopencm3/include/libopencm3/sam/common/pio_common_3a3u3x.h deleted file mode 100644 index 45f016e..0000000 --- a/libopencm3/include/libopencm3/sam/common/pio_common_3a3u3x.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * COpyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PIO.H -The order of header inclusion is important. pio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_PIO_H) - -#ifndef LIBOPENCM3_PIO_COMMON_3A3U3X_H -#define LIBOPENCM3_PIO_COMMON_3A3U3X_H - -#include - -/* --- PIO registers ----------------------------------------------------- */ - -/* Peripheral AB Select Register */ -#define PIO_ABSR(port) MMIO32((port) + 0x0070) - -/* System Clock Glitch Input Filter Select Register */ -#define PIO_SCIFSR(port) MMIO32((port) + 0x0080) - -/* Debouncing Input Filter Select Register */ -#define PIO_DIFSR(port) MMIO32((port) + 0x0084) - -/* Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define PIO_IFDGSR(port) MMIO32((port) + 0x0088) - - -#endif - -#else -#warning "pio_common_3a3u3x.h should not be included explicitly, only via pio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pio_common_3n3s.h b/libopencm3/include/libopencm3/sam/common/pio_common_3n3s.h deleted file mode 100644 index 09d54dc..0000000 --- a/libopencm3/include/libopencm3/sam/common/pio_common_3n3s.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * COpyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PIO.H -The order of header inclusion is important. pio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_PIO_H) - -#ifndef LIBOPENCM3_PIO_COMMON_3N3S_H -#define LIBOPENCM3_PIO_COMMON_3N3S_H - -#include - -/* --- PIO registers ----------------------------------------------------- */ - -/* Peripheral Select Register 1 */ -#define PIO_ABCDSR1(port) MMIO32((port) + 0x0070) - -/* Peripheral Select Register 2 */ -#define PIO_ABCDSR2(port) MMIO32((port) + 0x0074) - -/* Input Filter Slow Clock Disable Register */ -#define PIO_IFSCDR(port) MMIO32((port) + 0x0080) - -/* Input Filter Slow Clock Enable Register */ -#define PIO_IFSCER(port) MMIO32((port) + 0x0084) - -/* Input Filter Slow Clock Status Register */ -#define PIO_IFSCSR(port) MMIO32((port) + 0x0088) - -/* Pad Pull-down Disable Register */ -#define PIO_PPDDR(port) MMIO32((port) + 0x0090) - -/* Pad Pull-down Enable Register */ -#define PIO_PPDER(port) MMIO32((port) + 0x0094) - -/* Pad Pull-down Status Register */ -#define PIO_PPDSR(port) MMIO32((port) + 0x0098) - -/* Schmitt Trigger Register */ -#define PIO_SCHMITT(port) MMIO32((port) + 0x0100) - - -#endif - -#else -#warning "pio_common_3n3s.h should not be included explicitly, only via pio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pio_common_all.h b/libopencm3/include/libopencm3/sam/common/pio_common_all.h deleted file mode 100644 index 2c262f4..0000000 --- a/libopencm3/include/libopencm3/sam/common/pio_common_all.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PIO.H -The order of header inclusion is important. pio.h includes the device -specific memorymap.h header before including this header file.*/ - -#if defined(LIBOPENCM3_PIO_H) - -#ifndef LIBOPENCM3_PIO_COMMON_ALL_H -#define LIBOPENCM3_PIO_COMMON_ALL_H - -#include - -/* --- Convenience macros ------------------------------------------------ */ - -/* GPIO port base addresses (for convenience) */ -#define PIOA PIOA_BASE -#define PIOB PIOB_BASE -#define PIOC PIOC_BASE -#define PIOD PIOD_BASE -#define PIOE PIOE_BASE -#define PIOF PIOF_BASE -#define PIOG PIOG_BASE -#define PIOH PIOH_BASE - -/* --- PIO registers ----------------------------------------------------- */ - -/* PIO Enable Register */ -#define PIO_PER(port) MMIO32((port) + 0x0000) - -/* PIO Disable Register */ -#define PIO_PDR(port) MMIO32((port) + 0x0004) - -/* PIO Status Register */ -#define PIO_PSR(port) MMIO32((port) + 0x0008) - -/* Output Enable Register */ -#define PIO_OER(port) MMIO32((port) + 0x0010) - -/* Output Disable Register */ -#define PIO_ODR(port) MMIO32((port) + 0x0014) - -/* Output Status Register */ -#define PIO_OSR(port) MMIO32((port) + 0x0018) - -/* Glitch Input Filter Enable Register */ -#define PIO_IFER(port) MMIO32((port) + 0x0020) - -/* Glitch Input Filter Disable Register */ -#define PIO_IFDR(port) MMIO32((port) + 0x0024) - -/* Glitch Input Filter Status Register */ -#define PIO_IFSR(port) MMIO32((port) + 0x0028) - -/* Set Output Data Register */ -#define PIO_SODR(port) MMIO32((port) + 0x0030) - -/* Clear Output Data Register */ -#define PIO_CODR(port) MMIO32((port) + 0x0034) - -/* Output Data Status Register */ -#define PIO_ODSR(port) MMIO32((port) + 0x0038) - -/* Pin Data Status Register */ -#define PIO_PDSR(port) MMIO32((port) + 0x003C) - -/* Interrupt Enable Register */ -#define PIO_IER(port) MMIO32((port) + 0x0040) - -/* Interrupt Disable Register */ -#define PIO_IDR(port) MMIO32((port) + 0x0044) - -/* Interrupt Mask Register */ -#define PIO_IMR(port) MMIO32((port) + 0x0048) - -/* Interrupt Status Register */ -#define PIO_ISR(port) MMIO32((port) + 0x004C) - -/* Multi-driver Enable Register */ -#define PIO_MDER(port) MMIO32((port) + 0x0050) - -/* Multi-driver Disable Register */ -#define PIO_MDDR(port) MMIO32((port) + 0x0054) - -/* Multi-driver Status Register */ -#define PIO_MDSR(port) MMIO32((port) + 0x0058) - -/* Pull-up Disable Register */ -#define PIO_PUDR(port) MMIO32((port) + 0x0060) - -/* Pull-up Enable Register */ -#define PIO_PUER(port) MMIO32((port) + 0x0064) - -/* Pad Pull-up Status Register */ -#define PIO_PUSR(port) MMIO32((port) + 0x0068) - -/* Slow Clock Divider Debouncing Register */ -#define PIO_SCDR(port) MMIO32((port) + 0x008C) - -/* Output Write Enable */ -#define PIO_OWER(port) MMIO32((port) + 0x00A0) - -/* Output Write Disable */ -#define PIO_OWDR(port) MMIO32((port) + 0x00A4) - -/* Output Write Status Register */ -#define PIO_OWSR(port) MMIO32((port) + 0x00A8) - -/* Additional Interrupt Modes Enable Register */ -#define PIO_AIMER(port) MMIO32((port) + 0x00B0) - -/* Additional Interrupt Modes Disables Register */ -#define PIO_AIMDR(port) MMIO32((port) + 0x00B4) - -/* Additional Interrupt Modes Mask Register */ -#define PIO_AIMMR(port) MMIO32((port) + 0x00B8) - -/* Edge Select Register */ -#define PIO_ESR(port) MMIO32((port) + 0x00C0) - -/* Level Select Register */ -#define PIO_LSR(port) MMIO32((port) + 0x00C4) - -/* Edge/Level Status Register */ -#define PIO_ELSR(port) MMIO32((port) + 0x00C8) - -/* Falling Edge/Low Level Select Register */ -#define PIO_FELLSR(port) MMIO32((port) + 0x00D0) - -/* Rising Edge/High Level Select Register */ -#define PIO_REHLSR(port) MMIO32((port) + 0x00D4) - -/* Fall/Rise - Low/High Status Register */ -#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8) - -/* Lock Status */ -#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0) - -/* Write Protect Mode Register */ -#define PIO_WPMR(port) MMIO32((port) + 0x00E4) - -/* Write Protect Status Register */ -#define PIO_WPSR(port) MMIO32((port) + 0x00E8) - - -#endif - -#else -#warning "pio_common_all.h should not be included explicitly, only via pio.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pmc_common_3a3s3x.h b/libopencm3/include/libopencm3/sam/common/pmc_common_3a3s3x.h deleted file mode 100644 index b009e08..0000000 --- a/libopencm3/include/libopencm3/sam/common/pmc_common_3a3s3x.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(LIBOPENCM3_PMC_H) - -#ifndef LIBOPENCM3_PMC_COMMON_3A3S3X_H -#define LIBOPENCM3_PMC_COMMON_3A3S3X_H - - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* Peripheral Clock Enable Register 0 */ -#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010) - -/* Peripheral Clock Disable Register 0 */ -#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014) - -/* Peripheral Clock Status Register 0 */ -#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018) - -/* USB Clock Register */ -#define PMC_USB MMIO32(PMC_BASE + 0x0038) - -/* Peripheral Clock Enable Register 1 */ -#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100) - -/* Peripheral Clock Disable Register 1 */ -#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104) - -/* Peripheral Clock Status Register 1 */ -#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC USB Clock Register (PMC_USB) ------------------------------------ */ - -/* Divider for USB Clock */ -#define PMC_USB_USBDIV_SHIFT 8 -#define PMC_USB_USBDIV_MASK (0x0F << PMC_USB_USBDIV_SHIFT) - -/* USB Input Clock Selection */ -#define PMC_USB_USBS (0x01 << 0) - - -#endif - -#else -#warning "pmc_common_3a3s3x.h should not be included explicitly, only via pmc.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pmc_common_3a3u3x.h b/libopencm3/include/libopencm3/sam/common/pmc_common_3a3u3x.h deleted file mode 100644 index 39917b2..0000000 --- a/libopencm3/include/libopencm3/sam/common/pmc_common_3a3u3x.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(LIBOPENCM3_PMC_H) - -#ifndef LIBOPENCM3_PMC_COMMON_3A3U3X_H -#define LIBOPENCM3_PMC_COMMON_3A3U3X_H - - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* UTMI Clock Register */ -#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC UTMI Clock Configuration Register (CKGR_UCKR) ------------------- */ - -/* UTMI PLL Start-up Time */ -#define CKGR_UCKR_UPLLCOUNT_SHIFT 20 -#define CKGR_UCKR_UPLLCOUNT_MASK (0x0F << CKGR_UCKR_UPLLCOUNT_SHIFT) - -/* UTMI PLL Enable */ -#define CKGR_UCKR_UPLLEN (0x01 << 16) - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* UPLL Divide by 2 */ -#define PMC_MCKR_UPLLDIV2 (0x01 << 13) - -/* Master Clock Source Selection */ -#define PMC_MCKR_CSS_UPLL_CLK (3 << PMC_MCKR_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK0_CSS_UPLL_CLK (3 << PMC_PCK0_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK1_CSS_UPLL_CLK (3 << PMC_PCK1_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */ - -/* Master Clock Source Selection */ -#define PMC_PCK2_CSS_UPLL_CLK (3 << PMC_PCK2_CSS_SHIFT) - - -/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */ - -/* UTMI PLL Lock Interrupt Enable */ -#define PMC_IER_LOCKU (0x01 << 6) - - -/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */ - -/* UTMI PLL Lock Interrupt Disable */ -#define PMC_IDR_LOCKU (0x01 << 6) - - -/* --- PMC Status Register (PMC_SR) ---------------------------------------- */ - -/* UTMI PLL Lock Status */ -#define PMC_SR_LOCKU (0x01 << 6) - - -/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */ - -/* UTMI PLL Lock Interrupt Mask */ -#define PMC_IMR_LOCKU (0x01 << 6) - - -#endif - -#else -#warning "pmc_common_3a3u3x.h should not be included explicitly, only via pmc.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pmc_common_3n3u.h b/libopencm3/include/libopencm3/sam/common/pmc_common_3n3u.h deleted file mode 100644 index 5f05355..0000000 --- a/libopencm3/include/libopencm3/sam/common/pmc_common_3n3u.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(LIBOPENCM3_PMC_H) - -#ifndef LIBOPENCM3_PMC_COMMON_3N3U_H -#define LIBOPENCM3_PMC_COMMON_3N3U_H - -/* Peripheral Clock Enable Register */ -#define PMC_PCER MMIO32(PMC_BASE + 0x0010) - -/* Peripheral Clock Disable Register */ -#define PMC_PCDR MMIO32(PMC_BASE + 0x0014) - -/* Peripheral Clock Status Register */ -#define PMC_PCSR MMIO32(PMC_BASE + 0x0018) - - -#endif - -#else -#warning "pmc_common_3n3u.h should not be included explicitly, only via pmc.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/pmc_common_all.h b/libopencm3/include/libopencm3/sam/common/pmc_common_all.h deleted file mode 100644 index 6667659..0000000 --- a/libopencm3/include/libopencm3/sam/common/pmc_common_all.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Gareth McMullin - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(LIBOPENCM3_PMC_H) - -#ifndef LIBOPENCM3_PMC_COMMON_ALL_H -#define LIBOPENCM3_PMC_COMMON_ALL_H - -#include - -/* --- Power Management Controller (PMC) registers ----------------------- */ - -/* System Clock Enable Register */ -#define PMC_SCER MMIO32(PMC_BASE + 0x0000) - -/* System Clock Disable Register */ -#define PMC_SCDR MMIO32(PMC_BASE + 0x0004) - -/* System Clock Status Register */ -#define PMC_SCSR MMIO32(PMC_BASE + 0x0008) - -/* Main Oscillator Register */ -#define CKGR_MOR MMIO32(PMC_BASE + 0x0020) - -/* Main Clock Frequency Register */ -#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024) - -/* PLLA Register */ -#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028) - -/* Master Clock Register */ -#define PMC_MCKR MMIO32(PMC_BASE + 0x0030) - -/* Programmable Clock 0 Register */ -#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040) - -/* Programmable Clock 1 Register */ -#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044) - -/* Programmable Clock 2 Register */ -#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048) - -/* Interrupt Enable Register */ -#define PMC_IER MMIO32(PMC_BASE + 0x0060) - -/* Interrupt Disable Register */ -#define PMC_IDR MMIO32(PMC_BASE + 0x0064) - -/* Status Register */ -#define PMC_SR MMIO32(PMC_BASE + 0x0068) - -/* Interrupt Mask Register */ -#define PMC_IMR MMIO32(PMC_BASE + 0x006C) - -/* Fast Startup Mode Register */ -#define PMC_FSMR MMIO32(PMC_BASE + 0x0070) - -/* Fast Startup Polarity Register */ -#define PMC_FSPR MMIO32(PMC_BASE + 0x0074) - -/* Fault Output Clear Register */ -#define PMC_FOCR MMIO32(PMC_BASE + 0x0078) - -/* Write Protect Mode Register */ -#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4) - -/* Write Protect Status Register */ -#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- PMC System Clock Enable Register (PMC_SCER) ------------------------- */ - -/* Programmable Clock Output Enable */ -#define PMC_SCER_PCK0 (0x01 << 8) -#define PMC_SCER_PCK1 (0x01 << 9) -#define PMC_SCER_PCK2 (0x01 << 10) - - -/* --- PMC System Clock Disable Register (PMC_SCDR) ------------------------ */ - -/* Programmable Clock Output Disable */ -#define PMC_SCDR_PCK0 (0x01 << 8) -#define PMC_SCDR_PCK1 (0x01 << 9) -#define PMC_SCDR_PCK2 (0x01 << 10) - - -/* --- PMC System Clock Status Register (PMC_SCSR) ------------------------- */ - -/* Programmable Clock Output Status */ -#define PMC_SCSR_PCK0 (0x01 << 8) -#define PMC_SCSR_PCK1 (0x01 << 9) -#define PMC_SCSR_PCK2 (0x01 << 10) - - -/* for bit definitions for PMC System Clock Enable/Disable/Status Register see - * periph.h */ - - -/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */ - -/* Clock Failure Detector Enable */ -#define CKGR_MOR_CFDEN (0x01 << 25) - -/* Main Oscillator Selection */ -#define CKGR_MOR_MOSCSEL (0x01 << 24) - -/* Password for changing settings */ -#define CKGR_MOR_KEY (0x37 << 16) - -/* Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST_SHIFT 8 -#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8) - -/* Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_SHIFT 4 -#define CKGR_MOR_MOSCRCF_MASK (0x07 << CKGR_MOR_MOSCRCF_SHIFT) - -/* Main On-Chip RC Oscillator selectable frequencies */ -#define CKGR_MOR_MOSCRCF_4MHZ (0 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCRCF_8MHZ (1 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCRCF_12MHZ (2 << CKGR_MOR_MOSCRCF_SHIFT) - -/* Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCEN (0x01 << 3) - -/* Main Crystal Oscillator Bypass */ -#define CKGR_MOR_MOSCXTBY (0x01 << 1) - -/* Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTEN (0x01 << 0) - - -/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */ - -/* Main Clock Ready */ -#define CKGR_MCFR_MAINFRDY (0x01 << 16) - -/* Main Clock Frequency */ -#define CKGR_MCFR_MAINF_SHIFT 0 -#define CKGR_MCFR_MAINF_MASK (0xFFFF << CKGR_MCFR_MAINF_SHIFT) - - -/* --- PMC Clock Generator PLLA Register (CKGR_PLLAR) ---------------------- */ - -/* must be set to program CKGR_PLLAR */ -#define CKGR_PLLAR_ONE (0x01 << 29) - -/* PLLA Multiplier */ -#define CKGR_PLLAR_MULA_SHIFT 16 -#define CKGR_PLLAR_MULA_MASK (0x7FF << CKGR_PLLAR_MULA_SHIFT) - -/* PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT_SHIFT 8 -#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << CKGR_PLLAR_PLLACOUNT_SHIFT) - -/* Divider */ -#define CKGR_PLLAR_DIVA_SHIFT 0 -#define CKGR_PLLAR_DIVA_MASK (0xFF << CKGR_PLLAR_DIVA_SHIFT) - - -/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */ - -/* Processor Clock Prescaler */ -#define PMC_MCKR_PRES_SHIFT 4 -#define PMC_MCKR_PRES_MASK (0x07 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_1 (0 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_2 (1 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_4 (2 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_8 (3 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_16 (4 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_32 (5 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_64 (6 << PMC_MCKR_PRES_SHIFT) -#define PMC_MCKR_PRES_CLK_3 (7 << PMC_MCKR_PRES_SHIFT) - -/* Master Clock Source Selection */ -#define PMC_MCKR_CSS_SHIFT 0 -#define PMC_MCKR_CSS_MASK (0x03 << PMC_MCKR_CSS_SHIFT) -#define PMC_MCKR_CSS_SLOW_CLK (0 << PMC_MCKR_CSS_SHIFT) -#define PMC_MCKR_CSS_MAIN_CLK (1 << PMC_MCKR_CSS_SHIFT) -#define PMC_MCKR_CSS_PLLA_CLK (2 << PMC_MCKR_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */ - -/* Programmable Clock Prescaler */ -#define PMC_PCK0_PRES_SHIFT 4 -#define PMC_PCK0_PRES_MASK (0x07 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_1 (0 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_2 (1 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_4 (2 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_8 (3 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_16 (4 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_32 (5 << PMC_PCK0_PRES_SHIFT) -#define PMC_PCK0_PRES_CLK_64 (6 << PMC_PCK0_PRES_SHIFT) - -/* Master Clock Source Selection */ -#define PMC_PCK0_CSS_SHIFT 0 -#define PMC_PCK0_CSS_MASK (0x07 << PMC_PCK0_CSS_SHIFT) -#define PMC_PCK0_CSS_SLOW_CLK (0 << PMC_PCK0_CSS_SHIFT) -#define PMC_PCK0_CSS_MAIN_CLK (1 << PMC_PCK0_CSS_SHIFT) -#define PMC_PCK0_CSS_PLLA_CLK (2 << PMC_PCK0_CSS_SHIFT) -#define PMC_PCK0_CSS_MCK (4 << PMC_PCK0_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */ - -/* Programmable Clock Prescaler */ -#define PMC_PCK1_PRES_SHIFT 4 -#define PMC_PCK1_PRES_MASK (0x07 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_1 (0 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_2 (1 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_4 (2 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_8 (3 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_16 (4 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_32 (5 << PMC_PCK1_PRES_SHIFT) -#define PMC_PCK1_PRES_CLK_64 (6 << PMC_PCK1_PRES_SHIFT) - -/* Master Clock Source Selection */ -#define PMC_PCK1_CSS_SHIFT 0 -#define PMC_PCK1_CSS_MASK (0x07 << PMC_PCK1_CSS_SHIFT) -#define PMC_PCK1_CSS_SLOW_CLK (0 << PMC_PCK1_CSS_SHIFT) -#define PMC_PCK1_CSS_MAIN_CLK (1 << PMC_PCK1_CSS_SHIFT) -#define PMC_PCK1_CSS_PLLA_CLK (2 << PMC_PCK1_CSS_SHIFT) -#define PMC_PCK1_CSS_MCK (4 << PMC_PCK1_CSS_SHIFT) - - -/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */ - -/* Programmable Clock Prescaler */ -#define PMC_PCK2_PRES_SHIFT 4 -#define PMC_PCK2_PRES_MASK (0x07 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_1 (0 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_2 (1 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_4 (2 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_8 (3 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_16 (4 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_32 (5 << PMC_PCK2_PRES_SHIFT) -#define PMC_PCK2_PRES_CLK_64 (6 << PMC_PCK2_PRES_SHIFT) - -/* Master Clock Source Selection */ -#define PMC_PCK2_CSS_SHIFT 0 -#define PMC_PCK2_CSS_MASK (0x07 << PMC_PCK2_CSS_SHIFT) -#define PMC_PCK2_CSS_SLOW_CLK (0 << PMC_PCK2_CSS_SHIFT) -#define PMC_PCK2_CSS_MAIN_CLK (1 << PMC_PCK2_CSS_SHIFT) -#define PMC_PCK2_CSS_PLLA_CLK (2 << PMC_PCK2_CSS_SHIFT) -#define PMC_PCK2_CSS_MCK (4 << PMC_PCK2_CSS_SHIFT) - - -/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */ - -/* Clock Failure Detector Event Interrupt Enable */ -#define PMC_IER_CFDEV (0x01 << 18) - -/* Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x01 << 17) - -/* Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x01 << 16) - -/* Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x01 << 10) - -/* Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x01 << 9) - -/* Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x01 << 8) - -/* Master Clock Ready Interrupt Enable */ -#define PMC_IER_MCKRDY (0x01 << 3) - -/* PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKA (0x01 << 1) - -/* Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_MOSCXTS (0x01 << 0) - - -/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */ - -/* Clock Failure Detector Event Interrupt Disable */ -#define PMC_IDR_CFDEV (0x01 << 18) - -/* Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x01 << 17) - -/* Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x01 << 16) - -/* Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x01 << 10) - -/* Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x01 << 9) - -/* Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x01 << 8) - -/* Master Clock Ready Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x01 << 3) - -/* PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKA (0x01 << 1) - -/* Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_MOSCXTS (0x01 << 0) - - -/* --- PMC Status Register (PMC_SR) ---------------------------------------- */ - -/* Clock Failure Detector Fault Output Status */ -#define PMC_SR_FOS (0x01 << 20) - -/* Clock Failure Detector Status */ -#define PMC_SR_CFDS (0x01 << 19) - -/* Clock Failure Detector Event */ -#define PMC_SR_CFDEV (0x01 << 18) - -/* Main On-Chip RC Oscillator Status */ -#define PMC_SR_MOSCRCS (0x01 << 17) - -/* Main Oscillator Selection Status */ -#define PMC_SR_MOSCSELS (0x01 << 16) - -/* Programmable Clock 2 Ready Status */ -#define PMC_SR_PCKRDY2 (0x01 << 10) - -/* Programmable Clock 1 Ready Status */ -#define PMC_SR_PCKRDY1 (0x01 << 9) - -/* Programmable Clock 0 Ready Status */ -#define PMC_SR_PCKRDY0 (0x01 << 8) - -/* Slow Clock Oscillator Selection */ -#define PMC_SR_OSCSELS (0x01 << 7) - -/* Master Clock Status */ -#define PMC_SR_MCKRDY (0x01 << 3) - -/* PLLA Lock Status */ -#define PMC_SR_LOCKA (0x01 << 1) - -/* Main XTAL Oscillator Status */ -#define PMC_SR_MOSCXTS (0x01 << 0) - - -/* --- PMC Interrupt Mask Register (PMC_IMR) ------------------------------- */ - -/* Clock Failure Detector Event Interrupt Mask */ -#define PMC_IMR_CFDEV (0x01 << 18) - -/* Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x01 << 17) - -/* Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x01 << 16) - -/* Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x01 << 10) - -/* Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x01 << 9) - -/* Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x01 << 8) - -/* Master Clock Ready Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x01 << 3) - -/* PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKA (0x01 << 1) - -/* Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_MOSCXTS (0x01 << 0) - - -/* --- PMC Fast Startup Mode Register (PMC_FSMR) --------------------------- */ - -/* Low Power Mode */ -#define PMC_FSMR_LPM (0x01 << 20) - -/* USB Alarm Enable */ -#define PMC_FSMR_USBAL (0x01 << 18) - -/* RTC Alarm Enable */ -#define PMC_FSMR_RTCAL (0x01 << 17) - -/* RTC Alarm Enable */ -#define PMC_FSMR_RTTAL (0x01 << 16) - -/* Fast Startup Input Enable 0 to 15 */ -#define PMC_FSMR_FSTT15 (0x01 << 15) -#define PMC_FSMR_FSTT14 (0x01 << 14) -#define PMC_FSMR_FSTT13 (0x01 << 13) -#define PMC_FSMR_FSTT12 (0x01 << 12) -#define PMC_FSMR_FSTT11 (0x01 << 11) -#define PMC_FSMR_FSTT10 (0x01 << 10) -#define PMC_FSMR_FSTT9 (0x01 << 9) -#define PMC_FSMR_FSTT8 (0x01 << 8) -#define PMC_FSMR_FSTT7 (0x01 << 7) -#define PMC_FSMR_FSTT6 (0x01 << 6) -#define PMC_FSMR_FSTT5 (0x01 << 5) -#define PMC_FSMR_FSTT4 (0x01 << 4) -#define PMC_FSMR_FSTT3 (0x01 << 3) -#define PMC_FSMR_FSTT2 (0x01 << 2) -#define PMC_FSMR_FSTT1 (0x01 << 1) -#define PMC_FSMR_FSTT0 (0x01 << 0) - - -/* --- PMC Fast Startup Polarity Register (PMC_FSPR) ----------------------- */ - -/* Fast Startup Input Polarity x */ -#define PMC_FSPR_FSTP15 (0x01 << 15) -#define PMC_FSPR_FSTP14 (0x01 << 14) -#define PMC_FSPR_FSTP13 (0x01 << 13) -#define PMC_FSPR_FSTP12 (0x01 << 12) -#define PMC_FSPR_FSTP11 (0x01 << 11) -#define PMC_FSPR_FSTP10 (0x01 << 10) -#define PMC_FSPR_FSTP9 (0x01 << 9) -#define PMC_FSPR_FSTP8 (0x01 << 8) -#define PMC_FSPR_FSTP7 (0x01 << 7) -#define PMC_FSPR_FSTP6 (0x01 << 6) -#define PMC_FSPR_FSTP5 (0x01 << 5) -#define PMC_FSPR_FSTP4 (0x01 << 4) -#define PMC_FSPR_FSTP3 (0x01 << 3) -#define PMC_FSPR_FSTP2 (0x01 << 2) -#define PMC_FSPR_FSTP1 (0x01 << 1) -#define PMC_FSPR_FSTP0 (0x01 << 0) - - -/* --- PMC Fault Output Clear Register (PMC_FOCR) -------------------------- */ - -/* Fault Output Clear */ -#define PMC_FOCR_FOCLR (0x01 << 0) - - -/* --- PMC Write Protect Mode Register (PMC_WPMR) -------------------------- */ - -/* Write Protect Key */ -#define PMC_WPMR_WPKEY_SHIFT 8 -#define PMC_WPMR_WPKEY (0x504D43 << PMC_WPMR_WPKEY_SHIFT) - -/* Write Protect Enable */ -#define PMC_WPMR_WPEN (0x01 << 0) - - -/* --- PMC Write Protect Status Register (PMC_WPSR) ------------------------ */ - -/* Write Protect Violation Source */ -#define PMC_WPSR_WPVSRC_SHIFT 8 -#define PMC_WPSR_WPVSRC_MASK (0xFFFF << PMC_WPSR_WPVSRC_SHIFT) - -/* Write Protect Violation Status */ -#define PMC_WPSR_WPVS (0x01 << 0) - - - - -extern uint32_t pmc_mck_frequency; - -enum mck_src { - MCK_SRC_SLOW = 0, - MCK_SRC_MAIN = 1, - MCK_SRC_PLLA = 2, - MCK_SRC_UPLL = 3, -}; - -void pmc_mck_set_source(enum mck_src src); -void pmc_xtal_enable(bool en, uint8_t startup_time); -void pmc_plla_config(uint8_t mul, uint8_t div); -void pmc_peripheral_clock_enable(uint8_t pid); -void pmc_peripheral_clock_disable(uint8_t pid); -void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void); -void pmc_clock_setup_in_rc_4mhz_out_84mhz(void); - -#endif - -#else -#warning "pmc_common_all.h should not be included explicitly, only via pmc.h" -#endif diff --git a/libopencm3/include/libopencm3/sam/common/smc_common_3a3u3x.h b/libopencm3/include/libopencm3/sam/common/smc_common_3a3u3x.h deleted file mode 100644 index 59a16c2..0000000 --- a/libopencm3/include/libopencm3/sam/common/smc_common_3a3u3x.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SMC_H -#define LIBOPENCM3_SMC_H - -#include - - -/* Chip Select Defines */ -#define SMC_CS_0 0 -#define SMC_CS_1 1 -#define SMC_CS_2 2 -#define SMC_CS_3 3 - - -/* --- Static Memory Controller (SMC) registers ---------------------------- */ - -/* NFC Configuration Register */ -#define SMC_CFG MMIO32(SMC_BASE + 0x00) - -/* NFC Control Register */ -#define SMC_CTRL MMIO32(SMC_BASE + 0x04) - -/* NFC Status Register */ -#define SMC_SR MMIO32(SMC_BASE + 0x08) - -/* NFC Interrupt Enable Register */ -#define SMC_IER MMIO32(SMC_BASE + 0x0C) - -/* NFC Interrupt Disable Register */ -#define SMC_IDR MMIO32(SMC_BASE + 0x10) - -/* Interrupt Mask Register */ -#define SMC_IMR MMIO32(SMC_BASE + 0x14) - -/* NFC Address Cycle Zero Register */ -#define SMC_ADDR MMIO32(SMC_BASE + 0x18) - -/* Bank Address Register */ -#define SMC_BANK MMIO32(SMC_BASE + 0x1C) - -/* ECC Control Register */ -#define SMC_ECC_CTRL MMIO32(SMC_BASE + 0x20) - -/* ECC Mode Register */ -#define SMC_ECC_MD MMIO32(SMC_BASE + 0x24) - -/* ECC Status 1 Register */ -#define SMC_ECC_SR1 MMIO32(SMC_BASE + 0x28) - -/* ECC Parity 0 Register */ -#define SMC_ECC_PR0 MMIO32(SMC_BASE + 0x2C) - -/* ECC parity 1 Register */ -#define SMC_ECC_PR1 MMIO32(SMC_BASE + 0x30) - -/* ECC status 2 Register */ -#define SMC_ECC_SR2 MMIO32(SMC_BASE + 0x34) - -/* ECC parity 2 Register */ -#define SMC_ECC_PR2 MMIO32(SMC_BASE + 0x38) - -/* ECC parity 3 Register */ -#define SMC_ECC_PR3 MMIO32(SMC_BASE + 0x3C) - -/* ECC parity 4 Register */ -#define SMC_ECC_PR4 MMIO32(SMC_BASE + 0x40) - -/* ECC parity 5 Register */ -#define SMC_ECC_PR5 MMIO32(SMC_BASE + 0x44) - -/* ECC parity 6 Register */ -#define SMC_ECC_PR6 MMIO32(SMC_BASE + 0x48) - -/* ECC parity 7 Register */ -#define SMC_ECC_PR7 MMIO32(SMC_BASE + 0x4C) - -/* ECC parity 8 Register */ -#define SMC_ECC_PR8 MMIO32(SMC_BASE + 0x50) - -/* ECC parity 9 Register */ -#define SMC_ECC_PR9 MMIO32(SMC_BASE + 0x54) - -/* ECC parity 10 Register */ -#define SMC_ECC_PR10 MMIO32(SMC_BASE + 0x58) - -/* ECC parity 11 Register */ -#define SMC_ECC_PR11 MMIO32(SMC_BASE + 0x5C) - -/* ECC parity 12 Register */ -#define SMC_ECC_PR12 MMIO32(SMC_BASE + 0x60) - -/* ECC parity 13 Register */ -#define SMC_ECC_PR13 MMIO32(SMC_BASE + 0x64) - -/* ECC parity 14 Register */ -#define SMC_ECC_PR14 MMIO32(SMC_BASE + 0x68) - -/* ECC parity 15 Register */ -#define SMC_ECC_PR15 MMIO32(SMC_BASE + 0x6C) - -/* Setup Register */ -#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \ - + 0x70) - -/* Pulse Register */ -#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \ - + 0x74) - -/* Cycle Register */ -#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \ - + 0x78) - -/* Timings Register */ -#define SMC_TIMINGS(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \ - + 0x7C) - -/* Mode Register */ -#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \ - + 0x80) - -/* Off Chip Memory Scrambling Mode Register */ -#define SMC_OCMS MMIO32(SMC_BASE + 0x110) - -/* Off Chip Memory Scrambling KEY1 Register */ -#define SMC_KEY1 MMIO32(SMC_BASE + 0x114) - -/* Off Chip Memory Scrambling KEY2 Register */ -#define SMC_KEY2 MMIO32(SMC_BASE + 0x118) - -/* Write Protection Control Register */ -#define SMC_WPCR MMIO32(SMC_BASE + 0x1E4) - -/* Write Protect Status Register */ -#define SMC_WPSR MMIO32(SMC_BASE + 0x1E8) - - -/* --- Register contents --------------------------------------------------- */ - - -/* --- SMC NFC Configuration Register (SMC_CFG) ---------------------------- */ - -/* Data Timeout Multiplier */ -#define SMC_CFG_DTOMUL_SHIFT 20 -#define SMC_CFG_DTOMUL_MASK (0x07 << SMC_DTOMUL_SHIFT) - -/* Data Timeout Multiplier Values */ -#define SMC_CFG_DTOMUL_X1 (0x00 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X16 (0x01 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X128 (0x02 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X256 (0x03 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X1024 (0x04 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X4096 (0x05 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X65536 (0x06 << SMC_DTOMUL_SHIFT) -#define SMC_CFG_DTOMUL_X1048576 (0x07 << SMC_DTOMUL_SHIFT) - -/* Data Timeout Cycle Number */ -#define SMC_CFG_DTOCYC_SHIFT 16 -#define SMC_CFG_DTOCYC_MASK (0x0F << SMC_DTOCYC_SHIFT) - -/* Ready/Busy Signal Edge Detection */ -#define SMC_CFG_RBEDGE (1 << 13) - -/* Rising/Falling Edge Detection Control */ -#define SMC_CFG_EDGECTRL (1 << 12) - -/* Read Spare Area */ -#define SMC_CFG_RSPARE (1 << 9) - -/* Write Spare Area */ -#define SMC_CFG_WSPARE (1 << 8) - -/* NAND Flash Page Size */ -#define SMC_CFG_PAGESIZE_SHIFT 0 -#define SMC_CFG_PAGESIZE_MASK (0x03 << SMC_CFG_PAGESIZE_SHIFT) - -/* NAND Flash Page Size Values */ -#define SMC_CFG_PAGESIZE_PS512_16 (0x00 << SMC_CFG_PAGESIZE_SHIFT) -#define SMC_CFG_PAGESIZE_PS1024_32 (0x01 << SMC_CFG_PAGESIZE_SHIFT) -#define SMC_CFG_PAGESIZE_PS2048_64 (0x02 << SMC_CFG_PAGESIZE_SHIFT) -#define SMC_CFG_PAGESIZE_PS4096_128 (0x03 << SMC_CFG_PAGESIZE_SHIFT) - - -/* --- SMC NFC Control Register (SMC_CTRL) --------------------------------- */ - -/* NAND Flash Controller Disable */ -#define SMC_CTRL_NFCDIS (1 << 1) - -/* NAND Flash Controller Enable */ -#define SMC_CTRL_NFCEN (1 << 0) - - -/* --- SMC NFC Status Register (SMC_SR) ------------------------------------ */ - -/* Ready/Busy Line 0 Edge Detected */ -#define SMC_SR_RB_EDGE0 (1 << 24) - -/* NFC Access Size Error */ -#define SMC_SR_NFCASE (1 << 23) - -/* Accessing While Busy */ -#define SMC_SR_AWB (1 << 22) - -/* Undefined Area Error */ -#define SMC_SR_UNDEF (1 << 21) - -/* Data Timeout Error */ -#define SMC_SR_DTOE (1 << 20) - -/* Command Done */ -#define SMC_SR_CMDDONE (1 << 17) - -/* NFC Data Transfer Terminated */ -#define SMC_SR_XFRDONE (1 << 16) - -/* NFC Chip Select ID */ -#define SMC_SR_NFCSID_SHIFT 12 -#define SMC_SR_NFCSID_MASK (0x07 << SMC_SR_NFCSID_SHIFT) - -/* NFC Write/Read Operation */ -#define SMC_SR_NFCWR (1 << 11) - -/* NFC Busy */ -#define SMC_SR_NFCBUSY (1 << 8) - -/* Selected Ready Busy Falling Edge Detected */ -#define SMC_SR_RB_FALL (1 << 5) - -/* Selected Ready Busy Rising Edge Detected */ -#define SMC_SR_RB_RISE (1 << 4) - -/* NAND Flash Controller status */ -#define SMC_SR_SMCSTS (1 << 0) - - -/* --- SMC NFC Interrupt Enable Register (SMC_IER) ------------------------- */ - -/* Ready/Busy Line 0 Interrupt Enable */ -#define SMC_IER_RB_EDGE0 (1 << 24) - -/* NFC Access Size Error Interrupt Enable */ -#define SMC_IER_NFCASE (1 << 23) - -/* Accessing While Busy Interrupt Enable */ -#define SMC_IER_AWB (1 << 22) - -/* Undefined Area Access Interrupt Enable */ -#define SMC_IER_UNDEF (1 << 21) - -/* Data Timeout Error Interrupt Enable */ -#define SMC_IER_DTOE (1 << 20) - -/* Command Done Interrupt Enable */ -#define SMC_IER_CMDDONE (1 << 17) - -/* Transfer Done Interrupt Enable */ -#define SMC_IER_XFRDONE (1 << 16) - -/* Ready Busy Falling Edge Detection Interrupt Enable */ -#define SMC_IER_RB_FALL (1 << 5) - -/* Ready Busy Rising Edge Detection Interrupt Enable */ -#define SMC_IER_RB_RISE (1 << 4) - - -/* --- SMC NFC Interrupt Disable Register (SMC_IDR) ------------------------ */ - -/* Ready/Busy Line 0 Interrupt Disable */ -#define SMC_IDR_RB_EDGE0 (1 << 24) - -/* NFC Access Size Error Interrupt Disable */ -#define SMC_IDR_NFCASE (1 << 23) - -/* Accessing While Busy Interrupt Disable */ -#define SMC_IDR_AWB (1 << 22) - -/* Undefined Area Access Interrupt Disable */ -#define SMC_IDR_UNDEF (1 << 21) - -/* Data Timeout Error Interrupt Disable */ -#define SMC_IDR_DTOE (1 << 20) - -/* Command Done Interrupt Disable */ -#define SMC_IDR_CMDDONE (1 << 17) - -/* Transfer Done Interrupt Disable */ -#define SMC_IDR_XFRDONE (1 << 16) - -/* Ready Busy Falling Edge Detection Interrupt Disable */ -#define SMC_IDR_RB_FALL (1 << 5) - -/* Ready Busy Rising Edge Detection Interrupt Disable */ -#define SMC_IDR_RB_RISE (1 << 4) - - -/* --- SMC NFC Interrupt Mask Register (SMC_IMR) --------------------------- */ - -/* Ready/Busy Line 0 Interrupt Mask */ -#define SMC_IMR_RB_EDGE0 (1 << 24) - -/* NFC Access Size Error Interrupt Mask */ -#define SMC_IMR_NFCASE (1 << 23) - -/* Accessing While Busy Interrupt Mask */ -#define SMC_IMR_AWB (1 << 22) - -/* Undefined Area Access Interrupt Mask */ -#define SMC_IMR_UNDEF (1 << 21) - -/* Data Timeout Error Interrupt Mask */ -#define SMC_IMR_DTOE (1 << 20) - -/* Command Done Interrupt Mask */ -#define SMC_IMR_CMDDONE (1 << 17) - -/* Transfer Done Interrupt Mask */ -#define SMC_IMR_XFRDONE (1 << 16) - -/* Ready Busy Falling Edge Detection Interrupt Mask */ -#define SMC_IMR_RB_FALL (1 << 5) - -/* Ready Busy Rising Edge Detection Interrupt Mask */ -#define SMC_IMR_RB_RISE (1 << 4) - - -/* --- SMC NFC Address Cycle Zero Register (SMC_ADDR) ---------------------- */ - -/* NAND Flash Array Address cycle 0 */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT 0 -#define SMC_ADDR_ADDR_CYCLE0_MASK (0xFF << SMC_ADDR_ADDR_CYCLE0_SHIFT) - - -/* --- SMC NFC Bank Register (SMC_BANK) ------------------------------------ */ - -/* Bank Identifier */ -#define SMC_BANK_BANK_SHIFT 0 -#define SMC_BANK_BANK_MASK (0x07 << SMC_BANK_BANK_SHIFT) - - -/* --- SMC ECC Control Register (SMC_ECC_CTRL) ----------------------------- */ - -/* Software Reset */ -#define SMC_ECC_CTRL_SWRST (1 << 1) - -/* Reset ECC */ -#define SMC_ECC_CTRL_RST (1 << 0) - - -/* --- SMC ECC MODE Register (SMC_ECC_MD) ---------------------------------- */ - -/* Type of Correction */ -#define SMC_ECC_MD_TYPCORREC_SHIFT 4 -#define SMC_ECC_MD_TYPCORREC_MASK (0x03 << SMC_ECC_MD_TYPCORREC_SHIFT) - -/* Type of Correction Values */ -#define SMC_ECC_MD_TYPCORREC_CPAGE (0x00 << SMC_ECC_MD_TYPCORREC_SHIFT) -#define SMC_ECC_MD_TYPCORREC_C256B (0x01 << SMC_ECC_MD_TYPCORREC_SHIFT) -#define SMC_ECC_MD_TYPCORREC_C512B (0x02 << SMC_ECC_MD_TYPCORREC_SHIFT) - -/* ECC Page Size */ -#define SMC_ECC_MD_ECC_PAGESIZE_SHIFT 0 -#define SMC_ECC_MD_ECC_PAGESIZE_MASK (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT) - -/* ECC Page Size Values */ -#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 \ - (0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT) -#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 \ - (0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT) -#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 \ - (0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT) -#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 \ - (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT) - - -/* --- SMC ECC Status Register 1 (SMC_ECC_SR1) ----------------------------- */ -/* currently unimplemented */ - - -/* --- SMC ECC Status Register 2 (SMC_ECC_SR2) ----------------------------- */ -/* currently unimplemented */ - - -/* --- SMC ECC Parity Register 0 (SMC_ECC_PR0) ----------------------------- */ -/* currently unimplemented */ - - -/* --- SMC ECC Parity Register 1 (SMC_ECC_PR1) ----------------------------- */ -/* currently unimplemented */ - - -/* --- SMC ECC Parity Registers (SMC_ECC_PRx) ------------------------------ */ -/* currently unimplemented */ - - -/* --- SMC Setup Register (SMC_SETUPx) ------------------------------------- */ - -/* NCS Setup length in Read access */ -#define SMC_SETUP_NCS_RD_SETUP_SHIFT 24 -#define SMC_SETUP_NCS_RD_SETUP_MASK (0x3F << SMC_SETUP_NCS_RD_SETUP_SHIFT) - -/* NRD Setup length */ -#define SMC_SETUP_NRD_SETUP_SHIFT 16 -#define SMC_SETUP_NRD_SETUP_MASK (0x3F << SMC_SETUP_NRD_SETUP_SHIFT) - -/* NCS Setup length in Write access */ -#define SMC_SETUP_NCS_WR_SETUP_SHIFT 8 -#define SMC_SETUP_NCS_WR_SETUP_MASK (0x3F << SMC_SETUP_NCS_WR_SETUP_SHIFT) - -/* NWE Setup Length */ -#define SMC_SETUP_NWE_SETUP_SHIFT 0 -#define SMC_SETUP_NWE_SETUP_MASK (0x3F << SMC_SETUP_NWE_SETUP_SHIFT) - - -/* --- SMC Pulse Register (SMC_PULSEx) ------------------------------------- */ - -/* NCS Pulse Length in READ Access */ -#define SMC_PULSE_NCS_RD_PULSE_SHIFT 24 -#define SMC_PULSE_NCS_RD_PULSE_MASK (0x3F << SMC_PULSE_NCS_RD_PULSE_SHIFT) - -/* NRD Pulse Length */ -#define SMC_PULSE_NRD_PULSE_SHIFT 16 -#define SMC_PULSE_NRD_PULSE_MASK (0x3F << SMC_PULSE_NRD_PULSE_SHIFT) - -/* NCS Pulse Length in WRITE Access */ -#define SMC_PULSE_NCS_WR_PULSE_SHIFT 8 -#define SMC_PULSE_NCS_WR_PULSE_MASK (0x3F << SMC_PULSE_NCS_WR_PULSE_SHIFT) - -/* NWE Pulse Length */ -#define SMC_PULSE_NWE_PULSE_SHIFT 0 -#define SMC_PULSE_NWE_PULSE_MASK (0x3F << SMC_PULSE_NWE_PULSE_SHIFT) - - -/* --- SMC Cycle Register (SMC_CYCLEx) ------------------------------------- */ - -/* Total Read Cycle Length */ -#define SMC_CYCLE_NRD_CYCLE_SHIFT 16 -#define SMC_CYCLE_NRD_CYCLE_MASK (0x1FF << SMC_CYCLE_NRD_CYCLE_SHIFT) - -/* Total Write Cycle Length */ -#define SMC_CYCLE_NWE_CYCLE_SHIFT 0 -#define SMC_CYCLE_NWE_CYCLE_MASK (0x1FF << SMC_CYCLE_NWE_CYCLE_SHIFT) - - -/* --- SMC Timings Register (SMC_TIMINGSx) --------------------------------- */ - -/* NAND Flash Selection */ -#define SMC_TIMINGS_NFSEL (1 << 31) - -/* Ready/Busy Line Selection */ -#define SMC_TIMINGS_RBNSEL_SHIFT 28 -#define SMC_TIMINGS_RBNSEL_MASK (0x07 << SMC_TIMINGS_RBNSEL_SHIFT) - -/* WEN High to REN to Busy */ -#define SMC_TIMINGS_TWB_SHIFT 24 -#define SMC_TIMINGS_TWB_MASK (0x0F << SMC_TIMINGS_TWB_SHIFT) - -/* Ready to REN Low Delay */ -#define SMC_TIMINGS_TRR_SHIFT 16 -#define SMC_TIMINGS_TRR_MASK (0x0F << SMC_TIMINGS_TRR_SHIFT) - -/* Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS_OCMS (1 << 12) - -/* ALE to REN Low Delay */ -#define SMC_TIMINGS_TAR_SHIFT 8 -#define SMC_TIMINGS_TAR_MASK (0x0F << SMC_TIMINGS_TAR_SHIFT) - -/* ALE to Data Start */ -#define SMC_TIMINGS_TADL_SHIFT 4 -#define SMC_TIMINGS_TADL_MASK (0x0F << SMC_TIMINGS_TADL_SHIFT) - -/* CLE to REN Low Delay */ -#define SMC_TIMINGS_TCLR_SHIFT 0 -#define SMC_TIMINGS_TCLR_MASK (0x0F << SMC_TIMINGS_TCLR_SHIFT) - - -/* --- SMC Mode Register (SMC_MODEx) --------------------------------------- */ - -/* TDF Optimization */ -#define SMC_MODE_TDF_MODE (1 << 20) - -/* Data Float Time */ -#define SMC_MODE_TDF_CYCLES_SHIFT 16 -#define SMC_MODE_TDF_CYCLES_MASK (0x0F << SMC_MODE_TDF_CYCLES_SHIFT) - -/* Data Bus Width */ -#define SMC_MODE_DBW (1 << 12) - -/* Data Bus Width Values */ -#define SMC_MODE_DBW_BIT_8 (0 << 12) -#define SMC_MODE_DBW_BIT_16 (1 << 12) - -/* Byte Access Type */ -#define SMC_MODE_BAT (1 << 8) - -/* NWAIT Mode */ -#define SMC_MODE_EXNW_MODE_SHIFT 4 -#define SMC_MODE_EXNW_MODE_MASK (0x03 << SMC_MODE_EXNW_MODE_SHIFT) - -/* NWAIT Mode Values */ -#define SMC_MODE_EXNW_MODE_DISABLED (0x00 << SMC_MODE_EXNW_MODE_SHIFT) -#define SMC_MODE_EXNW_MODE_FROZEN (0x02 << SMC_MODE_EXNW_MODE_SHIFT) -#define SMC_MODE_EXNW_MODE_READY (0x03 << SMC_MODE_EXNW_MODE_SHIFT) - -/* Write Mode */ -#define SMC_MODE_WRITE_MODE (1 << 1) - -/* Read Mode */ -#define SMC_MODE_READ_MODE (1 << 0) - - -/* --- SMC OCMS Register (SMC_OCMS) ---------------------------------------- */ - -/* SRAM Scrambling Enable */ -#define SMC_OCMS_SRSE (1 << 1) - -/* Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SMSE (1 << 0) - - -/* --- SMC Write Protection Control (SMC_WPCR) ----------------------------- */ - -/* Write Protect Key */ -#define SMC_WPCR_WPKEY_SHIFT 8 -#define SMC_WPCR_WPKEY_KEY (0x534D43 << SMC_WPCR_WPKEY_SHIFT) - -/* Write Protect Enable */ -#define SMC_WPCR_WPEN (1 << 0) - - -/* --- SMC Write Protection Status (SMC_WPSR) ------------------------------ */ - -/* Write Protection Violation Source */ -#define SMC_WPSR_WP_VSRC_SHIFT 8 -#define SMC_WPSR_WP_VSRC_MASK (0xFFFF << SMC_WPSR_WP_VSRC_SHIFT) - -/* Write Protection Violation Status */ -#define SMC_WPSR_WP_VS_SHIFT 0 -#define SMC_WPSR_WP_VS_MASK (0x0F << SMC_WPSR_WP_VS_SHIFT) - - -#endif diff --git a/libopencm3/include/libopencm3/sam/d/irq.json b/libopencm3/include/libopencm3/sam/d/irq.json deleted file mode 100644 index e940482..0000000 --- a/libopencm3/include/libopencm3/sam/d/irq.json +++ /dev/null @@ -1,26 +0,0 @@ -{ - "irqs": [ - "pm", - "sysctrl", - "wdt", - "rtc", - "eic", - "nvmctrl", - "dmac", - "reserved1", - "evsys", - "sercom0", - "sercom1", - "sercom2", - "tcc0", - "tc1", - "tc2", - "adc", - "ac", - "dac", - "ptc" - ], - "partname_humanreadable": "Atmel SAMD series", - "partname_doxygen": "SAMD", - "includeguard": "LIBOPENCM3_SAMD_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/d/memorymap.h b/libopencm3/include/libopencm3/sam/d/memorymap.h deleted file mode 100644 index 5633a05..0000000 --- a/libopencm3/include/libopencm3/sam/d/memorymap.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAMD_MEMORYMAP_H -#define SAMD_MEMORYMAP_H - -#include - -/* --- SAMD AHB-APB bridge A -------------------------------------------- */ -#define PM_BASE (0x40000400U) -#define SYSCTRL_BASE (0x40000800U) -#define GCLK_BASE (0x40000c00U) -#define WDT_BASE (0x40001000U) -#define RTC_BASE (0x40001400U) -#define EIC_BASE (0x40001800U) -/* --- SAMD AHB-APB bridge B -------------------------------------------- */ -#define DSU_BASE (0x41002000U) -#define NVMCTRL_BASE (0x41004000U) -#define PORT_BASE (0x41004400U) -#define DMAC_BASE (0x41004800U) -#define MTB_BASE (0x41006000U) -/* --- SAMD AHB-APB bridge C -------------------------------------------- */ -#define EVSYS_BASE (0x42000400U) -#define SERCOM0_BASE (0x42000800U) -#define SERCOM1_BASE (0x42000c00U) -#define SERCOM2_BASE (0x42001000U) -#define TCC0_BASE (0x42001400U) -#define TC1_BASE (0x42001800U) -#define TC2_BASE (0x42001c00U) -#define ADC_BASE (0x42002000U) -#define AC_BASE (0x42002400U) -#define DAC_BASE (0x42002800U) -#define PTC_BASE (0x42002c00U) - -#endif diff --git a/libopencm3/include/libopencm3/sam/d/port.h b/libopencm3/include/libopencm3/sam/d/port.h deleted file mode 100644 index 92ba7f1..0000000 --- a/libopencm3/include/libopencm3/sam/d/port.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -/* --- Convenience macros ------------------------------------------------ */ - -#define PORTA (PORT_BASE + 0) -#define PORTB (PORT_BASE + 0x80) - -/* --- PORT registers ----------------------------------------------------- */ - -/* Direction register */ -#define PORT_DIR(port) MMIO32((port) + 0x0000) - -/* Direction clear register */ -#define PORT_DIRCLR(port) MMIO32((port) + 0x0004) - -/* Direction set register */ -#define PORT_DIRSET(port) MMIO32((port) + 0x0008) - -/* Direction toggle register */ -#define PORT_DIRTGL(port) MMIO32((port) + 0x000c) - -/* output register */ -#define PORT_OUT(port) MMIO32((port) + 0x0010) - -/* output clear register */ -#define PORT_OUTCLR(port) MMIO32((port) + 0x0014) - -/* output set register */ -#define PORT_OUTSET(port) MMIO32((port) + 0x0018) - -/* output toggle register */ -#define PORT_OUTTGL(port) MMIO32((port) + 0x001c) - -/* input register */ -#define PORT_IN(port) MMIO32((port) + 0x0020) - -/* Control register */ -#define PORT_CTRL(port) MMIO32((port) + 0x0024) - -/* Write configuration register */ -#define PORT_WRCONFIG(port) MMIO32((port) + 0x0028) - -/* Peripheral multiplexing registers */ -#define PORT_PMUX(port, n) MMIO8((port) + 0x0030 + (n)) - -/* Pin configuration registers */ -#define PORT_PINCFG(port, n) MMIO8((port) + 0x0040 + (n)) diff --git a/libopencm3/include/libopencm3/sam/eefc.h b/libopencm3/include/libopencm3/sam/eefc.h deleted file mode 100644 index eb6d4d0..0000000 --- a/libopencm3/include/libopencm3/sam/eefc.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_EEFC_H -#define SAM3X_EEFC_H - -#include -#include - -/* --- Convenience macros ------------------------------------------------ */ -#define EEFC EEFC_BASE -#define EEFC0 EEFC0_BASE -#define EEFC1 EEFC1_BASE - -/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */ -#define EEFC_FMR(port) MMIO32((port) + 0x00) -#define EEFC_FCR(port) MMIO32((port) + 0x04) -#define EEFC_FSR(port) MMIO32((port) + 0x08) -#define EEFC_FRR(port) MMIO32((port) + 0x0C) -/* 0x0010 - Reserved */ - - -/* EEFC Flash Mode Register (EEFC_FMR) */ -/* Bit [31:25] - Reserved */ -#define EEFC_FMR_FAM (0x01 << 24) -/* Bit [23:12] - Reserved */ -#define EEFC_FMR_FWS_MASK (0x0F << 8) -/* Bit [7:1] - Reserved */ -#define EEFC_FMR_FRDY (0x01 << 0) - -/* EEFC Flash Command Register (EEFC_FCR) */ -#define EEFC_FCR_FKEY (0x5A << 24) -#define EEFC_FCR_FARG_MASK (0xFFFF << 8) -#define EEFC_FCR_FCMD_MASK (0xFF << 0) -#define EEFC_FCR_FCMD_GETD (0x00 << 0) -#define EEFC_FCR_FCMD_WP (0x01 << 0) -#define EEFC_FCR_FCMD_WPL (0x02 << 0) -#define EEFC_FCR_FCMD_EWP (0x03 << 0) -#define EEFC_FCR_FCMD_EWPL (0x04 << 0) -#define EEFC_FCR_FCMD_EA (0x05 << 0) -#define EEFC_FCR_FCMD_SLB (0x08 << 0) -#define EEFC_FCR_FCMD_CLB (0x09 << 0) -#define EEFC_FCR_FCMD_GLB (0x0A << 0) -#define EEFC_FCR_FCMD_SGPB (0x0B << 0) -#define EEFC_FCR_FCMD_CGPB (0x0C << 0) -#define EEFC_FCR_FCMD_GGPB (0x0D << 0) -#define EEFC_FCR_FCMD_STUI (0x0E << 0) -#define EEFC_FCR_FCMD_SPUI (0x0F << 0) - -/* EEFC Flash Status Register (EEFC_FSR) */ -/* Bit [31:3] - Reserved */ -#define EEFC_FSR_FLOCKE (0x01 << 2) -#define EEFC_FSR_FCMDE (0x01 << 1) -#define EEFC_FSR_FRDY (0x01 << 0) - -static inline void eefc_set_latency(uint8_t wait) -{ -#if defined(SAM3A) || defined(SAM3U) || defined(SAM3X) - EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8); - EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8); -#elif defined(SAM3N) || defined(SAM3S) - EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8); -#endif -} - -#endif - diff --git a/libopencm3/include/libopencm3/sam/gpio.h b/libopencm3/include/libopencm3/sam/gpio.h deleted file mode 100644 index 852f6f5..0000000 --- a/libopencm3/include/libopencm3/sam/gpio.h +++ /dev/null @@ -1,36 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#elif defined(SAM4L) -# include -#else -# error "sam family not defined." -#endif diff --git a/libopencm3/include/libopencm3/sam/memorymap.h b/libopencm3/include/libopencm3/sam/memorymap.h deleted file mode 100644 index ad0bb4d..0000000 --- a/libopencm3/include/libopencm3/sam/memorymap.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM_MEMORYMAP_H -#define SAM_MEMORYMAP_H - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#elif defined(SAM4L) -# include -#elif defined(SAMD) -# include -#else -# error "Processor family not defined." -#endif - -#endif - diff --git a/libopencm3/include/libopencm3/sam/periph.h b/libopencm3/include/libopencm3/sam/periph.h deleted file mode 100644 index e1ae621..0000000 --- a/libopencm3/include/libopencm3/sam/periph.h +++ /dev/null @@ -1,32 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#else -# error "sam family not defined." -#endif diff --git a/libopencm3/include/libopencm3/sam/pio.h b/libopencm3/include/libopencm3/sam/pio.h deleted file mode 100644 index ac0ca3a..0000000 --- a/libopencm3/include/libopencm3/sam/pio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#else -# error "sam family not defined." -#endif diff --git a/libopencm3/include/libopencm3/sam/pm.h b/libopencm3/include/libopencm3/sam/pm.h deleted file mode 100644 index 4db6278..0000000 --- a/libopencm3/include/libopencm3/sam/pm.h +++ /dev/null @@ -1,24 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM4L) -# include -#else -# error "PM undefined for your processor family." -#endif diff --git a/libopencm3/include/libopencm3/sam/pmc.h b/libopencm3/include/libopencm3/sam/pmc.h deleted file mode 100644 index 4856f27..0000000 --- a/libopencm3/include/libopencm3/sam/pmc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#else -# error "sam family not defined." -#endif diff --git a/libopencm3/include/libopencm3/sam/pwm.h b/libopencm3/include/libopencm3/sam/pwm.h deleted file mode 100644 index fabb8b1..0000000 --- a/libopencm3/include/libopencm3/sam/pwm.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_PWM_H -#define SAM3X_PWM_H - -#include -#include - -/* --- Pulse Width Modulation (PWM) registers ----------------------- */ - -#define PWM_CLK MMIO32(PWM_BASE + 0x0000) -#define PWM_ENA MMIO32(PWM_BASE + 0x0004) -#define PWM_DIS MMIO32(PWM_BASE + 0x0008) -#define PWM_SR MMIO32(PWM_BASE + 0x000C) -#define PWM_IER1 MMIO32(PWM_BASE + 0x0010) -#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014) -#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018) -#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C) -#define PWM_SCM MMIO32(PWM_BASE + 0x0020) -/* 0x0024 - Reserved */ -#define PWM_SCUC MMIO32(PWM_BASE + 0x0028) -#define PWM_SCUP MMIO32(PWM_BASE + 0x002C) -#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030) -#define PWM_IER2 MMIO32(PWM_BASE + 0x0034) -#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038) -#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C) -#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040) -#define PWM_OOV MMIO32(PWM_BASE + 0x0044) -#define PWM_OS MMIO32(PWM_BASE + 0x0048) -#define PWM_OSS MMIO32(PWM_BASE + 0x004C) -#define PWM_OSC MMIO32(PWM_BASE + 0x0050) -#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054) -#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058) -#define PWM_FMR MMIO32(PWM_BASE + 0x005C) -#define PWM_FSR MMIO32(PWM_BASE + 0x0060) -#define PWM_FCR MMIO32(PWM_BASE + 0x0064) -#define PWM_FPV MMIO32(PWM_BASE + 0x0068) -#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C) -#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070) -/* 0x0074:0x0078 - Reserved */ -#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C) -#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080) -/* 0x0084:0x00AC - Reserved */ -#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0) -/* 0x00B4:0x00E0 - Reserved */ -#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4) -#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8) -/* 0x00EC:0x00FC - Reserved */ -/* 0x0100:0x012C - Reserved */ -#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x)) -#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x)) -#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x)) -#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x)) -/* 0x01B0:0x01FC - Reserved */ -#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x)) -#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x)) -#if defined(SAM3X) -# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) -# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) -# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) -# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x)) -# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x)) -# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x)) -#elif defined(SAM3N) -# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) -# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) -# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) -#else -# error "Processor family not defined." -#endif - -static inline void pwm_set_period(int ch, uint32_t period) -{ - PWM_CPRD(ch) = period; -} - -static inline void pwm_set_duty(int ch, uint32_t duty) -{ - PWM_CDTY(ch) = duty; -} - -static inline void pwm_enable(int ch) -{ - PWM_ENA = 1 << ch; -} - -static inline void pwm_disable(int ch) -{ - PWM_DIS = 1 << ch; -} - -#endif diff --git a/libopencm3/include/libopencm3/sam/scif.h b/libopencm3/include/libopencm3/sam/scif.h deleted file mode 100644 index d6ebbcd..0000000 --- a/libopencm3/include/libopencm3/sam/scif.h +++ /dev/null @@ -1,24 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM4L) -# include -#else -# error "SCIF undefined for your processor family." -#endif diff --git a/libopencm3/include/libopencm3/sam/smc.h b/libopencm3/include/libopencm3/sam/smc.h deleted file mode 100644 index 8f2ab02..0000000 --- a/libopencm3/include/libopencm3/sam/smc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* This provides unification of code over SAM subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(SAM3A) -# include -#elif defined(SAM3N) -# error "sam3n doesn't have a static memory controller." -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#else -# error "sam family not defined." -#endif diff --git a/libopencm3/include/libopencm3/sam/tc.h b/libopencm3/include/libopencm3/sam/tc.h deleted file mode 100644 index 864cc4a..0000000 --- a/libopencm3/include/libopencm3/sam/tc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_TC_H -#define SAM3X_TC_H - -#include -#include - -/* --- Timer Counter (TC) registers -------------------------------------- */ - -#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x)) -#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x)) -#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x)) -/* 0x0C + 0x40*channel - Reserved */ -#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x)) -#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x)) -#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x)) -#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x)) -#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x)) -#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x)) -#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x)) -#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x)) -#define TC_BCR MMIO32(TC_BASE + 0xC0) -#define TC_BMR MMIO32(TC_BASE + 0xC4) -#define TC_QIER MMIO32(TC_BASE + 0xC8) -#define TC_QIDR MMIO32(TC_BASE + 0xCC) -#define TC_QIMR MMIO32(TC_BASE + 0xD0) -#define TC_QISR MMIO32(TC_BASE + 0xD4) -#define TC_FMR MMIO32(TC_BASE + 0xD8) -/* 0x00DC:0x00E0 - Undocumented */ -#define TC_WPMR MMIO32(TC_BASE + 0xE4) -/* 0x00E8:0x00F8 - Undocumented */ -/* 0x00FC - Reserved */ - -#endif diff --git a/libopencm3/include/libopencm3/sam/uart.h b/libopencm3/include/libopencm3/sam/uart.h deleted file mode 100644 index becfcb5..0000000 --- a/libopencm3/include/libopencm3/sam/uart.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_UART_H -#define SAM3X_UART_H - -#include -#include - -/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */ -#define UART_CR MMIO32(UART_BASE + 0x0000) -#define UART_MR MMIO32(UART_BASE + 0x0004) -#define UART_IER MMIO32(UART_BASE + 0x0008) -#define UART_IDR MMIO32(UART_BASE + 0x000C) -#define UART_IMR MMIO32(UART_BASE + 0x0010) -#define UART_SR MMIO32(UART_BASE + 0x0014) -#define UART_RHR MMIO32(UART_BASE + 0x0018) -#define UART_THR MMIO32(UART_BASE + 0x001C) -#define UART_BRGR MMIO32(UART_BASE + 0x0020) -/* 0x0024:0x003C - Reserved */ -/* 0x004C:0x00FC - Reserved */ -/* 0x0100:0x0124 - PDC Area */ - - -/* UART Control Register (UART_CR) */ -/* Bits [31:9] - Reserved */ -#define UART_CR_RSTSTA (0x01 << 8) -#define UART_CR_TXDIS (0x01 << 7) -#define UART_CR_TXEN (0x01 << 6) -#define UART_CR_RXDIS (0x01 << 5) -#define UART_CR_RXEN (0x01 << 4) -#define UART_CR_RSTTX (0x01 << 3) -#define UART_CR_RSTRX (0x01 << 2) -/* Bit [1:0] - Reserved */ - -/* UART Mode Register (UART_MR) */ -/* Bits [31:16] - Reserved */ -#define UART_MR_CHMODE_MASK (0x03 << 14) -#define UART_MR_CHMODE_NORMAL (0x00 << 14) -#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14) -#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) -#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) -/* Bits [13:12] - Reserved */ -#define UART_MR_PAR_MASK (0x07 << 9) -#define UART_MR_PAR_EVEN (0x00 << 9) -#define UART_MR_PAR_ODD (0x01 << 9) -#define UART_MR_PAR_SPACE (0x02 << 9) -#define UART_MR_PAR_MARK (0x03 << 9) -#define UART_MR_PAR_NO (0x04 << 9) -/* Bits [8:0] - Reserved */ - -/* UART Status Register (UART_SR) */ -/* Bits [31:13] - Reserved */ -#define UART_SR_RXBUFF (0x01 << 12) -#define UART_SR_TXBUFF (0x01 << 11) -/* Bit [10] - Reserved */ -#define UART_SR_TXEMPTY (0x01 << 9) -/* Bit [8] - Reserved */ -#define UART_SR_PARE (0x01 << 7) -#define UART_SR_FRAME (0x01 << 6) -#define UART_SR_OVRE (0x01 << 5) -#define UART_SR_ENDTX (0x01 << 4) -#define UART_SR_ENDRX (0x01 << 3) -/* Bit [2] - Reserved */ -#define UART_SR_TXRDY (0x01 << 1) -#define UART_SR_RXRDY (0x01 << 0) - -#endif - diff --git a/libopencm3/include/libopencm3/sam/usart.h b/libopencm3/include/libopencm3/sam/usart.h deleted file mode 100644 index 97a8ddb..0000000 --- a/libopencm3/include/libopencm3/sam/usart.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM_USART_H -#define SAM_USART_H - -#include -#include - -#define USART0 USART0_BASE -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE - -/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */ -#define USART_CR(x) MMIO32((x) + 0x0000) -#define USART_MR(x) MMIO32((x) + 0x0004) -#define USART_IER(x) MMIO32((x) + 0x0008) -#define USART_IDR(x) MMIO32((x) + 0x000C) -#define USART_IMR(x) MMIO32((x) + 0x0010) -#define USART_CSR(x) MMIO32((x) + 0x0014) -#define USART_RHR(x) MMIO32((x) + 0x0018) -#define USART_THR(x) MMIO32((x) + 0x001C) -#define USART_BRGR(x) MMIO32((x) + 0x0020) -#define USART_RTOR(x) MMIO32((x) + 0x0024) -#define USART_TTGR(x) MMIO32((x) + 0x0028) -/* 0x002C:0x003C - Reserved */ -#define USART_FIDI(x) MMIO32((x) + 0x0040) -#define USART_NER(x) MMIO32((x) + 0x0044) -/* 0x0048 - Reserved */ -#define USART_IF(x) MMIO32((x) + 0x004C) -#define USART_MAN(x) MMIO32((x) + 0x0050) -#define USART_LINMR(x) MMIO32((x) + 0x0054) -#define USART_LINIR(x) MMIO32((x) + 0x0058) -/* 0x005C:0x00E0 - Reserved */ -#define USART_WPMR(x) MMIO32((x) + 0x00E4) -#define USART_WPSR(x) MMIO32((x) + 0x00E8) -/* 0x00EC:0x00F8 - Reserved */ -#define USART_VERSION(x) MMIO32((x) + 0x00FC) -/* 0x0100:0x0124 - PDC Area */ - - -/* USART Control Register (USART_CR) */ -/* Bits [31:22] - Reserved */ -#define USART_CR_LINWKUP (0x01 << 21) -#define USART_CR_LINABT (0x01 << 20) -#define USART_CR_RTSDIS (0x01 << 19) -#define USART_CR_RCS (0x01 << 19) -#define USART_CR_RTSEN (0x01 << 18) -#define USART_CR_FCS (0x01 << 18) -/* Bits [17:16] - Reserved */ -#define USART_CR_RETTO (0x01 << 15) -#define USART_CR_RSTNACK (0x01 << 14) -#define USART_CR_RSTIT (0x01 << 13) -#define USART_CR_SENDA (0x01 << 12) -#define USART_CR_STTTO (0x01 << 11) -#define USART_CR_STPBRK (0x01 << 10) -#define USART_CR_STTBRK (0x01 << 9) -#define USART_CR_RSTSTA (0x01 << 8) -#define USART_CR_TXDIS (0x01 << 7) -#define USART_CR_TXEN (0x01 << 6) -#define USART_CR_RXDIS (0x01 << 5) -#define USART_CR_RXEN (0x01 << 4) -#define USART_CR_RSTTX (0x01 << 3) -#define USART_CR_RSTRX (0x01 << 2) -/* Bits [1:0] - Reserved */ - -/* USART Mode Register (USART_MR) */ -#define USART_MR_ONEBIT (0x01 << 31) -#define USART_MR_MODSYNC (0x01 << 30) -#define USART_MR_MAN (0x01 << 29) -#define USART_MR_FILTER (0x01 << 28) -/* Bit [27] - Reserved */ -#define USART_MR_MAX_ITERATION_MASK (0x07 << 24) -#define USART_MR_INVDATA (0x01 << 23) -#define USART_MR_VAR_SYNC (0x01 << 22) -#define USART_MR_DSNACK (0x01 << 21) -#define USART_MR_INACK (0x01 << 20) -#define USART_MR_OVER (0x01 << 19) -#define USART_MR_CLKO (0x01 << 18) -#define USART_MR_MODE9 (0x01 << 17) -#define USART_MR_MSBF (0x01 << 16) -#define USART_MR_CPOL (0x01 << 16) -#define USART_MR_CHMODE_MASK (0x03 << 14) -#define USART_MR_CHMODE_NORMAL (0x00 << 14) -#define USART_MR_CHMODE_AUTOMATIC (0x01 << 14) -#define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) -#define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) -#define USART_MR_NBSTOP_MASK (0x03 << 12) -#define USART_MR_NBSTOP_1_BIT (0x00 << 12) -#define USART_MR_NBSTOP_1_5_BIT (0x01 << 12) -#define USART_MR_NBSTOP_2_BIT (0x02 << 12) -/* Bits [13:12] - Reserved */ -#define USART_MR_PAR_MASK (0x07 << 9) -#define USART_MR_PAR_EVEN (0x00 << 9) -#define USART_MR_PAR_ODD (0x01 << 9) -#define USART_MR_PAR_SPACE (0x02 << 9) -#define USART_MR_PAR_MARK (0x03 << 9) -#define USART_MR_PAR_NO (0x04 << 9) -/* Bits [8:0] - Reserved */ -#define USART_MR_SYNC (0x01 << 8) -#define USART_MR_CPHA (0x01 << 8) -#define USART_MR_CHRL_SHIFT (6) -#define USART_MR_CHRL_MASK (0x03 << USART_MR_CHRL_SHIFT) -#define USART_MR_CHRL_5BIT (0x00 << USART_MR_CHRL_SHIFT) -#define USART_MR_CHRL_6BIT (0x01 << USART_MR_CHRL_SHIFT) -#define USART_MR_CHRL_7BIT (0x02 << USART_MR_CHRL_SHIFT) -#define USART_MR_CHRL_8BIT (0x03 << USART_MR_CHRL_SHIFT) -#define USART_MR_USCLKS_SHIFT (4) -#define USART_MR_USCLKS_MASK (0x03 << USART_MR_USCLKS_SHIFT) -#define USART_MR_USCLKS_MCK (0x00 << 4) -#define USART_MR_USCLKS_DIV (0x01 << 4) -#define USART_MR_USCLKS_SCK (0x03 << 4) -#define USART_MR_MODE_MASK (0x0F << 0) -#define USART_MR_MODE_NORMAL (0x00 << 0) -#define USART_MR_MODE_RS485 (0x01 << 0) -#define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0) -#define USART_MR_MODE_ISO7816_T_0 (0x03 << 0) -#define USART_MR_MODE_ISO7816_T_1 (0x04 << 0) -#define USART_MR_MODE_IRDA (0x06 << 0) -#define USART_MR_MODE_LIN_MASTER (0x0A << 0) -#define USART_MR_MODE_LIN_SLAVE (0x0B << 0) -#define USART_MR_MODE_SPI_MASTER (0x0E << 0) -#define USART_MR_MODE_SPI_SLAVE (0x0F << 0) - -/* USART Status Register (USART_CSR) */ -/* Bits [31:30] - Reserved */ -#define USART_CSR_LINSNRE (0x01 << 29) -#define USART_CSR_LINCE (0x01 << 28) -#define USART_CSR_LINIPE (0x01 << 27) -#define USART_CSR_LINSFE (0x01 << 26) -#define USART_CSR_LINBE (0x01 << 25) -#define USART_CSR_MANERR (0x01 << 24) -#define USART_CSR_CTS (0x01 << 23) -#define USART_CSR_LINBLS (0x01 << 23) -/* Bits [22:20] - Reserved */ -#define USART_CSR_CTSIC (0x01 << 19) -/* Bits [18:16] - Reserved */ -#define USART_CSR_LINTC (0x01 << 15) -#define USART_CSR_LINID (0x01 << 14) -#define USART_CSR_NACK (0x01 << 13) -#define USART_CSR_LINBK (0x01 << 13) -#define USART_CSR_RXBUFF (0x01 << 12) -#define USART_CSR_TXBUFE (0x01 << 11) -/* Bit [10] - Reserved */ -#define USART_CSR_TXEMPTY (0x01 << 9) -/* Bit [8] - Reserved */ -#define USART_CSR_PARE (0x01 << 7) -#define USART_CSR_FRAME (0x01 << 6) -#define USART_CSR_OVRE (0x01 << 5) -#define USART_CSR_ENDTX (0x01 << 4) -#define USART_CSR_ENDRX (0x01 << 3) -/* Bit [2] - Reserved */ -#define USART_CSR_TXRDY (0x01 << 1) -#define USART_CSR_RXRDY (0x01 << 0) - -#define USART_WPMR_KEY (0x555341 << 8) -#define USART_WPMR_WPEN (0x01 << 0) - -enum usart_stopbits { - USART_STOPBITS_1, - USART_STOPBITS_1_5, - USART_STOPBITS_2, -}; - -enum usart_parity { - USART_PARITY_EVEN, - USART_PARITY_ODD, - USART_PARITY_SPACE, - USART_PARITY_MARK, - USART_PARITY_NONE, - USART_PARITY_MULTIDROP, -}; - -enum usart_mode { - USART_MODE_DISABLED, - USART_MODE_RX, - USART_MODE_TX, - USART_MODE_TX_RX, -}; - -enum usart_flowcontrol { - USART_FLOWCONTROL_NONE, - USART_FLOWCONTROL_RTS_CTS, -}; - -enum usart_clock { - USART_CLOCK_CLK_USART, - USART_CLOCK_CLK_USART_DIV, - USART_CLOCK_CLK = 3, -}; - -enum usart_chrl { - USART_CHRL_5BIT, - USART_CHRL_6BIT, - USART_CHRL_7BIT, - USART_CHRL_8BIT, -}; - -BEGIN_DECLS - -void usart_set_baudrate(uint32_t usart, uint32_t baud); -void usart_set_databits(uint32_t usart, int bits); -void usart_set_stopbits(uint32_t usart, enum usart_stopbits); -void usart_set_parity(uint32_t usart, enum usart_parity); -void usart_set_mode(uint32_t usart, enum usart_mode); -void usart_set_character_length(uint32_t usart, enum usart_chrl chrl); -void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol); -void usart_enable(uint32_t usart); -void usart_disable(uint32_t usart); -void usart_send(uint32_t usart, uint16_t data); -uint16_t usart_recv(uint32_t usart); -void usart_wait_send_ready(uint32_t usart); -void usart_wait_recv_ready(uint32_t usart); -void usart_send_blocking(uint32_t usart, uint16_t data); -uint16_t usart_recv_blocking(uint32_t usart); -void usart_enable_rx_interrupt(uint32_t usart); -void usart_disable_rx_interrupt(uint32_t usart); -void usart_wp_disable(uint32_t usart); -void usart_wp_enable(uint32_t usart); -void usart_select_clock(uint32_t usart, enum usart_clock clk); - -END_DECLS - -#endif - diff --git a/libopencm3/include/libopencm3/sam/wdt.h b/libopencm3/include/libopencm3/sam/wdt.h deleted file mode 100644 index 566ac95..0000000 --- a/libopencm3/include/libopencm3/sam/wdt.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef SAM3X_WDT_H -#define SAM3X_WDT_H - -#include -#include - - -/* --- WDT registers ----------------------------------------------------- */ - -#define WDT_CR MMIO32(WDT_BASE + 0x00) -#define WDT_MR MMIO32(WDT_BASE + 0x04) -#define WDT_SR MMIO32(WDT_BASE + 0x08) - -/* --- WDT_CR values ------------------------------------------------------ */ - -#define WDT_CR_KEY (0xA5 << 24) -/* Bits [23:1]: Reserved. */ -#define WDT_CR_WDRSTT (1 << 0) - -/* --- WDT_MR values ------------------------------------------------------ */ - -/* Bits [31:32]: Reserved. */ -#define WDT_MR_WDIDLEHLT (1 << 29) -#define WDT_MR_WDDBGHLT (1 << 28) -#define WDT_MR_WDD_MASK (0xFFF << 16) -#define WDT_MR_WDDIS (1 << 15) -#define WDT_MR_WDRPROC (1 << 14) -#define WDT_MR_WDRSTEN (1 << 13) -#define WDT_MR_WDFIEN (1 << 12) -#define WDT_MR_WDV_MASK (0xFFF << 0) - -/* --- WDT_SR values ------------------------------------------------------ */ - -/* Bits [31:2]: Reserved. */ -#define WDT_SR_WDERR (1 << 1) -#define WDT_SR_WDUNF (1 << 0) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/adc.h b/libopencm3/include/libopencm3/stm32/adc.h deleted file mode 100644 index fed4a3b..0000000 --- a/libopencm3/include/libopencm3/stm32/adc.h +++ /dev/null @@ -1,44 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/can.h b/libopencm3/include/libopencm3/stm32/can.h deleted file mode 100644 index 7983b84..0000000 --- a/libopencm3/include/libopencm3/stm32/can.h +++ /dev/null @@ -1,681 +0,0 @@ -/** @defgroup can_defines CAN defines - -@ingroup STM32F_defines - -@brief libopencm3 Defined Constants and Types for STM32 CAN - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 12 November 2012 - -LGPL License Terms @ref lgpl_license -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CAN_H -#define LIBOPENCM3_CAN_H - -#include -#include - -/**@{*/ - -/* --- Convenience macros -------------------------------------------------- */ - -/* CAN register base addresses (for convenience) */ -/*****************************************************************************/ -/** @defgroup can_reg_base CAN register base address -@ingroup can_defines - -@{*/ -#define CAN1 BX_CAN1_BASE -#define CAN2 BX_CAN2_BASE -/**@}*/ - -/* --- CAN registers ------------------------------------------------------- */ - -/* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32((can_base) + 0x000) -/* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32((can_base) + 0x004) -/* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32((can_base) + 0x008) - -/* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C) -/* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32((can_base) + 0x010) - -/* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32((can_base) + 0x014) -/* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32((can_base) + 0x018) -/* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32((can_base) + 0x01C) - -/* Registers in the offset range 0x020 to 0x17F are reserved. */ - -/* --- CAN mailbox registers ----------------------------------------------- */ - -/* CAN mailbox / FIFO register offsets */ -#define CAN_MBOX0 0x180 -#define CAN_MBOX1 0x190 -#define CAN_MBOX2 0x1A0 -#define CAN_FIFO0 0x1B0 -#define CAN_FIFO1 0x1C0 - -/* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0) -#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) -#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) -#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) - -/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2) - -/* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2) - -/* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2) - -/* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1) - -/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1) - -/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1) - -/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1) - -/* --- CAN filter registers ------------------------------------------------ */ - -/* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32((can_base) + 0x200) - -/* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32((can_base) + 0x204) - -/* Register offset 0x208 is reserved. */ - -/* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C) - -/* Register offset 0x210 is reserved. */ - -/* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214) - -/* Register offset 0x218 is reserved. */ - -/* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C) - -/* Register offset 0x220 is reserved. */ - -/* Registers with offset 0x224 to 0x23F are reserved. */ - -/* CAN filter bank registers (CAN_FiRx) */ -/* - * Connectivity line devices have 28 banks so the bank ID spans 0..27 - * all other devices have 14 banks so the bank ID spans 0..13. - */ -#define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \ - ((bank) * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \ - ((bank) * 0x8) + 0x4) - -/* --- CAN_MCR values ------------------------------------------------------ */ - -/* 31:17 Reserved, forced by hardware to 0 */ - -/* DBF: Debug freeze */ -#define CAN_MCR_DBF (1 << 16) - -/* RESET: bxCAN software master reset */ -#define CAN_MCR_RESET (1 << 15) - -/* 14:8 Reserved, forced by hardware to 0 */ - -/* TTCM: Time triggered communication mode */ -#define CAN_MCR_TTCM (1 << 7) - -/* ABOM: Automatic bus-off management */ -#define CAN_MCR_ABOM (1 << 6) - -/* AWUM: Automatic wakeup mode */ -#define CAN_MCR_AWUM (1 << 5) - -/* NART: No automatic retransmission */ -#define CAN_MCR_NART (1 << 4) - -/* RFLM: Receive FIFO locked mode */ -#define CAN_MCR_RFLM (1 << 3) - -/* TXFP: Transmit FIFO priority */ -#define CAN_MCR_TXFP (1 << 2) - -/* SLEEP: Sleep mode request */ -#define CAN_MCR_SLEEP (1 << 1) - -/* INRQ: Initialization request */ -#define CAN_MCR_INRQ (1 << 0) - -/* --- CAN_MSR values ------------------------------------------------------ */ - -/* 31:12 Reserved, forced by hardware to 0 */ - -/* RX: CAN Rx signal */ -#define CAN_MSR_RX (1 << 11) - -/* SAMP: Last sample point */ -#define CAN_MSR_SAMP (1 << 10) - -/* RXM: Receive mode */ -#define CAN_MSR_RXM (1 << 9) - -/* TXM: Transmit mode */ -#define CAN_MSR_TXM (1 << 8) - -/* 7:5 Reserved, forced by hardware to 0 */ - -/* SLAKI: Sleep acknowledge interrupt */ -#define CAN_MSR_SLAKI (1 << 4) - -/* WKUI: Wakeup interrupt */ -#define CAN_MSR_WKUI (1 << 3) - -/* ERRI: Error interrupt */ -#define CAN_MSR_ERRI (1 << 2) - -/* SLAK: Sleep acknowledge */ -#define CAN_MSR_SLAK (1 << 1) - -/* INAK: Initialization acknowledge */ -#define CAN_MSR_INAK (1 << 0) - -/* --- CAN_TSR values ------------------------------------------------------ */ - -/* LOW2: Lowest priority flag for mailbox 2 */ -#define CAN_TSR_LOW2 (1 << 31) - -/* LOW1: Lowest priority flag for mailbox 1 */ -#define CAN_TSR_LOW1 (1 << 30) - -/* LOW0: Lowest priority flag for mailbox 0 */ -#define CAN_TSR_LOW0 (1 << 29) - -/* TME2: Transmit mailbox 2 empty */ -#define CAN_TSR_TME2 (1 << 28) - -/* TME1: Transmit mailbox 1 empty */ -#define CAN_TSR_TME1 (1 << 27) - -/* TME0: Transmit mailbox 0 empty */ -#define CAN_TSR_TME0 (1 << 26) - -/* CODE[1:0]: Mailbox code */ -#define CAN_TSR_CODE_MASK (0x3 << 24) - -/* ABRQ2: Abort request for mailbox 2 */ -#define CAN_TSR_ABRQ2 (1 << 23) - -/* 22:20 Reserved, forced by hardware to 0 */ - -/* TERR2: Transmission error for mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) - -/* ALST2: Arbitration lost for mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) - -/* TXOK2: Transmission OK for mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) - -/* RQCP2: Request completed mailbox 2 */ -#define CAN_TSR_RQCP2 (1 << 16) - -/* ABRQ1: Abort request for mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* TERR1: Transmission error for mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) - -/* ALST1: Arbitration lost for mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) - -/* TXOK1: Transmission OK for mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) - -/* RQCP1: Request completed mailbox 1 */ -#define CAN_TSR_RQCP1 (1 << 8) - -/* ABRQ0: Abort request for mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) - -/* 6:4 Reserved, forced by hardware to 0 */ - -/* TERR0: Transmission error for mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) - -/* ALST0: Arbitration lost for mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) - -/* TXOK0: Transmission OK for mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) - -/* RQCP0: Request completed mailbox 0 */ -#define CAN_TSR_RQCP0 (1 << 0) - -/* --- CAN_RF0R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM0: Release FIFO 0 output mailbox */ -#define CAN_RF0R_RFOM0 (1 << 5) - -/* FOVR0: FIFO 0 overrun */ -#define CAN_RF0R_FOVR0 (1 << 4) - -/* FULL0: FIFO 0 full */ -#define CAN_RF0R_FULL0 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP0[1:0]: FIFO 0 message pending */ -#define CAN_RF0R_FMP0_MASK (0x3 << 0) - -/* --- CAN_RF1R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM1: Release FIFO 1 output mailbox */ -#define CAN_RF1R_RFOM1 (1 << 5) - -/* FOVR1: FIFO 1 overrun */ -#define CAN_RF1R_FOVR1 (1 << 4) - -/* FULL1: FIFO 1 full */ -#define CAN_RF1R_FULL1 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP1[1:0]: FIFO 1 message pending */ -#define CAN_RF1R_FMP1_MASK (0x3 << 0) - -/* --- CAN_IER values ------------------------------------------------------ */ - -/* 32:18 Reserved, forced by hardware to 0 */ - -/* SLKIE: Sleep interrupt enable */ -#define CAN_IER_SLKIE (1 << 17) - -/* WKUIE: Wakeup interrupt enable */ -#define CAN_IER_WKUIE (1 << 16) - -/* ERRIE: Error interrupt enable */ -#define CAN_IER_ERRIE (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* LECIE: Last error code interrupt enable */ -#define CAN_IER_LECIE (1 << 11) - -/* BOFIE: Bus-off interrupt enable */ -#define CAN_IER_BOFIE (1 << 10) - -/* EPVIE: Error passive interrupt enable */ -#define CAN_IER_EPVIE (1 << 9) - -/* EWGIE: Error warning interrupt enable */ -#define CAN_IER_EWGIE (1 << 8) - -/* 7 Reserved, forced by hardware to 0 */ - -/* FOVIE1: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE1 (1 << 6) - -/* FFIE1: FIFO full interrupt enable */ -#define CAN_IER_FFIE1 (1 << 5) - -/* FMPIE1: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE1 (1 << 4) - -/* FOVIE0: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE0 (1 << 3) - -/* FFIE0: FIFO full interrupt enable */ -#define CAN_IER_FFIE0 (1 << 2) - -/* FMPIE0: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE0 (1 << 1) - -/* TMEIE: Transmit mailbox empty interrupt enable */ -#define CAN_IER_TMEIE (1 << 0) - -/* --- CAN_ESR values ------------------------------------------------------ */ - -/* REC[7:0]: Receive error counter */ -#define CAN_ESR_REC_MASK (0xF << 24) - -/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ -#define CAN_ESR_TEC_MASK (0xF << 16) - -/* 15:7 Reserved, forced by hardware to 0 */ - -/* LEC[2:0]: Last error code */ -#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) -#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) -#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) -#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) -#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) -#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) -#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) -#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) -#define CAN_ESR_LEC_MASK (0x7 << 4) - -/* 3 Reserved, forced by hardware to 0 */ - -/* BOFF: Bus-off flag */ -#define CAN_ESR_BOFF (1 << 2) - -/* EPVF: Error passive flag */ -#define CAN_ESR_EPVF (1 << 1) - -/* EWGF: Error warning flag */ -#define CAN_ESR_EWGF (1 << 0) - -/* --- CAN_BTR values ------------------------------------------------------ */ - -/* SILM: Silent mode (debug) */ -#define CAN_BTR_SILM (1 << 31) - -/* LBKM: Loop back mode (debug) */ -#define CAN_BTR_LBKM (1 << 30) - -/* 29:26 Reserved, forced by hardware to 0 */ - -/* SJW[1:0]: Resynchronization jump width */ -#define CAN_BTR_SJW_1TQ (0x0 << 24) -#define CAN_BTR_SJW_2TQ (0x1 << 24) -#define CAN_BTR_SJW_3TQ (0x2 << 24) -#define CAN_BTR_SJW_4TQ (0x3 << 24) -#define CAN_BTR_SJW_MASK (0x3 << 24) -#define CAN_BTR_SJW_SHIFT 24 - -/* 23 Reserved, forced by hardware to 0 */ - -/* TS2[2:0]: Time segment 2 */ -#define CAN_BTR_TS2_1TQ (0x0 << 20) -#define CAN_BTR_TS2_2TQ (0x1 << 20) -#define CAN_BTR_TS2_3TQ (0x2 << 20) -#define CAN_BTR_TS2_4TQ (0x3 << 20) -#define CAN_BTR_TS2_5TQ (0x4 << 20) -#define CAN_BTR_TS2_6TQ (0x5 << 20) -#define CAN_BTR_TS2_7TQ (0x6 << 20) -#define CAN_BTR_TS2_8TQ (0x7 << 20) -#define CAN_BTR_TS2_MASK (0x7 << 20) -#define CAN_BTR_TS2_SHIFT 20 - -/* TS1[3:0]: Time segment 1 */ -#define CAN_BTR_TS1_1TQ (0x0 << 16) -#define CAN_BTR_TS1_2TQ (0x1 << 16) -#define CAN_BTR_TS1_3TQ (0x2 << 16) -#define CAN_BTR_TS1_4TQ (0x3 << 16) -#define CAN_BTR_TS1_5TQ (0x4 << 16) -#define CAN_BTR_TS1_6TQ (0x5 << 16) -#define CAN_BTR_TS1_7TQ (0x6 << 16) -#define CAN_BTR_TS1_8TQ (0x7 << 16) -#define CAN_BTR_TS1_9TQ (0x8 << 16) -#define CAN_BTR_TS1_10TQ (0x9 << 16) -#define CAN_BTR_TS1_11TQ (0xA << 16) -#define CAN_BTR_TS1_12TQ (0xB << 16) -#define CAN_BTR_TS1_13TQ (0xC << 16) -#define CAN_BTR_TS1_14TQ (0xD << 16) -#define CAN_BTR_TS1_15TQ (0xE << 16) -#define CAN_BTR_TS1_16TQ (0xF << 16) -#define CAN_BTR_TS1_MASK (0xF << 16) -#define CAN_BTR_TS1_SHIFT 16 - -/* 15:10 Reserved, forced by hardware to 0 */ - -/* BRP[9:0]: Baud rate prescaler */ -#define CAN_BTR_BRP_MASK (0x3FFUL << 0) - -/* --- CAN_TIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_TIxR_STID_MASK (0x7FF << 21) -#define CAN_TIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_TIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_TIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_TIxR_RTR (1 << 1) - -/* TXRQ: Transmit mailbox request */ -#define CAN_TIxR_TXRQ (1 << 0) - -/* --- CAN_TDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_TDTxR_TIME_SHIFT 15 - -/* 15:6 Reserved, forced by hardware to 0 */ - -/* TGT: Transmit global time */ -#define CAN_TDTxR_TGT (1 << 5) - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_TDTxR_DLC_MASK (0xF << 0) -#define CAN_TDTxR_DLC_SHIFT 0 - -/* --- CAN_TDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_TDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_RIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_RIxR_STID_MASK (0x7FF) -#define CAN_RIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_RIxR_EXID_MASK (0x1FFFFFFF) -#define CAN_RIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_RIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_RIxR_RTR (1 << 1) - -/* 0 Reserved */ - -/* --- CAN_RDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_RDTxR_TIME_MASK (0xFFFF << 16) -#define CAN_RDTxR_TIME_SHIFT 16 - -/* FMI[7:0]: Filter match index */ -#define CAN_RDTxR_FMI_MASK (0xFF << 8) -#define CAN_RDTxR_FMI_SHIFT 8 - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_RDTxR_DLC_MASK (0xF << 0) -#define CAN_RDTxR_DLC_SHIFT 0 - -/* --- CAN_RDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_RDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_FMR values ------------------------------------------------------- */ - -/* 31:14 Reserved, forced to reset value */ - -/* - * CAN2SB[5:0]: CAN2 start bank - * (only on connectivity line devices otherwise reserved) - */ -#define CAN_FMR_CAN2SB_SHIFT 8 -#define CAN_FMR_CAN2SB_MASK (0x3F << CAN_FMR_CAN2SB_SHIFT) - -/* 7:1 Reserved, forced to reset value */ - -/* FINIT: Filter init mode */ -#define CAN_FMR_FINIT (1 << 0) - -/* --- CAN_FM1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FBMx: Filter mode - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FS1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FSCx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FFA1R values ----------------------------------------------------- */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FFAx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FA1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FACTx: Filter active - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FiRx values ------------------------------------------------------ */ - -/* FB[31:0]: Filter bits */ - -/* --- CAN functions -------------------------------------------------------- */ - -BEGIN_DECLS - -void can_reset(uint32_t canport); -int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, - bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, - uint32_t brp, bool loopback, bool silent); - -void can_filter_init(uint32_t nr, bool scale_32bit, - bool id_list_mode, uint32_t fr1, uint32_t fr2, - uint32_t fifo, bool enable); -void can_filter_id_mask_16bit_init(uint32_t nr, uint16_t id1, - uint16_t mask1, uint16_t id2, - uint16_t mask2, uint32_t fifo, bool enable); -void can_filter_id_mask_32bit_init(uint32_t nr, uint32_t id, - uint32_t mask, uint32_t fifo, bool enable); -void can_filter_id_list_16bit_init(uint32_t nr, uint16_t id1, - uint16_t id2, uint16_t id3, uint16_t id4, - uint32_t fifo, bool enable); -void can_filter_id_list_32bit_init(uint32_t nr, uint32_t id1, - uint32_t id2, uint32_t fifo, bool enable); - -void can_enable_irq(uint32_t canport, uint32_t irq); -void can_disable_irq(uint32_t canport, uint32_t irq); - -int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, - uint8_t length, uint8_t *data); -uint32_t can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, - bool *ext, bool *rtr, uint8_t *fmi, uint8_t *length, - uint8_t *data, uint16_t *timestamp); - -void can_fifo_release(uint32_t canport, uint8_t fifo); -bool can_available_mailbox(uint32_t canport); -uint32_t can_fifo_pending(uint32_t canport, uint8_t fifo); -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/cec.h b/libopencm3/include/libopencm3/stm32/cec.h deleted file mode 100644 index 51f860e..0000000 --- a/libopencm3/include/libopencm3/stm32/cec.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h deleted file mode 100644 index 6d0752f..0000000 --- a/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h +++ /dev/null @@ -1,429 +0,0 @@ -/** @addtogroup adc_defines - -@author @htmlonly © @endhtmlonly 2014 Karl Palsson - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H -The order of header inclusion is important. adc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_ADC_H -/** @endcond */ -#ifndef LIBOPENCM3_ADC_COMMON_V1_H -#define LIBOPENCM3_ADC_COMMON_V1_H - -/* --- Convenience macros -------------------------------------------------- */ - -/* ADC port base addresses (for convenience) */ -/****************************************************************************/ -/** @defgroup adc_reg_base ADC register base addresses -@ingroup STM32xx_adc_defines - -@{*/ -#define ADC1 ADC1_BASE -/**@}*/ - -/* --- ADC registers ------------------------------------------------------- */ - -/* ADC status register (ADC_SR) */ -#define ADC_SR(block) MMIO32((block) + 0x00) - -/* ADC control register 1 (ADC_CR1) */ -#define ADC_CR1(block) MMIO32((block) + 0x04) - -/* ADC control register 2 (ADC_CR2) */ -#define ADC_CR2(block) MMIO32((block) + 0x08) - -/* ADC sample time register 1 (ADC_SMPR1) */ -#define ADC_SMPR1(block) MMIO32((block) + 0x0c) - -/* ADC sample time register 2 (ADC_SMPR2) */ -#define ADC_SMPR2(block) MMIO32((block) + 0x10) - -#define ADC1_SR ADC_SR(ADC1) -#define ADC1_CR1 ADC_CR1(ADC1) -#define ADC1_CR2 ADC_CR2(ADC1) -#define ADC1_SMPR1 ADC_SMPR1(ADC1) -#define ADC1_SMPR2 ADC_SMPR2(ADC1) - -#define ADC1_JOFR1 ADC_JOFR1(ADC1) -#define ADC1_JOFR2 ADC_JOFR2(ADC1) -#define ADC1_JOFR3 ADC_JOFR3(ADC1) -#define ADC1_JOFR4 ADC_JOFR4(ADC1) - -#define ADC1_HTR ADC_HTR(ADC1) -#define ADC1_LTR ADC_LTR(ADC1) - -#define ADC1_SQR1 ADC_SQR1(ADC1) -#define ADC1_SQR2 ADC_SQR2(ADC1) -#define ADC1_SQR3 ADC_SQR3(ADC1) -#define ADC1_JSQR ADC_JSQR(ADC1) - -#define ADC1_JDR1 ADC_JDR1(ADC1) -#define ADC1_JDR2 ADC_JDR2(ADC1) -#define ADC1_JDR3 ADC_JDR3(ADC1) -#define ADC1_JDR4 ADC_JDR4(ADC1) -#define ADC1_DR ADC_DR(ADC1) - -#if defined(ADC2_BASE) -#define ADC2 ADC2_BASE -#define ADC2_SR ADC_SR(ADC2) -#define ADC2_CR1 ADC_CR1(ADC2) -#define ADC2_CR2 ADC_CR2(ADC2) -#define ADC2_SMPR1 ADC_SMPR1(ADC2) -#define ADC2_SMPR2 ADC_SMPR2(ADC2) - -#define ADC2_JOFR1 ADC_JOFR1(ADC2) -#define ADC2_JOFR2 ADC_JOFR2(ADC2) -#define ADC2_JOFR3 ADC_JOFR3(ADC2) -#define ADC2_JOFR4 ADC_JOFR4(ADC2) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC2_HTR ADC_HTR(ADC2) -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC2_LTR ADC_LTR(ADC2) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC2_SQR1 ADC_SQR1(ADC2) -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC2_SQR2 ADC_SQR2(ADC2) -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC2_SQR3 ADC_SQR3(ADC2) -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC2_JSQR ADC_JSQR(ADC2) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC2_JDR1 ADC_JDR1(ADC2) -#define ADC2_JDR2 ADC_JDR2(ADC2) -#define ADC2_JDR3 ADC_JDR3(ADC2) -#define ADC2_JDR4 ADC_JDR4(ADC2) -/* ADC regular data register (ADC_DR) */ -#define ADC2_DR ADC_DR(ADC2) -#endif - -#if defined(ADC3_BASE) -#define ADC3 ADC3_BASE -#define ADC3_SR ADC_SR(ADC3) -#define ADC3_CR1 ADC_CR1(ADC3) -#define ADC3_CR2 ADC_CR2(ADC3) -#define ADC3_SMPR1 ADC_SMPR1(ADC3) -#define ADC3_SMPR2 ADC_SMPR2(ADC3) - -#define ADC3_JOFR1 ADC_JOFR1(ADC3) -#define ADC3_JOFR2 ADC_JOFR2(ADC3) -#define ADC3_JOFR3 ADC_JOFR3(ADC3) -#define ADC3_JOFR4 ADC_JOFR4(ADC3) - -#define ADC3_HTR ADC_HTR(ADC3) -#define ADC3_LTR ADC_LTR(ADC3) - -#define ADC3_SQR1 ADC_SQR1(ADC3) -#define ADC3_SQR2 ADC_SQR2(ADC3) -#define ADC3_SQR3 ADC_SQR3(ADC3) -#define ADC3_JSQR ADC_JSQR(ADC3) - -#define ADC3_JDR1 ADC_JDR1(ADC3) -#define ADC3_JDR2 ADC_JDR2(ADC3) -#define ADC3_JDR3 ADC_JDR3(ADC3) -#define ADC3_JDR4 ADC_JDR4(ADC3) -#define ADC3_DR ADC_DR(ADC3) -#endif - - - -/* --- ADC Channels ------------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup adc_channel ADC Channel Numbers -@ingroup STM32xx_adc_defines - -@{*/ -#define ADC_CHANNEL0 0x00 -#define ADC_CHANNEL1 0x01 -#define ADC_CHANNEL2 0x02 -#define ADC_CHANNEL3 0x03 -#define ADC_CHANNEL4 0x04 -#define ADC_CHANNEL5 0x05 -#define ADC_CHANNEL6 0x06 -#define ADC_CHANNEL7 0x07 -#define ADC_CHANNEL8 0x08 -#define ADC_CHANNEL9 0x09 -#define ADC_CHANNEL10 0x0A -#define ADC_CHANNEL11 0x0B -#define ADC_CHANNEL12 0x0C -#define ADC_CHANNEL13 0x0D -#define ADC_CHANNEL14 0x0E -#define ADC_CHANNEL15 0x0F -#define ADC_CHANNEL16 0x10 -#define ADC_CHANNEL17 0x11 -#define ADC_CHANNEL18 0x12 -/**@}*/ -#define ADC_CHANNEL_MASK 0x1F - - -/* --- ADC_SR values ------------------------------------------------------- */ -/****************************************************************************/ -/** @defgroup adc_sr_values ADC Status Register Flags -@ingroup STM32xx_adc_defines - -@{*/ - -/* STRT:*//** Regular channel Start flag */ -#define ADC_SR_STRT (1 << 4) - -/* JSTRT:*//** Injected channel Start flag */ -#define ADC_SR_JSTRT (1 << 3) - -/* JEOC:*//** Injected channel end of conversion */ -#define ADC_SR_JEOC (1 << 2) - -/* EOC:*//** End of conversion */ -#define ADC_SR_EOC (1 << 1) - -/* AWD:*//** Analog watchdog flag */ -#define ADC_SR_AWD (1 << 0) -/**@}*/ - -/* --- ADC_CR1 values ------------------------------------------------------ */ - -/* AWDEN: Analog watchdog enable on regular channels */ -#define ADC_CR1_AWDEN (1 << 23) - -/* JAWDEN: Analog watchdog enable on injected channels */ -#define ADC_CR1_JAWDEN (1 << 22) - -/* Note: Bits [21:20] are reserved, and must be kept at reset value. */ - - -/* DISCNUM[2:0]: Discontinuous mode channel count. */ -/****************************************************************************/ -/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. -@ingroup STM32_adc_defines - -@{*/ -#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) -#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) -#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) -#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) -#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) -#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) -#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) -#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) -/**@}*/ -#define ADC_CR1_DISCNUM_MASK (0x7 << 13) -#define ADC_CR1_DISCNUM_SHIFT 13 - -/* JDISCEN: */ /** Discontinuous mode on injected channels. */ -#define ADC_CR1_JDISCEN (1 << 12) - -/* DISCEN: */ /** Discontinuous mode on regular channels. */ -#define ADC_CR1_DISCEN (1 << 11) - -/* JAUTO: */ /** Automatic Injection Group conversion. */ -#define ADC_CR1_JAUTO (1 << 10) - -/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ -#define ADC_CR1_AWDSGL (1 << 9) - -/* SCAN: */ /** Scan mode. */ -#define ADC_CR1_SCAN (1 << 8) - -/* JEOCIE: */ /** Interrupt enable for injected channels. */ -#define ADC_CR1_JEOCIE (1 << 7) - -/* AWDIE: */ /** Analog watchdog interrupt enable. */ -#define ADC_CR1_AWDIE (1 << 6) - -/* EOCIE: */ /** Interrupt enable EOC. */ -#define ADC_CR1_EOCIE (1 << 5) - -/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ -/* Notes: Depending on part, and ADC peripheral, some channels are connected - * to V_SS, or to temperature/reference/battery inputs - */ -/****************************************************************************/ -/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ -/** @defgroup adc_watchdog_channel ADC watchdog channel -@ingroup STM32xx_adc_defines - -@{*/ -#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) -#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) -#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) -#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) -#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) -#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) -#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) -#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) -#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) -#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) -#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) -#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) -#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) -#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) -#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) -#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) -#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) -#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) -/**@}*/ -#define ADC_CR1_AWDCH_MASK (0x1F << 0) -#define ADC_CR1_AWDCH_SHIFT 0 - -/* --- ADC_CR2 values ------------------------------------------------------ */ - -/* ALIGN: Data alignement. */ -#define ADC_CR2_ALIGN_RIGHT (0 << 11) -#define ADC_CR2_ALIGN_LEFT (1 << 11) -#define ADC_CR2_ALIGN (1 << 11) - -/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ -#define ADC_CR2_DMA (1 << 8) - -/* CONT: Continuous conversion. */ -#define ADC_CR2_CONT (1 << 1) - -/* ADON: A/D converter On/Off. */ -/* Note: If any other bit in this register apart from ADON is changed at the - * same time, then conversion is not triggered. This is to prevent triggering - * an erroneous conversion. - * Conclusion: Must be separately written. - */ -#define ADC_CR2_ADON (1 << 0) - -/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ - -#define ADC_JOFFSET_LSB 0 -#define ADC_JOFFSET_MSK 0xfff -#define ADC_HT_LSB 0 -#define ADC_HT_MSK 0xfff -#define ADC_LT_LSB 0 -#define ADC_LT_MSK 0xfff - -/* --- ADC_SQR1 values ----------------------------------------------------- */ -/* The sequence length field is always in the same place, but sized - * differently on various parts */ -#define ADC_SQR1_L_LSB 20 - -/* --- ADC_JSQR values ----------------------------------------------------- */ -#define ADC_JSQR_JL_LSB 20 -#define ADC_JSQR_JSQ4_LSB 15 -#define ADC_JSQR_JSQ3_LSB 10 -#define ADC_JSQR_JSQ2_LSB 5 -#define ADC_JSQR_JSQ1_LSB 0 - -/* JL[2:0]: Discontinous mode channel count injected channels. */ -/****************************************************************************/ -/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous injected mode -@ingroup STM32xx_adc_defines - -@{*/ -#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) -#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) -#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) -#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) -/**@}*/ -#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) -#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) -#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) -#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) -#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) - -#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5)) -#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_LSB) - -#if (defined(THESE_HAVE_BAD_NAMES_PROBABLY) && (THESE_HAVE_BAD_NAMES_PROBABLY)) -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) -#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) -/* ADC1 only (dual mode) */ -#endif - - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void adc_power_on(uint32_t adc); -void adc_power_off(uint32_t adc); -void adc_enable_analog_watchdog_regular(uint32_t adc); -void adc_disable_analog_watchdog_regular(uint32_t adc); -void adc_enable_analog_watchdog_injected(uint32_t adc); -void adc_disable_analog_watchdog_injected(uint32_t adc); -void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); -void adc_disable_discontinuous_mode_regular(uint32_t adc); -void adc_enable_discontinuous_mode_injected(uint32_t adc); -void adc_disable_discontinuous_mode_injected(uint32_t adc); -void adc_enable_automatic_injected_group_conversion(uint32_t adc); -void adc_disable_automatic_injected_group_conversion(uint32_t adc); -void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); -void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, - uint8_t channel); -void adc_enable_scan_mode(uint32_t adc); -void adc_disable_scan_mode(uint32_t adc); -void adc_enable_eoc_interrupt_injected(uint32_t adc); -void adc_disable_eoc_interrupt_injected(uint32_t adc); -void adc_enable_awd_interrupt(uint32_t adc); -void adc_disable_awd_interrupt(uint32_t adc); -void adc_enable_eoc_interrupt(uint32_t adc); -void adc_disable_eoc_interrupt(uint32_t adc); -void adc_set_left_aligned(uint32_t adc); -void adc_set_right_aligned(uint32_t adc); -bool adc_eoc(uint32_t adc); -bool adc_eoc_injected(uint32_t adc); -uint32_t adc_read_regular(uint32_t adc); -int32_t adc_read_injected(uint32_t adc, uint8_t reg); -void adc_set_continuous_conversion_mode(uint32_t adc); -void adc_set_single_conversion_mode(uint32_t adc); -void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); -void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); -void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); -void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); -void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); -void adc_start_conversion_regular(uint32_t adc); -void adc_start_conversion_injected(uint32_t adc); -void adc_enable_dma(uint32_t adc); -void adc_disable_dma(uint32_t adc); -bool adc_get_flag(uint32_t adc, uint32_t flag); -void adc_clear_flag(uint32_t adc, uint32_t flag); - -/* common methods that have slight differences */ -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); -void adc_disable_external_trigger_regular(uint32_t adc); -void adc_disable_external_trigger_injected(uint32_t adc); - -END_DECLS - -#endif -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v1_multi.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v1_multi.h deleted file mode 100644 index 05a2ac6..0000000 --- a/libopencm3/include/libopencm3/stm32/common/adc_common_v1_multi.h +++ /dev/null @@ -1,379 +0,0 @@ -/** @addtogroup adc_defines - -@author @htmlonly © @endhtmlonly 2014 Karl Palsson - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Matthew Lai - * Copyright (C) 2009 Edward Cheeseman - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H -The order of header inclusion is important. adc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_ADC_H -/** @endcond */ -#ifndef LIBOPENCM3_ADC_COMMON_V1_MULTI_H -#define LIBOPENCM3_ADC_COMMON_V1_MULTI_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - - -/* ADC common (shared) registers */ -#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) -#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) -#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) -#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) - -/* --- ADC Channels ------------------------------------------------------- */ - - -/* --- ADC_SR values ------------------------------------------------------- */ - -/** @defgroup adc_sr_values ADC Status Register Flags - * @ingroup adc_defines - *@{*/ - -/* OVR:*//** Overrun */ -#define ADC_SR_OVR (1 << 5) -/**@}*/ - -/* OVRIE: Overrun interrupt enable */ -#define ADC_CR1_OVRIE (1 << 26) - -/* RES[1:0]: Resolution */ -/****************************************************************************/ -/** @defgroup adc_cr1_res ADC Resolution. -@ingroup adc_defines - -@{*/ -#define ADC_CR1_RES_12BIT (0x0 << 24) -#define ADC_CR1_RES_10BIT (0x1 << 24) -#define ADC_CR1_RES_8BIT (0x2 << 24) -#define ADC_CR1_RES_6BIT (0x3 << 24) -/**@}*/ -#define ADC_CR1_RES_MASK (0x3 << 24) -#define ADC_CR1_RES_SHIFT 24 - -/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ - - - -/* --- ADC_CR2 values ------------------------------------------------------ */ - -/* SWSTART: Start conversion of regular channels. */ -#define ADC_CR2_SWSTART (1 << 30) - -/* EXTEN[1:0]: External trigger enable for regular channels. */ -/****************************************************************************/ -#define ADC_CR2_EXTEN_SHIFT 28 -#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT) -/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity -@ingroup adc_defines -@{*/ -#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT) -/**@}*/ - -/* EXTSEL[3:0]: External event selection for regular group. */ -/****************************************************************************/ -/* Note: Selection values are family-dependent. */ -#define ADC_CR2_EXTSEL_MASK (0xF << 24) -#define ADC_CR2_EXTSEL_SHIFT 24 - -/* Bit 23 is reserved */ - -/* JSWSTART: Start conversion of injected channels. */ -#define ADC_CR2_JSWSTART (1 << 22) - -/* JEXTEN[1:0]: External trigger enable for injected channels. */ -/****************************************************************************/ -#define ADC_CR2_JEXTEN_SHIFT 20 -#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT) -/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity -@ingroup adc_defines -@{*/ -#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT) -/**@}*/ - -/* JEXTSEL[3:0]: External event selection for injected group. */ -/****************************************************************************/ -/* Note: Selection values are family-dependent. */ -#define ADC_CR2_JEXTSEL_SHIFT 16 -#define ADC_CR2_JEXTSEL_MASK (0xF << ADC_CR2_JEXTSEL_SHIFT) - -/* ALIGN: Data alignement. */ -#define ADC_CR2_ALIGN_RIGHT (0 << 11) -#define ADC_CR2_ALIGN_LEFT (1 << 11) -#define ADC_CR2_ALIGN (1 << 11) - -/* EOCS: End of conversion selection. */ -#define ADC_CR2_EOCS (1 << 10) - -/* DDS: DMA disable selection */ -#define ADC_CR2_DDS (1 << 9) - -/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ -#define ADC_CR2_DMA (1 << 8) - -/* Note: Bits [7:2] are reserved and must be kept at reset value. */ - -/* CONT: Continuous conversion. */ -#define ADC_CR2_CONT (1 << 1) - -/* ADON: A/D converter On/Off. */ -/* Note: If any other bit in this register apart from ADON is changed at the - * same time, then conversion is not triggered. This is to prevent triggering - * an erroneous conversion. - * Conclusion: Must be separately written. - */ -#define ADC_CR2_ADON (1 << 0) - - -/* --- ADC_SMPRx values --------------------------------------------------- */ -/****************************************************************************/ - -#define ADC_SQRx_MASK 0x1f - -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) - -/* --- Common Registers ---------------------------------------------------- */ - -/* --- ADC_CSR values (read only images) ------------------------------------ */ - -/* OVR3: Overrun ADC3. */ -#define ADC_CSR_OVR3 (1 << 21) - -/* STRT3: Regular channel start ADC3. */ -#define ADC_CSR_STRT3 (1 << 20) - -/* JSTRT3: Injected channel start ADC3. */ -#define ADC_CSR_JSTRT3 (1 << 19) - -/* JEOC3: Injected channel end of conversion ADC3. */ -#define ADC_CSR_JEOC3 (1 << 18) - -/* EOC3: Regular channel end of conversion ADC3. */ -#define ADC_CSR_EOC3 (1 << 17) - -/* EOC3: Regular channel end of conversion ADC3. */ -#define ADC_CSR_AWD3 (1 << 16) - -/* Bits 15:14 Reserved, must be kept at reset value */ - -/* OVR2: Overrun ADC2. */ -#define ADC_CSR_OVR2 (1 << 13) - -/* STRT2: Regular channel start ADC2. */ -#define ADC_CSR_STRT2 (1 << 12) - -/* JSTRT2: Injected channel start ADC2. */ -#define ADC_CSR_JSTRT2 (1 << 11) - -/* JEOC2: Injected channel end of conversion ADC2. */ -#define ADC_CSR_JEOC2 (1 << 10) - -/* EOC2: Regular channel end of conversion ADC2. */ -#define ADC_CSR_EOC2 (1 << 9) - -/* EOC2: Regular channel end of conversion ADC2. */ -#define ADC_CSR_AWD2 (1 << 8) - -/* Bits 7:6 Reserved, must be kept at reset value */ - -/* OVR1: Overrun ADC1. */ -#define ADC_CSR_OVR1 (1 << 5) - -/* STRT1: Regular channel start ADC1. */ -#define ADC_CSR_STRT1 (1 << 4) - -/* JSTRT1: Injected channel start ADC1. */ -#define ADC_CSR_JSTRT1 (1 << 3) - -/* JEOC1: Injected channel end of conversion ADC1. */ -#define ADC_CSR_JEOC1 (1 << 2) - -/* EOC1: Regular channel end of conversion ADC1. */ -#define ADC_CSR_EOC1 (1 << 1) - -/* EOC1: Regular channel end of conversion ADC1. */ -#define ADC_CSR_AWD1 (1 << 0) - -/* --- ADC_CCR values ------------------------------------------------------ */ - -/* TSVREFE: Temperature sensor and Vrefint enable. */ -#define ADC_CCR_TSVREFE (1 << 23) - -/* VBATE: VBat enable. */ -#define ADC_CCR_VBATE (1 << 22) - -/* Bit 18:21 reserved, must be kept at reset value. */ - -/* DMA: Direct memory access mode for multi ADC mode. */ -/****************************************************************************/ -/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode -@ingroup adc_defines - -@{*/ -#define ADC_CCR_DMA_DISABLE (0x0 << 14) -#define ADC_CCR_DMA_MODE_1 (0x1 << 14) -#define ADC_CCR_DMA_MODE_2 (0x2 << 14) -#define ADC_CCR_DMA_MODE_3 (0x3 << 14) -/**@}*/ -#define ADC_CCR_DMA_MASK (0x3 << 14) -#define ADC_CCR_DMA_SHIFT 14 - -/* DDS: DMA disable selection (for multi-ADC mode). */ -#define ADC_CCR_DDS (1 << 13) - -/* Bit 12 reserved, must be kept at reset value */ - -/* DELAY: Delay between 2 sampling phases. */ -/****************************************************************************/ -/** @defgroup adc_delay ADC Delay between 2 sampling phases -@ingroup adc_defines - -@{*/ -#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) -#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) -#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) -#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) -#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) -#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) -#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) -#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) -#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) -#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) -#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) -#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) -#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) -#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) -#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) -#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) -/**@}*/ -#define ADC_CCR_DELAY_MASK (0xf << 8) -#define ADC_CCR_DELAY_SHIFT 8 - -/* Bit 7:5 reserved, must be kept at reset value */ - -/* MULTI: Multi ADC mode selection. */ -/****************************************************************************/ -/** @defgroup adc_multi_mode ADC Multi mode selection -@ingroup adc_defines - -@{*/ - -/** All ADCs independent */ -#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) - -/* Dual modes (ADC1 + ADC2) */ -/** - * Dual modes (ADC1 + ADC2) Combined regular simultaneous + - * injected simultaneous mode. - */ -#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) -/** - * Dual modes (ADC1 + ADC2) Combined regular simultaneous + - * alternate trigger mode. - */ -#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) -/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) -/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) -/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ -#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) -/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) - -/* Triple modes (ADC1 + ADC2 + ADC3) */ -/** - * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + - * injected simultaneous mode. - */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) -/** - * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + - * alternate trigger mode. - */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) -/**@}*/ - -#define ADC_CCR_MULTI_MASK (0x1f << 0) -#define ADC_CCR_MULTI_SHIFT 0 - -/* --- ADC_CDR values ------------------------------------------------------ */ - -#define ADC_CDR_DATA2_MASK (0xffff << 16) -#define ADC_CDR_DATA2_SHIFT 16 - -#define ADC_CDR_DATA1_MASK (0xffff << 0) -#define ADC_CDR_DATA1_SHIFT 0 - -BEGIN_DECLS - -void adc_set_clk_prescale(uint32_t prescaler); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_set_resolution(uint32_t adc, uint32_t resolution); -void adc_enable_overrun_interrupt(uint32_t adc); -void adc_disable_overrun_interrupt(uint32_t adc); -bool adc_get_overrun_flag(uint32_t adc); -void adc_clear_overrun_flag(uint32_t adc); -bool adc_awd(uint32_t adc); -void adc_eoc_after_each(uint32_t adc); -void adc_eoc_after_group(uint32_t adc); -void adc_set_dma_continue(uint32_t adc); -void adc_set_dma_terminate(uint32_t adc); -void adc_enable_temperature_sensor(void); -void adc_disable_temperature_sensor(void); - -END_DECLS - -#endif -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v2.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v2.h deleted file mode 100644 index bd3845a..0000000 --- a/libopencm3/include/libopencm3/stm32/common/adc_common_v2.h +++ /dev/null @@ -1,264 +0,0 @@ -/** @addtogroup adc_defines - -@author @htmlonly © @endhtmlonly 2015 Karl Palsson - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H -The order of header inclusion is important. adc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_ADC_H -/** @endcond */ -#ifndef LIBOPENCM3_ADC_COMMON_V2_H -#define LIBOPENCM3_ADC_COMMON_V2_H - -/** @defgroup adc_registers ADC registers -@{*/ -/* ----- ADC registers -----------------------------------------------------*/ -/** ADC interrupt and status register */ -#define ADC_ISR(adc) MMIO32((adc) + 0x00) -/** Interrupt Enable Register */ -#define ADC_IER(adc) MMIO32((adc) + 0x04) -/** Control Register */ -#define ADC_CR(adc) MMIO32((adc) + 0x08) -/** Configuration Register 1 */ -#define ADC_CFGR1(adc) MMIO32((adc) + 0x0C) -/** Configuration Register 2 */ -#define ADC_CFGR2(adc) MMIO32((adc) + 0x10) -/** Sample Time Register 1 */ -#define ADC_SMPR1(adc) MMIO32((adc) + 0x14) -/** Watchdog Threshold Register 1*/ -#define ADC_TR1(adc) MMIO32((adc) + 0x20) -/** Regular Data Register */ -#define ADC_DR(adc) MMIO32((adc) + 0x40) -/* CALFACT for all but f0 :(*/ - -/** Common Configuration register */ -#define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8) -/**@}*/ - -/* --- Register values -------------------------------------------------------*/ - -/* ADC_ISR Values -----------------------------------------------------------*/ -/** @defgroup adc_isr ISR ADC interrupt status register -@{*/ - -/** AWD1: Analog watchdog 1 flag */ -#define ADC_ISR_AWD1 (1 << 7) -/** OVR: Overrun flag */ -#define ADC_ISR_OVR (1 << 4) -/** EOS: End of sequence conversions flag */ -#define ADC_ISR_EOS (1 << 3) // FIXME - move to single/multi here. -#define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ -/** EOS: End of regular conversion flag */ -#define ADC_ISR_EOC (1 << 2) -/** EOSMP: End of sampling flag */ -#define ADC_ISR_EOSMP (1 << 1) -/** ADRDY: Ready flag */ -#define ADC_ISR_ADRDY (1 << 0) - -/**@}*/ - -/* ADC_IER Values -----------------------------------------------------------*/ -/** @defgroup adc_ier IER ADC interrupt enable register -@{*/ - -/** AWD1IE: Analog watchdog 1 interrupt enable */ -#define ADC_IER_AWD1IE (1 << 7) -/** OVRIE: Overrun interrupt enable */ -#define ADC_IER_OVRIE (1 << 4) -/** EOSIE: End of regular sequence of conversions interrupt enable */ -#define ADC_IER_EOSIE (1 << 3) -#define ADC_IER_EOSEQIE ADC_IER_EOSIE /* TODO - keep only one? */ -/** EOCIE: End of regular conversion interrupt enable */ -#define ADC_IER_EOCIE (1 << 2) -/** EOSMPIE: End of sampling flag interrupt enable for regular conversions */ -#define ADC_IER_EOSMPIE (1 << 1) -/** ADRDYIE: ADC ready interrupt enable */ -#define ADC_IER_ADRDYIE (1 << 0) - -/**@}*/ - -/* ADC_CR Values -----------------------------------------------------------*/ -/** @defgroup adc_cr CR ADC control register -@{*/ - -/** ADCAL: ADC calibration */ -#define ADC_CR_ADCAL (1 << 31) -/** ADSTP: ADC stop of regular conversion command */ -#define ADC_CR_ADSTP (1 << 4) -/** ADSTART: ADC start of regular conversion */ -#define ADC_CR_ADSTART (1 << 2) -/** ADDIS: ADC disable command */ -#define ADC_CR_ADDIS (1 << 1) -/** ADEN: ADC enable control */ -#define ADC_CR_ADEN (1 << 0) - -/**@}*/ - -/* ADC_CFGR1 Values -----------------------------------------------------------*/ -/** @defgroup adc_cfgr1 CFGR1 ADC configuration register 1 -@{*/ - -#define ADC_CFGR1_AWD1CH_SHIFT 26 -#define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) -/** AWD1CH: Analog watchdog 1 channel selection */ -#define ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT) - -/** AWD1EN: Analog watchdog 1 enable on regular channels */ -#define ADC_CFGR1_AWD1EN (1 << 23) -/** AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR1_AWD1SGL (1 << 22) -/** DISCEN: Discontinuous mode for regular channels */ -#define ADC_CFGR1_DISCEN (1 << 16) -/** AUTDLY: Delayed conversion mode */ -#define ADC_CFGR1_AUTDLY (1 << 14) -/** CONT: Single / continuous conversion mode for regular conversions */ -#define ADC_CFGR1_CONT (1 << 13) -/** OVRMOD: Overrun Mode */ -#define ADC_CFGR1_OVRMOD (1 << 12) - -#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) -/** @defgroup adc_cfgr1_exten EXTEN: External trigger enable and polarity selection for regular channels -@{*/ -#define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10) -#define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10) -#define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10) -#define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10) -/**@}*/ - -/** ALIGN: Data alignment */ -#define ADC_CFGR1_ALIGN (1 << 5) - -#define ADC_CFGR1_RES_MASK (0x3 << 3) -/** @defgroup adc_cfgr1_res RES: Data resolution -@{*/ -#define ADC_CFGR1_RES_12_BIT (0x0 << 3) -#define ADC_CFGR1_RES_10_BIT (0x1 << 3) -#define ADC_CFGR1_RES_8_BIT (0x2 << 3) -#define ADC_CFGR1_RES_6_BIT (0x3 << 3) -/**@}*/ - -/** DMACFG: Direct memory access configuration */ -#define ADC_CFGR1_DMACFG (1 << 1) - -/** DMAEN: Direct memory access enable */ -#define ADC_CFGR1_DMAEN (1 << 0) - -/**@}*/ - -/* ADC_SMPR Values -----------------------------------------------------------*/ -/** @defgroup adc_smpr SMPR ADC sample time register -@{*/ - -/**@}*/ - -/* ADC_CFGR2 Values -----------------------------------------------------------*/ -/** @defgroup adc_cfgr2 CFGR2 ADC configuration register 2 -@{*/ - -/**@}*/ - -/* ADC_TR1 Values ------------------------------------------------------------*/ -/** @defgroup adc_tr1 TR1 ADC watchdog threshold register 1 -@{*/ - -#define ADC_TR1_LT_SHIFT 0 -#define ADC_TR1_LT_MASK 0xFFF -#define ADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT) -/** TR1_LT: analog watchdog 1 threshold low */ -#define ADC_TR1_LT_VAL(x) (((x) & ADC_TR1_LT_MASK) << ADC_TR1_LT_SHIFT) - -#define ADC_TR1_HT_SHIFT 16 -#define ADC_TR1_HT_MASK 0xFFF -#define ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT) -/** TR1_HT: analog watchdog 1 threshold high */ -#define ADC_TR1_HT_VAL(x) (((x) & ADC_TR1_HT_MASK) << ADC_TR1_HT_SHIFT) - -/**@}*/ - -/* ADC_CCR Values -----------------------------------------------------------*/ -/** @defgroup adc_ccr CCR ADC common configuration register -@{*/ - -/** VBATEN: Enable VBAT Channel */ -#define ADC_CCR_VBATEN (1 << 24) - -/** TSEN: Enable Temperature Sensor */ -#define ADC_CCR_TSEN (1 << 23) - -/** VREFEN: Enable internal Voltage Reference */ -#define ADC_CCR_VREFEN (1 << 22) - -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void adc_power_on_async(uint32_t adc); -void adc_power_on(uint32_t adc); -bool adc_is_power_on(uint32_t adc); -void adc_power_off_async(uint32_t adc); -void adc_power_off(uint32_t adc); -bool adc_is_power_off(uint32_t adc); -void adc_calibrate_async(uint32_t adc); -bool adc_is_calibrating(uint32_t adc); -void adc_calibrate(uint32_t adc); -void adc_set_continuous_conversion_mode(uint32_t adc); -void adc_set_single_conversion_mode(uint32_t adc); -void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); -void adc_enable_temperature_sensor(void); -void adc_disable_temperature_sensor(void); -void adc_enable_vrefint(void); -void adc_disable_vrefint(void); -void adc_set_resolution(uint32_t adc, uint16_t resolution); -void adc_set_left_aligned(uint32_t adc); -void adc_set_right_aligned(uint32_t adc); -void adc_enable_dma(uint32_t adc); -void adc_disable_dma(uint32_t adc); -bool adc_eoc(uint32_t adc); -bool adc_eos(uint32_t adc); -void adc_enable_eoc_interrupt(uint32_t adc); -void adc_disable_eoc_interrupt(uint32_t adc); -void adc_enable_overrun_interrupt(uint32_t adc); -void adc_disable_overrun_interrupt(uint32_t adc); -bool adc_get_overrun_flag(uint32_t adc); -void adc_clear_overrun_flag(uint32_t adc); -uint32_t adc_read_regular(uint32_t adc); -void adc_start_conversion_regular(uint32_t adc); -void adc_enable_dma_circular_mode(uint32_t adc); -void adc_disable_dma_circular_mode(uint32_t adc); -void adc_enable_delayed_conversion_mode(uint32_t adc); -void adc_disable_delayed_conversion_mode(uint32_t adc); -END_DECLS - -#endif -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v2_multi.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v2_multi.h deleted file mode 100644 index 374889b..0000000 --- a/libopencm3/include/libopencm3/stm32/common/adc_common_v2_multi.h +++ /dev/null @@ -1,187 +0,0 @@ -/** @addtogroup adc_defines - -@author @htmlonly © @endhtmlonly 2015 Karl Palsson - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H -The order of header inclusion is important. adc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_ADC_H -/** @endcond */ -#ifndef LIBOPENCM3_ADC_COMMON_V2_MULTI_H -#define LIBOPENCM3_ADC_COMMON_V2_MULTI_H - -/* - * The adc v2 peripheral optionally supports per channel sampling, injected - * sequences, watchdogs, offsets and other "advanced" features, and is - * found on the (so far) F3 and L4, - * or only a much "simpler" version as found on (so far) f0 and l0. - */ - -/** @addtogroup adc_registers - *@{*/ -/* ----- ADC registers -----------------------------------------------------*/ -/* Sample Time Register 2 */ -#define ADC_SMPR2(adc) MMIO32((adc) + 0x18) -/* Watchdog Threshold Register 2 */ -#define ADC_TR2(adc) MMIO32((adc) + 0x24) -/* Watchdog Threshold Register 3 */ -#define ADC_TR3(adc) MMIO32((adc) + 0x28) -/* Regular Sequence Register x (ADCx_SQRy, x=1..4, y=1..4) SQRy */ -#define ADC_SQR1(adc) MMIO32((adc) + 0x30) -#define ADC_SQR2(adc) MMIO32((adc) + 0x34) -#define ADC_SQR3(adc) MMIO32((adc) + 0x38) -#define ADC_SQR4(adc) MMIO32((adc) + 0x3C) - -/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ -#define ADC_JSQR(adc) MMIO32((adc) + 0x30) - -/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ -#define ADC_OFR1(adc) MMIO32((adc) + 0x60) -#define ADC_OFR2(adc) MMIO32((adc) + 0x64) -#define ADC_OFR3(adc) MMIO32((adc) + 0x68) -#define ADC_OFR4(adc) MMIO32((adc) + 0x6C) - -/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ -#define ADC_JDR1(adc) MMIO32((adc) + 0x80) -#define ADC_JDR2(adc) MMIO32((adc) + 0x84) -#define ADC_JDR3(adc) MMIO32((adc) + 0x88) -#define ADC_JDR4(adc) MMIO32((adc) + 0x8C) - -/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ -#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0) -/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ -#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4) - -/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ -#define ADC_DIFSEL(adc) MMIO32((adc) + 0xB0) - -/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ -#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4) - -/* ADC common (shared) registers */ -#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0) -#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xc) -/**@}*/ - -/* --- Register values ------------------------------------------------------*/ -/* ADC_ISR Values -----------------------------------------------------------*/ - -/* QOVF: Injected context queue overflow */ -#define ADC_ISR_JQOVF (1 << 10) -/* AWD3: Analog watchdog 3 flag */ -#define ADC_ISR_AWD3 (1 << 9) -/* AWD2: Analog watchdog 2 flag */ -#define ADC_ISR_AWD2 (1 << 8) -/* JEOS: Injected channel end of sequence flag */ -#define ADC_ISR_JEOS (1 << 6) -/* JEOC: Injected channel end of conversion flag */ -#define ADC_ISR_JEOC (1 << 5) - -/* ADC_IER Values -----------------------------------------------------------*/ - -/* JQOVFIE: Injected context queue overflow interrupt enable */ -#define ADC_IER_JQOVFIE (1 << 10) -/* AWD3IE: Analog watchdog 3 interrupt enable */ -#define ADC_IER_AWD3IE (1 << 9) -/* AWD2IE: Analog watchdog 2 interrupt enable */ -#define ADC_IER_AWD2IE (1 << 8) -/* JEOSIE: End of injected sequence of conversions interrupt enable */ -#define ADC_IER_JEOSIE (1 << 6) -/* JEOCIE: End of injected conversion interrupt enable */ -#define ADC_IER_JEOCIE (1 << 5) - -/* ADC_CR Values ------------------------------------------------------------*/ - -/* ADCALDIF: Differential mode for calibration */ -#define ADC_CR_ADCALDIF (1 << 30) -/* JADSTP: ADC stop of injected conversion command */ -#define ADC_CR_JADSTP (1 << 5) -/* JADSTART: ADC start of injected conversion */ -#define ADC_CR_JADSTART (1 << 3) - -/* ADC_CFGR1 Values ---------------------------------------------------------*/ - -/* JAUTO: Autoamtic injected group conversion */ -#define ADC_CFGR1_JAUTO (1 << 25) - -/* JAWD1EN: Analog watchdog 1 enable on injected channels */ -#define ADC_CFGR1_JAWD1EN (1 << 24) - -/* JQM: JSQR queue mode */ -#define ADC_CFGR1_JQM (1 << 21) - -/* JDISCEN: Discontinuous mode on injected channels */ -#define ADC_CFGR1_JDISCEN (1 << 20) - -/* DISCNUM[2:0]: Discontinuous mode channel count */ -#define ADC_CFGR1_DISCNUM_SHIFT 17 -#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT) -#define ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT) - -/* EXTSEL[3:0]: External trigger selection for regular group */ -#define ADC_CFGR1_EXTSEL_SHIFT 6 -#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT) -#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) - -/* ADC_SQRx Values: Regular Sequence ordering------------------------------- */ - -#define ADC_SQR1_L_SHIFT 0 -#define ADC_SQR1_L_MASK 0xf -#define ADC_SQRx_SQx_MASK 0x1f -#define ADC_SQR1_SQ1_SHIFT 6 -#define ADC_SQR1_SQ2_SHIFT 12 -#define ADC_SQR1_SQ3_SHIFT 18 -#define ADC_SQR1_SQ4_SHIFT 24 -#define ADC_SQR2_SQ5_SHIFT 0 -#define ADC_SQR2_SQ6_SHIFT 6 -#define ADC_SQR2_SQ7_SHIFT 12 -#define ADC_SQR2_SQ8_SHIFT 18 -#define ADC_SQR2_SQ9_SHIFT 24 -#define ADC_SQR3_SQ10_SHIFT 0 -#define ADC_SQR3_SQ11_SHIFT 6 -#define ADC_SQR3_SQ12_SHIFT 12 -#define ADC_SQR3_SQ13_SHIFT 18 -#define ADC_SQR3_SQ14_SHIFT 24 -#define ADC_SQR4_SQ15_SHIFT 0 -#define ADC_SQR4_SQ16_SHIFT 6 - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); -void adc_enable_regulator(uint32_t adc); -void adc_disable_regulator(uint32_t adc); - -END_DECLS - -#endif -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v2_single.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v2_single.h deleted file mode 100644 index 32616cf..0000000 --- a/libopencm3/include/libopencm3/stm32/common/adc_common_v2_single.h +++ /dev/null @@ -1,86 +0,0 @@ -/** @addtogroup adc_defines - -@author @htmlonly © @endhtmlonly 2015 Karl Palsson - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H -The order of header inclusion is important. adc.h includes the device -specific memorymap.h header before including this header file.*/ - -/* - * The adc v2 peripheral optionally supports per channel sampling, injected - * sequences, watchdogs, offsets and other "advanced" features, and is - * found on the (so far) F3 and L4, - * or only a much "simpler" version as found on (so far) f0 and l0. - */ - -/** @cond */ -#ifdef LIBOPENCM3_ADC_H -/** @endcond */ -#ifndef LIBOPENCM3_ADC_COMMON_V2_SINGLE_H -#define LIBOPENCM3_ADC_COMMON_V2_SINGLE_H - -/** @addtogroup adc_registers - *@{*/ -/* ----- ADC registers -----------------------------------------------------*/ -/** Channel Select Register */ -#define ADC_CHSELR(adc) MMIO32((adc) + 0x28) -/**@}*/ - -/* ----- ADC registers values -----------------------------------------------*/ -/* ADC_CFGR1 values */ -/** @addtogroup adc_cfgr1 -@{*/ -/** Wait conversion mode */ -#define ADC_CFGR1_WAIT (1<<14) -/** Auto off mode */ -#define ADC_CFGR1_AUTOFF (1 << 15) - -#define ADC_CFGR1_EXTSEL_SHIFT 6 -#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) -/** EXTSEL[2:0]: External trigger selection for regular group */ -#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) - -/** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */ -#define ADC_CFGR1_SCANDIR (1 << 2) -/**@}*/ - -/* ADC_CHSELR Values --------------------------------------------------------*/ -/** @defgroup adc_chselr CHSELR ADC Channel Selection register -@{*/ -#define ADC_CHSELR_CHSEL(x) (1 << (x)) -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -END_DECLS - -#endif -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/crc_common_all.h b/libopencm3/include/libopencm3/stm32/common/crc_common_all.h deleted file mode 100644 index 360e5cc..0000000 --- a/libopencm3/include/libopencm3/stm32/common/crc_common_all.h +++ /dev/null @@ -1,125 +0,0 @@ -/** @addtogroup crc_defines - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H -The order of header inclusion is important. crc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_CRC_H -/** @endcond */ -#ifndef LIBOPENCM3_CRC_COMMON_ALL_H -#define LIBOPENCM3_CRC_COMMON_ALL_H - -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/**@defgroup crc_registers CRC Registers - @{*/ -/** CRC_DR Data register */ -#define CRC_DR MMIO32(CRC_BASE + 0x00) - -/** CRC_IDR Independent data register */ -#define CRC_IDR MMIO32(CRC_BASE + 0x04) - -/** CRC_CR Control register */ -#define CRC_CR MMIO32(CRC_BASE + 0x08) -/*@}*/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- CRC_DR values ------------------------------------------------------- */ - -/* Bits [31:0]: Data register */ - -/* --- CRC_IDR values ------------------------------------------------------ */ - -/* Bits [31:8]: Reserved */ - -/* Bits [7:0]: General-purpose 8-bit data register bits */ - - -/** @defgroup crc_cr_values CRC_CR values - @{*/ -/** CRC_CR_RESET reset the CRC peripheral */ -#define CRC_CR_RESET (1 << 0) -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -/* TODO */ - -/** - * Reset the CRC calculator to initial values. - */ -void crc_reset(void); - -/** - * Writes a data word to the register, the write operation stalling until - * the computation is complete. - * @param[in] data new word to add to the CRC calculator - * @returns int32 Computed CRC result - */ -uint32_t crc_calculate(uint32_t data); - -/** - * Add a block of data to the CRC calculator and return the final result. - * Writes data words consecutively to the register, the write operation - * stalling until the computation of each word is complete, then - * returns the final result - * @param[in] datap pointer to an array of 32 bit data words. - * @param[in] size length of data, in 32bit increments - * @return final CRC calculator value - */ -uint32_t crc_calculate_block(uint32_t *datap, int size); - -END_DECLS - -/**@}*/ - -#endif -/** @cond */ -#else -#warning "crc_common_all.h should not be included explicitly, only via crc.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/crc_v2.h b/libopencm3/include/libopencm3/stm32/common/crc_v2.h deleted file mode 100644 index 515f757..0000000 --- a/libopencm3/include/libopencm3/stm32/common/crc_v2.h +++ /dev/null @@ -1,107 +0,0 @@ -/** @addtogroup crc_defines - - @author @htmlonly © @endhtmlonly 2016 Cem Basoglu - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Cem Basoglu - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H - The order of header inclusion is important. crc.h includes the device - specific memorymap.h header before including this header file.*/ - -#pragma once - -/**@{*/ - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/** @addtogroup crc_registers CRC Registers -@{*/ -/** CRC_DR Data register 8bit wide access */ -#define CRC_DR8 MMIO8(CRC_BASE + 0x00) -/** CRC_DR Data register 16bit wide access */ -#define CRC_DR16 MMIO16(CRC_BASE + 0x00) - -/** CRC_INIT Initial CRC Value */ -#define CRC_INIT MMIO32(CRC_BASE + 0x10) - -/** CRC_POL CRC Polynomial */ -#define CRC_POL MMIO32(CRC_BASE + 0x14) -/**@}*/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ -/** @addtogroup crc_cr_values CRC_CR values - @{*/ -#define CRC_CR_REV_OUT (1 << 7) - -#define CRC_CR_REV_IN_SHIFT 5 -#define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT) -/** @defgroup crc_rev_in CRC Reverse input options - @{*/ -#define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT) -#define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT) -#define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT) -#define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT) -/**@}*/ - -#define CRC_CR_POLYSIZE_SHIFT 3 -#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) -/** - * @defgroup crc_polysize CRC Polynomial size - * @{ - */ -#define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) -#define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) -#define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) -#define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) -/**@}*/ - -/**@}*/ - -/** Default polynomial */ -#define CRC_POL_DEFAULT 0x04C11DB7 - - -BEGIN_DECLS - -void crc_reverse_output_enable(void); -void crc_reverse_output_disable(void); - -void crc_set_reverse_input(uint32_t reverse_in); -void crc_set_polysize(uint32_t polysize); - -void crc_set_polynomial(uint32_t polynomial); -void crc_set_initial(uint32_t initial); - -END_DECLS - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/crs_common_all.h b/libopencm3/include/libopencm3/stm32/common/crs_common_all.h deleted file mode 100644 index 2ce29f3..0000000 --- a/libopencm3/include/libopencm3/stm32/common/crs_common_all.h +++ /dev/null @@ -1,133 +0,0 @@ -/** @defgroup CRS_defines CRS Defines - * - * @brief STM32 Clock Recovery System: Defined Constants and Types - * - * @ingroup STM32_defines - * - * @version 1.0.0 - * - * @date 5 Feb 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRS_H -#define LIBOPENCM3_CRS_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -#define CRS CRS_BASE - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define CRS_CR MMIO32(CRS_BASE + 0x00) -#define CRS_CFGR MMIO32(CRS_BASE + 0x04) -#define CRS_ISR MMIO32(CRS_BASE + 0x08) -#define CRS_ICR MMIO32(CRS_BASE + 0x0c) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* CEC_CR Values ------------------------------------------------------------*/ - -#define CRS_CR_TRIM_SHIFT 8 -#define CRS_CR_TRIM (0x3F << CRS_CR_TRIM_SHIFT) - -#define CRS_CR_SWSYNC (1 << 7) -#define CRS_CR_AUTOTRIMEN (1 << 6) -#define CRS_CR_CEN (1 << 5) -#define CRS_CR_ESYNCIE (1 << 3) -#define CRS_CR_ERRIE (1 << 2) -#define CRS_CR_SYNCWARNIE (1 << 1) -#define CRS_CR_SYNCOKIE (1 << 0) - -/* CEC_CFGR Values ----------------------------------------------------------*/ - -#define CRS_CFGR_SYNCPOL (1 << 31) - -#define CRS_CFGR_SYNCSRC_SHIFT 28 -#define CRS_CFGR_SYNCSRC (3 << CRS_CFGR_SYNCSRC_SHIFT) -#define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) -#define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) -#define CRS_CFGR_SYNCSRC_USB_SOF (2 << CRS_CFGR_SYNCSRC_SHIFT) - -#define CRS_CFGR_SYNCDIV_SHIFT 24 -#define CRS_CFGR_SYNCDIV (7 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_NODIV (0 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV2 (1 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV4 (2 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV8 (3 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV16 (4 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV32 (5 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV64 (6 << CRS_CFGR_SYNCDIV_SHIFT) -#define CRS_CFGR_SYNCDIV_DIV128 (7 << CRS_CFGR_SYNCDIV_SHIFT) - -#define CRS_CFGR_FELIM_SHIFT 16 -#define CRS_CFGR_FELIM (0xFF << CRS_CFGR_FELIM_SHIFT) -#define CRS_CFGR_FELIM_VAL(x) ((x) << CRS_CFGR_FELIM_SHIFT) - -#define CRS_CFGR_RELOAD_SHIFT 0 -#define CRS_CFGR_RELOAD (0xFFFF << CRS_CFGR_RELOAD_SHIFT) -#define CRS_CFGR_RELOAD_VAL(x) ((x) << CRS_CFGR_RELOAD_SHIFT) - -/* CEC_ISR Values -----------------------------------------------------------*/ - -#define CRS_ISR_FECAP_SHIFT 16 -#define CRS_ISR_FECAP (0xFFFF << CRS_ISR_FECAP_SHIFT) - -#define CRS_ISR_FEDIR (1 << 15) -#define CRS_ISR_TRIMOVF (1 << 10) -#define CRS_ISR_SYNCMISS (1 << 9) -#define CRS_ISR_SYNCERR (1 << 8) -#define CRS_ISR_ESYNCF (1 << 3) -#define CRS_ISR_ERRF (1 << 2) -#define CRS_ISR_SYNCWARNF (1 << 1) -#define CRS_ISR_SYNCOOKF (1 << 0) - -/* CEC_ICR Values -----------------------------------------------------------*/ - -#define CRS_ICR_ESYNCC (1 << 3) -#define CRS_ICR_ERRC (1 << 2) -#define CRS_ICR_SYNCWARNC (1 << 1) -#define CRS_ICR_SYNCOKC (1 << 0) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -void crs_autotrim_usb_enable(void); - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h b/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h deleted file mode 100644 index eb885c8..0000000 --- a/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h +++ /dev/null @@ -1,290 +0,0 @@ -/** @addtogroup crypto_defines - * - * @warning The CRYP subsystem is present only in a limited set of devices, - * see next section for list of supported devices. - * - * @section crypto_api_supported Supported devices - * - * - STM32F205 - * - STM32F207 - * - STM32F215 - * - STM32F217 - * - STM32F405 - * - STM32F407 - * - STM32F415 - * - STM32F417 (tested) - * - STM32F427 - * - STM32F437 - * - * @section crypto_api_theory Theory of operation - * - * - * - * @section crypto_api_basic Basic handling API - * - * - * @b Example @b 1: Blocking mode - * - * @code - * //[enable-clocks] - * crypto_set_key(CRYPTO_KEY_128BIT,key); - * crypto_set_iv(iv); // only in CBC or CTR mode - * crypto_set_datatype(CRYPTO_DATA_16BIT); - * crypto_set_algorithm(ENCRYPT_AES_ECB); - * crypto_start(); - * foreach(block in blocks) - * crypto_process_block(plaintext,ciphertext,blocksize); - * crypto_stop(); - * @endcode - * - * @section crypto_api_interrupt Interrupt supported handling API - * - * @warning This operation mode is currently not supported. - * - * @b Example @b 2: Interrupt mode - * - * @code - * //[enable-clocks] - * crypto_set_key(CRYPTO_KEY_128BIT,key); - * crypto_set_iv(iv); // only in CBC or CTR mode - * crypto_set_datatype(CRYPTO_DATA_16BIT); - * crypto_set_algorithm(ENCRYPT_AES_ECB); - * crypto_start(); - * [... API to be described later ...] - * crypto_stop(); - * @endcode - * - * @section crypto_api_dma DMA handling API - * - * @warning This operation mode is currently not supported. - * - * @b Example @b 3: DMA mode - * - * @code - * //[enable-clocks] - * crypto_set_key(CRYPTO_KEY_128BIT,key); - * crypto_set_iv(iv); // only in CBC or CTR mode - * crypto_set_datatype(CRYPTO_DATA_16BIT); - * crypto_set_algorithm(ENCRYPT_AES_ECB); - * crypto_start(); - * [... API to be described later ...] - * crypto_stop(); - * @endcode - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H -The order of header inclusion is important. cryp.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_CRYPTO_H -/** @endcond */ - -#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H -#define LIBOPENCM3_CRYPTO_COMMON_F24_H - -/**@{*/ - -/* --- CRYP registers ------------------------------------------------------ */ -/** @defgroup crypto_registers_gen Registers (Generic) - * - * @brief Register access to the CRYP controller. (All chips) - * - * @ingroup crypto_defines - */ -/**@{*/ - -#define CRYP CRYP_BASE - -/* CRYP Control Register (CRYP_CR) */ -#define CRYP_CR MMIO32(CRYP_BASE + 0x00) - -/* CRYP Status Register (CRYP_SR) */ -#define CRYP_SR MMIO32(CRYP_BASE + 0x04) - -/* CRYP Data Input Register (CRYP_DIN) */ -#define CRYP_DIN MMIO32(CRYP_BASE + 0x08) - -/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */ -#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C) - -/* CRYP DMA Control Register (CRYP_DMACR) */ -#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10) - -/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */ -#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14) - -/* CRYP Raw Interrupt status register (CRYP_RISR) */ -#define CRYP_RISR MMIO32(CRYP_BASE + 0x18) - -/* CRYP Masked Interrupt status register (CRYP_MISR) */ -#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C) - -/* CRYP Key registers (CRYP_KxLR) x=0..3 */ -#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8) - -/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */ -#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8) - -/* --- CRYP_CR values ------------------------------------------------------ */ - -/* ALGODIR: Algorithm direction */ -#define CRYP_CR_ALGODIR (1 << 2) - -/* ALGOMODE: Algorithm mode */ -#define CRYP_CR_ALGOMODE_SHIFT 3 -#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT) -#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT) - -/* DATATYPE: Data type selection */ -#define CRYP_CR_DATATYPE_SHIFT 6 -#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT) -#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT) -#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT) -#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT) -#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT) - -/* KEYSIZE: Key size selection (AES mode only)*/ -#define CRYP_CR_KEYSIZE_SHIFT 8 -#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT) -#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT) -#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT) -#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT) - -/* FFLUSH: FIFO Flush */ -#define CRYP_CR_FFLUSH (1 << 14) - -/* CRYPEN: Cryptographic processor enable*/ -#define CRYP_CR_CRYPEN (1 << 15) - -/* --- CRYP_SR values ------------------------------------------------------ */ - -/* IFEM: Input FIFO empty */ -#define CRYP_SR_IFEM (1 << 0) - -/* IFNF: Input FIFO not full */ -#define CRYP_SR_IFNF (1 << 1) - -/* OFNE: Output FIFO not empty */ -#define CRYP_SR_OFNE (1 << 2) - -/* OFFU: Output FIFO full */ -#define CRYP_SR_OFFU (1 << 3) - -/* BUSY: Busy bit */ -#define CRYP_SR_BUSY (1 << 4) - -/* --- CRYP_DMACR values --------------------------------------------------- */ - -/* DIEN: DMA input enable */ -#define CRYP_DMACR_DIEN (1 << 0) - -/* DOEN: DMA output enable */ -#define CRYP_DMACR_DOEN (1 << 1) - -/* --- CRYP_IMSCR values --------------------------------------------------- */ - -/* INIM: Input FIFO service interrupt mask */ -#define CRYP_IMSCR_INIM (1 << 0) - -/* OUTIM: Output FIFO service interrupt mask */ -#define CRYP_IMSCR_OUTIM (1 << 1) - -/* --- CRYP_RISR values ---------------------------------------------------- */ - -/* INRIS: Input FIFO service raw interrupt status */ -#define CRYP_RISR_INRIS (1 << 0) - -/* OUTRIS: Output FIFO service raw data */ -#define CRYP_RISR_OUTRIS (1 << 0) - -/* --- CRYP_MISR values ---------------------------------------------------- */ - -/* INMIS: Input FIFO service masked interrupt status */ -#define CRYP_MISR_INMIS (1 << 0) - -/* OUTMIS: Output FIFO service masked interrupt status */ -#define CRYP_MISR_OUTMIS (1 << 0) - -/**@}*/ - -/** @defgroup crypto_api_gen API (Generic) - * - * @brief API for the CRYP controller - * - * @ingroup crypto_defines - */ -/**@{*/ - -enum crypto_mode { - ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB, - ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC, - ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB, - ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC, - ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB, - ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC, - ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR, - DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR, - DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR, - DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR, - DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR, - DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR, - DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR, - DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */ -}; -enum crypto_keysize { - CRYPTO_KEY_128BIT = 0, - CRYPTO_KEY_192BIT, - CRYPTO_KEY_256BIT, -}; -enum crypto_datatype { - - CRYPTO_DATA_32BIT = 0, - CRYPTO_DATA_16BIT, - CRYPTO_DATA_8BIT, - CRYPTO_DATA_BIT, -}; - -BEGIN_DECLS -void crypto_wait_busy(void); -void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]); -void crypto_set_iv(uint64_t iv[]); -void crypto_set_datatype(enum crypto_datatype datatype); -void crypto_set_algorithm(enum crypto_mode mode); -void crypto_start(void); -void crypto_stop(void); -uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length); -END_DECLS -/**@}*/ -/**@}*/ -#endif -/** @cond */ -#else -#warning "crypto_common_f24.h should not be included explicitly, " - "only via crypto.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/dac_common_all.h b/libopencm3/include/libopencm3/stm32/common/dac_common_all.h deleted file mode 100644 index 258af88..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dac_common_all.h +++ /dev/null @@ -1,435 +0,0 @@ -/** @addtogroup dac_defines - -@author @htmlonly © @endhtmlonly 2012 -Felix Held - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H -The order of header inclusion is important. dac.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_DAC_H -/** @endcond */ -#ifndef LIBOPENCM3_DAC_COMMON_ALL_H -#define LIBOPENCM3_DAC_COMMON_ALL_H - -/* --- DAC registers ------------------------------------------------------- */ - -/* DAC control register (DAC_CR) */ -#define DAC_CR MMIO32(DAC_BASE + 0x00) - -/* DAC software trigger register (DAC_SWTRIGR) */ -#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) - -/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ -#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) - -/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ -#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) - -/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ -#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) - -/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ -#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) - -/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ -#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) - -/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ -#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) - -/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ -#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) - -/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ -#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) - -/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ -#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) - -/* DAC channel1 data output register (DAC_DOR1) */ -#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) - -/* DAC channel2 data output register (DAC_DOR2) */ -#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) - -/** DAC status register. - * @note not available on F1 - */ -#define DAC_SR MMIO32(DAC_BASE + 0x34) - -/* --- DAC_CR values ------------------------------------------------------- */ - -/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE2 (1 << 29) - -/* DMAEN2: DAC channel2 DMA enable */ -#define DAC_CR_DMAEN2 (1 << 28) - -/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ -/* DAC_CR_MAMP2_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP2_SHIFT 24 -/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude -values -@ingroup dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 -@{*/ -#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) -/**@}*/ - -/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - */ -#define DAC_CR_WAVE2_SHIFT 22 -#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) -/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable -@ingroup dac_defines - -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) -#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) -/**@}*/ - -/* TSEL2[2:0]: DAC channel2 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event - * T8: Timer 8 TRGO event - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL2_SHIFT 19 -/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection -@ingroup dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) -@{*/ -#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) -/**@}*/ - -/* TEN2: DAC channel2 trigger enable */ -#define DAC_CR_TEN2 (1 << 18) - -/* BOFF2: DAC channel2 output buffer disable */ -#define DAC_CR_BOFF2 (1 << 17) - -/* EN2: DAC channel2 enable */ -#define DAC_CR_EN2 (1 << 16) - -/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE1 (1 << 13) - -/* DMAEN1: DAC channel1 DMA enable */ -#define DAC_CR_DMAEN1 (1 << 12) - -/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ -/* DAC_CR_MAMP1_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP1_SHIFT 8 -/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude -values -@ingroup dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 -@{*/ -#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) -/**@}*/ - -/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - */ -#define DAC_CR_WAVE1_SHIFT 6 -#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) -/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable -@ingroup dac_defines - -@li DIS: wave generation disabled -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) -#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) -/**@}*/ - -/* TSEL1[2:0]: DAC channel1 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event in connectivity line devices - * T8: Timer 8 TRGO event in high-density and XL-density devices - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL1_SHIFT 3 -/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection -@ingroup dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line 9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). -@{*/ -#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) -/**@}*/ - -/* TEN1: DAC channel1 trigger enable */ -#define DAC_CR_TEN1 (1 << 2) - -/* BOFF1: DAC channel1 output buffer disable */ -#define DAC_CR_BOFF1 (1 << 1) - -/* EN1: DAC channel1 enable */ -#define DAC_CR_EN1 (1 << 0) - - -/* --- DAC_SWTRIGR values -------------------------------------------------- */ - -/* SWTRIG2: DAC channel2 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) - -/* SWTRIG1: DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) - - -/* --- DAC_DHR12R1 values -------------------------------------------------- */ -#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12L1 values -------------------------------------------------- */ -#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) -#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R1 values --------------------------------------------------- */ -#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12R2 values -------------------------------------------------- */ -#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) - - -/* --- DAC_DHR12L2 values -------------------------------------------------- */ -#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) -#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R2 values --------------------------------------------------- */ -#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12RD values -------------------------------------------------- */ -#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) -#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12LD values -------------------------------------------------- */ -#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) -#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8RD values --------------------------------------------------- */ -#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) -#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) -#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DOR1 values ----------------------------------------------------- */ -#define DAC_DOR1_DACC1DOR_LSB (1 << 0) -#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) - - -/* --- DAC_DOR2 values ----------------------------------------------------- */ -#define DAC_DOR2_DACC2DOR_LSB (1 << 0) -#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) - -/** @defgroup dac_sr_values DAC_SR Values -@{*/ -/** DAC channel 1 DMA underrun flag */ -#define DAC_SR_DMAUDR1 (1 << 13) - -/** DAC channel 2 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) -/*@}*/ - -/** DAC channel identifier */ -typedef enum { - CHANNEL_1, CHANNEL_2, CHANNEL_D -} data_channel; - -/** DAC data size (8/12 bits), alignment (right/left) */ -typedef enum { - RIGHT8, RIGHT12, LEFT12 -} data_align; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dac_enable(data_channel dac_channel); -void dac_disable(data_channel dac_channel); -void dac_buffer_enable(data_channel dac_channel); -void dac_buffer_disable(data_channel dac_channel); -void dac_dma_enable(data_channel dac_channel); -void dac_dma_disable(data_channel dac_channel); -void dac_trigger_enable(data_channel dac_channel); -void dac_trigger_disable(data_channel dac_channel); -void dac_set_trigger_source(uint32_t dac_trig_src); -void dac_set_waveform_generation(uint32_t dac_wave_ens); -void dac_disable_waveform_generation(data_channel dac_channel); -void dac_set_waveform_characteristics(uint32_t dac_mamp); -void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, - data_channel dac_channel); -void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, - data_align dac_data_format); -void dac_software_trigger(data_channel dac_channel); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "dac_common_all.h should not be included explicitly, only via dac.h" -#endif -/** @endcond */ - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/dma2d_common_f47.h b/libopencm3/include/libopencm3/stm32/common/dma2d_common_f47.h deleted file mode 100644 index d66e37e..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dma2d_common_f47.h +++ /dev/null @@ -1,188 +0,0 @@ -/** @addtogroup dma2d_defines - * - * @version 1.0.0 - * - * @date 15 August 2016 - * - * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx - * series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * STM32F4xx/STM32F7xx DMA2D Register defines - * - * Copyright (C) 2016, Chuck McManis - * - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -#include -#include - -#ifndef DMA2D_H -#define DMA2D_H - -/**@{*/ - -/** DMA2D Control Register */ -#define DMA2D_CR MMIO32(DMA2D_BASE + 0x0U) -#define DMA2D_CR_MODE_SHIFT 16 -#define DMA2D_CR_MODE_MASK 0x3 -#define DMA2D_CR_MODE_M2M 0 /* memory to memory */ -#define DMA2D_CR_MODE_M2MWPFC 1 /* memory to memory with pix convert */ -#define DMA2D_CR_MODE_M2MWB 2 /* memory to memory with blend */ -#define DMA2D_CR_MODE_R2M 3 /* register to memory */ -#define DMA2D_CR_CEIE (1 << 13) -#define DMA2D_CR_CTCIE (1 << 12) -#define DMA2D_CR_CAEIE (1 << 11) -#define DMA2D_CR_TWIE (1 << 10) -#define DMA2D_CR_TCIE (1 << 9) -#define DMA2D_CR_TEIE (1 << 8) -#define DMA2D_CR_ABORT (1 << 2) -#define DMA2D_CR_SUSP (1 << 1) -#define DMA2D_CR_START (1 << 0) - -/** DMA2D Interrupt Status Register */ -#define DMA2D_ISR MMIO32(DMA2D_BASE + 0x4U) -#define DMA2D_ISR_CEIF (1 << 5) -#define DMA2D_ISR_CTCIF (1 << 4) -#define DMA2D_ISR_CAEIF (1 << 3) -#define DMA2D_ISR_TWIF (1 << 2) -#define DMA2D_ISR_TCIF (1 << 1) -#define DMA2D_ISR_TEIF (1 << 0) - -/** DMA2D Interrupt Flag Clear Register */ -#define DMA2D_IFCR MMIO32(DMA2D_BASE + 0x8U) -#define DMA2D_IFCR_CCEIF (1 << 5) -#define DMA2D_IFCR_CCTCIF (1 << 4) -#define DMA2D_IFCR_CCAEIF (1 << 3) -#define DMA2D_IFCR_CTWIF (1 << 2) -#define DMA2D_IFCR_CTCIF (1 << 1) -#define DMA2D_IFCR_CTEIF (1 << 0) - -/** DMA2D Foreground Memory Address Register */ -#define DMA2D_FGMAR MMIO32(DMA2D_BASE + 0xCU) - -/** DMA2D Foreground Offset Register */ -#define DMA2D_FGOR MMIO32(DMA2D_BASE + 0x10U) -#define DMA2D_FGOR_LO_SHIFT 0 -#define DMA2D_FGOR_LO_MASK 0x3fff - -/** DMA2D Background Memory Address Register */ -#define DMA2D_BGMAR MMIO32(DMA2D_BASE + 0x14U) - -/** DMA2D Background Offset Register */ -#define DMA2D_BGOR MMIO32(DMA2D_BASE + 0x18U) -#define DMA2D_BGOR_LO_SHIFT 0 -#define DMA2D_BGOR_LO_MASK 0x3fff - -/** DMA2D Foreground and Background PFC Control Register */ -#define DMA2D_FGPFCCR MMIO32(DMA2D_BASE + 0x1cU) -#define DMA2D_BGPFCCR MMIO32(DMA2D_BASE + 0x24U) - -#define DMA2D_xPFCCR_ALPHA_SHIFT 24 -#define DMA2D_xPFCCR_ALPHA_MASK 0xff -#define DMA2D_xPFCCR_AM_SHIFT 16 -#define DMA2D_xPFCCR_AM_MASK 0x3 -#define DMA2D_xPFCCR_AM_NONE 0 -#define DMA2D_xPFCCR_AM_FORCE 1 -#define DMA2D_xPFCCR_AM_PRODUCT 2 -#define DMA2D_xPFCCR_CS_SHIFT 8 -#define DMA2D_xPFCCR_CS_MASK 0xff -#define DMA2D_xPFCCR_START (1 << 5) -#define DMA2D_xPFCCR_CCM_ARGB8888 (0 << 4) -#define DMA2D_xPFCCR_CCM_RGB888 (1 << 4) -#define DMA2D_xPFCCR_CM_SHIFT 0 -#define DMA2D_xPFCCR_CM_MASK 0xf -#define DMA2D_xPFCCR_CM_ARGB8888 0 -#define DMA2D_xPFCCR_CM_RGB888 1 -#define DMA2D_xPFCCR_CM_RGB565 2 -#define DMA2D_xPFCCR_CM_ARGB1555 3 -#define DMA2D_xPFCCR_CM_ARGB4444 4 -#define DMA2D_xPFCCR_CM_L8 5 -#define DMA2D_xPFCCR_CM_AL44 6 -#define DMA2D_xPFCCR_CM_AL88 7 -#define DMA2D_xPFCCR_CM_L4 8 -#define DMA2D_xPFCCR_CM_A8 9 -#define DMA2D_xPFCCR_CM_A4 10 - -/** DMA2D Foreground and Background Color Register */ -#define DMA2D_FGCOLR MMIO32(DMA2D_BASE + 0x20U) -#define DMA2D_BGCOLR MMIO32(DMA2D_BASE + 0x28U) -#define DMA2D_xCOLR_RED_SHIFT 16 -#define DMA2D_xCOLR_RED_MASK 0xff -#define DMA2D_xCOLR_GREEN_SHIFT 8 -#define DMA2D_xCOLR_GREEN_MASK 0xff -#define DMA2D_xCOLR_BLUE_SHIFT 0 -#define DMA2D_xCOLR_BLUE_MASK 0xff - -/** DMA2D Foreground CLUT Memory Address Register */ -#define DMA2D_FGCMAR MMIO32(DMA2D_BASE + 0x2CU) - -/** DMA2D Background CLUT Memory Address Register */ -#define DMA2D_BGCMAR MMIO32(DMA2D_BASE + 0x30U) - -/** DMA2D Output PFC Control Register */ -#define DMA2D_OPFCCR MMIO32(DMA2D_BASE + 0x34U) -#define DMA2D_OPFCCR_CM_SHIFT 0 -#define DMA2D_OPFCCR_CM_MASK 0x3 -#define DMA2D_OPFCCR_CM_ARGB8888 0 -#define DMA2D_OPFCCR_CM_RGB888 1 -#define DMA2D_OPFCCR_CM_RGB565 2 -#define DMA2D_OPFCCR_CM_ARGB1555 3 -#define DMA2D_OPFCCR_CM_ARGB4444 4 - -/** DMA2D Output Color Register */ -/* The format of this register depends on PFC control above */ -#define DMA2D_OCOLR MMIO32(DMA2D_BASE + 0x38U) - -/** DMA2D Output Memory Address Register */ -#define DMA2D_OMAR MMIO32(DMA2D_BASE + 0x3CU) - -/** DMA2D Output offset Register */ -#define DMA2D_OOR MMIO32(DMA2D_BASE + 0x40U) -#define DMA2D_OOR_LO_SHIFT 0 -#define DMA2D_OOR_LO_MASK 0x3fff - -/** DMA2D Number of Lines Register */ -#define DMA2D_NLR MMIO32(DMA2D_BASE + 0x44U) -#define DMA2D_NLR_PL_SHIFT 16 -#define DMA2D_NLR_PL_MASK 0x3fff -#define DMA2D_NLR_NL_SHIFT 0 -#define DMA2D_NLR_NL_MASK 0xffff - -/** DMA2D Line Watermark Register */ -#define DMA2D_LWR MMIO32(DMA2D_BASE + 0x48U) -#define DMA2D_LWR_LW_SHIFT 0 -#define DMA2D_LWR_LW_MASK 0xffff - -/** DMA2D AHB Master Timer Config Register */ -#define DMA2D_AMTCR MMIO32(DMA2D_BASE + 0x4CU) -#define DMA2D_AMTCR_DT_SHIFT 8 -#define DMA2D_AMTCR_DT_MASK 0xff -#define DMA2D_AMTCR_EN (1 << 0) - -/** DMA2D Foreground Color Lookup table */ -#define DMA2D_FG_CLUT (uint32_t *)(DMA2D_BASE + 0x400U) - -/** DMA2D Background Color Lookup table */ -#define DMA2D_BG_CLUT (uint32_t *)(DMA2D_BASE + 0x800U) - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_csel.h b/libopencm3/include/libopencm3/stm32/common/dma_common_csel.h deleted file mode 100644 index 755bb1d..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dma_common_csel.h +++ /dev/null @@ -1,56 +0,0 @@ -/** @addtogroup dma_defines -*/ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H -The order of header inclusion is important. dma.h includes the device -specific memorymap.h header before including this header file.*/ - -/**@{*/ - -/** @cond */ -#ifdef LIBOPENCM3_DMA_H -/** @endcond */ -#pragma once - - -/* DMA channel selection register (DMAx_CSELR) */ -#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8) -#define DMA1_CSELR DMA_CSELR(DMA1) -#define DMA2_CSELR DMA_CSELR(DMA2) - -/* --- DMA_CSELR values -------------------------------------------- */ - -#define DMA_CSELR_CxS_SHIFT(channel) (4 * ((channel) - 1)) -#define DMA_CSELR_CxS_MASK (0x0f) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request); - -END_DECLS - -/** @cond */ -#else -#warning "dma_common_csel.h should not be included explicitly, only via dma.h" -#endif -/** @endcond */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h b/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h deleted file mode 100644 index 63ca380..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h +++ /dev/null @@ -1,627 +0,0 @@ -/** @addtogroup dma_defines - -@author @htmlonly © @endhtmlonly 2011 -Fergus Noble -@author @htmlonly © @endhtmlonly 2012 -Ken Sarkies - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H -The order of header inclusion is important. dma.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_DMA_H -/** @endcond */ -#ifndef LIBOPENCM3_DMA_COMMON_F24_H -#define LIBOPENCM3_DMA_COMMON_F24_H - -/**@{*/ - -/* --- Convenience macros -------------------------------------------------- */ - -/* DMA controller base addresses (for convenience) */ -#define DMA1 DMA1_BASE -#define DMA2 DMA2_BASE - -/* DMA stream base addresses (for API parameters) */ -/** @defgroup dma_st_number DMA Stream Number -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_STREAM0 0 -#define DMA_STREAM1 1 -#define DMA_STREAM2 2 -#define DMA_STREAM3 3 -#define DMA_STREAM4 4 -#define DMA_STREAM5 5 -#define DMA_STREAM6 6 -#define DMA_STREAM7 7 -/**@}*/ - -#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) -#define DMA1_STREAM(n) DMA_STREAM(DMA1, (n)) -#define DMA2_STREAM(n) DMA_STREAM(DMA2, (n)) - -#define DMA1_STREAM0 DMA1_STREAM(0) -#define DMA1_STREAM1 DMA1_STREAM(1) -#define DMA1_STREAM2 DMA1_STREAM(2) -#define DMA1_STREAM3 DMA1_STREAM(3) -#define DMA1_STREAM4 DMA1_STREAM(4) -#define DMA1_STREAM5 DMA1_STREAM(5) -#define DMA1_STREAM6 DMA1_STREAM(6) -#define DMA1_STREAM7 DMA1_STREAM(7) - -#define DMA2_STREAM0 DMA2_STREAM(0) -#define DMA2_STREAM1 DMA2_STREAM(1) -#define DMA2_STREAM2 DMA2_STREAM(2) -#define DMA2_STREAM3 DMA2_STREAM(3) -#define DMA2_STREAM4 DMA2_STREAM(4) -#define DMA2_STREAM5 DMA2_STREAM(5) -#define DMA2_STREAM6 DMA2_STREAM(6) -#define DMA2_STREAM7 DMA2_STREAM(7) - -/* --- DMA controller registers -------------------------------------------- */ - -/* DMA low interrupt status register (DMAx_LISR) */ -#define DMA_LISR(port) MMIO32((port) + 0x00) -#define DMA1_LISR DMA_LISR(DMA1) -#define DMA2_LISR DMA_LISR(DMA2) - -/* DMA high interrupt status register (DMAx_HISR) */ -#define DMA_HISR(port) MMIO32((port) + 0x04) -#define DMA1_HISR DMA_HISR(DMA1) -#define DMA2_HISR DMA_HISR(DMA2) - -/* DMA low interrupt flag clear register (DMAx_LIFCR) */ -#define DMA_LIFCR(port) MMIO32((port) + 0x08) -#define DMA1_LIFCR DMA_LIFCR(DMA1) -#define DMA2_LIFCR DMA_LIFCR(DMA2) - -/* DMA high interrupt flag clear register (DMAx_HIFCR) */ -#define DMA_HIFCR(port) MMIO32((port) + 0x0C) -#define DMA1_HIFCR DMA_HIFCR(DMA1) -#define DMA2_HIFCR DMA_HIFCR(DMA2) - -/* --- DMA stream registers ------------------------------------------------ */ - -/* DMA Stream x configuration register (DMA_SxCR) */ -#define DMA_SCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x00) -#define DMA1_SCR(n) DMA_SCR(DMA1, (n)) -#define DMA2_SCR(n) DMA_SCR(DMA2, (n)) - -#define DMA1_S0CR DMA1_SCR(0) -#define DMA1_S1CR DMA1_SCR(1) -#define DMA1_S2CR DMA1_SCR(2) -#define DMA1_S3CR DMA1_SCR(3) -#define DMA1_S4CR DMA1_SCR(4) -#define DMA1_S5CR DMA1_SCR(5) -#define DMA1_S6CR DMA1_SCR(6) -#define DMA1_S7CR DMA1_SCR(7) - -#define DMA2_S0CR DMA2_SCR(0) -#define DMA2_S1CR DMA2_SCR(1) -#define DMA2_S2CR DMA2_SCR(2) -#define DMA2_S3CR DMA2_SCR(3) -#define DMA2_S4CR DMA2_SCR(4) -#define DMA2_S5CR DMA2_SCR(5) -#define DMA2_S6CR DMA2_SCR(6) -#define DMA2_S7CR DMA2_SCR(7) - -/* DMA Stream x number of data register (DMA_SxNDTR) */ -#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x04) -#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, (n)) -#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, (n)) - -#define DMA1_S0NDTR DMA1_SNDTR(0) -#define DMA1_S1NDTR DMA1_SNDTR(1) -#define DMA1_S2NDTR DMA1_SNDTR(2) -#define DMA1_S3NDTR DMA1_SNDTR(3) -#define DMA1_S4NDTR DMA1_SNDTR(4) -#define DMA1_S5NDTR DMA1_SNDTR(5) -#define DMA1_S6NDTR DMA1_SNDTR(6) -#define DMA1_S7NDTR DMA1_SNDTR(7) - -#define DMA2_S0NDTR DMA2_SNDTR(0) -#define DMA2_S1NDTR DMA2_SNDTR(1) -#define DMA2_S2NDTR DMA2_SNDTR(2) -#define DMA2_S3NDTR DMA2_SNDTR(3) -#define DMA2_S4NDTR DMA2_SNDTR(4) -#define DMA2_S5NDTR DMA2_SNDTR(5) -#define DMA2_S6NDTR DMA2_SNDTR(6) -#define DMA2_S7NDTR DMA2_SNDTR(7) - -/* DMA Stream x peripheral address register (DMA_SxPAR) */ -#define DMA_SPAR(port, n) (*(volatile void **)\ - (DMA_STREAM((port), (n)) + 0x08)) -#define DMA1_SPAR(n) DMA_SPAR(DMA1, (n)) -#define DMA2_SPAR(n) DMA_SPAR(DMA2, (n)) - -#define DMA1_S0PAR DMA1_SPAR(0) -#define DMA1_S1PAR DMA1_SPAR(1) -#define DMA1_S2PAR DMA1_SPAR(2) -#define DMA1_S3PAR DMA1_SPAR(3) -#define DMA1_S4PAR DMA1_SPAR(4) -#define DMA1_S5PAR DMA1_SPAR(5) -#define DMA1_S6PAR DMA1_SPAR(6) -#define DMA1_S7PAR DMA1_SPAR(7) - -#define DMA2_S0PAR DMA2_SPAR(0) -#define DMA2_S1PAR DMA2_SPAR(1) -#define DMA2_S2PAR DMA2_SPAR(2) -#define DMA2_S3PAR DMA2_SPAR(3) -#define DMA2_S4PAR DMA2_SPAR(4) -#define DMA2_S5PAR DMA2_SPAR(5) -#define DMA2_S6PAR DMA2_SPAR(6) -#define DMA2_S7PAR DMA2_SPAR(7) - -/* DMA Stream x memory address 0 register (DMA_SxM0AR) */ -#define DMA_SM0AR(port, n) (*(volatile void **) \ - (DMA_STREAM((port), (n)) + 0x0c)) -#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, (n)) -#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, (n)) - -#define DMA1_S0M0AR DMA1_SM0AR(0) -#define DMA1_S1M0AR DMA1_SM0AR(1) -#define DMA1_S2M0AR DMA1_SM0AR(2) -#define DMA1_S3M0AR DMA1_SM0AR(3) -#define DMA1_S4M0AR DMA1_SM0AR(4) -#define DMA1_S5M0AR DMA1_SM0AR(5) -#define DMA1_S6M0AR DMA1_SM0AR(6) -#define DMA1_S7M0AR DMA1_SM0AR(7) - -#define DMA2_S0M0AR DMA2_SM0AR(0) -#define DMA2_S1M0AR DMA2_SM0AR(1) -#define DMA2_S2M0AR DMA2_SM0AR(2) -#define DMA2_S3M0AR DMA2_SM0AR(3) -#define DMA2_S4M0AR DMA2_SM0AR(4) -#define DMA2_S5M0AR DMA2_SM0AR(5) -#define DMA2_S6M0AR DMA2_SM0AR(6) -#define DMA2_S7M0AR DMA2_SM0AR(7) - -/* DMA Stream x memory address 1 register (DMA_SxM1AR) */ -#define DMA_SM1AR(port, n) (*(volatile void **)\ - (DMA_STREAM((port), (n)) + 0x10)) -#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, (n)) -#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, (n)) - -#define DMA1_S0M1AR DMA1_SM1AR(0) -#define DMA1_S1M1AR DMA1_SM1AR(1) -#define DMA1_S2M1AR DMA1_SM1AR(2) -#define DMA1_S3M1AR DMA1_SM1AR(3) -#define DMA1_S4M1AR DMA1_SM1AR(4) -#define DMA1_S5M1AR DMA1_SM1AR(5) -#define DMA1_S6M1AR DMA1_SM1AR(6) -#define DMA1_S7M1AR DMA1_SM1AR(7) - -#define DMA2_S0M1AR DMA2_SM1AR(0) -#define DMA2_S1M1AR DMA2_SM1AR(1) -#define DMA2_S2M1AR DMA2_SM1AR(2) -#define DMA2_S3M1AR DMA2_SM1AR(3) -#define DMA2_S4M1AR DMA2_SM1AR(4) -#define DMA2_S5M1AR DMA2_SM1AR(5) -#define DMA2_S6M1AR DMA2_SM1AR(6) -#define DMA2_S7M1AR DMA2_SM1AR(7) - -/* DMA Stream x FIFO control register (DMA_SxFCR) */ -#define DMA_SFCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x14) -#define DMA1_SFCR(n) DMA_SFCR(DMA1, (n)) -#define DMA2_SFCR(n) DMA_SFCR(DMA2, (n)) - -#define DMA1_S0FCR DMA1_SFCR(0) -#define DMA1_S1FCR DMA1_SFCR(1) -#define DMA1_S2FCR DMA1_SFCR(2) -#define DMA1_S3FCR DMA1_SFCR(3) -#define DMA1_S4FCR DMA1_SFCR(4) -#define DMA1_S5FCR DMA1_SFCR(5) -#define DMA1_S6FCR DMA1_SFCR(6) -#define DMA1_S7FCR DMA1_SFCR(7) - -#define DMA2_S0FCR DMA2_SFCR(0) -#define DMA2_S1FCR DMA2_SFCR(1) -#define DMA2_S2FCR DMA2_SFCR(2) -#define DMA2_S3FCR DMA2_SFCR(3) -#define DMA2_S4FCR DMA2_SFCR(4) -#define DMA2_S5FCR DMA2_SFCR(5) -#define DMA2_S6FCR DMA2_SFCR(6) -#define DMA2_S7FCR DMA2_SFCR(7) - -/* --- DMA Interrupt Flag offset values ------------------------------------- */ - -/* For API parameters. These are based on every interrupt flag and flag clear -being at the same relative location */ -/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. -@ingroup dma_defines - -@{*/ -/** Transfer Complete Interrupt Flag */ -#define DMA_TCIF (1 << 5) -/** Half Transfer Interrupt Flag */ -#define DMA_HTIF (1 << 4) -/** Transfer Error Interrupt Flag */ -#define DMA_TEIF (1 << 3) -/** Direct Mode Error Interrupt Flag */ -#define DMA_DMEIF (1 << 2) -/** FIFO Error Interrupt Flag */ -#define DMA_FEIF (1 << 0) -/**@}*/ - -/* Offset within interrupt status register to start of stream interrupt flag - * field - */ -#define DMA_ISR_OFFSET(stream) (6*((stream) & 0x01)+16*(((stream) & 0x02) >> 1)) -#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ - DMA_FEIF) -#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) - -/* --- DMA_LISR values ----------------------------------------------------- */ - -#define DMA_LISR_FEIF0 (1 << 0) -#define DMA_LISR_DMEIF0 (1 << 2) -#define DMA_LISR_TEIF0 (1 << 3) -#define DMA_LISR_HTIF0 (1 << 4) -#define DMA_LISR_TCIF0 (1 << 5) - -#define DMA_LISR_FEIF1 (1 << 6) -#define DMA_LISR_DMEIF1 (1 << 8) -#define DMA_LISR_TEIF1 (1 << 9) -#define DMA_LISR_HTIF1 (1 << 10) -#define DMA_LISR_TCIF1 (1 << 11) - -#define DMA_LISR_FEIF2 (1 << 16) -#define DMA_LISR_DMEIF2 (1 << 18) -#define DMA_LISR_TEIF2 (1 << 19) -#define DMA_LISR_HTIF2 (1 << 20) -#define DMA_LISR_TCIF2 (1 << 21) - -#define DMA_LISR_FEIF3 (1 << 22) -#define DMA_LISR_DMEIF3 (1 << 24) -#define DMA_LISR_TEIF3 (1 << 25) -#define DMA_LISR_HTIF3 (1 << 26) -#define DMA_LISR_TCIF3 (1 << 27) - -/* --- DMA_HISR values ----------------------------------------------------- */ - -#define DMA_HISR_FEIF4 (1 << 0) -#define DMA_HISR_DMEIF4 (1 << 2) -#define DMA_HISR_TEIF4 (1 << 3) -#define DMA_HISR_HTIF4 (1 << 4) -#define DMA_HISR_TCIF4 (1 << 5) - -#define DMA_HISR_FEIF5 (1 << 6) -#define DMA_HISR_DMEIF5 (1 << 8) -#define DMA_HISR_TEIF5 (1 << 9) -#define DMA_HISR_HTIF5 (1 << 10) -#define DMA_HISR_TCIF5 (1 << 11) - -#define DMA_HISR_FEIF6 (1 << 16) -#define DMA_HISR_DMEIF6 (1 << 18) -#define DMA_HISR_TEIF6 (1 << 19) -#define DMA_HISR_HTIF6 (1 << 20) -#define DMA_HISR_TCIF6 (1 << 21) - -#define DMA_HISR_FEIF7 (1 << 22) -#define DMA_HISR_DMEIF7 (1 << 24) -#define DMA_HISR_TEIF7 (1 << 25) -#define DMA_HISR_HTIF7 (1 << 26) -#define DMA_HISR_TCIF7 (1 << 27) - -/* --- DMA_LIFCR values ----------------------------------------------------- */ - -#define DMA_LIFCR_CFEIF0 (1 << 0) -#define DMA_LIFCR_CDMEIF0 (1 << 2) -#define DMA_LIFCR_CTEIF0 (1 << 3) -#define DMA_LIFCR_CHTIF0 (1 << 4) -#define DMA_LIFCR_CTCIF0 (1 << 5) - -#define DMA_LIFCR_CFEIF1 (1 << 6) -#define DMA_LIFCR_CDMEIF1 (1 << 8) -#define DMA_LIFCR_CTEIF1 (1 << 9) -#define DMA_LIFCR_CHTIF1 (1 << 10) -#define DMA_LIFCR_CTCIF1 (1 << 11) - -#define DMA_LIFCR_CFEIF2 (1 << 16) -#define DMA_LIFCR_CDMEIF2 (1 << 18) -#define DMA_LIFCR_CTEIF2 (1 << 19) -#define DMA_LIFCR_CHTIF2 (1 << 20) -#define DMA_LIFCR_CTCIF2 (1 << 21) - -#define DMA_LIFCR_CFEIF3 (1 << 22) -#define DMA_LIFCR_CDMEIF3 (1 << 24) -#define DMA_LIFCR_CTEIF3 (1 << 25) -#define DMA_LIFCR_CHTIF3 (1 << 26) -#define DMA_LIFCR_CTCIF3 (1 << 27) - -/* --- DMA_HIFCR values ----------------------------------------------------- */ - -#define DMA_HIFCR_CFEIF4 (1 << 0) -#define DMA_HIFCR_CDMEIF4 (1 << 2) -#define DMA_HIFCR_CTEIF4 (1 << 3) -#define DMA_HIFCR_CHTIF4 (1 << 4) -#define DMA_HIFCR_CTCIF4 (1 << 5) - -#define DMA_HIFCR_CFEIF5 (1 << 6) -#define DMA_HIFCR_CDMEIF5 (1 << 8) -#define DMA_HIFCR_CTEIF5 (1 << 9) -#define DMA_HIFCR_CHTIF5 (1 << 10) -#define DMA_HIFCR_CTCIF5 (1 << 11) - -#define DMA_HIFCR_CFEIF6 (1 << 16) -#define DMA_HIFCR_CDMEIF6 (1 << 18) -#define DMA_HIFCR_CTEIF6 (1 << 19) -#define DMA_HIFCR_CHTIF6 (1 << 20) -#define DMA_HIFCR_CTCIF6 (1 << 21) - -#define DMA_HIFCR_CFEIF7 (1 << 22) -#define DMA_HIFCR_CDMEIF7 (1 << 24) -#define DMA_HIFCR_CTEIF7 (1 << 25) -#define DMA_HIFCR_CHTIF7 (1 << 26) -#define DMA_HIFCR_CTCIF7 (1 << 27) - -/* --- DMA_SxCR values ----------------------------------------------------- */ - -/* EN: Stream enable */ -#define DMA_SxCR_EN (1 << 0) -/* DMEIE: Direct Mode error interrupt enable */ -#define DMA_SxCR_DMEIE (1 << 1) -/* TEIE: Transfer error interrupt enable */ -#define DMA_SxCR_TEIE (1 << 2) -/* HTIE: Half transfer interrupt enable */ -#define DMA_SxCR_HTIE (1 << 3) -/* TCIE: Transfer complete interrupt enable */ -#define DMA_SxCR_TCIE (1 << 4) -/* PFCTRL: Peripheral Flow Controller */ -#define DMA_SxCR_PFCTRL (1 << 5) - -/* DIR[7:6]: Data transfer direction */ -/** @defgroup dma_st_dir DMA Stream Data transfer direction -@ingroup dma_defines - -@{*/ -#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6) -#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6) -#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6) -/**@}*/ -#define DMA_SxCR_DIR_SHIFT 6 -#define DMA_SxCR_DIR_MASK (3 << 6) - -/* CIRC: Circular mode */ -#define DMA_SxCR_CIRC (1 << 8) -/* PINC: Peripheral increment mode */ -#define DMA_SxCR_PINC (1 << 9) -/* MINC: Memory increment mode */ -#define DMA_SxCR_MINC (1 << 10) - -/* PSIZE[12:11]: Peripheral size */ -/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_SxCR_PSIZE_8BIT (0 << 11) -#define DMA_SxCR_PSIZE_16BIT (1 << 11) -#define DMA_SxCR_PSIZE_32BIT (2 << 11) -/**@}*/ -#define DMA_SxCR_PSIZE_SHIFT 11 -#define DMA_SxCR_PSIZE_MASK (3 << 11) - -/* MSIZE[14:13]: Memory size */ -/** @defgroup dma_st_memwidth DMA Stream Memory Word Width -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_SxCR_MSIZE_8BIT (0 << 13) -#define DMA_SxCR_MSIZE_16BIT (1 << 13) -#define DMA_SxCR_MSIZE_32BIT (2 << 13) -/**@}*/ -#define DMA_SxCR_MSIZE_SHIFT 13 -#define DMA_SxCR_MSIZE_MASK (3 << 13) - -/* PINCOS: Peripheral increment offset size */ -#define DMA_SxCR_PINCOS (1 << 15) - -/* PL[17:16]: Stream priority level */ -/** @defgroup dma_st_pri DMA Stream Priority Levels -@ingroup dma_defines - -@{*/ -#define DMA_SxCR_PL_LOW (0 << 16) -#define DMA_SxCR_PL_MEDIUM (1 << 16) -#define DMA_SxCR_PL_HIGH (2 << 16) -#define DMA_SxCR_PL_VERY_HIGH (3 << 16) -/**@}*/ -#define DMA_SxCR_PL_SHIFT 16 -#define DMA_SxCR_PL_MASK (3 << 16) - -/* DBM: Double buffered mode */ -#define DMA_SxCR_DBM (1 << 18) -/* CT: Current target (in double buffered mode) */ -#define DMA_SxCR_CT (1 << 19) - -/* Bit 20 reserved */ - -/* PBURST[13:12]: Peripheral Burst Configuration */ -/** @defgroup dma_pburst DMA Peripheral Burst Length -@ingroup dma_defines - -@{*/ -#define DMA_SxCR_PBURST_SINGLE (0 << 21) -#define DMA_SxCR_PBURST_INCR4 (1 << 21) -#define DMA_SxCR_PBURST_INCR8 (2 << 21) -#define DMA_SxCR_PBURST_INCR16 (3 << 21) -/**@}*/ -#define DMA_SxCR_PBURST_SHIFT 21 -#define DMA_SxCR_PBURST_MASK (3 << 21) - -/* MBURST[13:12]: Memory Burst Configuration */ -/** @defgroup dma_mburst DMA Memory Burst Length -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_SxCR_MBURST_SINGLE (0 << 23) -#define DMA_SxCR_MBURST_INCR4 (1 << 23) -#define DMA_SxCR_MBURST_INCR8 (2 << 23) -#define DMA_SxCR_MBURST_INCR16 (3 << 23) -/**@}*/ -#define DMA_SxCR_MBURST_SHIFT 23 -#define DMA_SxCR_MBURST_MASK (3 << 23) - -/* CHSEL[25:27]: Channel Select */ -/** @defgroup dma_ch_sel DMA Channel Select -@ingroup dma_defines - -@{*/ -#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT) -#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT) -/**@}*/ -#define DMA_SxCR_CHSEL_SHIFT 25 -#define DMA_SxCR_CHSEL_MASK (7 << 25) -#define DMA_SxCR_CHSEL(n) ((n) << DMA_SxCR_CHSEL_SHIFT) - -/* Reserved [31:28] */ - -/* --- DMA_SxNDTR values --------------------------------------------------- */ - -/* DMA_SxNDTR[15:0]: Number of data register. */ - -/* --- DMA_SxPAR values ---------------------------------------------------- */ - -/* DMA_SxPAR[31:0]: Peripheral address register. */ - -/* --- DMA_SxM0AR values --------------------------------------------------- */ - -/* DMA_SxM0AR[31:0]: Memory 0 address register. */ - -/* --- DMA_SxM1AR values --------------------------------------------------- */ - -/* DMA_SxM1AR[31:0]: Memory 1 address register. */ - -/* --- DMA_SxFCR values ---------------------------------------------------- */ - -/* FTH[1:0]: FIFO Threshold selection */ -/** @defgroup dma_fifo_thresh FIFO Threshold selection -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_SxFCR_FTH_1_4_FULL (0 << 0) -#define DMA_SxFCR_FTH_2_4_FULL (1 << 0) -#define DMA_SxFCR_FTH_3_4_FULL (2 << 0) -#define DMA_SxFCR_FTH_4_4_FULL (3 << 0) -/**@}*/ -#define DMA_SxFCR_FTH_SHIFT 0 -#define DMA_SxFCR_FTH_MASK (3 << 0) - -/* DMDIS: Direct Mode disable */ -#define DMA_SxFCR_DMDIS (1 << 2) - -/* FS[5:3]: FIFO Status */ -/** @defgroup dma_fifo_status FIFO Status -@ingroup STM32F4xx_dma_defines - -@{*/ -#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0) -#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0) -#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0) -#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0) -#define DMA_SxFCR_FS_FULL (4 << 3) -#define DMA_SxFCR_FS_EMPTY (5 << 3) -/**@}*/ -#define DMA_SxFCR_FS_SHIFT 3 -#define DMA_SxFCR_FS_MASK (7 << 3) - -/* [6]: reserved */ - -/* FEIE[7]: FIFO error interrupt enable */ -#define DMA_SxFCR_FEIE (1 << 7) - -/* [31:8]: Reserved */ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -/* - * Note: The F2 and F4 series have a completely new DMA peripheral with - * different configuration options. - */ - -void dma_stream_reset(uint32_t dma, uint8_t stream); -void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, - uint32_t interrupts); -bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt); -void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction); -void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio); -void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size); -void dma_set_peripheral_size(uint32_t dma, uint8_t stream, - uint32_t peripheral_size); -void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream); -void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream); -void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream); -void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream); -void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream); -void dma_enable_circular_mode(uint32_t dma, uint8_t stream); -void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel); -void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst); -void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst); -void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory); -uint8_t dma_get_target(uint32_t dma, uint8_t stream); -void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream); -void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream); -void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream); -void dma_set_dma_flow_control(uint32_t dma, uint8_t stream); -void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream); -void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream); -void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream); -void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream); -void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); -void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); -uint32_t dma_fifo_status(uint32_t dma, uint8_t stream); -void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); -void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); -void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream); -void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream); -void dma_enable_direct_mode(uint32_t dma, uint8_t stream); -void dma_enable_fifo_mode(uint32_t dma, uint8_t stream); -void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold); -void dma_enable_stream(uint32_t dma, uint8_t stream); -void dma_disable_stream(uint32_t dma, uint8_t stream); -void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address); -void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address); -void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address); -uint16_t dma_get_number_of_data(uint32_t dma, uint8_t stream); -void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number); - -END_DECLS -/**@}*/ -#endif -/** @cond */ -#else -#warning "dma_common_f24.h should not be included explicitly, only via dma.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h b/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h deleted file mode 100644 index 489c9de..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h +++ /dev/null @@ -1,426 +0,0 @@ -/** @addtogroup dma_defines - -@author @htmlonly © @endhtmlonly 2010 -Thomas Otto -@author @htmlonly © @endhtmlonly 2012 -Piotr Esden-Tempski - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H -The order of header inclusion is important. dma.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_DMA_H -/** @endcond */ -#ifndef LIBOPENCM3_DMA_COMMON_F13_H -#define LIBOPENCM3_DMA_COMMON_F13_H - -/* --- Convenience macros -------------------------------------------------- */ - -/* DMA register base adresses (for convenience) */ -#define DMA1 DMA1_BASE -#define DMA2 DMA2_BASE - -/* --- DMA registers ------------------------------------------------------- */ - -/* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32((dma_base) + 0x00) -#define DMA1_ISR DMA_ISR(DMA1) -#define DMA2_ISR DMA_ISR(DMA2) - -/* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32((dma_base) + 0x04) -#define DMA1_IFCR DMA_IFCR(DMA1) -#define DMA2_IFCR DMA_IFCR(DMA2) - -/* DMA channel configuration register (DMAx_CCRy) */ -#define DMA_CCR(dma_base, channel) MMIO32((dma_base) + 0x08 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) -#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) -#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) -#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) -#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) -#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) -#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) -#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) - -#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) -#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) -#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) -#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) -#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) -#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) - -/* DMA number of data register (DMAx_CNDTRy) */ -#define DMA_CNDTR(dma_base, channel) MMIO32((dma_base) + 0x0C + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) -#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) -#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) -#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) -#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) -#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) -#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) -#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) - -#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) -#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) -#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) -#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) -#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) -#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) - -/* DMA peripheral address register (DMAx_CPARy) */ -#define DMA_CPAR(dma_base, channel) MMIO32((dma_base) + 0x10 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) -#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) -#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) -#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) -#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) -#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) -#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) -#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) - -#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) -#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) -#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) -#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) -#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) -#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) - -/* DMA memory address register (DMAx_CMARy) */ - -#define DMA_CMAR(dma_base, channel) MMIO32((dma_base) + 0x14 + \ - (0x14 * ((channel) - 1))) - -#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) -#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) -#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) -#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) -#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) -#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) -#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) -#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) - -#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) -#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) -#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) -#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) -#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) -#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) - -/* --- DMA_ISR values ------------------------------------------------------ */ - -/* --- DMA Interrupt Flag offset values ------------------------------------- */ -/* These are based on every interrupt flag and flag clear being at the same - * relative location - */ -/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag -group. -@ingroup dma_defines - -@{*/ -/** Transfer Error Interrupt Flag */ -#define DMA_TEIF (1 << 3) -/** Half Transfer Interrupt Flag */ -#define DMA_HTIF (1 << 2) -/** Transfer Complete Interrupt Flag */ -#define DMA_TCIF (1 << 1) -/** Global Interrupt Flag */ -#define DMA_GIF (1 << 0) -/**@}*/ - -/* Offset within interrupt status register to start of channel interrupt flag - * field - */ -#define DMA_FLAG_OFFSET(channel) (4*((channel) - 1)) -#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ - DMA_GIF) -#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) - -/* TEIF: Transfer error interrupt flag */ -#define DMA_ISR_TEIF_BIT DMA_TEIF -#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) -#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) -#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) -#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) -#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) -#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) -#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) - -/* HTIF: Half transfer interrupt flag */ -#define DMA_ISR_HTIF_BIT DMA_HTIF -#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) -#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) -#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) -#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) -#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) -#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) -#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) - -/* TCIF: Transfer complete interrupt flag */ -#define DMA_ISR_TCIF_BIT DMA_TCIF -#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) -#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) -#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) -#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) -#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) -#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) -#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) - -/* GIF: Global interrupt flag */ -#define DMA_ISR_GIF_BIT DMA_GIF -#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) -#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) -#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) -#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) -#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) -#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) -#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) - -/* --- DMA_IFCR values ----------------------------------------------------- */ - -/* CTEIF: Transfer error clear */ -#define DMA_IFCR_CTEIF_BIT DMA_TEIF -#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) -#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) -#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) -#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) -#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) -#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) - -/* CHTIF: Half transfer clear */ -#define DMA_IFCR_CHTIF_BIT DMA_HTIF -#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) -#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) -#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) -#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) -#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) -#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) - -/* CTCIF: Transfer complete clear */ -#define DMA_IFCR_CTCIF_BIT DMA_TCIF -#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) -#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) -#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) -#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) -#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) -#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) - -/* CGIF: Global interrupt clear */ -#define DMA_IFCR_CGIF_BIT DMA_GIF -#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) -#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) -#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) -#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) -#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) -#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) - -/* Clear interrupts mask */ -#define DMA_IFCR_CIF_BIT 0xF -#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \ - (DMA_FLAG_OFFSET(channel))) - -#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) -#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) -#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) -#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) -#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) -#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) -#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) - -/* --- DMA_CCRx generic values --------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -/** @defgroup dma_ch_pri DMA Channel Priority Levels -@ingroup dma_defines - -@{*/ -#define DMA_CCR_PL_LOW (0x0 << 12) -#define DMA_CCR_PL_MEDIUM (0x1 << 12) -#define DMA_CCR_PL_HIGH (0x2 << 12) -#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) -/**@}*/ -#define DMA_CCR_PL_MASK (0x3 << 12) -#define DMA_CCR_PL_SHIFT 12 - -/* MSIZE[11:10]: Memory size */ -/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width -@ingroup dma_defines - -@{*/ -#define DMA_CCR_MSIZE_8BIT (0x0 << 10) -#define DMA_CCR_MSIZE_16BIT (0x1 << 10) -#define DMA_CCR_MSIZE_32BIT (0x2 << 10) -/**@}*/ -#define DMA_CCR_MSIZE_MASK (0x3 << 10) -#define DMA_CCR_MSIZE_SHIFT 10 - -/* PSIZE[9:8]: Peripheral size */ -/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width -@ingroup dma_defines - -@{*/ -#define DMA_CCR_PSIZE_8BIT (0x0 << 8) -#define DMA_CCR_PSIZE_16BIT (0x1 << 8) -#define DMA_CCR_PSIZE_32BIT (0x2 << 8) -/**@}*/ -#define DMA_CCR_PSIZE_MASK (0x3 << 8) -#define DMA_CCR_PSIZE_SHIFT 8 - -/* MINC: Memory increment mode */ -#define DMA_CCR_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR_EN (1 << 0) - -/* --- DMA_CNDTRx values --------------------------------------------------- */ - -/* NDT[15:0]: Number of data to transfer */ - -/* --- DMA_CPARx values ---------------------------------------------------- */ - -/* PA[31:0]: Peripheral address */ - -/* --- DMA_CMARx values ---------------------------------------------------- */ - -/* MA[31:0]: Memory address */ - -/* --- Generic values ------------------------------------------------------ */ - -/** @defgroup dma_ch DMA Channel Number -@ingroup dma_defines - -@{*/ -#define DMA_CHANNEL1 1 -#define DMA_CHANNEL2 2 -#define DMA_CHANNEL3 3 -#define DMA_CHANNEL4 4 -#define DMA_CHANNEL5 5 -#define DMA_CHANNEL6 6 -#define DMA_CHANNEL7 7 -/**@}*/ - -/* --- function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dma_channel_reset(uint32_t dma, uint8_t channel); -void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, - uint32_t interrupts); -bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts); -void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel); -void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio); -void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size); -void dma_set_peripheral_size(uint32_t dma, uint8_t channel, - uint32_t peripheral_size); -void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel); -void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); -void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel); -void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); -void dma_enable_circular_mode(uint32_t dma, uint8_t channel); -void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel); -void dma_set_read_from_memory(uint32_t dma, uint8_t channel); -void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel); -void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel); -void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel); -void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel); -void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); -void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); -void dma_enable_channel(uint32_t dma, uint8_t channel); -void dma_disable_channel(uint32_t dma, uint8_t channel); -void dma_set_peripheral_address(uint32_t dma, uint8_t channel, - uint32_t address); -void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address); -uint16_t dma_get_number_of_data(uint32_t dma, uint8_t channel); -void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "dma_common_f13.h should not be included explicitly, only via dma.h" -#endif -/** @endcond */ - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/dmamux_common_all.h b/libopencm3/include/libopencm3/stm32/common/dmamux_common_all.h deleted file mode 100644 index c3bd0bf..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dmamux_common_all.h +++ /dev/null @@ -1,214 +0,0 @@ -/** @addtogroup dmamux_defines - * - * @author @htmlonly © @endhtmlonly 2019 - * Guillaume Revaillot - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @cond */ -#if defined(LIBOPENCM3_DMAMUX_H) -/** @endcond */ -#ifndef LIBOPENCM3_DMAMUX_COMMON_ALL_H -#define LIBOPENCM3_DMAMUX_COMMON_ALL_H - -/**@{*/ - -#define DMAMUX_CxCR(dmamux_base, dma_channel) MMIO32((dmamux_base) + 0x04 * ((dma_channel) - 1)) -#define DMAMUX1_CxCR(dma_channel) DMAMUX_CxCR(DMAMUX1, (dma_channel)) -#define DMAMUX2_CxCR(dma_channel) DMAMUX_CxCR(DMAMUX2, (dma_channel)) - -#define DMAMUX_CSR(dmamux_base) MMIO32((dmamux_base) + 0x80) -#define DMAMUX1_CSR(dmamux_base) DMAMUX_CSR(DMAMUX1) -#define DMAMUX2_CSR(dmamux_base) DMAMUX_CSR(DMAMUX2) - -#define DMAMUX_CFR(dmamux_base) MMIO32((dmamux_base) + 0x84) -#define DMAMUX1_CFR(dmamux_base) DMAMUX_CFR(DMAMUX1) -#define DMAMUX2_CFR(dmamux_base) DMAMUX_CFR(DMAMUX2) - -#define DMAMUX_RGxCR(dmamux_base, rg_channel) MMIO32((dmamux_base) + 0x100 + 0x04 * ((rg_channel) - 1)) -#define DMAMUX1_RGxCR(dmamux_base, rg_channel) DMAMUX_RGxCR(DMAMUX1, (rg_channel)) -#define DMAMUX2_RGxCR(dmamux_base, rg_channel) DMAMUX_RGxCR(DMAMUX2, (rg_channel)) - -#define DMAMUX_RGSR(dmamux_base) MMIO32((dmamux_base) + 0x140) -#define DMAMUX1_RGSR(dmamux_base) DMAMUX_RSGR(DMAMUX1) -#define DMAMUX2_RGSR(dmamux_base) DMAMUX_RSGR(DMAMUX2) - -#define DMAMUX_RGCFR(dmamux_base) MMIO32((dmamux_base) + 0x144) -#define DMAMUX1_RGCFR(dmamux_base) DMAMUX_RGCFR(DMAMUX1) -#define DMAMUX2_RGCFR(dmamux_base) DMAMUX_RGCFR(DMAMUX2) - -/** @defgroup dmamux_cxcr CxCR DMA request line multiplexer channel x control register -@{*/ - -/** DMAMUX_CxCR_SYNC_ID Synchronization input selected */ -#define DMAMUX_CxCR_SYNC_ID_SHIFT 24 -#define DMAMUX_CxCR_SYNC_ID_MASK 0x1f - -/** DMAMUX_CxCR_NBREQ Number (minus 1) of DMA requests to forward */ -#define DMAMUX_CxCR_NBREQ_SHIFT 19 -#define DMAMUX_CxCR_NBREQ_MASK 0x1f - -#define DMAMUX_CxCR_SPOL_SHIFT 17 -#define DMAMUX_CxCR_SPOL_MASK 0x03 -/** @defgroup dmamux_cxcr_spol SPOL Event Polarity -* @brief Synchronization event type selector -@{*/ -#define DMAMUX_CxCR_SPOL_NO_EVENT 0 -#define DMAMUX_CxCR_SPOL_RISING_EDGE 1 -#define DMAMUX_CxCR_SPOL_FALLING_EDEG 2 -#define DMAMUX_CxCR_SPOL_BOTH_EDGES 3 -/**@}*/ - -/** DMAMUX_CxCR_SE Synchronous operating mode enable/disable */ -#define DMAMUX_CxCR_SE (1 << 16) - -/** DMAMUX_CxCR_EGE Event generation enable/disable */ -#define DMAMUX_CxCR_EGE (1 << 9) - -/** DMAMUX_CxCR_SOIE Interrupt enable at synchronization event overrun */ -#define DMAMUX_CxCR_SOIE (1 << 8) - -/** DMAMUX_CxCR_DMAREQ_ID Input DMA request line selected */ -#define DMAMUX_CxCR_DMAREQ_ID_SHIFT 0 -#define DMAMUX_CxCR_DMAREQ_ID_MASK 0xff - -/**@}*/ - -/** @defgroup dmamux_csr CSR request line multiplexer interrupt channel status register -@{*/ - -/** DMAMUX_CSR_SOF Synchronization overrun event flag */ -#define DMAMUX_CSR_SOF(dma_channel) (1 << ((dma_channel) - 1)) - -/**@}*/ - -/** @defgroup dmamux_cfr CFR request line multiplexer interrupt clear flag register -@{*/ - -/** DMAMUX_CFR_CSOF Clear synchronization overrun event flag */ -#define DMAMUX_CFR_CSOF(dma_channel) (1 << ((dma_channel) - 1)) - -/**@}*/ - -/** @defgroup dmamux_rgxcr RGxCR DMA request generator channel x control register -@{*/ - -/** DMAMUX_RGxCR_GNBREQ GNBREQ Number (minus 1) of DMA requests to generate */ -#define DMAMUX_RGxCR_GNBREQ_SHIFT 19 -#define DMAMUX_RGxCR_GNBREQ_MASK 0x1f - -#define DMAMUX_RGxCR_GPOL_SHIFT 17 -#define DMAMUX_RGxCR_GPOL_MASK 0x03 -/** @defgroup dmamux_rgxcr_gpol GPOL Event Polarity -* @brief DMA request generator trigger event type selection -@{*/ -#define DMAMUX_RGxCR_GPOL_NO_EVENT 0 -#define DMAMUX_RGxCR_GPOL_RISING_EDGE 1 -#define DMAMUX_RGxCR_GPOL_FALLING_EDEG 2 -#define DMAMUX_RGxCR_GPOL_BOTH_EDGES 3 -/**@}*/ - -/** DMAMUX_RGxCR_GE GE DMA request generator channel enable/disable */ -#define DMAMUX_RGxCR_GE (1 << 16) - -/** DMAMUX_RGxCR_OIE OIE Interrupt enable at trigger event overrun */ -#define DMAMUX_RGxCR_OIE (1 << 8) - -/** DMAMUX_RGxCR_SIG_ID SIG_ID DMA request trigger input selected */ -#define DMAMUX_RGxCR_SIG_ID_SHIFT 0 -#define DMAMUX_RGxCR_SIG_ID_MASK 0x1f - -/**@}*/ - -/** @defgroup dmamux_rgsr RGSR DMA request generator interrupt status register -@{*/ - -/** DMAMUX_RGSR_OF Trigger OF event overrun flag */ -#define DMAMUX_RGSR_OF(rg_channel) (1 << ((rg_channel) - 1)) - -/**@}*/ - -/** @defgroup dmamux_rgcfr RGCFR DMA request generator clear flag register -@{*/ - -/** DMAMUX_RGCFR_COF COF Clear trigger event overrun flag */ -#define DMAMUX_RGCFR_COF(rg_channel) (1 << ((rg_channel) - 1)) - -/**@}*/ - -/* --- Generic values ---------------------------------------- */ - -/** @defgroup dmamux_rg_channel DMAMUX Request Generator Channel Number -@{*/ -#define DMAMUX_RG_CHANNEL1 1 -#define DMAMUX_RG_CHANNEL2 2 -#define DMAMUX_RG_CHANNEL3 3 -#define DMAMUX_RG_CHANNEL4 4 -/**@}*/ - -/* --- function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dmamux_reset_dma_channel(uint32_t dmamux, uint8_t channel); -void dmamux_enable_dma_request_event_generation(uint32_t dmamux, uint8_t channel); -void dmamux_disable_dma_request_event_generation(uint32_t dmamux, uint8_t channel); - -void dmamux_set_dma_channel_request(uint32_t dmamux, uint8_t channel, uint8_t request_id); -uint8_t dmamux_get_dma_channel_request(uint32_t dmamux, uint8_t channel); - -void dmamux_enable_dma_request_sync(uint32_t dmamux, uint8_t channel); -void dmamux_disable_dma_request_sync(uint32_t dmamux, uint8_t channel); - -void dmamux_set_dma_request_sync_input(uint32_t dmamux, uint8_t channel, uint8_t sync_id); -void dmamux_set_dma_request_sync_pol(uint32_t dmamux, uint8_t channel, uint8_t polarity); -void dmamux_set_dma_request_sync_nbreq(uint32_t dmamux, uint8_t channel, uint8_t nbreq); - -void dmamux_enable_dma_request_sync_overrun_interrupt(uint32_t dmamux, uint8_t channel); -void dmamux_disable_dma_request_sync_overrun_interrupt(uint32_t dmamux, uint8_t channel); -uint32_t dmamux_get_dma_request_sync_overrun(uint32_t dmamux, uint8_t channel); -void dmamux_clear_dma_request_sync_overrun(uint32_t dmamux, uint8_t channel); - -void dmamux_reset_request_generator_channel(uint32_t dmamux, uint8_t rg_channel); -void dmamux_enable_request_generator(uint32_t dmamux, uint8_t rg_channel); -void dmamux_disable_request_generator(uint32_t dmamux, uint8_t rg_channel); - -void dmamux_set_request_generator_trigger(uint32_t dmamux, uint8_t rg_channel, uint8_t sig_id); -void dmamux_set_request_generator_trigger_pol(uint32_t dmamux, uint8_t rg_channel, uint8_t polarity); -void dmamux_set_request_generator_trigger_gnbreq(uint32_t dmamux, uint8_t rg_channel, uint8_t gnbreq); - -void dmamux_enable_request_generator_trigger_overrun_interrupt(uint32_t dmamux, uint8_t rg_channel); -void dmamux_disable_request_generator_trigger_overrun_interrupt(uint32_t dmamux, uint8_t rg_channel); -uint32_t dmamux_get_request_generator_trigger_overrun_interrupt(uint32_t dmamux, uint8_t rg_channel); -void dmamux_clear_request_generator_trigger_overrun_interrupt(uint32_t dmamux, uint8_t rg_channel); - -END_DECLS - -/**@}*/ - -#endif -/** @cond */ -#else -#warning "dmamux_common_all.h should not be included explicitly, only via dmamux.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/dsi_common_f47.h b/libopencm3/include/libopencm3/stm32/common/dsi_common_f47.h deleted file mode 100644 index 963c3dc..0000000 --- a/libopencm3/include/libopencm3/stm32/common/dsi_common_f47.h +++ /dev/null @@ -1,824 +0,0 @@ -/** @addtogroup dsi_defines - * - * @version 1.0.0 - * - * @date 7 July 2016 - * - * @author @htmlonly © @endhtmlonly 2016 - * Chuck McManis - * - * This library supports the Display Serial Interface Host and Wrapper in - * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by - * ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * STM32F4/7 DSI Host Defines - * - * Copyright (C) 2016, Chuck McManis - * - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -#include -#include - -/** @cond */ -#ifndef DSI_H -/** @endcond */ -#define DSI_H - -/**@{*/ - - -/** - * DSI Host Version Register - */ -#define DSI_VR MMIO32(DSI_BASE + 0x0U) - -/** - * DSI Host Control Register - */ -#define DSI_CR MMIO32(DSI_BASE + 0x4U) -#define DSI_CR_EN (1 << 0) - -/** - * DSI Host Clock Control Register - */ -#define DSI_CCR MMIO32(DSI_BASE + 0x8U) -#define DSI_CCR_TOCKDIV_SHIFT 8 -#define DSI_CCR_TOCKDIV_MASK 0xff -#define DSI_CCR_TXECKDIV_SHIFT 0 -#define DSI_CCR_TXECKDIV_MASK 0xff - -/** - * DSI Host LTDC VCID Register - */ -#define DSI_LVCIDR MMIO32(DSI_BASE + 0xcU) -#define DSI_LVCIDR_VCID_SHIFT 0 -#define DSI_LVCIDR_VCID_MASK 0x3 - -/** - * DSI Host LTDC Color Coding Register - */ -#define DSI_LCOLCR MMIO32(DSI_BASE + 0x10U) -#define DSI_LCOLCR_LPE (1 << 8) -#define DSI_LCOLCR_COLC_SHIFT 0 -#define DSI_LCOLCR_COLC_MASK 0xf - -/** - * DSI Host LTDC Polarity Configuration Register - */ -#define DSI_LPCR MMIO32(DSI_BASE + 0x14U) -#define DSI_LPCR_HSP (1 << 2) -#define DSI_LPCR_VSP (1 << 1) -#define DSI_LPCR_DEP (1 << 0) - -/** - * DSI Host Low-power Configuration Register - */ -#define DSI_LPMCR MMIO32(DSI_BASE + 0x18U) -#define DSI_LPMCR_LPSIZE_SHIFT 16 -#define DSI_LPMCR_LPSIZE_MASK 0xff -#define DSI_LPMCR_VLPSIZE_SHIFT 0 -#define DSI_LPMCR_VLPSIZE_MASK 0xff - -/** - * DSI Host Protocol Configuration Register - */ -#define DSI_PCR MMIO32(DSI_BASE + 0x2cU) -#define DSI_PCR_CRCRXE (1 << 4) -#define DSI_PCR_ECCRXE (1 << 3) -#define DSI_PCR_BTAE (1 << 2) -#define DSI_PCR_ETRXE (1 << 1) -#define DSI_PCR_ETTXE (1 << 0) - -/** - * DSI Host Generic VCID Register - */ -#define DSI_GVCIDR MMIO32(DSI_BASE + 0x30U) -#define DSI_GVCIDR_VCID_SHIFT 0 -#define DSI_GVCIDR_VCID_MASK 0x3 - -/** - * DSI Host mode Configuration Register - */ -#define DSI_MCR MMIO32(DSI_BASE + 0x34U) -#define DSI_MCR_CMDM (1 << 0) - -/** - * DSI Host Video mode Configuration Register - */ -#define DSI_VMCR MMIO32(DSI_BASE + 0x38U) -#define DSI_VMCR_PGO (1 << 24) -#define DSI_VMCR_PGM (1 << 20) -#define DSI_VMCR_PGE (1 << 16) -#define DSI_VMCR_LPCE (1 << 15) -#define DSI_VMCR_FBTAAE (1 << 14) -#define DSI_VMCR_LPHFPE (1 << 13) -#define DSI_VMCR_LPHBPE (1 << 12) -#define DSI_VMCR_LPVAE (1 << 11) -#define DSI_VMCR_LPVFPE (1 << 10) -#define DSI_VMCR_LPVBPE (1 << 9) -#define DSI_VMCR_LPVSAE (1 << 8) -#define DSI_VMCR_VMT_SHIFT 0 -#define DSI_VMCR_VMT_MASK 0x3 -#define DSI_VMCR_VMT_NON_BURST_PULSE 0x0 -#define DSI_VMCR_VMT_NON_BURSE_EVENT 0x1 -#define DSI_VMCR_VMT_BURST 0x2 - -/** - * DSI Host Video Packet Configuration Register - */ -#define DSI_VPCR MMIO32(DSI_BASE + 0x3CU) -#define DSI_VPCR_VPSIZE_SHIFT 0 -#define DSI_VPCR_VPSIZE_MASK 0x3fff - -/** - * DSI Host Video Chunks Configuration Register - */ -#define DSI_VCCR MMIO32(DSI_BASE + 0x40U) -#define DSI_VCCR_NUMC_SHIFT 0 -#define DSI_VCCR_NUMC_MASK 0x1fff - -/** - * DSI Host Video Null Packet Configuration Register - */ -#define DSI_VNPCR MMIO32(DSI_BASE + 0x44U) -#define DSI_VNPCR_NPSIZE_SHIFT 0 -#define DSI_VNPCR_NPSIZE_MASK 0x1fff - -/** - * DSI Host Video HSA Configuration Register - */ -#define DSI_VHSACR MMIO32(DSI_BASE + 0x48U) -#define DSI_VHSACR_HSA_SHIFT 0 -#define DSI_VHSACR_HSA_MASK 0xfff - -/** - * DSI Host Video HBP Configuration Register - */ -#define DSI_VHBPCR MMIO32(DSI_BASE + 0x4CU) -#define DSI_VHBPCR_HBP_SHIFT 0 -#define DSI_VHBPCR_HBP_MASK 0xfff - -/** - * DSI Host Video Line Configuration Register - */ -#define DSI_VLCR MMIO32(DSI_BASE + 0x50U) -#define DSI_VLCR_HLINE_SHIFT 0 -#define DSI_VLCR_HLINE_MASK 0x7fff - -/** - * DSI Host Video VSA Configuration Register - */ -#define DSI_VVSACR MMIO32(DSI_BASE + 0x54U) -#define DSI_VVSACR_VSA_SHIFT 0 -#define DSI_VVSACR_VSA_MASK 0x3ff - -/** - * DSI Host Video VBP Configuration Register - */ -#define DSI_VVBPCR MMIO32(DSI_BASE + 0x58U) -#define DSI_VVBPCR_VBP_SHIFT 0 -#define DSI_VVBPCR_VBP_MASK 0x3ff - -/** - * DSI Host Video VFP Configuration Register - */ -#define DSI_VVFPCR MMIO32(DSI_BASE + 0x5CU) -#define DSI_VVFPCR_VFP_SHIFT 0 -#define DSI_VVFPCR_VFP_MASK 0x3ff - -/** - * DSI Host Video VA Configuration Register - */ -#define DSI_VVACR MMIO32(DSI_BASE + 0x60U) -#define DSI_VVACR_VA_SHIFT 0 -#define DSI_VVACR_VA_MASK 0x3fff - -/** - * DSI Host LTDC Command Configuration Register - */ -#define DSI_LCCR MMIO32(DSI_BASE + 0x64U) -#define DSI_LCCR_CMDSIZE_SHIFT 0 -#define DSI_LCCR_CMDSIZE_MASK 0xffff - -/** - * DSI Host Command mode Configuration Register - */ -#define DSI_CMCR MMIO32(DSI_BASE + 0x68U) -#define DSI_CMCR_MRDPS (1 << 24) -#define DSI_CMCR_DLWTX (1 << 19) -#define DSI_CMCR_DSR0TX (1 << 18) -#define DSI_CMCR_DSW1TX (1 << 17) -#define DSI_CMCR_DSW0TX (1 << 16) -/* Bit 15 reserved */ -#define DSI_CMCR_GLWTX (1 << 14) -#define DSI_CMCR_GSR2TX (1 << 13) -#define DSI_CMCR_GSR1TX (1 << 12) -#define DSI_CMCR_GSR0TX (1 << 11) -#define DSI_CMCR_GSW2TX (1 << 10) -#define DSI_CMCR_GSW1TX (1 << 9) -#define DSI_CMCR_GSW0TX (1 << 8) -/* Bits 7:2 Reserved */ -#define DSI_CMCR_ARE (1 << 1) -#define DSI_CMCR_TEARE (1 << 0) - -/** - * DSI Host Generic Header Configuration Register - */ -#define DSI_GHCR MMIO32(DSI_BASE + 0x6CU) -#define DSI_GHCR_WCMSB_SHIFT 16 -#define DSI_GHCR_WCMSB_MASK 0xff -#define DSI_GHCR_WCLSB_SHIFT 8 -#define DSI_GHCR_WCLSB_MASK 0xff -#define DSI_GHCR_DATA1_SHIFT 16 /* data 1 in 'short' mode */ -#define DSI_GHCR_DATA1_MASK 0xff -#define DSI_GHCR_DATA0_SHIFT 8 /* data 0 in 'short' mode */ -#define DSI_GHCR_DATA0_MASK 0xff -#define DSI_GHCR_VCID_SHIFT 6 -#define DSI_GHCR_VCID_MASK 0x3 -#define DSI_GHCR_DT_SHIFT 0 -#define DSI_GHCR_DT_MASK 0x3f - -/** - * DSI Host Generic Payload Data Register - */ -#define DSI_GPDR MMIO32(DSI_BASE + 0x70U) -#define DSI_GPDR_BYTE4_SHIFT 24 -#define DSI_GPDR_BYTE4_MASK 0xff -#define DSI_GPDR_BYTE3_SHIFT 16 -#define DSI_GPDR_BYTE3_MASK 0xff -#define DSI_GPDR_BYTE2_SHIFT 8 -#define DSI_GPDR_BYTE2_MASK 0xff -#define DSI_GPDR_BYTE1_SHIFT 0 -#define DSI_GPDR_BYTE1_MASK 0xff - -/** - * DSI Host Generate Packet Status Register - */ -#define DSI_GPSR MMIO32(DSI_BASE + 0x74U) -/* Reserved 31:7 */ -#define DSI_GPSR_RCB (1 << 6) -#define DSI_GPSR_PRDFF (1 << 5) -#define DSI_GPSR_PRDFE (1 << 4) -#define DSI_GPSR_PWRFF (1 << 3) -#define DSI_GPSR_PWRFE (1 << 2) -#define DSI_GPSR_CMDFF (1 << 1) -#define DSI_GPSR_CMDFE (1 << 0) - -/** - * DSI Host Timeout Counter Configuration Register - */ -#define DSI_TCCR0 MMIO32(DSI_BASE + 0x78U) -#define DSI_TCCR0_HSTX_TOCNT_SHIFT 16 -#define DSI_TCCR0_HSTX_TOCNT_MASK 0xffff -#define DSI_TCCR0_LPRX_TOCNT_SHIFT 0 -#define DSI_TCCR0_LPRX_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 1 - */ -#define DSI_TCCR1 MMIO32(DSI_BASE + 0x7CU) -#define DSI_TCCR1_HSRD_TOCNT_SHIFT 0 -#define DSI_TCCR1_HSRD_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 2 - */ -#define DSI_TCCR2 MMIO32(DSI_BASE + 0x80U) -#define DSI_TCCR2_LPRD_TOCNT_SHIFT 0 -#define DSI_TCCR2_LPRD_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 3 - */ -#define DSI_TCCR3 MMIO32(DSI_BASE + 0x84U) -#define DSI_TCCR3_PM (1 << 24) -#define DSI_TCCR3_HSWR_TOCNT_SHIFT 0 -#define DSI_TCCR3_HSWR_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 4 - */ -#define DSI_TCCR4 MMIO32(DSI_BASE + 0x88U) -#define DSI_TCCR4_LPWR_TOCNT_SHIFT 0 -#define DSI_TCCR4_LPWR_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 5 - */ -#define DSI_TCCR5 MMIO32(DSI_BASE + 0x8CU) -#define DSI_TCCR5_BTA_TOCNT_SHIFT 0 -#define DSI_TCCR5_BTA_TOCNT_MASK 0xffff - -/** - * DSI Host Clock Lane Configuration Register - */ -#define DSI_CLCR MMIO32(DSI_BASE + 0x94U) -#define DSI_CLCR_ACR (1 << 1) -#define DSI_CLCR_DPCC (1 << 0) - -/** - * DSI Host Clock Lane Timer Configuration Register - */ -#define DSI_CLTCR MMIO32(DSI_BASE + 0x98U) -#define DSI_CLTCR_HS2LP_TIME_SHIFT 16 -#define DSI_CLTCR_HS2LP_TIME_MASK 0x3ff -#define DSI_CLTCR_LP2HS_TIME_SHIFT 0 -#define DSI_CLTCR_LP2HS_TIME_MASK 0x3ff - -/** - * DSI Host Data Lane Time Configuration Register - */ -#define DSI_DLTCR MMIO32(DSI_BASE + 0x9CU) -#define DSI_DLTCR_HS2LP_TIME_SHIFT 24 -#define DSI_DLTCR_HS2LP_TIME_MASK 0xff -#define DSI_DLTCR_LP2HS_TIME_SHIFT 16 -#define DSI_DLTCR_LP2HS_TIME_MASK 0xff -#define DSI_DLTCR_MRD_TIME_SHIFT 0 -#define DSI_DLTCR_MRD_TIME_MASK 0x7fff - -/** - * DSI Host PHY Control Register - */ -#define DSI_PCTLR MMIO32(DSI_BASE + 0xA0U) -#define DSI_PCTLR_CKE (1 << 2) -#define DSI_PCTLR_DEN (1 << 1) - -/** - * DSI Host PHY Configuration Register - */ -#define DSI_PCONFR MMIO32(DSI_BASE + 0xA4U) -#define DSI_PCONFR_SW_TIME_SHIFT 8 -#define DSI_PCONFR_SW_TIME_MASK 0xff -#define DSI_PCONFR_NL_SHIFT 0 -#define DSI_PCONFR_NL_MASK 0x3 -#define DSI_PCONFR_NL_1LANE 0 -#define DSI_PCONFR_NL_2LANE 1 - -/** - * DSI Host PHY ULPS Control Register - */ -#define DSI_PUCR MMIO32(DSI_BASE + 0xA8U) -#define DSI_PUCR_UEDL (1 << 3) -#define DSI_PUCR_URDL (1 << 2) -#define DSI_PUCR_UECL (1 << 1) -#define DSI_PUCR_URCL (1 << 0) - -/** - * DSI Host PHY TX Triggers Configuration Register - */ -#define DSI_PTTCR MMIO32(DSI_BASE + 0xACU) -#define DSI_PTTCR_TX_TRIG_SHIFT 0 -#define DSI_PTTCR_TX_TRIG_MASK 0xf -#define DSI_PTTCR_TX_TRIG_1 0x1 -#define DSI_PTTCR_TX_TRIG_2 0x2 -#define DSI_PTTCR_TX_TRIG_3 0x4 -#define DSI_PTTCR_TX_TRIG_4 0x8 - -/** - * DSI Host PHY Status Register - */ -#define DSI_PSR MMIO32(DSI_BASE + 0xB0U) -#define DSI_PSR_UAN1 (1 << 8) -#define DSI_PSR_PSS1 (1 << 7) -#define DSI_PSR_RUE0 (1 << 6) -#define DSI_PSR_UAN0 (1 << 5) -#define DSI_PSR_PSS0 (1 << 4) -#define DSI_PSR_UANC (1 << 3) -#define DSI_PSR_PSSC (1 << 2) -#define DSI_PSR_PD (1 << 1) - -/** - * DSI Host Interrupt & Status Register 0 - */ -#define DSI_ISR0 MMIO32(DSI_BASE + 0xBCU) -#define DSI_ISR0_PE4 (1 << 20) -#define DSI_ISR0_PE3 (1 << 19) -#define DSI_ISR0_PE2 (1 << 18) -#define DSI_ISR0_PE1 (1 << 17) -#define DSI_ISR0_PE0 (1 << 16) -#define DSI_ISR0_AE15 (1 << 15) -#define DSI_ISR0_AE14 (1 << 14) -#define DSI_ISR0_AE13 (1 << 13) -#define DSI_ISR0_AE12 (1 << 12) -#define DSI_ISR0_AE11 (1 << 11) -#define DSI_ISR0_AE10 (1 << 10) -#define DSI_ISR0_AE9 (1 << 9) -#define DSI_ISR0_AE8 (1 << 8) -#define DSI_ISR0_AE7 (1 << 7) -#define DSI_ISR0_AE6 (1 << 6) -#define DSI_ISR0_AE5 (1 << 5) -#define DSI_ISR0_AE4 (1 << 4) -#define DSI_ISR0_AE3 (1 << 3) -#define DSI_ISR0_AE2 (1 << 2) -#define DSI_ISR0_AE1 (1 << 1) -#define DSI_ISR0_AE0 (1 << 0) - -/** - * DSI Host Interrupt & Status Register 1 - */ -#define DSI_ISR1 MMIO32(DSI_BASE + 0xC0U) -#define DSI_ISR1_GPRXE (1 << 12) -#define DSI_ISR1_GPRDE (1 << 11) -#define DSI_ISR1_GPTXE (1 << 10) -#define DSI_ISR1_GPWRE (1 << 9) -#define DSI_ISR1_GCWRE (1 << 8) -#define DSI_ISR1_LPWRE (1 << 7) -#define DSI_ISR1_EOTPE (1 << 6) -#define DSI_ISR1_PSE (1 << 5) -#define DSI_ISR1_CRCE (1 << 4) -#define DSI_ISR1_ECCME (1 << 3) -#define DSI_ISR1_ECCSE (1 << 2) -#define DSI_ISR1_TOLPRX (1 << 1) -#define DSI_ISR1_TOHSTX (1 << 0) - -/** - * DSI Host Interrupt Enable Register 0 - */ -#define DSI_IER0 MMIO32(DSI_BASE + 0xC4U) -#define DSI_IER0_PE4IE (1 << 20) -#define DSI_IER0_PE3IE (1 << 19) -#define DSI_IER0_PE2IE (1 << 18) -#define DSI_IER0_PE1IE (1 << 17) -#define DSI_IER0_PE0IE (1 << 16) -#define DSI_IER0_AE15IE (1 << 15) -#define DSI_IER0_AE14IE (1 << 14) -#define DSI_IER0_AE13IE (1 << 13) -#define DSI_IER0_AE12IE (1 << 12) -#define DSI_IER0_AE11IE (1 << 11) -#define DSI_IER0_AE10IE (1 << 10) -#define DSI_IER0_AE9IE (1 << 9) -#define DSI_IER0_AE8IE (1 << 8) -#define DSI_IER0_AE7IE (1 << 7) -#define DSI_IER0_AE6IE (1 << 6) -#define DSI_IER0_AE5IE (1 << 5) -#define DSI_IER0_AE4IE (1 << 4) -#define DSI_IER0_AE3IE (1 << 3) -#define DSI_IER0_AE2IE (1 << 2) -#define DSI_IER0_AE1IE (1 << 1) -#define DSI_IER0_AE0IE (1 << 0) - -/** - * DSI Host Interrupt Enable Register 1 - */ -#define DSI_IER1 MMIO32(DSI_BASE + 0xC8U) -#define DSI_IER1_GPRXEIE (1 << 12) -#define DSI_IER1_GPRDEIE (1 << 11) -#define DSI_IER1_GPTXEIE (1 << 10) -#define DSI_IER1_GPWREIE (1 << 9) -#define DSI_IER1_GCWREIE (1 << 8) -#define DSI_IER1_LPWREIE (1 << 7) -#define DSI_IER1_EOTPEIE (1 << 6) -#define DSI_IER1_PSEIE (1 << 5) -#define DSI_IER1_CRCEIE (1 << 4) -#define DSI_IER1_ECCMEIE (1 << 3) -#define DSI_IER1_ECCSEIE (1 << 2) -#define DSI_IER1_TOLPRXIE (1 << 1) -#define DSI_IER1_TOHSTXIE (1 << 0) - -/** - * DSI Host Force Interrupt Register 0 - */ -#define DSI_FIR0 MMIO32(DSI_BASE + 0xD8U) -#define DSI_FIR0_FPE4 (1 << 20) -#define DSI_FIR0_FPE3 (1 << 19) -#define DSI_FIR0_FPE2 (1 << 18) -#define DSI_FIR0_FPE1 (1 << 17) -#define DSI_FIR0_FPE0 (1 << 16) -#define DSI_FIR0_FAE15 (1 << 15) -#define DSI_FIR0_FAE14 (1 << 14) -#define DSI_FIR0_FAE13 (1 << 13) -#define DSI_FIR0_FAE12 (1 << 12) -#define DSI_FIR0_FAE11 (1 << 11) -#define DSI_FIR0_FAE10 (1 << 10) -#define DSI_FIR0_FAE9 (1 << 9) -#define DSI_FIR0_FAE8 (1 << 8) -#define DSI_FIR0_FAE7 (1 << 7) -#define DSI_FIR0_FAE6 (1 << 6) -#define DSI_FIR0_FAE5 (1 << 5) -#define DSI_FIR0_FAE4 (1 << 4) -#define DSI_FIR0_FAE3 (1 << 3) -#define DSI_FIR0_FAE2 (1 << 2) -#define DSI_FIR0_FAE1 (1 << 1) -#define DSI_FIR0_FAE0 (1 << 0) - -/** - * DSI Host Force Interrupt Register 1 - */ -#define DSI_FIR1 MMIO32(DSI_BASE + 0xDCU) -#define DSI_FIR1_FGPRXE (1 << 12) -#define DSI_FIR1_FGPRDE (1 << 11) -#define DSI_FIR1_FGPTXE (1 << 10) -#define DSI_FIR1_FGPWRE (1 << 9) -#define DSI_FIR1_FGCWRE (1 << 8) -#define DSI_FIR1_FLPWRE (1 << 7) -#define DSI_FIR1_FEOTPE (1 << 6) -#define DSI_FIR1_FPSE (1 << 5) -#define DSI_FIR1_FCRCE (1 << 4) -#define DSI_FIR1_FECCME (1 << 3) -#define DSI_FIR1_FECCSE (1 << 2) -#define DSI_FIR1_FTOLPRX (1 << 1) -#define DSI_FIR1_FTOHSTX (1 << 0) - -/** - * DSI Host Video Shadow Control Register - */ -#define DSI_VSCR MMIO32(DSI_BASE + 0x100U) -#define DSI_VSCR_UR (1 << 8) -#define DSI_VSCR_EN (1 << 0) - -/** - * DSI Host LTDC Current VCID Register - */ -#define DSI_LCVCIDR MMIO32(DSI_BASE + 0x10CU) -#define DSI_LCVCIDR_VCID_SHIFT 0 -#define DSI_LCVCIDR_VCID_MASK 0x3 - -/** - * DSI Host LTCD Current Color Coding Register - */ -#define DSI_LCCCR MMIO32(DSI_BASE + 0x110U) -#define DSI_LCCR_LPE (1 << 8) -#define DSI_LCCR_COLC_SHIFT 0 -#define DSI_LCCR_COLC_MASK 0xf - -/** - * DSI Host Low-power mode Current Configuration Register - */ -#define DSI_LPMCCR MMIO32(DSI_BASE + 0x118U) -#define DSI_LPMCCR_LPSIZE_SHIFT 16 -#define DSI_LPMCCR_LPSIZE_MASK 0xff -#define DSI_LPMCCR_VLPSIZE_SHIFT 0 -#define DSI_LPMCCR_VLPSIZE_MASK 0xff - -/** - * DSI Host Video mode Current Configuration Register - */ -#define DSI_VMCCR MMIO32(DSI_BASE + 0x138U) -#define DSI_VMCCR_LPCE (1 << 9) -#define DSI_VMCCR_FBTAAE (1 << 8) -#define DSI_VMCCR_LPHFE (1 << 7) -#define DSI_VMCCR_LPHBPE (1 << 6) -#define DSI_VMCCR_LPVAE (1 << 5) -#define DSI_VMCCR_LPVFPE (1 << 4) -#define DSI_VMCCR_LPVBPE (1 << 3) -#define DSI_VMCCR_LPVSAE (1 << 2) -#define DSI_VMCCR_VMT_SHIFT 0 -#define DSI_VMCCR_VMT_MASK 0x3 - -/** - * DSI Host Video Packet Current Configuration Register - */ -#define DSI_VPCCR MMIO32(DSI_BASE + 0x13CU) -#define DSI_VPCCR_VPSIZE_SHIFT 0 -#define DSI_VPCCR_VPSIZE_MASK 0x3fff - -/** - * DSI Host Video Chunks Current Configuration Register - */ -#define DSI_VCCCR MMIO32(DSI_BASE + 0x140U) -#define DSI_VCCCR_NUMC_SHIFT 0 -#define DSI_VCCCR_NUMC_MASK 0x1fff - -/** - * DSI Host Video Null Packet Current Configuration Register - */ -#define DSI_VNPCCR MMIO32(DSI_BASE + 0x144U) -#define DSI_VNPCCR_NPSIZE_SHIFT 0 -#define DSI_VNPCCR_NPSIZE_MASK 0x1fff - -/** - * DSI Host Video HSA Current Configuration Register - */ -#define DSI_VHSACCR MMIO32(DSI_BASE + 0x148U) -#define DSI_VHSACCR_HSA_SHIFT 0 -#define DSI_VHSACCR_HSA_MASK 0xfff - -/** - * DSI Host Video HBP Current Configuration Register - */ -#define DSI_VHBPCCR MMIO32(DSI_BASE + 0x14CU) -#define DSI_VHBPCCR_HBP_SHIFT 0 -#define DSI_VHBPCCR_HBP_MASK 0xfff - -/** - * DSI Host Video Line Current Configuration Register - */ -#define DSI_VLCCR MMIO32(DSI_BASE + 0x150U) -#define DSI_VLCCR_HLINE_SHIFT 0 -#define DSI_VLCCR_HLINE_MASK 0x7fff - -/** - * DSI Host Video VSA Current Configuration Register - */ -#define DSI_VVSACCR MMIO32(DSI_BASE + 0x154U) -#define DSI_VVSACCR_VSA_SHIFT 0 -#define DSI_VVSACCR_VSA_MASK 0x3ff - -/** - * DSI Host Video VBP Current Configuration Register - */ -#define DSI_VVBPCCR MMIO32(DSI_BASE + 0x0158U) -#define DSI_VVBPCCR_VBP_SHIFT 0 -#define DSI_VVBPCCR_VBP_MAST 0x3ff - -/** - * DSI Host Video VFP Current Configuration Register - */ -#define DSI_VVFPCCR MMIO32(DSI_BASE + 0x15CU) -#define DSI_VVFPCCR_VFP_SHIFT 0 -#define DSI_VVFPCCR_VFP_MASK 0x3ff - -/** - * DSI Host Video VA Current Configuration Register - */ -#define DSI_VVACCR MMIO32(DSI_BASE + 0x160U) -#define DSI_VVACCR_VA_SHIFT 0 -#define DSI_VVACCR_VA_MASK 0x3fff - -/** - * DSI Wrapper Configuration Register - */ -#define DSI_WCFGR MMIO32(DSI_BASE + 0x400U) -#define DSI_WCFGR_VSPOL (1 << 7) -#define DSI_WCFGR_AR (1 << 6) -#define DSI_WCFGR_TEPOL (1 << 5) -#define DSI_WCFGR_TESRC (1 << 4) -#define DSI_WCFGR_COLMUX_SHIFT 1 -#define DSI_WCFGR_COLMUX_MASK 7 -#define DSI_WCFGR_DSIM (1 << 0) - -/** - * DSI Wrapper Control Register - */ -#define DSI_WCR MMIO32(DSI_BASE + 0x404U) -#define DSI_WCR_DSIEN (1 << 3) -#define DSI_WCR_LTDCEN (1 << 2) -#define DSI_WCR_SHTDN (1 << 1) -#define DSI_WCR_COLM (1 << 0) - -/** - * DSI Wrapper Interrupt Enable Register - */ -#define DSI_WIER MMIO32(DSI_BASE + 0x408U) -#define DSI_WIER_RRIE (1 << 13) -#define DSI_WIER_PLLUIE (1 << 10) -#define DSI_WIER_PLLLIE (1 << 9) -#define DSI_WIER_ERIE (1 << 1) -#define DSI_WIER_TEIE (1 << 0) - -/** - * DSI Wrapper Interrupt & Status Register - */ -#define DSI_WISR MMIO32(DSI_BASE + 0x40CU) -/* reserved 31:14 */ -#define DSI_WISR_RRIF (1 << 13) -#define DSI_WISR_RRS (1 << 12) -#define DSI_WISR_PLLUIF (1 << 10) -#define DSI_WISR_PLLLIF (1 << 9) -#define DSI_WISR_PLLLS (1 << 8) -/* reserved 7:3 */ -#define DSI_WISR_BUSY (1 << 2) -#define DSI_WISR_ERIF (1 << 1) -#define DSI_WISR_TEIF (1 << 0) - -/** - * DSI Wrapper Interrupt Flag Clear Register - */ -#define DSI_WIFCR MMIO32(DSI_BASE + 0x410U) -/* reserved 31:14 */ -#define DSI_WIFCR_CRRIF (1 << 13) -/* reserved 12:11 */ -#define DSI_WIFCR_CPLLUIF (1 << 10) -#define DSI_WIFCR_CPLLLIF (1 << 9) -/* reserved 8:2 */ -#define DSI_WIFCR_CERIF (1 << 1) -#define DSI_WIFCR_CTEIF (1 << 0) - -/** - * DSI Wrapper PHY Configuration Register 0 - */ -#define DSI_WPCR0 MMIO32(DSI_BASE + 0x418U) -#define DSI_WPCR0_TCLKPOSTEN (1 << 27) -#define DSI_WPCR0_TLPXCEN (1 << 26) -#define DSI_WPCR0_THSEXITEN (1 << 25) -#define DSI_WPCR0_TLPXDEN (1 << 24) -#define DSI_WPCR0_THSZEROEN (1 << 23) -#define DSI_WPCR0_THSTRAILEN (1 << 22) -#define DSI_WPCR0_THSPREPEN (1 << 21) -#define DSI_WPCR0_TCLKZEROEN (1 << 20) -#define DSI_WPCR0_TCLKPREPEN (1 << 19) -#define DSI_WPCR0_PDEN (1 << 18) -#define DSI_WPCR0_TDDL (1 << 16) -#define DSI_WPCR0_CDOFFDL (1 << 14) -#define DSI_WPCR0_FTXSMDL (1 << 13) -#define DSI_WPCR0_FTXSMCL (1 << 12) -#define DSI_WPCR0_HSIDL1 (1 << 11) -#define DSI_WPCR0_HSIDL0 (1 << 10) -#define DSI_WPCR0_HSICL (1 << 9) -#define DSI_WPCR0_SWDL1 (1 << 8) -#define DSI_WPCR0_SWDL0 (1 << 7) -#define DSI_WPCR0_SWCL (1 << 6) -#define DSI_WPCR0_UIX4_SHIFT 0 -#define DSI_WPCR0_UIX4_MASK 0x3f - -/** - * DSI Wrapper PHY Configration Register 1 - */ -#define DSI_WPCR1 MMIO32(DSI_BASE + 0x41CU) -#define DSI_WPCR1_LPRXFT_SHIFT 25 -#define DSI_WPCR1_LPRXFT_MASK 0x3 -#define DSI_WPCR1_FLPRXLPM (1 << 22) -#define DSI_WPCR1_HSTXSRCDL_SHIFT 18 -#define DSI_WPCR1_HSTXSRCDL_MASK 0x3 -#define DSI_WPCR1_HSTXSRCCL_SHIFT 16 -#define DSI_WPCR1_HSTXSRCCL_MASK 0x3 -#define DSI_WPCR1_SDDC (1 << 12) -#define DSI_WPCR1_LPSRCDL_SHIFT 8 -#define DSI_WPCR1_LPSRCDL_MASK 0x3 -#define DSI_WPCR1_HSTXDDL_SHIFT 2 -#define DSI_WPCR1_HSTXDDL_MASK 0x3 -#define DSI_WPCR1_HSTXDCL_SHIFT 0 -#define DSI_WPCR1_HSTXDCL_MASK 0x3 - -/** - * DSI Wrapper PHY Configuration Register 2 - */ -#define DSI_WPCR2 MMIO32(DSI_BASE + 0x420U) -#define DSI_WPCR2_THSTRAIL_SHIFT 24 -#define DSI_WPCR2_THSTRAIL_MASK 0xff -#define DSI_WPCR2_THSPREP_SHIFT 16 -#define DSI_WPCR2_THSPREP_MASK 0xff -#define DSI_WPCR2_TCLKZERO_SHIFT 8 -#define DSI_WPCR2_TCLKZERO_MASK 0xff -#define DSI_WPCR2_TCLKPREP_SHIFT 0 -#define DSI_WPCR2_TCLKPREP_MASK 0xff - -/** - * DSI Wrapper PHY Configuration Register 3 - */ -#define DSI_WPCR3 MMIO32(DSI_BASE + 0x424U) -#define DSI_WPCR3_TLPXC_SHIFT 24 -#define DSI_WPCR3_TLPXC_MASK 0xff -#define DSI_WPCR3_THSEXIT_SHIFT 16 -#define DSI_WPCR3_THSEXIT_MASK 0xff -#define DSI_WPCR3_TLPXD_SHIFT 8 -#define DSI_WPCR3_TLPXD_MASK 0xff -#define DSI_WPCR3_THSZERO_SHIFT 0 -#define DSI_WPCR3_THSZERO_MASK 0xff - -/** - * DSI Wrapper PHY Configuration Register 4 - */ -#define DSI_WPCR4 MMIO32(DSI_BASE + 0x428U) -#define DSI_WPCR4_TCLKPOST_SHIFT 0 -#define DSI_WPCR4_TCLKPOST_MASK 0xff - -/** - * DSI Wrapper Regulator and PLL Control Register - */ -#define DSI_WRPCR MMIO32(DSI_BASE + 0x430U) -#define DSI_WRPCR_REGEN (1 << 24) -#define DSI_WRPCR_ODF_SHIFT 16 -#define DSI_WRPCR_ODF_MASK 0x3 -#define DSI_WRPCR_ODF_DIV_1 0 -#define DSI_WRPCR_ODF_DIV_2 1 -#define DSI_WRPCR_ODF_DIV_4 2 -#define DSI_WRPCR_ODF_DIV_8 3 -#define DSI_WRPCR_IDF_SHIFT 11 -#define DSI_WRPCR_IDF_MASK 0xf -#define DSI_WRPCR_IDF_DIV_1 1 -#define DSI_WRPCR_IDF_DIV_2 2 -#define DSI_WRPCR_IDF_DIV_3 3 -#define DSI_WRPCR_IDF_DIV_4 4 -#define DSI_WRPCR_IDF_DIV_5 5 -#define DSI_WRPCR_IDF_DIV_6 6 -#define DSI_WRPCR_IDF_DIV_7 7 -/* valid NDIV values 10 - 125 all other reserved */ -#define DSI_WRPCR_NDIV_SHIFT 2 -#define DSI_WRPCR_NDIV_MASK 0x7f -#define DSI_WRPCR_PLLEN (1 << 0) - -/** @cond */ -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_all.h b/libopencm3/include/libopencm3/stm32/common/exti_common_all.h deleted file mode 100644 index 6175361..0000000 --- a/libopencm3/include/libopencm3/stm32/common/exti_common_all.h +++ /dev/null @@ -1,97 +0,0 @@ -/** @addtogroup exti_defines - * - * @author @htmlonly © @endhtmlonly 2010 - * Mark Butler - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @cond */ -#if defined(LIBOPENCM3_EXTI_H) -/** @endcond */ -#ifndef LIBOPENCM3_EXTI_COMMON_ALL_H -#define LIBOPENCM3_EXTI_COMMON_ALL_H -/**@{*/ - -/* EXTI number definitions */ -#define EXTI0 (1 << 0) -#define EXTI1 (1 << 1) -#define EXTI2 (1 << 2) -#define EXTI3 (1 << 3) -#define EXTI4 (1 << 4) -#define EXTI5 (1 << 5) -#define EXTI6 (1 << 6) -#define EXTI7 (1 << 7) -#define EXTI8 (1 << 8) -#define EXTI9 (1 << 9) -#define EXTI10 (1 << 10) -#define EXTI11 (1 << 11) -#define EXTI12 (1 << 12) -#define EXTI13 (1 << 13) -#define EXTI14 (1 << 14) -#define EXTI15 (1 << 15) -#define EXTI16 (1 << 16) -#define EXTI17 (1 << 17) -#define EXTI18 (1 << 18) -#define EXTI19 (1 << 19) -#define EXTI20 (1 << 20) -#define EXTI21 (1 << 21) -#define EXTI22 (1 << 22) -#define EXTI23 (1 << 23) -#define EXTI24 (1 << 24) -#define EXTI25 (1 << 25) -#define EXTI26 (1 << 26) -#define EXTI27 (1 << 27) -#define EXTI28 (1 << 28) -#define EXTI29 (1 << 29) -#define EXTI30 (1 << 30) -#define EXTI31 (1 << 31) - -#define EXTI32 (1 << 0) -#define EXTI33 (1 << 1) -#define EXTI34 (1 << 2) -#define EXTI35 (1 << 3) -#define EXTI36 (1 << 4) -#define EXTI37 (1 << 5) - -/* Trigger types */ -enum exti_trigger_type { - EXTI_TRIGGER_RISING, - EXTI_TRIGGER_FALLING, - EXTI_TRIGGER_BOTH, -}; - -BEGIN_DECLS - -void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig); -void exti_enable_request(uint32_t extis); -void exti_disable_request(uint32_t extis); -void exti_reset_request(uint32_t extis); -void exti_select_source(uint32_t exti, uint32_t gpioport); -uint32_t exti_get_flag_status(uint32_t exti); - -END_DECLS -/**@}*/ - -#endif -/** @cond */ -#else -#warning "exti_common_all.h should not be included directly, only via exti.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_v1.h b/libopencm3/include/libopencm3/stm32/common/exti_common_v1.h deleted file mode 100644 index 9b091ed..0000000 --- a/libopencm3/include/libopencm3/stm32/common/exti_common_v1.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @addtogroup exti_defines */ -#pragma once - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @cond */ -#if defined(LIBOPENCM3_EXTI_H) -/** @endcond */ - -/**@{*/ - -/* --- EXTI registers ------------------------------------------------------ */ - -/** @defgroup exti_registers EXTI Registers -@{*/ -/** EXTI Interrupt Mask Registers */ -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -/** EXTI Event Mask Register */ -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -/** EXTI Rising Trigger Selection Register */ -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -/** EXTI Falling Triger Selection Register */ -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -/** EXTI Software Interrupt Event Register */ -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -/** EXTI Pending Register */ -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -/** @cond */ -#else -#warning "exti_common_v1.h should not be included directly, only via exti.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_v2.h b/libopencm3/include/libopencm3/stm32/common/exti_common_v2.h deleted file mode 100644 index d6ddb24..0000000 --- a/libopencm3/include/libopencm3/stm32/common/exti_common_v2.h +++ /dev/null @@ -1,91 +0,0 @@ -/** @addtogroup exti_defines - * - * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/** @cond */ -#if defined(LIBOPENCM3_EXTI_H) -/** @endcond */ -#ifndef LIBOPENCM3_EXTI_COMMON_V2_H -#define LIBOPENCM3_EXTI_COMMON_V2_H - -/* --- EXTI registers ------------------------------------------------------ */ - -/** @defgroup exti_registers EXTI Registers -@{*/ -/** EXTI Rising Trigger Selection Register 1 */ -#define EXTI_RTSR1 MMIO32(EXTI_BASE + 0x00) -#define EXTI_RTSR EXTI_RTSR1 - -/** EXTI Falling Trigger Selection Register 1 */ -#define EXTI_FTSR1 MMIO32(EXTI_BASE + 0x04) -#define EXTI_FTSR EXTI_FTSR1 - -/** EXTI Software Interrupt Event Register */ -#define EXTI_SWIER1 MMIO32(EXTI_BASE + 0x08) - -/** EXTI Interrupt Mask Registers 1 */ -#define EXTI_IMR1 MMIO32(EXTI_BASE + 0x80) -#define EXTI_IMR EXTI_IMR1 - -/** EXTI Event Mask Registers 1 */ -#define EXTI_EMR1 MMIO32(EXTI_BASE + 0x84) -#define EXTI_EMR EXTI_EMR1 - -/** EXTI Interrupt Mask Registers 2 */ -#define EXTI_IMR2 MMIO32(EXTI_BASE + 0x90) -/** EXTI Event Mask Registers 2 */ -#define EXTI_EMR2 MMIO32(EXTI_BASE + 0x94) -/**@}*/ - -/* --- EXTI_EXTICR Values -------------------------------------------------*/ - -#define EXTI_EXTICR_FIELDSIZE 8 -#define EXTI_EXTICR_GPIOA 0 -#define EXTI_EXTICR_GPIOB 1 -#define EXTI_EXTICR_GPIOC 2 -#define EXTI_EXTICR_GPIOD 3 -#define EXTI_EXTICR_GPIOE 4 -#define EXTI_EXTICR_GPIOF 5 -#define EXTI_EXTICR_GPIOG 6 -#define EXTI_EXTICR_GPIOH 7 - -BEGIN_DECLS - -uint32_t exti_get_rising_flag_status(uint32_t exti); -uint32_t exti_get_falling_flag_status(uint32_t exti); - -void exti_reset_rising_request(uint32_t extis); -void exti_reset_falling_request(uint32_t extis); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "exti_common_v2.h should not be included directly, only via exti.h" -#endif -/** @endcond */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_all.h b/libopencm3/include/libopencm3/stm32/common/flash_common_all.h deleted file mode 100644 index ad7b556..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_all.h +++ /dev/null @@ -1,74 +0,0 @@ -/** @addtogroup flash_defines - * - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -BEGIN_DECLS - -/** - * This buffer is used for instruction fetches and is enabled by default after - * reset. - * - * Note carefully the clock restrictions under which the prefetch buffer may be - * enabled or disabled. Changes are normally made while the clock is running in - * the power-on low frequency mode before being set to a higher speed mode. - * - * See the reference manual for details. - */ -void flash_prefetch_enable(void); - -/** - * Note carefully the clock restrictions under which the prefetch buffer may be - * set to disabled. See the reference manual for details. - */ -void flash_prefetch_disable(void); - - -/** Set the Number of Wait States. - -Used to match the system clock to the FLASH memory access time. See the -programming manual for more information on clock speed ranges. The latency must -be changed to the appropriate value before any increase in clock -speed, or after any decrease in clock speed. - -@param[in] ws values from @ref flash_latency. -*/ -void flash_set_ws(uint32_t ws); - -/** Lock the Flash Program and Erase Controller - * Used to prevent spurious writes to FLASH. - */ -void flash_lock(void); - -/** Unlock the Flash Program and Erase Controller - * This enables write access to the Flash memory. It is locked by default on - * reset. - */ -void flash_unlock(void); - -/** Unlock the Option Byte Access. - * This enables write access to the option bytes. It is locked by default on - * reset. - */ -void flash_unlock_option_bytes(void); - -END_DECLS \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f.h deleted file mode 100644 index fc400a7..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_f.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @addtogroup flash_defines - * - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -BEGIN_DECLS - -/** - * Clear the End of OPeration flag. - */ -void flash_clear_eop_flag(void); - -/** - * Clear all status flags. - * The number of bits can vary across families. - */ -void flash_clear_status_flags(void); - -/** Wait until Last Operation has Ended. - * This loops indefinitely until an operation (write or erase) has completed by - * testing the busy flag - */ -void flash_wait_for_last_operation(void); - -END_DECLS \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h deleted file mode 100644 index f310fee..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h +++ /dev/null @@ -1,125 +0,0 @@ -/** @addtogroup flash_defines - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * For details see: - * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming - * September 2011, Doc ID 018520 Rev 1 - * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf - */ - -/** @cond */ -#ifdef LIBOPENCM3_FLASH_H -/** @endcond */ -#ifndef LIBOPENCM3_FLASH_COMMON_F01_H -#define LIBOPENCM3_FLASH_COMMON_F01_H -/**@{*/ - -/* --- FLASH registers ----------------------------------------------------- */ - -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) -#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -/* Only present in STM32F10x XL series */ -#define FLASH_KEYR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) -#define FLASH_SR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) -#define FLASH_CR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) -#define FLASH_AR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x54) - -/* --- FLASH_OPTION bytes ------------------------------------------------- */ - -#define FLASH_OPTION_BYTE(i) MMIO16(INFO_BASE+0x0800 + (i)*2) - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 7 - -#define FLASH_ACR_PRFTBS (1 << 5) -#define FLASH_ACR_PRFTBE (1 << 4) -/** Compatibility define */ -#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTBE - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_EOP (1 << 5) -#define FLASH_SR_WRPRTERR (1 << 4) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_EOPIE (1 << 12) -#define FLASH_CR_ERRIE (1 << 10) -#define FLASH_CR_OPTWRE (1 << 9) -#define FLASH_CR_LOCK (1 << 7) -#define FLASH_CR_STRT (1 << 6) -#define FLASH_CR_OPTER (1 << 5) -#define FLASH_CR_OPTPG (1 << 4) -#define FLASH_CR_MER (1 << 2) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_PG (1 << 0) - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -#define FLASH_OBR_RDPRT_SHIFT 1 -#define FLASH_OBR_OPTERR (1 << 0) - -/* --- FLASH Keys -----------------------------------------------------------*/ - -#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) - -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_clear_pgerr_flag(void); -void flash_clear_wrprterr_flag(void); -uint32_t flash_get_status_flags(void); -void flash_program_word(uint32_t address, uint32_t data); -void flash_program_half_word(uint32_t address, uint16_t data); -void flash_erase_page(uint32_t page_address); -void flash_erase_all_pages(void); -void flash_erase_option_bytes(void); -void flash_program_option_bytes(uint32_t address, uint16_t data); - -END_DECLS -/**@}*/ - -#endif -/** @cond */ -#else -#warning "flash_common_f01.h should not be included directly," -#warning "only via flash.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h deleted file mode 100644 index 27b1ee1..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h +++ /dev/null @@ -1,170 +0,0 @@ -/** @addtogroup flash_defines - * - * @author @htmlonly © @endhtmlonly 2010 - * Thomas Otto - * @author @htmlonly © @endhtmlonly 2010 - * Mark Butler - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * For details see: - * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming - * September 2011, Doc ID 018520 Rev 1 - * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf - */ - -/** @cond */ -#ifdef LIBOPENCM3_FLASH_H -/** @endcond */ -#ifndef LIBOPENCM3_FLASH_COMMON_F24_H -#define LIBOPENCM3_FLASH_COMMON_F24_H -/**@{*/ - -#include - -/** @defgroup flash_registers Flash Registers - * @ingroup flash_defines -@{*/ -/** Flash Access Control register */ -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -/** Flash Key register */ -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -/** Flash Option bytes key register */ -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -/** Flash Status register*/ -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -/** Flash Control register */ -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -/** Flash Option Control register */ -#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -/** Flash Option Control register 1 (bank 2) */ -#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) -/*@}*/ - -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK) -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -#define FLASH_ACR_LATENCY_2WS 0x02 -#define FLASH_ACR_LATENCY_3WS 0x03 -#define FLASH_ACR_LATENCY_4WS 0x04 -#define FLASH_ACR_LATENCY_5WS 0x05 -#define FLASH_ACR_LATENCY_6WS 0x06 -#define FLASH_ACR_LATENCY_7WS 0x07 -/*@}*/ -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 0x0f - -/** @defgroup flash_acr_values FLASH_ACR values - * @ingroup flash_registers - * @brief Access Control register values - * @{*/ -#define FLASH_ACR_PRFTEN (1 << 8) -/**@}*/ - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_BSY (1 << 16) -#define FLASH_SR_PGPERR (1 << 6) -#define FLASH_SR_PGAERR (1 << 5) -#define FLASH_SR_WRPERR (1 << 4) -#define FLASH_SR_OPERR (1 << 1) -#define FLASH_SR_EOP (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_LOCK (1 << 31) -#define FLASH_CR_ERRIE (1 << 25) -#define FLASH_CR_EOPIE (1 << 24) -#define FLASH_CR_STRT (1 << 16) -#define FLASH_CR_MER (1 << 2) -#define FLASH_CR_SER (1 << 1) -#define FLASH_CR_PG (1 << 0) -#define FLASH_CR_SNB_SHIFT 3 -#define FLASH_CR_SNB_MASK 0x1f -#define FLASH_CR_PROGRAM_MASK 0x3 -#define FLASH_CR_PROGRAM_SHIFT 8 -/** @defgroup flash_cr_program_width Flash programming width -@ingroup flash_group - -@{*/ -#define FLASH_CR_PROGRAM_X8 0 -#define FLASH_CR_PROGRAM_X16 1 -#define FLASH_CR_PROGRAM_X32 2 -#define FLASH_CR_PROGRAM_X64 3 -/**@}*/ - -/* --- FLASH_OPTCR values -------------------------------------------------- */ - -/* FLASH_OPTCR[27:16]: nWRP */ -/* FLASH_OBR[15:8]: RDP */ -#define FLASH_OPTCR_NRST_STDBY (1 << 7) -#define FLASH_OPTCR_NRST_STOP (1 << 6) -#define FLASH_OPTCR_OPTSTRT (1 << 1) -#define FLASH_OPTCR_OPTLOCK (1 << 0) -#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2) -#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2) -#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2) -#define FLASH_OPTCR_BOR_OFF (0x03 << 2) - -/* --- FLASH_OPTCR1 values ------------------------------------------------- */ -/* Only on some devices */ -/* FLASH_OPTCR1[27:16]: nWRP bank 2 */ - -/* --- FLASH Keys -----------------------------------------------------------*/ - -#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) - -#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) -#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_lock_option_bytes(void); -void flash_clear_pgperr_flag(void); -void flash_clear_wrperr_flag(void); -void flash_clear_pgaerr_flag(void); -void flash_erase_all_sectors(uint32_t program_size); -void flash_erase_sector(uint8_t sector, uint32_t program_size); -void flash_program_double_word(uint32_t address, uint64_t data); -void flash_program_word(uint32_t address, uint32_t data); -void flash_program_half_word(uint32_t address, uint16_t data); -void flash_program_byte(uint32_t address, uint8_t data); -void flash_program(uint32_t address, const uint8_t *data, uint32_t len); -void flash_program_option_bytes(uint32_t data); - -END_DECLS -/**@}*/ - -#endif -/** @cond */ -#else -#warning "flash_common_f24.h should not be included direcitly," -#warning "only via flash.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_idcache.h b/libopencm3/include/libopencm3/stm32/common/flash_common_idcache.h deleted file mode 100644 index ab83498..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_idcache.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @addtogroup flash_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#include - -/**@{*/ - -/** @addtogroup flash_acr_values - * @{ - */ -#define FLASH_ACR_DCRST (1 << 12) -#define FLASH_ACR_ICRST (1 << 11) -#define FLASH_ACR_DCEN (1 << 10) -#define FLASH_ACR_ICEN (1 << 9) -/**@}*/ - - -BEGIN_DECLS - -/** Enable the data cache */ -void flash_dcache_enable(void); - -/** Disable the data cache */ -void flash_dcache_disable(void); - -/** Enable the Instruction Cache */ -void flash_icache_enable(void); - -/** Disable the Instruction Cache */ -void flash_icache_disable(void); - -/** Reset the Data Cache. - * The data cache must be disabled for this to have effect. - */ -void flash_dcache_reset(void); - -/** Reset the Instruction Cache. - * The instruction cache must be disabled for this to have effect. - */ -void flash_icache_reset(void); - -END_DECLS -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_l01.h b/libopencm3/include/libopencm3/stm32/common/flash_common_l01.h deleted file mode 100644 index 442c000..0000000 --- a/libopencm3/include/libopencm3/stm32/common/flash_common_l01.h +++ /dev/null @@ -1,136 +0,0 @@ -/** @addtogroup flash_defines - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @cond */ -#ifdef LIBOPENCM3_FLASH_H -/** @endcond */ -#ifndef LIBOPENCM3_FLASH_COMMON_L01_H -#define LIBOPENCM3_FLASH_COMMON_L01_H -/**@{*/ - -#include - -/* --- FLASH registers ----------------------------------------------------- */ - -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) -#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) - -/* --- FLASH_ACR values ---------------------------------------------------- */ -#define FLASH_ACR_RUNPD (1 << 4) -#define FLASH_ACR_SLEEPPD (1 << 3) -#define FLASH_ACR_PRFTEN (1 << 1) -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 1 -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -/**@}*/ - -/* --- FLASH_PECR values. Program/erase control register */ -#define FLASH_PECR_OBL_LAUNCH (1 << 18) -#define FLASH_PECR_ERRIE (1 << 17) -#define FLASH_PECR_EOPIE (1 << 16) -#define FLASH_PECR_PARALLBANK (1 << 15) -#define FLASH_PECR_FPRG (1 << 10) -#define FLASH_PECR_ERASE (1 << 9) -#define FLASH_PECR_FTDW (1 << 8) -#define FLASH_PECR_DATA (1 << 4) -#define FLASH_PECR_PROG (1 << 3) -#define FLASH_PECR_OPTLOCK (1 << 2) -#define FLASH_PECR_PRGLOCK (1 << 1) -#define FLASH_PECR_PELOCK (1 << 0) - -/* Power down key register (FLASH_PDKEYR) */ -#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) -#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD) - -/* Program/erase key register (FLASH_PEKEYR) */ -#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF) -#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405) - -/* Program memory key register (FLASH_PRGKEYR) */ -#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF) -#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516) - -/* Option byte key register (FLASH_OPTKEYR) */ -#define FLASH_OPTKEYR_KEY1 ((uint32_t)0xFBEAD9C8) -#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x24252627) - -/* --- FLASH_SR values ----------------------------------------------------- */ -#define FLASH_SR_OPTVERR (1 << 11) -#define FLASH_SR_SIZEERR (1 << 10) -#define FLASH_SR_PGAERR (1 << 9) -#define FLASH_SR_WRPERR (1 << 8) -#define FLASH_SR_READY (1 << 3) -#define FLASH_SR_ENDHV (1 << 2) -#define FLASH_SR_EOP (1 << 1) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_OBR values ----------------------------------------------------- */ -#define FLASH_OBR_BFB2 (1 << 23) -#define FLASH_OBR_NRST_STDBY (1 << 22) -#define FLASH_OBR_NRST_STOP (1 << 21) -#define FLASH_OBR_IWDG_SW (1 << 20) -#define FLASH_OBR_BOR_OFF (0x0 << 16) -#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16) -#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16) -#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16) -#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16) -#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16) -#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa) -#define FLASH_OBR_RDPRT_LEVEL_1 (0x00) -#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc) - -BEGIN_DECLS - -void flash_unlock_pecr(void); -void flash_lock_pecr(void); -void flash_unlock_progmem(void); -void flash_lock_progmem(void); -void flash_lock_option_bytes(void); -void flash_unlock_acr(void); - -void eeprom_program_word(uint32_t address, uint32_t data); -void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); - -END_DECLS -/**@}*/ - -#endif -/** @cond */ -#else -#error "flash_common_l01.h should not be included directly, only via flash.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/fmc_common_f47.h b/libopencm3/include/libopencm3/stm32/common/fmc_common_f47.h deleted file mode 100644 index 91fe410..0000000 --- a/libopencm3/include/libopencm3/stm32/common/fmc_common_f47.h +++ /dev/null @@ -1,269 +0,0 @@ -/** @addtogroup fmc_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Chuck McManis - * - * @date 2013 - * - * This library supports the Flexible Memory Controller (FMC) in the STM32F4xx - * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Chuck McManis - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_FMC_COMMON_F47_H -#define LIBOPENCM3_FMC_COMMON_F47_H - -#ifndef LIBOPENCM3_FSMC_H -#error "This file should not be included directly, it is included with fsmc.h" -#endif - -/* --- Convenience macros -------------------------------------------------- */ -#define FMC_BANK5_BASE 0xa0000000U -#define FMC_BANK6_BASE 0xb0000000U -#define FMC_BANK7_BASE 0xc0000000U -#define FMC_BANK8_BASE 0xd0000000U - -/* --- FMC registers ------------------------------------------------------ */ - -/* SDRAM Control Registers 1 .. 2 */ -#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) -#define FMC_SDCR1 FMC_SDCR(0) -#define FMC_SDCR2 FMC_SDCR(1) - - -/* SDRAM Timing Registers 1 .. 2 */ -#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) -#define FMC_SDTR1 FMC_SDTR(0) -#define FMC_SDTR2 FMC_SDTR(1) - -/* SDRAM Command Mode Register */ -#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) - -/* SDRAM Refresh Timer Register */ -#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) - -/* SDRAM Status Register */ -#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) - -/* --- FMC_SDCRx values ---------------------------------------------------- */ - -/* Bits [31:15]: Reserved. */ - -/* RPIPE: Read Pipe */ -#define FMC_SDCR_RPIPE_SHIFT 13 -#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT) - -/* RBURST: Burst Read */ -#define FMC_SDCR_RBURST (1 << 12) - -/* SDCLK: SDRAM Clock Configuration */ -#define FMC_SDCR_SDCLK_SHIFT 10 -#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT) - -/* WP: Write Protect */ -#define FMC_SDCR_WP_ENABLE (1 << 9) - -/* CAS: CAS Latency */ -#define FMC_SDCR_CAS_SHIFT 7 -#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT) -#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT) -#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT) - -/* NB: Number of Internal banks */ -#define FMC_SDCR_NB2 0 -#define FMC_SDCR_NB4 (1 << 6) - -/* MWID: Memory width */ -#define FMC_SDCR_MWID_SHIFT 4 -#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT) -#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT) -#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT) - -/* NR: Number of rows */ -#define FMC_SDCR_NR_SHIFT 2 -#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT) -#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT) -#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT) - -/* NC: Number of Columns */ -#define FMC_SDCR_NC_SHIFT 0 -#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT) - -/* --- FMC_SDTRx values --------------------------------------------------- */ - -/* Bits [31:28]: Reserved. */ - -/* TRCD: Row to Column Delay */ -#define FMC_SDTR_TRCD_SHIFT 24 -#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT) - -/* TRP: Row Precharge Delay */ -#define FMC_SDTR_TRP_SHIFT 20 -#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT) - -/* TWR: Recovery Delay */ -#define FMC_SDTR_TWR_SHIFT 16 -#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT) - -/* TRC: Row Cycle Delay */ -#define FMC_SDTR_TRC_SHIFT 12 -#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT) - -/* TRAS: Self Refresh Time */ -#define FMC_SDTR_TRAS_SHIFT 8 -#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT) - -/* TXSR: Exit Self-refresh Delay */ -#define FMC_SDTR_TXSR_SHIFT 4 -#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT) - -/* TRMD: Load Mode Register to Active */ -#define FMC_SDTR_TMRD_SHIFT 0 -#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT) - -/* - * Some config bits only count in CR1 or TR1, even if you - * are just configuring bank 2, so these masks let you copy - * out those bits after you have computed values for CR2 and - * TR2 and put them into CR1 and TR1 - */ -#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK) -#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \ - FMC_SDCR_RPIPE_MASK | \ - FMC_SDCR_RBURST) - -/* --- FMC_SDCMR values --------------------------------------------------- */ - -/* Bits [31:22]: Reserved. */ - -/* MRD: Mode Register Definition */ -#define FMC_SDCMR_MRD_SHIFT 9 -#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT) - -/* NRFS: Number of Auto-refresh */ -#define FMC_SDCMR_NRFS_SHIFT 5 -#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT) - -/* CTB1: Command Target Bank 1 */ -#define FMC_SDCMR_CTB1 (1 << 4) - -/* CTB2: Command Target Bank 2 */ -#define FMC_SDCMR_CTB2 (1 << 3) - -/* MODE: Command Mode */ -#define FMC_SDCMR_MODE_SHIFT 0 -#define FMC_SDCMR_MODE_MASK 7 -#define FMC_SDCMR_MODE_NORMAL 0 -#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 -#define FMC_SDCMR_MODE_PALL 2 -#define FMC_SDCMR_MODE_AUTO_REFRESH 3 -#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 -#define FMC_SDCMR_MODE_SELF_REFRESH 5 -#define FMC_SDCMR_MODE_POWER_DOWN 6 - -/* --- FMC_SDRTR values ---------------------------------------------------- */ - -/* Bits [31:15]: Reserved. */ - -/* REIE: Refresh Error Interrupt Enable */ -#define FMC_SDRTR_REIE (1 << 14) - -/* COUNT: Refresh Timer Count */ -#define FMC_SDRTR_COUNT_SHIFT 1 -#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT) - -/* CRE: Clear Refresh Error Flag */ -#define FMC_SDRTR_CRE (1 << 0) - -/* --- FMC_SDSR values ---------------------------------------------------- */ - -/* Bits [31:6]: Reserved. */ - -/* BUSY: Set if the SDRAM is working on the command */ -#define FMC_SDSR_BUSY (1 << 5) - -/* MODES: Status modes */ -#define FMC_SDSR_MODE_NORMAL 0 -#define FMC_SDSR_MODE_SELF_REFRESH 1 -#define FMC_SDSR_MODE_POWER_DOWN 2 - -/* Mode shift */ -#define FMC_SDSR_MODE2_SHIFT 3 -#define FMC_SDSR_MODE1_SHIFT 1 - -/* RE: Refresh Error */ -#define FMC_SDSR_RE (1 << 0) - -/* Helper function for setting the timing parameters */ -struct sdram_timing { - int trcd; /* RCD Delay */ - int trp; /* RP Delay */ - int twr; /* Write Recovery Time */ - int trc; /* Row Cycle Delay */ - int tras; /* Self Refresh TIme */ - int txsr; /* Exit Self Refresh Time */ - int tmrd; /* Load to Active delay */ -}; - -/* Mode register parameters */ -#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; -enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, - SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, - SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; - -/* Send an array of timing parameters (indices above) to create SDTR register - * value - */ -BEGIN_DECLS - -uint32_t sdram_timing(struct sdram_timing *t); -void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, - int autorefresh, int modereg); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h deleted file mode 100644 index fcfd31e..0000000 --- a/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h +++ /dev/null @@ -1,91 +0,0 @@ -/** @addtogroup gpio_defines - * - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_GPIO_H) -/** @endcond */ -#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H -#define LIBOPENCM3_GPIO_COMMON_ALL_H - -/**@{*/ - -/* --- Convenience macros -------------------------------------------------- */ - -/* --- GPIO_LCKR values ---------------------------------------------------- */ - -#define GPIO_LCKK (1 << 16) -/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ - -/* GPIO number definitions (for convenience) */ -/** @defgroup gpio_pin_id GPIO Pin Identifiers -@ingroup gpio_defines - -@{*/ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL 0xffff -/**@}*/ - -BEGIN_DECLS - -void gpio_set(uint32_t gpioport, uint16_t gpios); -void gpio_clear(uint32_t gpioport, uint16_t gpios); -uint16_t gpio_get(uint32_t gpioport, uint16_t gpios); -void gpio_toggle(uint32_t gpioport, uint16_t gpios); -uint16_t gpio_port_read(uint32_t gpioport); -void gpio_port_write(uint32_t gpioport, uint16_t data); -void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios); - -END_DECLS - -/**@}*/ -#endif -/** @cond */ -#else -#warning "gpio_common_all.h should not be included explicitly, only via gpio.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h deleted file mode 100644 index d635dd4..0000000 --- a/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h +++ /dev/null @@ -1,294 +0,0 @@ -/** @addtogroup gpio_defines - * - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_GPIO_H -/** @endcond */ -#ifndef LIBOPENCM3_GPIO_COMMON_F234_H -#define LIBOPENCM3_GPIO_COMMON_F234_H - -/**@{*/ - -#include - -/* GPIO port base addresses (for convenience) */ -/** @defgroup gpio_port_id GPIO Port IDs -@ingroup gpio_defines - -@{*/ -#define GPIOA GPIO_PORT_A_BASE -#define GPIOB GPIO_PORT_B_BASE -#define GPIOC GPIO_PORT_C_BASE -#define GPIOD GPIO_PORT_D_BASE -#define GPIOE GPIO_PORT_E_BASE -#define GPIOF GPIO_PORT_F_BASE -#define GPIOG GPIO_PORT_G_BASE -#define GPIOH GPIO_PORT_H_BASE - -/**@}*/ - -/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ - -/* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32((port) + 0x00) -#define GPIOA_MODER GPIO_MODER(GPIOA) -#define GPIOB_MODER GPIO_MODER(GPIOB) -#define GPIOC_MODER GPIO_MODER(GPIOC) -#define GPIOD_MODER GPIO_MODER(GPIOD) -#define GPIOE_MODER GPIO_MODER(GPIOE) -#define GPIOF_MODER GPIO_MODER(GPIOF) -#define GPIOG_MODER GPIO_MODER(GPIOG) -#define GPIOH_MODER GPIO_MODER(GPIOH) - -/* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32((port) + 0x04) -#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) -#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) -#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) -#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) -#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) -#define GPIOF_OTYPER GPIO_OTYPER(GPIOF) -#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) -#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) - -/* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) -#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) -#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) -#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) -#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) -#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) -#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) -#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) -#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) - -/* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) -#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) -#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) -#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) -#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) -#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) -#define GPIOF_PUPDR GPIO_PUPDR(GPIOF) -#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) -#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) - -/* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32((port) + 0x10) -#define GPIOA_IDR GPIO_IDR(GPIOA) -#define GPIOB_IDR GPIO_IDR(GPIOB) -#define GPIOC_IDR GPIO_IDR(GPIOC) -#define GPIOD_IDR GPIO_IDR(GPIOD) -#define GPIOE_IDR GPIO_IDR(GPIOE) -#define GPIOF_IDR GPIO_IDR(GPIOF) -#define GPIOG_IDR GPIO_IDR(GPIOG) -#define GPIOH_IDR GPIO_IDR(GPIOH) - -/* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32((port) + 0x14) -#define GPIOA_ODR GPIO_ODR(GPIOA) -#define GPIOB_ODR GPIO_ODR(GPIOB) -#define GPIOC_ODR GPIO_ODR(GPIOC) -#define GPIOD_ODR GPIO_ODR(GPIOD) -#define GPIOE_ODR GPIO_ODR(GPIOE) -#define GPIOF_ODR GPIO_ODR(GPIOF) -#define GPIOG_ODR GPIO_ODR(GPIOG) -#define GPIOH_ODR GPIO_ODR(GPIOH) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32((port) + 0x18) -#define GPIOA_BSRR GPIO_BSRR(GPIOA) -#define GPIOB_BSRR GPIO_BSRR(GPIOB) -#define GPIOC_BSRR GPIO_BSRR(GPIOC) -#define GPIOD_BSRR GPIO_BSRR(GPIOD) -#define GPIOE_BSRR GPIO_BSRR(GPIOE) -#define GPIOF_BSRR GPIO_BSRR(GPIOF) -#define GPIOG_BSRR GPIO_BSRR(GPIOG) -#define GPIOH_BSRR GPIO_BSRR(GPIOH) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32((port) + 0x1c) -#define GPIOA_LCKR GPIO_LCKR(GPIOA) -#define GPIOB_LCKR GPIO_LCKR(GPIOB) -#define GPIOC_LCKR GPIO_LCKR(GPIOC) -#define GPIOD_LCKR GPIO_LCKR(GPIOD) -#define GPIOE_LCKR GPIO_LCKR(GPIOE) -#define GPIOF_LCKR GPIO_LCKR(GPIOF) -#define GPIOG_LCKR GPIO_LCKR(GPIOG) -#define GPIOH_LCKR GPIO_LCKR(GPIOH) - -/* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32((port) + 0x20) -#define GPIOA_AFRL GPIO_AFRL(GPIOA) -#define GPIOB_AFRL GPIO_AFRL(GPIOB) -#define GPIOC_AFRL GPIO_AFRL(GPIOC) -#define GPIOD_AFRL GPIO_AFRL(GPIOD) -#define GPIOE_AFRL GPIO_AFRL(GPIOE) -#define GPIOF_AFRL GPIO_AFRL(GPIOF) -#define GPIOG_AFRL GPIO_AFRL(GPIOG) -#define GPIOH_AFRL GPIO_AFRL(GPIOH) - -/* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32((port) + 0x24) -#define GPIOA_AFRH GPIO_AFRH(GPIOA) -#define GPIOB_AFRH GPIO_AFRH(GPIOB) -#define GPIOC_AFRH GPIO_AFRH(GPIOC) -#define GPIOD_AFRH GPIO_AFRH(GPIOD) -#define GPIOE_AFRH GPIO_AFRH(GPIOE) -#define GPIOF_AFRH GPIO_AFRH(GPIOF) -#define GPIOG_AFRH GPIO_AFRH(GPIOG) -#define GPIOH_AFRH GPIO_AFRH(GPIOH) - -/* --- GPIOx_MODER values -------------------------------------------------- */ - -#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) -#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode -@ingroup gpio_defines -@{*/ -#define GPIO_MODE_INPUT 0x0 -#define GPIO_MODE_OUTPUT 0x1 -#define GPIO_MODE_AF 0x2 -#define GPIO_MODE_ANALOG 0x3 -/**@}*/ - -/* --- GPIOx_OTYPER values ------------------------------------------------- */ - -/** @defgroup gpio_output_type GPIO Output Pin Driver Type -@ingroup gpio_defines -@{*/ -/** Push Pull */ -#define GPIO_OTYPE_PP 0x0 -/** Open Drain */ -#define GPIO_OTYPE_OD 0x1 -/**@}*/ - -/* --- GPIOx_OSPEEDR values ------------------------------------------------ */ - -#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) -#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_speed GPIO Output Pin Speed -@ingroup gpio_defines -@{*/ -#define GPIO_OSPEED_2MHZ 0x0 -#define GPIO_OSPEED_25MHZ 0x1 -#define GPIO_OSPEED_50MHZ 0x2 -#define GPIO_OSPEED_100MHZ 0x3 -/**@}*/ - -/* --- GPIOx_PUPDR values -------------------------------------------------- */ - -#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) -#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_pup GPIO Output Pin Pullup -@ingroup gpio_defines -@{*/ -#define GPIO_PUPD_NONE 0x0 -#define GPIO_PUPD_PULLUP 0x1 -#define GPIO_PUPD_PULLDOWN 0x2 -/**@}*/ - -/* --- GPIOx_IDR values ---------------------------------------------------- */ - -/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ - -/* --- GPIOx_ODR values ---------------------------------------------------- */ - -/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ - -/* --- GPIOx_BSRR values --------------------------------------------------- */ - -/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ -/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ - -/* --- GPIOx_LCKR values --------------------------------------------------- */ - -#define GPIO_LCKK (1 << 16) -/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ - -/* --- GPIOx_AFRL/H values ------------------------------------------------- */ - -/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ -/* See datasheet table 6 (pg. 48) for alternate function mappings. */ - -#define GPIO_AFR(n, af) ((af) << ((n) * 4)) -#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) -/** @defgroup gpio_af_num Alternate Function Pin Selection -@ingroup gpio_defines -@{*/ -#define GPIO_AF0 0x0 -#define GPIO_AF1 0x1 -#define GPIO_AF2 0x2 -#define GPIO_AF3 0x3 -#define GPIO_AF4 0x4 -#define GPIO_AF5 0x5 -#define GPIO_AF6 0x6 -#define GPIO_AF7 0x7 -#define GPIO_AF8 0x8 -#define GPIO_AF9 0x9 -#define GPIO_AF10 0xa -#define GPIO_AF11 0xb -#define GPIO_AF12 0xc -#define GPIO_AF13 0xd -#define GPIO_AF14 0xe -#define GPIO_AF15 0xf -/**@}*/ - -/* Note: EXTI source selection is now in the SYSCFG peripheral. */ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -/* - * Note: The F2 and F4 series have a completely new GPIO peripheral with - * different configuration options. Here we implement a different API partly to - * more closely match the peripheral capabilities and also to deliberately - * break compatibility with old F1 code so there is no confusion with similar - * sounding functions that have very different functionality. - */ - -void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, - uint16_t gpios); -void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, - uint16_t gpios); -void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); - -END_DECLS -/**@}*/ -#endif -/** @cond */ -#else -#warning "gpio_common_f234.h should not be included explicitly, only via gpio.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h deleted file mode 100644 index 31b18ce..0000000 --- a/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @addtogroup gpio_defines - * - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H -The order of header inclusion is important. gpio.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_GPIO_H -/** @endcond */ -#ifndef LIBOPENCM3_GPIO_COMMON_F24_H -#define LIBOPENCM3_GPIO_COMMON_F24_H - -/**@{*/ - -#include - -/* GPIO port base addresses (for convenience) */ -/** @defgroup gpio_port_id GPIO Port IDs -@ingroup gpio_defines - -@{*/ -#define GPIOI GPIO_PORT_I_BASE -#define GPIOJ GPIO_PORT_J_BASE -#define GPIOK GPIO_PORT_K_BASE -/**@}*/ - -/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ - -/* Port mode register (GPIOx_MODER) */ -#define GPIOI_MODER GPIO_MODER(GPIOI) -#define GPIOJ_MODER GPIO_MODER(GPIOJ) -#define GPIOK_MODER GPIO_MODER(GPIOK) - -/* Port output type register (GPIOx_OTYPER) */ -#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) -#define GPIOJ_OTYPER GPIO_OTYPER(GPIOJ) -#define GPIOK_OTYPER GPIO_OTYPER(GPIOK) - -/* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) -#define GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ) -#define GPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK) - -/* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) -#define GPIOJ_PUPDR GPIO_PUPDR(GPIOJ) -#define GPIOK_PUPDR GPIO_PUPDR(GPIOK) - -/* Port input data register (GPIOx_IDR) */ -#define GPIOI_IDR GPIO_IDR(GPIOI) -#define GPIOJ_IDR GPIO_IDR(GPIOJ) -#define GPIOK_IDR GPIO_IDR(GPIOK) - -/* Port output data register (GPIOx_ODR) */ -#define GPIOI_ODR GPIO_ODR(GPIOI) -#define GPIOJ_ODR GPIO_ODR(GPIOJ) -#define GPIOK_ODR GPIO_ODR(GPIOK) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIOI_BSRR GPIO_BSRR(GPIOI) -#define GPIOJ_BSRR GPIO_BSRR(GPIOJ) -#define GPIOK_BSRR GPIO_BSRR(GPIOK) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIOI_LCKR GPIO_LCKR(GPIOI) -#define GPIOJ_LCKR GPIO_LCKR(GPIOJ) -#define GPIOK_LCKR GPIO_LCKR(GPIOK) - -/* Alternate function low register (GPIOx_AFRL) */ -#define GPIOI_AFRL GPIO_AFRL(GPIOI) -#define GPIOJ_AFRL GPIO_AFRL(GPIOJ) -#define GPIOK_AFRL GPIO_AFRL(GPIOK) - -/* Alternate function high register (GPIOx_AFRH) */ -#define GPIOI_AFRH GPIO_AFRH(GPIOI) -#define GPIOJ_AFRH GPIO_AFRH(GPIOJ) -#define GPIOK_AFRH GPIO_AFRH(GPIOK) - -/**@}*/ -#endif -/** @cond */ -#else -#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h deleted file mode 100644 index 6c43302..0000000 --- a/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h +++ /dev/null @@ -1,181 +0,0 @@ -/** @addtogroup hash_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Mikhail Avkhimenia - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Mikhail Avkhimenia - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/** @cond */ -#ifdef LIBOPENCM3_HASH_H -/** @endcond */ -#ifndef LIBOPENCM3_HASH_COMMON_F24_H -#define LIBOPENCM3_HASH_COMMON_F24_H - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup hash_reg_base HASH register base addresses -@ingroup STM32F_hash_defines - -@{*/ -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) -#define HASH HASH_BASE -/**@}*/ - -/* --- HASH registers ------------------------------------------------------ */ - -/* HASH control register (HASH_CR) */ -#define HASH_CR MMIO32(HASH + 0x00) - -/* HASH data input register (HASH_DIR) */ -#define HASH_DIN MMIO32(HASH + 0x04) - -/* HASH start register (HASH_STR) */ -#define HASH_STR MMIO32(HASH + 0x08) - -/* HASH digest registers (HASH_HR[5]) */ -#define HASH_HR (&MMIO32(HASH + 0x0C)) /* x5 */ - -/* HASH interrupt enable register (HASH_IMR) */ -#define HASH_IMR MMIO32(HASH + 0x20) - -/* HASH status register (HASH_SR) */ -#define HASH_SR MMIO32(HASH + 0x28) - -/* HASH context swap registers (HASH_CSR[51]) */ -#define HASH_CSR (&MMIO32(HASH + 0xF8)) /* x51 */ - -/* --- HASH_CR values ------------------------------------------------------ */ - -/* INIT: Initialize message digest calculation */ -#define HASH_CR_INIT (1 << 2) - -/* DMAE: DMA enable */ -#define HASH_CR_DMAE (1 << 3) - -/* DATATYPE: Data type selection */ -/****************************************************************************/ -/** @defgroup hash_data_type HASH Data Type -@ingroup hash_defines - -@{*/ -#define HASH_DATA_32BIT (0 << 4) -#define HASH_DATA_16BIT (1 << 4) -#define HASH_DATA_8BIT (2 << 4) -#define HASH_DATA_BITSTRING (3 << 4) -/**@}*/ -#define HASH_CR_DATATYPE (3 << 4) - -/* MODE: Mode selection */ -/****************************************************************************/ -/** @defgroup hash_mode HASH Mode -@ingroup hash_defines - -@{*/ -#define HASH_MODE_HASH (0 << 6) -#define HASH_MODE_HMAC (1 << 6) -/**@}*/ -#define HASH_CR_MODE (1 << 6) - -/* ALGO: Algorithm selection */ -/****************************************************************************/ -/** @defgroup hash_algorithm HASH Algorithm -@ingroup hash_defines - -@{*/ -#define HASH_ALGO_SHA1 (0 << 7) -#define HASH_ALGO_MD5 (1 << 7) -/**@}*/ -#define HASH_CR_ALGO (1 << 7) - -/* NBW: Number of words already pushed */ -#define HASH_CR_NBW (15 << 8) - -/* DINNE: DIN(Data input register) not empty */ -#define HASH_CR_DINNE (1 << 12) - -/* LKEY: Long key selection */ -/****************************************************************************/ -/** @defgroup hash_key_length HASH Key length -@ingroup hash_defines - -@{*/ -#define HASH_KEY_SHORT (0 << 16) -#define HASH_KEY_LONG (1 << 16) -/**@}*/ -#define HASH_CR_LKEY (1 << 16) - -/* --- HASH_STR values ----------------------------------------------------- */ - -/* NBLW: Number of valid bits in the last word of the message in the bit string - */ -#define HASH_STR_NBW (31 << 0) - -/* DCAL: Digest calculation */ -#define HASH_STR_DCAL (1 << 8) - -/* --- HASH_IMR values ----------------------------------------------------- */ - -/* DINIE: Data input interrupt enable */ -#define HASH_IMR_DINIE (1 << 0) - -/* DCIE: Digest calculation completion interrupt enable */ -#define HASH_IMR_DCIE (1 << 1) - -/* --- HASH_SR values ------------------------------------------------------ */ - -/* DINIS: Data input interrupt status */ -#define HASH_SR_DINIS (1 << 0) - -/* DCIS: Digest calculation completion interrupt status */ -#define HASH_SR_DCIS (1 << 1) - -/* DMAS: DMA Status */ -#define HASH_SR_DMAS (1 << 2) - -/* BUSY: Busy bit */ -#define HASH_SR_BUSY (1 << 3) - -/* --- HASH function prototypes -------------------------------------------- */ - -BEGIN_DECLS - -void hash_set_mode(uint8_t mode); -void hash_set_algorithm(uint8_t algorithm); -void hash_set_data_type(uint8_t datatype); -void hash_set_key_length(uint8_t keylength); -void hash_set_last_word_valid_bits(uint8_t validbits); -void hash_init(void); -void hash_add_data(uint32_t data); -void hash_digest(void); -void hash_get_result(uint32_t *data); - -END_DECLS -/**@}*/ -#endif -/** @cond */ -#else -#warning "hash_common_f24.h should not be included explicitly, only via hash.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/hrtim_common_all.h b/libopencm3/include/libopencm3/stm32/common/hrtim_common_all.h deleted file mode 100644 index ae4094c..0000000 --- a/libopencm3/include/libopencm3/stm32/common/hrtim_common_all.h +++ /dev/null @@ -1,3005 +0,0 @@ -/** @addtogroup hrtim_defines - -@author @htmlonly © @endhtmlonly 2017 -Florian Larysch - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Florian Larysch - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA HRTIM.H -The order of header inclusion is important. hrtim.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_HRTIM_H -/** @endcond */ -#ifndef LIBOPENCM3_HRTIM_COMMON_ALL_H -#define LIBOPENCM3_HRTIM_COMMON_ALL_H - -/** @defgroup hrtim_registers_common HRTIM Common Registers - * @ingroup hrtim_defines - * @{ - */ -/** Control Register 1 (CR1) */ -#define HRTIM_CR1 MMIO32(HRTIM_BASE + 0x380 + 0x00) - -/** Control Register 2 (CR2) */ -#define HRTIM_CR2 MMIO32(HRTIM_BASE + 0x380 + 0x04) - -/** Interrupt Status Register (ISR) */ -#define HRTIM_ISR MMIO32(HRTIM_BASE + 0x380 + 0x08) - -/** Interrupt Clear Register (ICR) */ -#define HRTIM_ICR MMIO32(HRTIM_BASE + 0x380 + 0x0c) - -/** Interrupt Enable Register (IER) */ -#define HRTIM_IER MMIO32(HRTIM_BASE + 0x380 + 0x10) - -/** Output Enable Register (OENR) */ -#define HRTIM_OENR MMIO32(HRTIM_BASE + 0x380 + 0x14) - -/** Output Disable Register (ODISR) */ -#define HRTIM_ODISR MMIO32(HRTIM_BASE + 0x380 + 0x18) - -/** Output Disable Status Register (ODSR) */ -#define HRTIM_ODSR MMIO32(HRTIM_BASE + 0x380 + 0x1c) - -/** Burst Mode Control Register (BMCR) */ -#define HRTIM_BMCR MMIO32(HRTIM_BASE + 0x380 + 0x20) - -/** Burst Mode Trigger Register (BMTRGR) */ -#define HRTIM_BMTRGR MMIO32(HRTIM_BASE + 0x380 + 0x24) - -/** Burst Mode Compare Register (BMCMPR) */ -#define HRTIM_BMCMPR6 MMIO32(HRTIM_BASE + 0x380 + 0x28) - -/** Burst Mode Period Register (BMPER) */ -#define HRTIM_BMPER MMIO32(HRTIM_BASE + 0x380 + 0x2c) - -/** Timer External Event Control Register 1 (EECR1) */ -#define HRTIM_EECR1 MMIO32(HRTIM_BASE + 0x380 + 0x30) - -/** Timer External Event Control Register 2 (EECR2) */ -#define HRTIM_EECR2 MMIO32(HRTIM_BASE + 0x380 + 0x34) - -/** Timer External Event Control Register 3 (EECR3) */ -#define HRTIM_EECR3 MMIO32(HRTIM_BASE + 0x380 + 0x38) - -/** ADC Trigger 1 Register (ADC1R) */ -#define HRTIM_ADC1R MMIO32(HRTIM_BASE + 0x380 + 0x3c) - -/** ADC Trigger 2 Register (ADC2R) */ -#define HRTIM_ADC2R MMIO32(HRTIM_BASE + 0x380 + 0x40) - -/** ADC Trigger 3 Register (ADC3R) */ -#define HRTIM_ADC3R MMIO32(HRTIM_BASE + 0x380 + 0x44) - -/** ADC Trigger 4 Register (ADC4R) */ -#define HRTIM_ADC4R MMIO32(HRTIM_BASE + 0x380 + 0x48) - -/** DLL Control Register (DLLCR) */ -#define HRTIM_DLLCR MMIO32(HRTIM_BASE + 0x380 + 0x4c) - -/** HRTIM Fault Input Register 1 (FLTINR1) */ -#define HRTIM_FLTINR1 MMIO32(HRTIM_BASE + 0x380 + 0x50) - -/** HRTIM Fault Input Register 2 (FLTINR2) */ -#define HRTIM_FLTINR2 MMIO32(HRTIM_BASE + 0x380 + 0x54) - -/** Burst DMA Master timer update Register (BDMUPDR) */ -#define HRTIM_BDMUPDR MMIO32(HRTIM_BASE + 0x380 + 0x58) - -/** Burst DMA Timerx update Register (BDTxUPR) */ -#define HRTIM_BDTxUPR(x) MMIO32(HRTIM_BASE + 0x380 + 0x5c + (x)*4) - -/** Burst DMA Data Register (BDMADR) */ -#define HRTIM_BDMADR MMIO32(HRTIM_BASE + 0x380 + 0x70) -/**@}*/ - - -/** @defgroup hrtim_registers_master HRTIM Master Registers - * @ingroup hrtim_defines - * @{ - */ -/** Master Timer Control Register (MCR) */ -#define HRTIM_MCR MMIO32(HRTIM_BASE + 0x00) - -/** Master Timer Interrupt Status Register (MISR) */ -#define HRTIM_MISR MMIO32(HRTIM_BASE + 0x04) - -/** Master Timer Interrupt Clear Register (MICR) */ -#define HRTIM_MICR MMIO32(HRTIM_BASE + 0x08) - -/** Master Timer DMA / Interrupt Enable Register (MDIER) */ -#define HRTIM_MDIER MMIO32(HRTIM_BASE + 0x0c) - -/** Master Timer Counter Register (MCNTR) */ -#define HRTIM_MCNTR MMIO32(HRTIM_BASE + 0x10) - -/** Master Timer Period Register (MPER) */ -#define HRTIM_MPER MMIO32(HRTIM_BASE + 0x14) - -/** Master Timer Repetition Register (MREP) */ -#define HRTIM_MREP MMIO32(HRTIM_BASE + 0x18) - -/** Master Timer Compare 1 Register (MCMP1R) */ -#define HRTIM_MCMP1R MMIO32(HRTIM_BASE + 0x1c) - -/** Master Timer Compare 2 Register (MCMP2R) */ -#define HRTIM_MCMP2R MMIO32(HRTIM_BASE + 0x24) - -/** Master Timer Compare 3 Register (MCMP3R) */ -#define HRTIM_MCMP3R MMIO32(HRTIM_BASE + 0x28) - -/** Master Timer Compare 4 Register (MCMP4R) */ -#define HRTIM_MCMP4R MMIO32(HRTIM_BASE + 0x2c) -/**@}*/ - - -/** @defgroup hrtim_registers_timer HRTIM TIMx Registers - * @ingroup hrtim_defines - * @{ - */ -#define HRTIM_TIMx_BASE(x) (HRTIM_BASE + 0x80 + (x) * 0x80) - -#define HRTIM_TIMA 0 -#define HRTIM_TIMB 1 -#define HRTIM_TIMC 2 -#define HRTIM_TIMD 3 -#define HRTIM_TIME 4 - -/** Timerx Control Register (TIMCR) */ -#define HRTIM_TIMx_TIMCR(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x00) - -/** Timerx Interrupt Status Register (ISR) */ -#define HRTIM_TIMx_ISR(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x04) - -/** Timerx Interrupt Clear Register (ICR) */ -#define HRTIM_TIMx_ICR(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x08) - -/** Timerx DMA / Interrupt Enable Register (DIER) */ -#define HRTIM_TIMx_DIER(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x0c) - -/** Timerx Counter Register (CNT) */ -#define HRTIM_TIMx_CNT(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x10) - -/** Timerx Period Register (PER) */ -#define HRTIM_TIMx_PER(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x14) - -/** Timerx Repetition Register (REP) */ -#define HRTIM_TIMx_REP(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x18) - -/** Timerx Compare 1 Register (CMP1) */ -#define HRTIM_TIMx_CMP1(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x1c) - -/** Timerx Compare 1 Compound Register (CMP1C) */ -#define HRTIM_TIMx_CMP1C(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x20) - -/** Timerx Compare 2 Register (CMP2) */ -#define HRTIM_TIMx_CMP2(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x24) - -/** Timerx Compare 3 Register (CMP3) */ -#define HRTIM_TIMx_CMP3(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x28) - -/** Timerx Compare 4 Register (CMP4) */ -#define HRTIM_TIMx_CMP4(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x2c) - -/** Timerx Capture 1 Register (CPT1) */ -#define HRTIM_TIMx_CPT1(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x30) - -/** Timerx Capture 2 Register (CPT2) */ -#define HRTIM_TIMx_CPT2(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x34) - -/** Timerx Deadtime Register (DT) */ -#define HRTIM_TIMx_DT(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x38) - -/** Timerx Output1 Set Register (SET1) */ -#define HRTIM_TIMx_SET1(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x3c) - -/** Timerx Output1 Reset Register (RST1) */ -#define HRTIM_TIMx_RST1(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x40) - -/** Timerx Output2 Set Register (SET2) */ -#define HRTIM_TIMx_SET2(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x44) - -/** Timerx Output2 Reset Register (RST2) */ -#define HRTIM_TIMx_RST2(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x48) - -/** Timerx External Event Filtering Register 1 (EEF1) */ -#define HRTIM_TIMx_EEF1(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x4c) - -/** Timerx External Event Filtering Register 2 (EEF2) */ -#define HRTIM_TIMx_EEF2(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x50) - -/** TimerA Reset Register (RST) */ -#define HRTIM_TIMx_RST(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x54) - -/** Timerx Chopper Register (CHP) */ -#define HRTIM_TIMx_CHP(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x58) - -/** Timerx Capture 1 Control Register (CPT1CR) */ -#define HRTIM_TIMx_CPT1CR(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x5c) - -/** Timerx Capture 2 Control Register (CPT2CR) */ -#define HRTIM_TIMx_CPT2CR(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x60) - -/** Timerx Output Register (OUT) */ -#define HRTIM_TIMx_OUT(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x64) - -/** Timerx Fault Register (FLT) */ -#define HRTIM_TIMx_FLT(x) MMIO32(HRTIM_TIMx_BASE(x) + 0x68) - -/**@}*/ - -/** @defgroup hrtim_cr1_values HRTIM_CR1 Values - * @ingroup hrtim_defines - * @{ - */ -/** AD4USRC[27:25]: ADC Trigger 4 Update Source */ -#define HRTIM_CR1_AD4USRC_SHIFT 25 -#define HRTIM_CR1_AD4USRC_MASK (0x7 << HRTIM_CR1_AD4USRC_SHIFT) - -/** AD3USRC[24:22]: ADC Trigger 3 Update Source */ -#define HRTIM_CR1_AD3USRC_SHIFT 22 -#define HRTIM_CR1_AD3USRC_MASK (0x7 << HRTIM_CR1_AD3USRC_SHIFT) - -/** AD2USRC[21:19]: ADC Trigger 2 Update Source */ -#define HRTIM_CR1_AD2USRC_SHIFT 19 -#define HRTIM_CR1_AD2USRC_MASK (0x7 << HRTIM_CR1_AD2USRC_SHIFT) - -/** AD1USRC[18:16]: ADC Trigger 1 Update Source */ -#define HRTIM_CR1_AD1USRC_SHIFT 16 -#define HRTIM_CR1_AD1USRC_MASK (0x7 << HRTIM_CR1_AD1USRC_SHIFT) - -#define HRTIM_CR1_ADxUSRC_MASTER 0x0 -#define HRTIM_CR1_ADxUSRC_TIMA 0x1 -#define HRTIM_CR1_ADxUSRC_TIMB 0x2 -#define HRTIM_CR1_ADxUSRC_TIMC 0x3 -#define HRTIM_CR1_ADxUSRC_TIMD 0x4 -#define HRTIM_CR1_ADxUSRC_TIME 0x5 - -/** TEUDIS: Timer E Update Disable */ -#define HRTIM_CR1_TEUDIS (1 << 5) - -/** TDUDIS: Timer D Update Disable */ -#define HRTIM_CR1_TDUDIS (1 << 4) - -/** TCUDIS: Timer C Update Disable */ -#define HRTIM_CR1_TCUDIS (1 << 3) - -/** TBUDIS: Timer B Update Disable */ -#define HRTIM_CR1_TBUDIS (1 << 2) - -/** TAUDIS: Timer A Update Disable */ -#define HRTIM_CR1_TAUDIS (1 << 1) - -/** MUDIS: Master Update Disable */ -#define HRTIM_CR1_MUDIS (1 << 0) -/**@}*/ - - -/** @defgroup hrtim_cr2_values HRTIM_CR2 Values - * @ingroup hrtim_defines - * @{ - */ - -/** TERST: Timer E counter software reset */ -#define HRTIM_CR2_TERST (1 << 13) - -/** TDRST: Timer D counter software reset */ -#define HRTIM_CR2_TDRST (1 << 12) - -/** TCRST: Timer C counter software reset */ -#define HRTIM_CR2_TCRST (1 << 11) - -/** TBRST: Timer B counter software reset */ -#define HRTIM_CR2_TBRST (1 << 10) - -/** TARST: Timer A counter software reset */ -#define HRTIM_CR2_TARST (1 << 9) - -/** MRST: Master Counter software reset */ -#define HRTIM_CR2_MRST (1 << 8) - -/** TESWU: Timer E Software Update */ -#define HRTIM_CR2_TESWU (1 << 5) - -/** TDSWU: Timer D Software Update */ -#define HRTIM_CR2_TDSWU (1 << 4) - -/** TCSWU: Timer C Software Update */ -#define HRTIM_CR2_TCSWU (1 << 3) - -/** TBSWU: Timer B Software Update */ -#define HRTIM_CR2_TBSWU (1 << 2) - -/** TASWU: Timer A Software update */ -#define HRTIM_CR2_TASWU (1 << 1) - -/** MSWU: Master Timer Software update */ -#define HRTIM_CR2_MSWU (1 << 0) -/**@}*/ - - -/** @defgroup hrtim_isr_values HRTIM_ISR Values - * @ingroup hrtim_defines - * @{ - */ - -/** BMPER: Burst mode Period Interrupt Flag */ -#define HRTIM_ISR_BMPER (1 << 17) - -/** DLLRDY: DLL Ready Interrupt Flag */ -#define HRTIM_ISR_DLLRDY (1 << 16) - -/** SYSFLT: System Fault Interrupt Flag */ -#define HRTIM_ISR_SYSFLT (1 << 5) - -/** FLT5: Fault 5 Interrupt Flag */ -#define HRTIM_ISR_FLT5 (1 << 4) - -/** FLT4: Fault 4 Interrupt Flag */ -#define HRTIM_ISR_FLT4 (1 << 3) - -/** FLT3: Fault 3 Interrupt Flag */ -#define HRTIM_ISR_FLT3 (1 << 2) - -/** FLT2: Fault 2 Interrupt Flag */ -#define HRTIM_ISR_FLT2 (1 << 1) - -/** FLT1: Fault 1 Interrupt Flag */ -#define HRTIM_ISR_FLT1 (1 << 0) -/**@}*/ - -/** @defgroup hrtim_icr_values HRTIM_ICR Values - * @ingroup hrtim_defines - * @{ - */ - -/** BMPERC: Burst mode period flag Clear */ -#define HRTIM_ICR_BMPERC (1 << 17) - -/** DLLRDYC: DLL Ready Interrupt flag Clear */ -#define HRTIM_ICR_DLLRDYC (1 << 16) - -/** SYSFLTC: System Fault Interrupt Flag Clear */ -#define HRTIM_ICR_SYSFLTC (1 << 5) - -/** FLT5C: Fault 5 Interrupt Flag Clear */ -#define HRTIM_ICR_FLT5C (1 << 4) - -/** FLT4C: Fault 4 Interrupt Flag Clear */ -#define HRTIM_ICR_FLT4C (1 << 3) - -/** FLT3C: Fault 3 Interrupt Flag Clear */ -#define HRTIM_ICR_FLT3C (1 << 2) - -/** FLT2C: Fault 2 Interrupt Flag Clear */ -#define HRTIM_ICR_FLT2C (1 << 1) - -/** FLT1C: Fault 1 Interrupt Flag Clear */ -#define HRTIM_ICR_FLT1C (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_ier_values HRTIM_IER Values - * @ingroup hrtim_defines - * @{ - */ - -/** BMPERIE: Burst mode period Interrupt Enable */ -#define HRTIM_IER_BMPERIE (1 << 17) - -/** DLLRDYIE: DLL Ready Interrupt Enable */ -#define HRTIM_IER_DLLRDYIE (1 << 16) - -/** SYSFLTE: System Fault Interrupt Enable */ -#define HRTIM_IER_SYSFLTE (1 << 5) - -/** FLT5IE: Fault 5 Interrupt Enable */ -#define HRTIM_IER_FLT5IE (1 << 4) - -/** FLT4IE: Fault 4 Interrupt Enable */ -#define HRTIM_IER_FLT4IE (1 << 3) - -/** FLT3IE: Fault 3 Interrupt Enable */ -#define HRTIM_IER_FLT3IE (1 << 2) - -/** FLT2IE: Fault 2 Interrupt Enable */ -#define HRTIM_IER_FLT2IE (1 << 1) - -/** FLT1IE: Fault 1 Interrupt Enable */ -#define HRTIM_IER_FLT1IE (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_oenr_values HRTIM_OENR Values - * @ingroup hrtim_defines - * @{ - */ - -/** TE2OEN: Timer E Output 2 Enable */ -#define HRTIM_OENR_TE2OEN (1 << 9) - -/** TE1OEN: Timer E Output 1 Enable */ -#define HRTIM_OENR_TE1OEN (1 << 8) - -/** TD2OEN: Timer D Output 2 Enable */ -#define HRTIM_OENR_TD2OEN (1 << 7) - -/** TD1OEN: Timer D Output 1 Enable */ -#define HRTIM_OENR_TD1OEN (1 << 6) - -/** TC2OEN: Timer C Output 2 Enable */ -#define HRTIM_OENR_TC2OEN (1 << 5) - -/** TC1OEN: Timer C Output 1 Enable */ -#define HRTIM_OENR_TC1OEN (1 << 4) - -/** TB2OEN: Timer B Output 2 Enable */ -#define HRTIM_OENR_TB2OEN (1 << 3) - -/** TB1OEN: Timer B Output 1 Enable */ -#define HRTIM_OENR_TB1OEN (1 << 2) - -/** TA2OEN: Timer A Output 2 Enable */ -#define HRTIM_OENR_TA2OEN (1 << 1) - -/** TA1OEN: Timer A Output 1 Enable */ -#define HRTIM_OENR_TA1OEN (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_odisr_values HRTIM_ODISR Values - * @ingroup hrtim_defines - * @{ - */ - -/** TE2ODIS: Timer E Output 2 disable */ -#define HRTIM_DISR_TE2ODIS (1 << 9) - -/** TE1ODIS: Timer E Output 1 disable */ -#define HRTIM_DISR_TE1ODIS (1 << 8) - -/** TD2ODIS: Timer D Output 2 disable */ -#define HRTIM_DISR_TD2ODIS (1 << 7) - -/** TD1ODIS: Timer D Output 1 disable */ -#define HRTIM_DISR_TD1ODIS (1 << 6) - -/** TC2ODIS: Timer C Output 2 disable */ -#define HRTIM_DISR_TC2ODIS (1 << 5) - -/** TC1ODIS: Timer C Output 1 disable */ -#define HRTIM_DISR_TC1ODIS (1 << 4) - -/** TB2ODIS: Timer B Output 2 disable */ -#define HRTIM_DISR_TB2ODIS (1 << 3) - -/** TB1ODIS: Timer B Output 1 disable */ -#define HRTIM_DISR_TB1ODIS (1 << 2) - -/** TA2ODIS: Timer A Output 2 disable */ -#define HRTIM_DISR_TA2ODIS (1 << 1) - -/** TA1ODIS: Timer A Output 1 disable */ -#define HRTIM_DISR_TA1ODIS (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_odsr_values HRTIM_ODSR Values - * @ingroup hrtim_defines - * @{ - */ - -/** TE2ODS: Timer E Output 2 disable status */ -#define HRTIM_ODSR_TE2ODS (1 << 9) - -/** TE1ODS: Timer E Output 1 disable status */ -#define HRTIM_ODSR_TE1ODS (1 << 8) - -/** TD2ODS: Timer D Output 2 disable status */ -#define HRTIM_ODSR_TD2ODS (1 << 7) - -/** TD1ODS: Timer D Output 1 disable status */ -#define HRTIM_ODSR_TD1ODS (1 << 6) - -/** TC2ODS: Timer C Output 2 disable status */ -#define HRTIM_ODSR_TC2ODS (1 << 5) - -/** TC1ODS: Timer C Output 1 disable status */ -#define HRTIM_ODSR_TC1ODS (1 << 4) - -/** TB2ODS: Timer B Output 2 disable status */ -#define HRTIM_ODSR_TB2ODS (1 << 3) - -/** TB1ODS: Timer B Output 1 disable status */ -#define HRTIM_ODSR_TB1ODS (1 << 2) - -/** TA2ODS: Timer A Output 2 disable status */ -#define HRTIM_ODSR_TA2ODS (1 << 1) - -/** TA1ODS: Timer A Output 1 disable status */ -#define HRTIM_ODSR_TA1ODS (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_bmcr_values HRTIM_BMCR Values - * @ingroup hrtim_defines - * @{ - */ - -/** BMSTAT: Burst Mode Status */ -#define HRTIM_BMCR_BMSTAT (1 << 31) - -/** TEBM: Timer E Burst Mode */ -#define HRTIM_BMCR_TEBM (1 << 21) - -/** TDBM: Timer D Burst Mode */ -#define HRTIM_BMCR_TDBM (1 << 20) - -/** TCBM: Timer C Burst Mode */ -#define HRTIM_BMCR_TCBM (1 << 19) - -/** TBBM: Timer B Burst Mode */ -#define HRTIM_BMCR_TBBM (1 << 18) - -/** TABM: Timer A Burst Mode */ -#define HRTIM_BMCR_TABM (1 << 17) - -/** MTBM: Master Timer Burst Mode */ -#define HRTIM_BMCR_MTBM (1 << 16) - -/** BMPREN: Burst Mode Preload Enable */ -#define HRTIM_BMCR_BMPREN (1 << 10) - -/** BMPRSC[9:6]: Burst Mode Prescaler */ -#define HRTIM_BMCR_BMPRSC_SHIFT 6 -#define HRTIM_BMCR_BMPRSC_MASK (0xf << HRTIM_BMCR_BMPRSC_SHIFT) - -#define HRTIM_BMCR_BMPRSC_1 ( 0 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_2 ( 1 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_4 ( 2 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_8 ( 3 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_16 ( 4 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_32 ( 5 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_64 ( 6 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_128 ( 7 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_256 ( 8 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_512 ( 9 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_1024 (10 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_2048 (11 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_4096 (12 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_8192 (13 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_16384 (14 << HRTIM_BMCR_BMPRSC_SHIFT) -#define HRTIM_BMCR_BMPRSC_32768 (15 << HRTIM_BMCR_BMPRSC_SHIFT) - -/** BMCLK[5:2]: Burst Mode Clock source */ -#define HRTIM_BMCR_BMCLK_SHIFT 2 -#define HRTIM_BMCR_BMCLK_MASK (0xf << HRTIM_BMCR_BMCLK_SHIFT) - -#define HRTIM_BMCR_BMCLK_MASTER ( 0 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_TIMA ( 1 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_TIMB ( 2 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_TIMC ( 3 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_TIMD ( 4 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_TIME ( 5 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_BMC1 ( 6 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_BMC2 ( 7 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_BMC3 ( 8 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_BMC4 ( 9 << HRTIM_BMCR_BMCLK_SHIFT) -#define HRTIM_BMCR_BMCLK_HRTIM (10 << HRTIM_BMCR_BMCLK_SHIFT) - -/** BMOM: Burst Mode operating mode */ -#define HRTIM_BMCR_BMOM (1 << 1) - -/** BME: Burst Mode enable */ -#define HRTIM_BMCR_BME (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_bmtrgr_values HRTIM_BMTRGR Values - * @ingroup hrtim_defines - * @{ - */ - -/** OCHPEV: On-chip Event */ -#define HRTIM_BMTRGR_OCHPEV (1 << 31) - -/** EEV8: External Event 8 */ -#define HRTIM_BMTRGR_EEV8 (1 << 30) - -/** EEV7: External Event 7 */ -#define HRTIM_BMTRGR_EEV7 (1 << 29) - -/** TDEEV8: Timer D period following External Event 8 */ -#define HRTIM_BMTRGR_TDEEV8 (1 << 28) - -/** TAEEV7: Timer A period following External Event 7 */ -#define HRTIM_BMTRGR_TAEEV7 (1 << 27) - -/** TECMP2: Timer E Compare 2 event */ -#define HRTIM_BMTRGR_TECMP2 (1 << 26) - -/** TECMP1: Timer E Compare 1 event */ -#define HRTIM_BMTRGR_TECMP1 (1 << 25) - -/** TEREP: Timer E repetition */ -#define HRTIM_BMTRGR_TEREP (1 << 24) - -/** TERST: Timer E reset or roll-over */ -#define HRTIM_BMTRGR_TERST (1 << 23) - -/** TDCMP2: Timer D Compare 2 event */ -#define HRTIM_BMTRGR_TDCMP2 (1 << 22) - -/** TDCMP1: Timer D Compare 1 event */ -#define HRTIM_BMTRGR_TDCMP1 (1 << 21) - -/** TDREP: Timer D repetition */ -#define HRTIM_BMTRGR_TDREP (1 << 20) - -/** TDRST: Timer D reset or roll-over */ -#define HRTIM_BMTRGR_TDRST (1 << 19) - -/** TCCMP2: Timer C Compare 2 event */ -#define HRTIM_BMTRGR_TCCMP2 (1 << 18) - -/** TCCMP1: Timer C Compare 1 event */ -#define HRTIM_BMTRGR_TCCMP1 (1 << 17) - -/** TCREP: Timer C repetition */ -#define HRTIM_BMTRGR_TCREP (1 << 16) - -/** TCRST: Timer C reset or roll-over */ -#define HRTIM_BMTRGR_TCRST (1 << 15) - -/** TBCMP2: Timer B Compare 2 event */ -#define HRTIM_BMTRGR_TBCMP2 (1 << 14) - -/** TBCMP1: Timer B Compare 1 event */ -#define HRTIM_BMTRGR_TBCMP1 (1 << 13) - -/** TBREP: Timer B repetition */ -#define HRTIM_BMTRGR_TBREP (1 << 12) - -/** TBRST: Timer B reset or roll-over */ -#define HRTIM_BMTRGR_TBRST (1 << 11) - -/** TACMP2: Timer A Compare 2 event */ -#define HRTIM_BMTRGR_TACMP2 (1 << 10) - -/** TACMP1: Timer A Compare 1 event */ -#define HRTIM_BMTRGR_TACMP1 (1 << 9) - -/** TAREP: Timer A repetition */ -#define HRTIM_BMTRGR_TAREP (1 << 8) - -/** TARST: Timer A reset or roll-over */ -#define HRTIM_BMTRGR_TARST (1 << 7) - -/** MSTCMP4: Master Compare 4 */ -#define HRTIM_BMTRGR_MSTCMP4 (1 << 6) - -/** MSTCMP3: Master Compare 3 */ -#define HRTIM_BMTRGR_MSTCMP3 (1 << 5) - -/** MSTCMP2: Master Compare 2 */ -#define HRTIM_BMTRGR_MSTCMP2 (1 << 4) - -/** MSTCMP1: Master Compare 1 */ -#define HRTIM_BMTRGR_MSTCMP1 (1 << 3) - -/** MSTREP: Master repetition */ -#define HRTIM_BMTRGR_MSTREP (1 << 2) - -/** MSTRST: Master reset or roll-over */ -#define HRTIM_BMTRGR_MSTRST (1 << 1) - -/** SW: Software start */ -#define HRTIM_BMTRGR_SW (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_eecrx_values HRTIM_EECRx Values - * @ingroup hrtim_defines - * @{ - */ - -/** EExFAST: External Event x Fast mode */ -#define HRTIM_EECR_EExFAST(x) (1 << ((x) * 6 - 1)) - -/** EExSNS: External Event x Sensitivity */ -#define HRTIM_EECR_EExSNS_SHIFT(x) ((x) * 6 - 3) -#define HRTIM_EECR_EExSNS_MASK(x) (0x3 << HRTIM_EECR_EExSNS_SHIFT(x)) - -#define HRTIM_EECR_EExSNS_LEVEL(x) (0 << HRTIM_EECR_EExSNS_SHIFT(x)) -#define HRTIM_EECR_EExSNS_RISING(x) (1 << HRTIM_EECR_EExSNS_SHIFT(x)) -#define HRTIM_EECR_EExSNS_FALLING(x) (2 << HRTIM_EECR_EExSNS_SHIFT(x)) -#define HRTIM_EECR_EExSNS_BOTH(x) (3 << HRTIM_EECR_EExSNS_SHIFT(x)) - -/** EExPOL: External Event x Polarity */ -#define HRTIM_EECR_EExPOL (1 << ((x) * 6 - 4)) - -/** EExSRC: External Event x Source */ -#define HRTIM_EECR_EExSRC_SHIFT(x) ((x) * 6 - 6) -#define HRTIM_EECR_EExSRC_MASK(x) (0x3 << HRTIM_EECR_EExSRC_SHIFT(x)) - - -/* --- HRTIM_EECR3 values -------------------------------------------- */ - -/** EExF: External Event x Filter */ -#define HRTIM_EECR3_EExF_SHIFT(x) ((x - 6) * 4) -#define HRTIM_EECR3_EExF_MASK(x) (0xF << HRTIM_EECR3_EExF_SHIFT(x)) - -/**@}*/ - -/** @defgroup hrtim_adc1r_values HRTIM_ADC1R Values - * @ingroup hrtim_defines - * @{ - */ - -/** AD1TEPER: ADC trigger 1 on Timer E Period */ -#define HRTIM_ADC1R_AD1TEPER (1 << 31) - -/** AD1TE4: ADC trigger 1 on Timer E Compare 4 */ -#define HRTIM_ADC1R_AD1TEC4 (1 << 30) - -/** AD1TE3: ADC trigger 1 on Timer E Compare 3 */ -#define HRTIM_ADC1R_AD1TEC3 (1 << 29) - -/** AD1TE2: ADC trigger 1 on Timer E Compare 2 */ -#define HRTIM_ADC1R_AD1TEC2 (1 << 28) - -/** AD1TDPER: ADC trigger 1 on Timer D Period */ -#define HRTIM_ADC1R_AD1TDPER (1 << 27) - -/** AD1TD4: ADC trigger 1 on Timer D Compare 4 */ -#define HRTIM_ADC1R_AD1TDC4 (1 << 26) - -/** AD1TD3: ADC trigger 1 on Timer D Compare 3 */ -#define HRTIM_ADC1R_AD1TDC3 (1 << 25) - -/** AD1TD2: ADC trigger 1 on Timer D Compare 2 */ -#define HRTIM_ADC1R_AD1TDC2 (1 << 24) - -/** AD1TCPER: ADC trigger 1 on Timer C Period */ -#define HRTIM_ADC1R_AD1TCPER (1 << 23) - -/** AD1TC4: ADC trigger 1 on Timer C Compare 4 */ -#define HRTIM_ADC1R_AD1TCC4 (1 << 22) - -/** AD1TC3: ADC trigger 1 on Timer C Compare 3 */ -#define HRTIM_ADC1R_AD1TCC3 (1 << 21) - -/** AD1TC2: ADC trigger 1 on Timer C Compare 2 */ -#define HRTIM_ADC1R_AD1TCC2 (1 << 20) - -/** AD1TBRST: ADC trigger 1 on Timer B Reset and counter roll-over */ -#define HRTIM_ADC1R_AD1TBRST (1 << 19) - -/** AD1TBPER: ADC trigger 1 on Timer B Period */ -#define HRTIM_ADC1R_AD1TBPER (1 << 18) - -/** AD1TB4: ADC trigger 1 on Timer B Compare 4 */ -#define HRTIM_ADC1R_AD1TBC4 (1 << 17) - -/** AD1TB3: ADC trigger 1 on Timer B Compare 3 */ -#define HRTIM_ADC1R_AD1TBC3 (1 << 16) - -/** AD1TB2: ADC trigger 1 on Timer B Compare 2 */ -#define HRTIM_ADC1R_AD1TBC2 (1 << 15) - -/** AD1TARST: ADC trigger 1 on Timer A Reset and counter roll-over */ -#define HRTIM_ADC1R_AD1TARST (1 << 14) - -/** AD1TAPER: ADC trigger 1 on Timer A Period */ -#define HRTIM_ADC1R_AD1TAPER (1 << 13) - -/** AD1TA4: ADC trigger 1 on Timer A Compare 4 */ -#define HRTIM_ADC1R_AD1TAC4 (1 << 12) - -/** AD1TA3: ADC trigger 1 on Timer A Compare 3 */ -#define HRTIM_ADC1R_AD1TAC3 (1 << 11) - -/** AD1TA2: ADC trigger 1 on Timer A Compare 2 */ -#define HRTIM_ADC1R_AD1TAC2 (1 << 10) - -/** AD1EEV5: ADC trigger 1 on External Event 5 */ -#define HRTIM_ADC1R_AD1EEV5 (1 << 9) - -/** AD1EEV4: ADC trigger 1 on External Event 4 */ -#define HRTIM_ADC1R_AD1EEV4 (1 << 8) - -/** AD1EEV3: ADC trigger 1 on External Event 3 */ -#define HRTIM_ADC1R_AD1EEV3 (1 << 7) - -/** AD1EEV2: ADC trigger 1 on External Event 2 */ -#define HRTIM_ADC1R_AD1EEV2 (1 << 6) - -/** AD1EEV1: ADC trigger 1 on External Event 1 */ -#define HRTIM_ADC1R_AD1EEV1 (1 << 5) - -/** AD1MPER: ADC trigger 1 on Master Period */ -#define HRTIM_ADC1R_AD1MPER (1 << 4) - -/** AD1MC4: ADC trigger 1 on Master Compare 4 */ -#define HRTIM_ADC1R_AD1MC4 (1 << 3) - -/** AD1MC3: ADC trigger 1 on Master Compare 3 */ -#define HRTIM_ADC1R_AD1MC3 (1 << 2) - -/** AD1MC2: ADC trigger 1 on Master Compare 2 */ -#define HRTIM_ADC1R_AD1MC2 (1 << 1) - -/** AD1MC1: ADC trigger 1 on Master Compare 1 */ -#define HRTIM_ADC1R_AD1MC1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_adc2r_values HRTIM_ADC2R Values - * @ingroup hrtim_defines - * @{ - */ - -/** AD2TERST: ADC trigger 2 on Timer E Reset and counter roll-over */ -#define HRTIM_ADC2R_AD2TERST (1 << 31) - -/** AD2TE4: ADC trigger 2 on Timer E Compare 4 */ -#define HRTIM_ADC2R_AD2TEC4 (1 << 30) - -/** AD2TE3: ADC trigger 2 on Timer E Compare 3 */ -#define HRTIM_ADC2R_AD2TEC3 (1 << 29) - -/** AD2TE2: ADC trigger 2 on Timer E Compare 2 */ -#define HRTIM_ADC2R_AD2TEC2 (1 << 28) - -/** AD2TDRST: ADC trigger 2 on Timer D Reset and counter roll-over */ -#define HRTIM_ADC2R_AD2TDRST (1 << 27) - -/** AD2TDPER: ADC trigger 2 on Timer D Period */ -#define HRTIM_ADC2R_AD2TDPER (1 << 26) - -/** AD2TD4: ADC trigger 2 on Timer D Compare 4 */ -#define HRTIM_ADC2R_AD2TDC4 (1 << 25) - -/** AD2TD3: ADC trigger 2 on Timer D Compare 3 */ -#define HRTIM_ADC2R_AD2TDC3 (1 << 24) - -/** AD2TD2: ADC trigger 2 on Timer D Compare 2 */ -#define HRTIM_ADC2R_AD2TDC2 (1 << 23) - -/** AD2TCRST: ADC trigger 2 on Timer C Reset and counter roll-over */ -#define HRTIM_ADC2R_AD2TCRST (1 << 22) - -/** AD2TCPER: ADC trigger 2 on Timer C Period */ -#define HRTIM_ADC2R_AD2TCPER (1 << 21) - -/** AD2TC4: ADC trigger 2 on Timer C Compare 4 */ -#define HRTIM_ADC2R_AD2TCC4 (1 << 20) - -/** AD2TC3: ADC trigger 2 on Timer C Compare 3 */ -#define HRTIM_ADC2R_AD2TCC3 (1 << 19) - -/** AD2TC2: ADC trigger 2 on Timer C Compare 2 */ -#define HRTIM_ADC2R_AD2TCC2 (1 << 18) - -/** AD2TBPER: ADC trigger 2 on Timer B Period */ -#define HRTIM_ADC2R_AD2TBPER (1 << 17) - -/** AD2TB4: ADC trigger 2 on Timer B Compare 4 */ -#define HRTIM_ADC2R_AD2TBC4 (1 << 16) - -/** AD2TB3: ADC trigger 2 on Timer B Compare 3 */ -#define HRTIM_ADC2R_AD2TBC3 (1 << 15) - -/** AD2TB2: ADC trigger 2 on Timer B Compare 2 */ -#define HRTIM_ADC2R_AD2TBC2 (1 << 14) - -/** AD2TAPER: ADC trigger 2 on Timer A Period */ -#define HRTIM_ADC2R_AD2TAPER (1 << 13) - -/** AD2TA4: ADC trigger 2 on Timer A Compare 4 */ -#define HRTIM_ADC2R_AD2TAC4 (1 << 12) - -/** AD2TA3: ADC trigger 2 on Timer A Compare 3 */ -#define HRTIM_ADC2R_AD2TAC3 (1 << 11) - -/** AD2TA2: ADC trigger 2 on Timer A Compare 2 */ -#define HRTIM_ADC2R_AD2TAC2 (1 << 10) - -/** AD2EEV10: ADC trigger 2 on External Event 10 */ -#define HRTIM_ADC2R_AD2EEV10 (1 << 9) - -/** AD2EEV9: ADC trigger 2 on External Event 9 */ -#define HRTIM_ADC2R_AD2EEV9 (1 << 8) - -/** AD2EEV8: ADC trigger 2 on External Event 8 */ -#define HRTIM_ADC2R_AD2EEV8 (1 << 7) - -/** AD2EEV7: ADC trigger 2 on External Event 7 */ -#define HRTIM_ADC2R_AD2EEV7 (1 << 6) - -/** AD2EEV6: ADC trigger 2 on External Event 6 */ -#define HRTIM_ADC2R_AD2EEV6 (1 << 5) - -/** AD2MPER: ADC trigger 2 on Master Period */ -#define HRTIM_ADC2R_AD2MPER (1 << 4) - -/** AD2MC4: ADC trigger 2 on Master Compare 4 */ -#define HRTIM_ADC2R_AD2MC4 (1 << 3) - -/** AD2MC3: ADC trigger 2 on Master Compare 3 */ -#define HRTIM_ADC2R_AD2MC3 (1 << 2) - -/** AD2MC2: ADC trigger 2 on Master Compare 2 */ -#define HRTIM_ADC2R_AD2MC2 (1 << 1) - -/** AD2MC1: ADC trigger 2 on Master Compare 1 */ -#define HRTIM_ADC2R_AD2MC1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_adc3r_values HRTIM_ADC3R Values - * @ingroup hrtim_defines - * @{ - */ - -/** AD1TEPER: ADC trigger 1 on Timer E Period */ -#define HRTIM_ADC3R_AD3TEPER (1 << 31) - -/** AD3TE4: ADC trigger 1 on Timer E Compare 4 */ -#define HRTIM_ADC3R_AD3TEC4 (1 << 30) - -/** AD3TE3: ADC trigger 1 on Timer E Compare 3 */ -#define HRTIM_ADC3R_AD3TEC3 (1 << 29) - -/** AD3TE2: ADC trigger 1 on Timer E Compare 2 */ -#define HRTIM_ADC3R_AD3TEC2 (1 << 28) - -/** AD3TDPER: ADC trigger 1 on Timer D Period */ -#define HRTIM_ADC3R_AD3TDPER (1 << 27) - -/** AD3TD4: ADC trigger 1 on Timer D Compare 4 */ -#define HRTIM_ADC3R_AD3TDC4 (1 << 26) - -/** AD3TD3: ADC trigger 1 on Timer D Compare 3 */ -#define HRTIM_ADC3R_AD3TDC3 (1 << 25) - -/** AD3TD2: ADC trigger 1 on Timer D Compare 2 */ -#define HRTIM_ADC3R_AD3TDC2 (1 << 24) - -/** AD3TCPER: ADC trigger 1 on Timer C Period */ -#define HRTIM_ADC3R_AD3TCPER (1 << 23) - -/** AD3TC4: ADC trigger 1 on Timer C Compare 4 */ -#define HRTIM_ADC3R_AD3TCC4 (1 << 22) - -/** AD3TC3: ADC trigger 1 on Timer C Compare 3 */ -#define HRTIM_ADC3R_AD3TCC3 (1 << 21) - -/** AD3TC2: ADC trigger 1 on Timer C Compare 2 */ -#define HRTIM_ADC3R_AD3TCC2 (1 << 20) - -/** AD3TBRST: ADC trigger 1 on Timer B Reset and counter roll-over */ -#define HRTIM_ADC3R_AD3TBRST (1 << 19) - -/** AD3TBPER: ADC trigger 1 on Timer B Period */ -#define HRTIM_ADC3R_AD3TBPER (1 << 18) - -/** AD3TB4: ADC trigger 1 on Timer B Compare 4 */ -#define HRTIM_ADC3R_AD3TBC4 (1 << 17) - -/** AD3TB3: ADC trigger 1 on Timer B Compare 3 */ -#define HRTIM_ADC3R_AD3TBC3 (1 << 16) - -/** AD3TB2: ADC trigger 1 on Timer B Compare 2 */ -#define HRTIM_ADC3R_AD3TBC2 (1 << 15) - -/** AD3TARST: ADC trigger 1 on Timer A Reset and counter roll-over */ -#define HRTIM_ADC3R_AD3TARST (1 << 14) - -/** AD3TAPER: ADC trigger 1 on Timer A Period */ -#define HRTIM_ADC3R_AD3TAPER (1 << 13) - -/** AD3TA4: ADC trigger 1 on Timer A Compare 4 */ -#define HRTIM_ADC3R_AD3TAC4 (1 << 12) - -/** AD3TA3: ADC trigger 1 on Timer A Compare 3 */ -#define HRTIM_ADC3R_AD3TAC3 (1 << 11) - -/** AD3TA2: ADC trigger 1 on Timer A Compare 2 */ -#define HRTIM_ADC3R_AD3TAC2 (1 << 10) - -/** AD3EEV5: ADC trigger 3 on External Event 5 */ -#define HRTIM_ADC3R_AD3EEV5 (1 << 9) - -/** AD3EEV4: ADC trigger 3 on External Event 4 */ -#define HRTIM_ADC3R_AD3EEV4 (1 << 8) - -/** AD3EEV3: ADC trigger 3 on External Event 3 */ -#define HRTIM_ADC3R_AD3EEV3 (1 << 7) - -/** AD3EEV2: ADC trigger 3 on External Event 2 */ -#define HRTIM_ADC3R_AD3EEV2 (1 << 6) - -/** AD3EEV1: ADC trigger 3 on External Event 1 */ -#define HRTIM_ADC3R_AD3EEV1 (1 << 5) - -/** AD3MPER: ADC trigger 3 on Master Period */ -#define HRTIM_ADC3R_AD3MPER (1 << 4) - -/** AD3MC4: ADC trigger 3 on Master Compare 4 */ -#define HRTIM_ADC3R_AD3MC4 (1 << 3) - -/** AD3MC3: ADC trigger 3 on Master Compare 3 */ -#define HRTIM_ADC3R_AD3MC3 (1 << 2) - -/** AD3MC2: ADC trigger 3 on Master Compare 2 */ -#define HRTIM_ADC3R_AD3MC2 (1 << 1) - -/** AD3MC1: ADC trigger 3 on Master Compare 1 */ -#define HRTIM_ADC3R_AD3MC1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_adc4r_values HRTIM_ADC4R Values - * @ingroup hrtim_defines - * @{ - */ - -/** AD4TERST: ADC trigger 2 on Timer E Reset and counter roll-over */ -#define HRTIM_ADC4R_AD4TERST (1 << 31) - -/** AD4TE4: ADC trigger 2 on Timer E Compare 4 */ -#define HRTIM_ADC4R_AD4TEC4 (1 << 30) - -/** AD4TE3: ADC trigger 2 on Timer E Compare 3 */ -#define HRTIM_ADC4R_AD4TEC3 (1 << 29) - -/** AD4TE2: ADC trigger 2 on Timer E Compare 2 */ -#define HRTIM_ADC4R_AD4TEC2 (1 << 28) - -/** AD4TDRST: ADC trigger 2 on Timer D Reset and counter roll-over */ -#define HRTIM_ADC4R_AD4TDRST (1 << 27) - -/** AD4TDPER: ADC trigger 2 on Timer D Period */ -#define HRTIM_ADC4R_AD4TDPER (1 << 26) - -/** AD4TD4: ADC trigger 2 on Timer D Compare 4 */ -#define HRTIM_ADC4R_AD4TDC4 (1 << 25) - -/** AD4TD3: ADC trigger 2 on Timer D Compare 3 */ -#define HRTIM_ADC4R_AD4TDC3 (1 << 24) - -/** AD4TD2: ADC trigger 2 on Timer D Compare 2 */ -#define HRTIM_ADC4R_AD4TDC2 (1 << 23) - -/** AD4TCRST: ADC trigger 2 on Timer C Reset and counter roll-over */ -#define HRTIM_ADC4R_AD4TCRST (1 << 22) - -/** AD4TCPER: ADC trigger 2 on Timer C Period */ -#define HRTIM_ADC4R_AD4TCPER (1 << 21) - -/** AD4TC4: ADC trigger 2 on Timer C Compare 4 */ -#define HRTIM_ADC4R_AD4TCC4 (1 << 20) - -/** AD4TC3: ADC trigger 2 on Timer C Compare 3 */ -#define HRTIM_ADC4R_AD4TCC3 (1 << 19) - -/** AD4TC2: ADC trigger 2 on Timer C Compare 2 */ -#define HRTIM_ADC4R_AD4TCC2 (1 << 18) - -/** AD4TBPER: ADC trigger 2 on Timer B Period */ -#define HRTIM_ADC4R_AD4TBPER (1 << 17) - -/** AD4TB4: ADC trigger 2 on Timer B Compare 4 */ -#define HRTIM_ADC4R_AD4TBC4 (1 << 16) - -/** AD4TB3: ADC trigger 2 on Timer B Compare 3 */ -#define HRTIM_ADC4R_AD4TBC3 (1 << 15) - -/** AD4TB2: ADC trigger 2 on Timer B Compare 2 */ -#define HRTIM_ADC4R_AD4TBC2 (1 << 14) - -/** AD4TAPER: ADC trigger 2 on Timer A Period */ -#define HRTIM_ADC4R_AD4TAPER (1 << 13) - -/** AD4TA4: ADC trigger 2 on Timer A Compare 4 */ -#define HRTIM_ADC4R_AD4TAC4 (1 << 12) - -/** AD4TA3: ADC trigger 2 on Timer A Compare 3 */ -#define HRTIM_ADC4R_AD4TAC3 (1 << 11) - -/** AD4TA2: ADC trigger 2 on Timer A Compare 2 */ -#define HRTIM_ADC4R_AD4TAC2 (1 << 10) - -/** AD4EEV10: ADC trigger 4 on External Event 10 */ -#define HRTIM_ADC4R_AD4EEV10 (1 << 9) - -/** AD4EEV9: ADC trigger 4 on External Event 9 */ -#define HRTIM_ADC4R_AD4EEV9 (1 << 8) - -/** AD4EEV8: ADC trigger 4 on External Event 8 */ -#define HRTIM_ADC4R_AD4EEV8 (1 << 7) - -/** AD4EEV7: ADC trigger 4 on External Event 7 */ -#define HRTIM_ADC4R_AD4EEV7 (1 << 6) - -/** AD4EEV6: ADC trigger 4 on External Event 6 */ -#define HRTIM_ADC4R_AD4EEV6 (1 << 5) - -/** AD4MPER: ADC trigger 4 on Master Period */ -#define HRTIM_ADC4R_AD4MPER (1 << 4) - -/** AD4MC4: ADC trigger 4 on Master Compare 4 */ -#define HRTIM_ADC4R_AD4MC4 (1 << 3) - -/** AD4MC3: ADC trigger 4 on Master Compare 3 */ -#define HRTIM_ADC4R_AD4MC3 (1 << 2) - -/** AD4MC2: ADC trigger 4 on Master Compare 2 */ -#define HRTIM_ADC4R_AD4MC2 (1 << 1) - -/** AD4MC1: ADC trigger 4 on Master Compare 1 */ -#define HRTIM_ADC4R_AD4MC1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_dllcr_values HRTIM_DLLCR Values - * @ingroup hrtim_defines - * @{ - */ - -/** CALRTE[3:2]: DLL Calibration rate */ -#define HRTIM_DLLCR_CALRTE_SHIFT 2 -#define HRTIM_DLLCR_CALRTE_MASK (0x3 << HRTIM_DLLCR_CALRTE_SHIFT) - -#define HRTIM_DLLCR_CALRTE_1048576 (0 << HRTIM_DLLCR_CALRTE_SHIFT) -#define HRTIM_DLLCR_CALRTE_131072 (1 << HRTIM_DLLCR_CALRTE_SHIFT) -#define HRTIM_DLLCR_CALRTE_16384 (2 << HRTIM_DLLCR_CALRTE_SHIFT) -#define HRTIM_DLLCR_CALRTE_2048 (3 << HRTIM_DLLCR_CALRTE_SHIFT) - -/** CALEN: DLL Calibration Enable */ -#define HRTIM_DLLCR_CALEN (1 << 1) - -/** CAL: DLL Calibration Start */ -#define HRTIM_DLLCR_CAL (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_fltinr1_values HRTIM_FLTINR1 Values - * @ingroup hrtim_defines - * @{ - */ - -/** FLTxLCK: FLTxLCK */ -#define HRTIM_FLTINR1_FLTxLCK(x) (1 << ((x) * 8 - 1)) - -/** FLTxF: FLTxF */ -#define HRTIM_FLTINR1_FLTxF_SHIFT(x) ((x) * 8 - 5) -#define HRTIM_FLTINR1_FLTxF_MASK(x) (0xf << HRTIM_FLTINR1_FLTxF_SHIFT(x)) - -/** FLTxSRC: FLTxSRC */ -#define HRTIM_FLTINR1_FLTxSRC(x) (1 << ((x) * 8 - 6)) - -/** FLTxP: FLTxP */ -#define HRTIM_FLTINR1_FLTxP(x) (1 << ((x) * 8 - 7)) - -/** FLTxE: FLTxE */ -#define HRTIM_FLTINR1_FLTxE(x) (1 << ((x) * 8 - 8)) - -/**@}*/ - -/** @defgroup hrtim_fltinr2_values HRTIM_FLTINR2 Values - * @ingroup hrtim_defines - * @{ - */ - -/** FLTSD[25:24]: FLTSD */ -#define HRTIM_FLTINR2_FLTSD_SHIFT 24 -#define HRTIM_FLTINR2_FLTSD_MASK (0x3 << HRTIM_FLTINR2_FLTSD_SHIFT) - -#define HRTIM_FLTINR2_FLTSD_DIV1 (0 << HRTIM_FLTINR2_FLTSD_SHIFT) -#define HRTIM_FLTINR2_FLTSD_DIV2 (1 << HRTIM_FLTINR2_FLTSD_SHIFT) -#define HRTIM_FLTINR2_FLTSD_DIV4 (2 << HRTIM_FLTINR2_FLTSD_SHIFT) -#define HRTIM_FLTINR2_FLTSD_DIV8 (3 << HRTIM_FLTINR2_FLTSD_SHIFT) - -/** FLT5LCK: FLT5LCK */ -#define HRTIM_FLTINR2_FLT5LCK (1 << 7) - -/** FLT5F[6:3]: FLT5F */ -#define HRTIM_FLTINR2_FLT5F_SHIFT 3 -#define HRTIM_FLTINR2_FLT5F_MASK (0xf << HRTIM_FLTINR2_FLT5F_SHIFT) - -/** FLT5SRC: FLT5SRC */ -#define HRTIM_FLTINR2_FLT5SRC (1 << 2) - -/** FLT5P: FLT5P */ -#define HRTIM_FLTINR2_FLT5P (1 << 1) - -/** FLT5E: FLT5E */ -#define HRTIM_FLTINR2_FLT5E (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_bmdupdr_values HRTIM_BDMUPDR Values - * @ingroup hrtim_defines - * @{ - */ - -/** MCMP4: MCMP4 register update enable */ -#define HRTIM_BDMUPDR_MCMP4 (1 << 9) - -/** MCMP3: MCMP3 register update enable */ -#define HRTIM_BDMUPDR_MCMP3 (1 << 8) - -/** MCMP2: MCMP2 register update enable */ -#define HRTIM_BDMUPDR_MCMP2 (1 << 7) - -/** MCMP1: MCMP1 register update enable */ -#define HRTIM_BDMUPDR_MCMP1 (1 << 6) - -/** MREP: MREP register update enable */ -#define HRTIM_BDMUPDR_MREP (1 << 5) - -/** MPER: MPER register update enable */ -#define HRTIM_BDMUPDR_MPER (1 << 4) - -/** MCNT: MCNT register update enable */ -#define HRTIM_BDMUPDR_MCNT (1 << 3) - -/** MDIER: MDIER register update enable */ -#define HRTIM_BDMUPDR_MDIER (1 << 2) - -/** MICR: MICR register update enable */ -#define HRTIM_BDMUPDR_MICR (1 << 1) - -/** MCR: MCR register update enable */ -#define HRTIM_BDMUPDR_MCR (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_bdtxupr_values HRTIM_BDTxUPR Values - * @ingroup hrtim_defines - * @{ - */ - -/** TIMxFLTR: HRTIM_FLTxR register update enable */ -#define HRTIM_BDTxUPR_TIMxFLTR (1 << 20) - -/** TIMxOUTR: HRTIM_OUTxR register update enable */ -#define HRTIM_BDTxUPR_TIMxOUTR (1 << 19) - -/** TIMxCHPR: HRTIM_CHPxR register update enable */ -#define HRTIM_BDTxUPR_TIMxCHPR (1 << 18) - -/** TIMxRSTR: HRTIM_RSTxR register update enable */ -#define HRTIM_BDTxUPR_TIMxRSTR (1 << 17) - -/** TIMxEEFR2: HRTIM_EEFxR2 register update enable */ -#define HRTIM_BDTxUPR_TIMxEEFR2 (1 << 16) - -/** TIMxEEFR1: HRTIM_EEFxR1 register update enable */ -#define HRTIM_BDTxUPR_TIMxEEFR1 (1 << 15) - -/** TIMxRST2R: HRTIM_RST2xR register update enable */ -#define HRTIM_BDTxUPR_TIMxRST2R (1 << 14) - -/** TIMxSET2R: HRTIM_SET2xR register update enable */ -#define HRTIM_BDTxUPR_TIMxSET2R (1 << 13) - -/** TIMxRST1R: HRTIM_RST1xR register update enable */ -#define HRTIM_BDTxUPR_TIMxRST1R (1 << 12) - -/** TIMxSET1R: HRTIM_SET1xR register update enable */ -#define HRTIM_BDTxUPR_TIMxSET1R (1 << 11) - -/** TIMx_DTxR: HRTIM_DTxR register update enable */ -#define HRTIM_BDTxUPR_TIMx_DTxR (1 << 10) - -/** TIMxCMP4: HRTIM_CMP4xR register update enable */ -#define HRTIM_BDTxUPR_TIMxCMP4 (1 << 9) - -/** TIMxCMP3: HRTIM_CMP3xR register update enable */ -#define HRTIM_BDTxUPR_TIMxCMP3 (1 << 8) - -/** TIMxCMP2: HRTIM_CMP2xR register update enable */ -#define HRTIM_BDTxUPR_TIMxCMP2 (1 << 7) - -/** TIMxCMP1: HRTIM_CMP1xR register update enable */ -#define HRTIM_BDTxUPR_TIMxCMP1 (1 << 6) - -/** TIMxREP: HRTIM_REPxR register update enable */ -#define HRTIM_BDTxUPR_TIMxREP (1 << 5) - -/** TIMxPER: HRTIM_PERxR register update enable */ -#define HRTIM_BDTxUPR_TIMxPER (1 << 4) - -/** TIMxCNT: HRTIM_CNTxR register update enable */ -#define HRTIM_BDTxUPR_TIMxCNT (1 << 3) - -/** TIMxDIER: HRTIM_TIMxDIER register update enable */ -#define HRTIM_BDTxUPR_TIMxDIER (1 << 2) - -/** TIMxICR: HRTIM_TIMxICR register update enable */ -#define HRTIM_BDTxUPR_TIMxICR (1 << 1) - -/** TIMxCR: HRTIM_TIMxCR register update enable */ -#define HRTIM_BDTxUPR_TIMxCR (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_mcr_values HRTIM_MCR Values - * @ingroup hrtim_defines - * @{ - */ - -/** BRSTDMA[31:30]: Burst DMA Update */ -#define HRTIM_MCR_BRSTDMA_SHIFT 30 -#define HRTIM_MCR_BRSTDMA_MASK (0x3 << HRTIM_MCR_BRSTDMA_SHIFT) - -#define HRTIM_MCR_BRSTDMA_INDEP (0 << HRTIM_MCR_BRSTDMA_SHIFT) -#define HRTIM_MCR_BRSTDMA_COMPL (1 << HRTIM_MCR_BRSTDMA_SHIFT) -#define HRTIM_MCR_BRSTDMA_ROLLOVR (2 << HRTIM_MCR_BRSTDMA_SHIFT) - -/** MREPU: Master Timer Repetition update */ -#define HRTIM_MCR_MREPU (1 << 29) - -/** PREEN: Preload enable */ -#define HRTIM_MCR_PREEN (1 << 27) - -/** DACSYNC[26:25]: AC Synchronization */ -#define HRTIM_MCR_DACSYNC_SHIFT 25 -#define HRTIM_MCR_DACSYNC_MASK (0x3 << HRTIM_MCR_DACSYNC_SHIFT) - -/** TECEN: Timer E counter enable */ -#define HRTIM_MCR_TECEN (1 << 21) - -/** TDCEN: Timer D counter enable */ -#define HRTIM_MCR_TDCEN (1 << 20) - -/** TCCEN: Timer C counter enable */ -#define HRTIM_MCR_TCCEN (1 << 19) - -/** TBCEN: Timer B counter enable */ -#define HRTIM_MCR_TBCEN (1 << 18) - -/** TACEN: Timer A counter enable */ -#define HRTIM_MCR_TACEN (1 << 17) - -/** MCEN: Master Counter enable */ -#define HRTIM_MCR_MCEN (1 << 16) - -/** SYNC_SRC[15:14]: Synchronization source */ -#define HRTIM_MCR_SYNC_SRC_SHIFT 14 -#define HRTIM_MCR_SYNC_SRC_MASK (0x3 << HRTIM_MCR_SYNC_SRC_SHIFT) - -#define HRTIM_MCR_SYNC_SRC_MSTART (0 << HRTIM_MCR_SYNC_SRC_SHIFT) -#define HRTIM_MCR_SYNC_SRC_MCMP1 (1 << HRTIM_MCR_SYNC_SRC_SHIFT) -#define HRTIM_MCR_SYNC_SRC_TIMA_START (2 << HRTIM_MCR_SYNC_SRC_SHIFT) -#define HRTIM_MCR_SYNC_SRC_TIMA_CMP1 (3 << HRTIM_MCR_SYNC_SRC_SHIFT) - -/** SYNC_OUT[13:12]: Synchronization output */ -#define HRTIM_MCR_SYNC_OUT_SHIFT 12 -#define HRTIM_MCR_SYNC_OUT_MASK (0x3 << HRTIM_MCR_SYNC_OUT_SHIFT) - -#define HRTIM_MCR_SYNC_OUT_DISABLE (0 << HRTIM_MCR_SYNC_OUT_SHIFT) -#define HRTIM_MCR_SYNC_OUT_POS (2 << HRTIM_MCR_SYNC_OUT_SHIFT) -#define HRTIM_MCR_SYNC_OUT_NEG (3 << HRTIM_MCR_SYNC_OUT_SHIFT) - -/** SYNCSTRTM: Synchronization Starts Master */ -#define HRTIM_MCR_SYNCSTRTM (1 << 11) - -/** SYNCRSTM: Synchronization Resets Master */ -#define HRTIM_MCR_SYNCRSTM (1 << 10) - -/** SYNC_IN[9:8]: ynchronization input */ -#define HRTIM_MCR_SYNC_IN_SHIFT 8 -#define HRTIM_MCR_SYNC_IN_MASK (0x3 << HRTIM_MCR_SYNC_IN_SHIFT) - -#define HRTIM_MCR_SYNC_IN_DISABLE (0 << HRTIM_MCR_SYNC_IN_SHIFT) -#define HRTIM_MCR_SYNC_IN_INT (1 << HRTIM_MCR_SYNC_IN_SHIFT) -#define HRTIM_MCR_SYNC_IN_EXT (2 << HRTIM_MCR_SYNC_IN_SHIFT) - -/** HALF: Half mode enable */ -#define HRTIM_MCR_HALF (1 << 5) - -/** RETRIG: Master Re-triggerable mode */ -#define HRTIM_MCR_RETRIG (1 << 4) - -/** CONT: Master Continuous mode */ -#define HRTIM_MCR_CONT (1 << 3) - -/** CK_PSC[2:0]: HRTIM Master Clock prescaler */ -#define HRTIM_MCR_CK_PSC_SHIFT 0 -#define HRTIM_MCR_CK_PSC_MASK (0x7 << HRTIM_MCR_CK_PSC_SHIFT) - -/**@}*/ - -/** @defgroup hrtim_misr_values HRTIM_MISR Values - * @ingroup hrtim_defines - * @{ - */ - -/** MUPD: Master Update Interrupt Flag */ -#define HRTIM_MISR_MUPD (1 << 6) - -/** SYNC: Sync Input Interrupt Flag */ -#define HRTIM_MISR_SYNC (1 << 5) - -/** MREP: Master Repetition Interrupt Flag */ -#define HRTIM_MISR_MREP (1 << 4) - -/** MCMP4: Master Compare 4 Interrupt Flag */ -#define HRTIM_MISR_MCMP4 (1 << 3) - -/** MCMP3: Master Compare 3 Interrupt Flag */ -#define HRTIM_MISR_MCMP3 (1 << 2) - -/** MCMP2: Master Compare 2 Interrupt Flag */ -#define HRTIM_MISR_MCMP2 (1 << 1) - -/** MCMP1: Master Compare 1 Interrupt Flag */ -#define HRTIM_MISR_MCMP1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_micr_values HRTIM_MICR Values - * @ingroup hrtim_defines - * @{ - */ - -/** MUPDC: Master update Interrupt flag clear */ -#define HRTIM_MICR_MUPDC (1 << 6) - -/** SYNCC: Sync Input Interrupt flag clear */ -#define HRTIM_MICR_SYNCC (1 << 5) - -/** MREPC: Repetition Interrupt flag clear */ -#define HRTIM_MICR_MREPC (1 << 4) - -/** MCMP4C: Master Compare 4 Interrupt flag clear */ -#define HRTIM_MICR_MCMP4C (1 << 3) - -/** MCMP3C: Master Compare 3 Interrupt flag clear */ -#define HRTIM_MICR_MCMP3C (1 << 2) - -/** MCMP2C: Master Compare 2 Interrupt flag clear */ -#define HRTIM_MICR_MCMP2C (1 << 1) - -/** MCMP1C: Master Compare 1 Interrupt flag clear */ -#define HRTIM_MICR_MCMP1C (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_mdier_values HRTIM_MDIER Values - * @ingroup hrtim_defines - * @{ - */ - -/** MUPDDE: Master Update DMA request Enable */ -#define HRTIM_MDIER_MUPDDE (1 << 22) - -/** SYNCDE: Sync Input DMA request Enable */ -#define HRTIM_MDIER_SYNCDE (1 << 21) - -/** MREPDE: Master Repetition DMA request Enable */ -#define HRTIM_MDIER_MREPDE (1 << 20) - -/** MCMP4DE: Master Compare 4 DMA request Enable */ -#define HRTIM_MDIER_MCMP4DE (1 << 19) - -/** MCMP3DE: Master Compare 3 DMA request Enable */ -#define HRTIM_MDIER_MCMP3DE (1 << 18) - -/** MCMP2DE: Master Compare 2 DMA request Enable */ -#define HRTIM_MDIER_MCMP2DE (1 << 17) - -/** MCMP1DE: Master Compare 1 DMA request Enable */ -#define HRTIM_MDIER_MCMP1DE (1 << 16) - -/** MUPDIE: Master Update Interrupt Enable */ -#define HRTIM_MDIER_MUPDIE (1 << 6) - -/** SYNCIE: Sync Input Interrupt Enable */ -#define HRTIM_MDIER_SYNCIE (1 << 5) - -/** MREPIE: Master Repetition Interrupt Enable */ -#define HRTIM_MDIER_MREPIE (1 << 4) - -/** MCMP4IE: Master Compare 4 Interrupt Enable */ -#define HRTIM_MDIER_MCMP4IE (1 << 3) - -/** MCMP3IE: Master Compare 3 Interrupt Enable */ -#define HRTIM_MDIER_MCMP3IE (1 << 2) - -/** MCMP2IE: Master Compare 2 Interrupt Enable */ -#define HRTIM_MDIER_MCMP2IE (1 << 1) - -/** MCMP1IE: Master Compare 1 Interrupt Enable */ -#define HRTIM_MDIER_MCMP1IE (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxcr_values HRTIM_TIMxCR Values - * @ingroup hrtim_defines - * @{ - */ - -/** UPDGAT[31:28]: Update Gating */ -#define HRTIM_TIMx_CR_UPDGAT_SHIFT 28 -#define HRTIM_TIMx_CR_UPDGAT_MASK (0xf << HRTIM_TIMx_CR_UPDGAT_SHIFT) - -#define HRTIM_TIMx_CR_UPDGAT_INDEP (0 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_DMA (1 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_DMA_POST (2 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN1 (3 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN2 (4 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN3 (5 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN1_POST (6 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN2_POST (7 << HRTIM_TIMx_CR_UPDGAT_SHIFT) -#define HRTIM_TIMx_CR_UPDGAT_IN3_POST (8 << HRTIM_TIMx_CR_UPDGAT_SHIFT) - -/** PREEN: Preload enable */ -#define HRTIM_TIMx_CR_PREEN (1 << 27) - -/** DACSYNC[26:25]: DAC Synchronization */ -#define HRTIM_TIMx_CR_DACSYNC_SHIFT 25 -#define HRTIM_TIMx_CR_DACSYNC_MASK (0x3 << HRTIM_TIMx_CR_DACSYNC_SHIFT) - -#define HRTIM_TIMx_CR_DACSYNC_NONE (0 << HRTIM_TIMx_CR_DACSYNC_SHIFT) -#define HRTIM_TIMx_CR_DACSYNC_1 (1 << HRTIM_TIMx_CR_DACSYNC_SHIFT) -#define HRTIM_TIMx_CR_DACSYNC_2 (2 << HRTIM_TIMx_CR_DACSYNC_SHIFT) -#define HRTIM_TIMx_CR_DACSYNC_3 (3 << HRTIM_TIMx_CR_DACSYNC_SHIFT) - -/** MSTU: Master Timer update */ -#define HRTIM_TIMx_CR_MSTU (1 << 24) - -/** TEU: Timer E update */ -#define HRTIM_TIMx_CR_TEU (1 << 23) - -/** TDU: Timer D update */ -#define HRTIM_TIMx_CR_TDU (1 << 22) - -/** TCU: Timer C update */ -#define HRTIM_TIMx_CR_TCU (1 << 21) - -/** TBU: Timer B update */ -#define HRTIM_TIMx_CR_TBU (1 << 20) - -/** TxRSTU: Timer x reset update */ -#define HRTIM_TIMx_CR_TxRSTU (1 << 18) - -/** TxREPU: Timer x Repetition update */ -#define HRTIM_TIMx_CR_TxREPU (1 << 17) - -/** DELCMP4[15:14]: CMP4 auto-delayed mode */ -#define HRTIM_TIMx_CR_DELCMP4_SHIFT 14 -#define HRTIM_TIMx_CR_DELCMP4_MASK (0x3 << HRTIM_TIMx_CR_DELCMP4_SHIFT) - -#define HRTIM_TIMx_CR_DELCMP4_ALWAYS (0 << HRTIM_TIMx_CR_DELCMP4_SHIFT) -#define HRTIM_TIMx_CR_DELCMP4_CAP2 (1 << HRTIM_TIMx_CR_DELCMP4_SHIFT) -#define HRTIM_TIMx_CR_DELCMP4_CAP2_COMP1 (2 << HRTIM_TIMx_CR_DELCMP4_SHIFT) -#define HRTIM_TIMx_CR_DELCMP4_CAP2_COMP3 (3 << HRTIM_TIMx_CR_DELCMP4_SHIFT) - -/** DELCMP2[13:12]: CMP2 auto-delayed mode */ -#define HRTIM_TIMx_CR_DELCMP2_SHIFT 12 -#define HRTIM_TIMx_CR_DELCMP2_MASK (0x3 << HRTIM_TIMx_CR_DELCMP2_SHIFT) - -#define HRTIM_TIMx_CR_DELCMP2_ALWAYS (0x << HRTIM_TIMx_CR_DELCMP2_SHIFT) -#define HRTIM_TIMx_CR_DELCMP2_CAP1 (0x << HRTIM_TIMx_CR_DELCMP2_SHIFT) -#define HRTIM_TIMx_CR_DELCMP2_CAP1_COMP1 (0x << HRTIM_TIMx_CR_DELCMP2_SHIFT) -#define HRTIM_TIMx_CR_DELCMP2_CAP1_COMP3 (0x << HRTIM_TIMx_CR_DELCMP2_SHIFT) - -/** SYNCSTRTx: Synchronization Starts Timer x */ -#define HRTIM_TIMx_CR_SYNCSTRTx (1 << 11) - -/** SYNCRSTx: Synchronization Resets Timer x */ -#define HRTIM_TIMx_CR_SYNCRSTx (1 << 10) - -/** PSHPLL: Push-Pull mode enable */ -#define HRTIM_TIMx_CR_PSHPLL (1 << 6) - -/** HALF: Half mode enable */ -#define HRTIM_TIMx_CR_HALF (1 << 5) - -/** RETRIG: Re-triggerable mode */ -#define HRTIM_TIMx_CR_RETRIG (1 << 4) - -/** CONT: Continuous mode */ -#define HRTIM_TIMx_CR_CONT (1 << 3) - -/** CK_PSCx[2:0]: HRTIM Timer x Clock prescaler */ -#define HRTIM_TIMx_CR_CK_PSCx_SHIFT 0 -#define HRTIM_TIMx_CR_CK_PSCx_MASK (0x7 << HRTIM_TIMx_CR_CK_PSCx_SHIFT) - -/**@}*/ - -/** @defgroup hrtim_timxisr_values HRTIM_TIMxISR Values - * @ingroup hrtim_defines - * @{ - */ - -/** O2STAT: Output 2 State */ -#define HRTIM_TIMx_ISR_O2STAT (1 << 19) - -/** O1STAT: Output 1 State */ -#define HRTIM_TIMx_ISR_O1STAT (1 << 18) - -/** IPPSTAT: Idle Push Pull Status */ -#define HRTIM_TIMx_ISR_IPPSTAT (1 << 17) - -/** CPPSTAT: Current Push Pull Status */ -#define HRTIM_TIMx_ISR_CPPSTAT (1 << 16) - -/** DLYPRT: Delayed Protection Flag */ -#define HRTIM_TIMx_ISR_DLYPRT (1 << 14) - -/** RST: Reset Interrupt Flag */ -#define HRTIM_TIMx_ISR_RST (1 << 13) - -/** RSTx2: Output 2 Reset Interrupt Flag */ -#define HRTIM_TIMx_ISR_RSTx2 (1 << 12) - -/** SETx2: Output 2 Set Interrupt Flag */ -#define HRTIM_TIMx_ISR_SETx2 (1 << 11) - -/** RSTx1: Output 1 Reset Interrupt Flag */ -#define HRTIM_TIMx_ISR_RSTx1 (1 << 10) - -/** SETx1: Output 1 Set Interrupt Flag */ -#define HRTIM_TIMx_ISR_SETx1 (1 << 9) - -/** CPT2: Capture2 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CPT2 (1 << 8) - -/** CPT1: Capture1 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CPT1 (1 << 7) - -/** UPD: Update Interrupt Flag */ -#define HRTIM_TIMx_ISR_UPD (1 << 6) - -/** REP: Repetition Interrupt Flag */ -#define HRTIM_TIMx_ISR_REP (1 << 4) - -/** CMP4: Compare 4 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CMP4 (1 << 3) - -/** CMP3: Compare 3 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CMP3 (1 << 2) - -/** CMP2: Compare 2 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CMP2 (1 << 1) - -/** CMP1: Compare 1 Interrupt Flag */ -#define HRTIM_TIMx_ISR_CMP1 (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxicr_values HRTIM_TIMxICR Values - * @ingroup hrtim_defines - * @{ - */ - -/** DLYPRTC: Delayed Protection Flag Clear */ -#define HRTIM_TIMx_ICR_DLYPRTC (1 << 14) - -/** RSTC: Reset Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_RSTC (1 << 13) - -/** RSTx2C: Output 2 Reset flag Clear */ -#define HRTIM_TIMx_ICR_RSTx2C (1 << 12) - -/** SET2xC: Output 2 Set flag Clear */ -#define HRTIM_TIMx_ICR_SET2xC (1 << 11) - -/** RSTx1C: Output 1 Reset flag Clear */ -#define HRTIM_TIMx_ICR_RSTx1C (1 << 10) - -/** SET1xC: Output 1 Set flag Clear */ -#define HRTIM_TIMx_ICR_SET1xC (1 << 9) - -/** CPT2C: Capture2 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CPT2C (1 << 8) - -/** CPT1C: Capture1 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CPT1C (1 << 7) - -/** UPDC: Update Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_UPDC (1 << 6) - -/** REPC: Repetition Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_REPC (1 << 4) - -/** CMP4C: Compare 4 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CMP4C (1 << 3) - -/** CMP3C: Compare 3 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CMP3C (1 << 2) - -/** CMP2C: Compare 2 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CMP2C (1 << 1) - -/** CMP1C: Compare 1 Interrupt flag Clear */ -#define HRTIM_TIMx_ICR_CMP1C (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxdier_values HRTIM_TIMxDIER Values - * @ingroup hrtim_defines - * @{ - */ - -/** DLYPRTDE: Delay Protection DMA request Enable */ -#define HRTIM_TIMx_DIER_DLYPRTDE (1 << 30) - -/** RSTDE: Reset/roll-over DMA request Enable */ -#define HRTIM_TIMx_DIER_RSTDE (1 << 29) - -/** RSTx2DE: Output 2 Reset DMA request Enable */ -#define HRTIM_TIMx_DIER_RSTx2DE (1 << 28) - -/** SETx2DE: Output 2 Set DMA request Enable */ -#define HRTIM_TIMx_DIER_SETx2DE (1 << 27) - -/** RSTx1DE: Output 1 Reset DMA request Enable */ -#define HRTIM_TIMx_DIER_RSTx1DE (1 << 26) - -/** SET1xDE: Output 1 Set DMA request Enable*/ -#define HRTIM_TIMx_DIER_SET1xDE (1 << 25) - -/** CPT2DE: Capture 2 DMA request Enable */ -#define HRTIM_TIMx_DIER_CPT2DE (1 << 24) - -/** CPT1DE: Capture 1 DMA request Enable */ -#define HRTIM_TIMx_DIER_CPT1DE (1 << 23) - -/** UPDDE: Update DMA request Enable */ -#define HRTIM_TIMx_DIER_UPDDE (1 << 22) - -/** REPDE: Repetition DMA request Enable */ -#define HRTIM_TIMx_DIER_REPDE (1 << 20) - -/** CMP4DE: Compare 4 DMA request Enable */ -#define HRTIM_TIMx_DIER_CMP4DE (1 << 19) - -/** CMP3DE: Compare 3 DMA request Enable */ -#define HRTIM_TIMx_DIER_CMP3DE (1 << 18) - -/** CMP2DE: Compare 2 DMA request Enable */ -#define HRTIM_TIMx_DIER_CMP2DE (1 << 17) - -/** CMP1DE: Compare 1 DMA request Enable */ -#define HRTIM_TIMx_DIER_CMP1DE (1 << 16) - -/** DLYPRTIE: Delay Protection Interrupt Enable */ -#define HRTIM_TIMx_DIER_DLYPRTIE (1 << 14) - -/** RSTIE: Reset/roll-over Interrupt Enable */ -#define HRTIM_TIMx_DIER_RSTIE (1 << 13) - -/** RSTx2IE: Output 2 Reset Interrupt Enable */ -#define HRTIM_TIMx_DIER_RSTx2IE (1 << 12) - -/** SETx2IE: Output 2 Set Interrupt Enable */ -#define HRTIM_TIMx_DIER_SETx2IE (1 << 11) - -/** RSTx1IE: Output 1 Reset Interrupt Enable */ -#define HRTIM_TIMx_DIER_RSTx1IE (1 << 10) - -/** SET1xIE: Output 1 Set Interrupt Enable */ -#define HRTIM_TIMx_DIER_SET1xIE (1 << 9) - -/** CPT2IE: Capture 2 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CPT2IE (1 << 8) - -/** CPT1IE: Capture 1 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CPT1IE (1 << 7) - -/** UPDIE: Update Interrupt Enable */ -#define HRTIM_TIMx_DIER_UPDIE (1 << 6) - -/** REPIE: Repetition Interrupt Enable */ -#define HRTIM_TIMx_DIER_REPIE (1 << 4) - -/** CMP4IE: Compare 4 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CMP4IE (1 << 3) - -/** CMP3IE: Compare 3 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CMP3IE (1 << 2) - -/** CMP2IE: Compare 2 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CMP2IE (1 << 1) - -/** CMP1IE: Compare 1 Interrupt Enable */ -#define HRTIM_TIMx_DIER_CMP1IE (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxcmp1c_values HRTIM_TIMxCMP1C Values - * @ingroup hrtim_defines - * @{ - */ - -/** REPx[23:16]: Timerx Repetition value (aliased from HRTIM_REPx register) */ -#define HRTIM_TIMx_CMP1C_REPx_SHIFT 16 -#define HRTIM_TIMx_CMP1C_REPx_MASK (0xff << HRTIM_TIMx_CMP1C_REPx_SHIFT) - -/** CMP1x[15:0]: Timerx Compare 1 value */ -#define HRTIM_TIMx_CMP1C_CMP1x_SHIFT 0 -#define HRTIM_TIMx_CMP1C_CMP1x_MASK (0xffff << HRTIM_TIMx_CMP1C_CMP1x_SHIFT) - -/**@}*/ - -/** @defgroup hrtim_timxdt_values HRTIM_TIMxDT Values - * @ingroup hrtim_defines - * @{ - */ - -/** DTFLKx: Deadtime Falling Lock */ -#define HRTIM_TIMx_DT_DTFLKx (1 << 31) - -/** DTFSLKx: Deadtime Falling Sign Lock */ -#define HRTIM_TIMx_DT_DTFSLKx (1 << 30) - -/** SDTFx: Sign Deadtime Falling value */ -#define HRTIM_TIMx_DT_SDTFx (1 << 25) - -/** DTFx[24:16]: Deadtime Falling value */ -#define HRTIM_TIMx_DT_DTFx_SHIFT 16 -#define HRTIM_TIMx_DT_DTFx_MASK (0x1ff << HRTIM_TIMx_DT_DTFx_SHIFT) - -/** DTRLKx: Deadtime Rising Lock */ -#define HRTIM_TIMx_DT_DTRLKx (1 << 15) - -/** DTRSLKx: Deadtime Rising Sign Lock */ -#define HRTIM_TIMx_DT_DTRSLKx (1 << 14) - -/** DTPRSC[12:10]: Deadtime Prescaler */ -#define HRTIM_TIMx_DT_DTPRSC_SHIFT 10 -#define HRTIM_TIMx_DT_DTPRSC_MASK (0x7 << HRTIM_TIMx_DT_DTPRSC_SHIFT) - -/** SDTRx: Sign Deadtime Rising value */ -#define HRTIM_TIMx_DT_SDTRx (1 << 9) - -/** DTRx[8:0]: Deadtime Rising value */ -#define HRTIM_TIMx_DT_DTRx_SHIFT 0 -#define HRTIM_TIMx_DT_DTRx_MASK (0x1ff << HRTIM_TIMx_DT_DTRx_SHIFT) - -/**@}*/ - -/** @defgroup hrtim_timxsety_values HRTIM_TIMxSETy Values - * @ingroup hrtim_defines - * @{ - */ - -/** UPDATE: Registers update (transfer preload to active) */ -#define HRTIM_TIMx_SETy_UPDATE (1 << 31) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMx_SETy_EXTEVNT10 (1 << 30) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMx_SETy_EXTEVNT9 (1 << 29) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMx_SETy_EXTEVNT8 (1 << 28) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMx_SETy_EXTEVNT7 (1 << 27) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMx_SETy_EXTEVNT6 (1 << 26) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMx_SETy_EXTEVNT5 (1 << 25) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMx_SETy_EXTEVNT4 (1 << 24) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMx_SETy_EXTEVNT3 (1 << 23) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMx_SETy_EXTEVNT2 (1 << 22) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMx_SETy_EXTEVNT1 (1 << 21) - -/** TIMEVNT9: Timer Event 9 */ -#define HRTIM_TIMx_SETy_TIMEVNT9 (1 << 20) - -/** TIMEVNT8: Timer Event 8 */ -#define HRTIM_TIMx_SETy_TIMEVNT8 (1 << 19) - -/** TIMEVNT7: Timer Event 7 */ -#define HRTIM_TIMx_SETy_TIMEVNT7 (1 << 18) - -/** TIMEVNT6: Timer Event 6 */ -#define HRTIM_TIMx_SETy_TIMEVNT6 (1 << 17) - -/** TIMEVNT5: Timer Event 5 */ -#define HRTIM_TIMx_SETy_TIMEVNT5 (1 << 16) - -/** TIMEVNT4: Timer Event 4 */ -#define HRTIM_TIMx_SETy_TIMEVNT4 (1 << 15) - -/** TIMEVNT3: Timer Event 3 */ -#define HRTIM_TIMx_SETy_TIMEVNT3 (1 << 14) - -/** TIMEVNT2: Timer Event 2 */ -#define HRTIM_TIMx_SETy_TIMEVNT2 (1 << 13) - -/** TIMEVNT1: Timer Event 1 */ -#define HRTIM_TIMx_SETy_TIMEVNT1 (1 << 12) - -/** MSTCMP4: Master Compare 4 */ -#define HRTIM_TIMx_SETy_MSTCMP4 (1 << 11) - -/** MSTCMP3: Master Compare 3 */ -#define HRTIM_TIMx_SETy_MSTCMP3 (1 << 10) - -/** MSTCMP2: Master Compare 2 */ -#define HRTIM_TIMx_SETy_MSTCMP2 (1 << 9) - -/** MSTCMP1: Master Compare 1 */ -#define HRTIM_TIMx_SETy_MSTCMP1 (1 << 8) - -/** MSTPER: Master Period */ -#define HRTIM_TIMx_SETy_MSTPER (1 << 7) - -/** CMP4: Timer x compare 4 */ -#define HRTIM_TIMx_SETy_CMP4 (1 << 6) - -/** CMP3: Timer x compare 3 */ -#define HRTIM_TIMx_SETy_CMP3 (1 << 5) - -/** CMP2: Timer x compare 2 */ -#define HRTIM_TIMx_SETy_CMP2 (1 << 4) - -/** CMP1: Timer x compare 1 */ -#define HRTIM_TIMx_SETy_CMP1 (1 << 3) - -/** PER: Timer x Period */ -#define HRTIM_TIMx_SETy_PER (1 << 2) - -/** RESYNC: Timer x resynchronizaton */ -#define HRTIM_TIMx_SETy_RESYNC (1 << 1) - -/** SST: Software Set trigger */ -#define HRTIM_TIMx_SETy_SST (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxrsty_values HRTIM_TIMxRSTy Values - * @ingroup hrtim_defines - * @{ - */ - -/** UPDATE: Registers update (transfer preload to active) */ -#define HRTIM_TIMx_RSTy_UPDATE (1 << 31) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMx_RSTy_EXTEVNT10 (1 << 30) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMx_RSTy_EXTEVNT9 (1 << 29) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMx_RSTy_EXTEVNT8 (1 << 28) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMx_RSTy_EXTEVNT7 (1 << 27) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMx_RSTy_EXTEVNT6 (1 << 26) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMx_RSTy_EXTEVNT5 (1 << 25) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMx_RSTy_EXTEVNT4 (1 << 24) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMx_RSTy_EXTEVNT3 (1 << 23) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMx_RSTy_EXTEVNT2 (1 << 22) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMx_RSTy_EXTEVNT1 (1 << 21) - -/** TIMEVNT9: Timer Event 9 */ -#define HRTIM_TIMx_RSTy_TIMEVNT9 (1 << 20) - -/** TIMEVNT8: Timer Event 8 */ -#define HRTIM_TIMx_RSTy_TIMEVNT8 (1 << 19) - -/** TIMEVNT7: Timer Event 7 */ -#define HRTIM_TIMx_RSTy_TIMEVNT7 (1 << 18) - -/** TIMEVNT6: Timer Event 6 */ -#define HRTIM_TIMx_RSTy_TIMEVNT6 (1 << 17) - -/** TIMEVNT5: Timer Event 5 */ -#define HRTIM_TIMx_RSTy_TIMEVNT5 (1 << 16) - -/** TIMEVNT4: Timer Event 4 */ -#define HRTIM_TIMx_RSTy_TIMEVNT4 (1 << 15) - -/** TIMEVNT3: Timer Event 3 */ -#define HRTIM_TIMx_RSTy_TIMEVNT3 (1 << 14) - -/** TIMEVNT2: Timer Event 2 */ -#define HRTIM_TIMx_RSTy_TIMEVNT2 (1 << 13) - -/** TIMEVNT1: Timer Event 1 */ -#define HRTIM_TIMx_RSTy_TIMEVNT1 (1 << 12) - -/** MSTCMP4: Master Compare 4 */ -#define HRTIM_TIMx_RSTy_MSTCMP4 (1 << 11) - -/** MSTCMP3: Master Compare 3 */ -#define HRTIM_TIMx_RSTy_MSTCMP3 (1 << 10) - -/** MSTCMP2: Master Compare 2 */ -#define HRTIM_TIMx_RSTy_MSTCMP2 (1 << 9) - -/** MSTCMP1: Master Compare 1 */ -#define HRTIM_TIMx_RSTy_MSTCMP1 (1 << 8) - -/** MSTPER: Master Period */ -#define HRTIM_TIMx_RSTy_MSTPER (1 << 7) - -/** CMP4: Timer x compare 4 */ -#define HRTIM_TIMx_RSTy_CMP4 (1 << 6) - -/** CMP3: Timer x compare 3 */ -#define HRTIM_TIMx_RSTy_CMP3 (1 << 5) - -/** CMP2: Timer x compare 2 */ -#define HRTIM_TIMx_RSTy_CMP2 (1 << 4) - -/** CMP1: Timer x compare 1 */ -#define HRTIM_TIMx_RSTy_CMP1 (1 << 3) - -/** PER: Timer x Period */ -#define HRTIM_TIMx_RSTy_PER (1 << 2) - -/** RESYNC: Timer x resynchronizaton */ -#define HRTIM_TIMx_RSTy_RESYNC (1 << 1) - -/** SST: Software Reset trigger */ -#define HRTIM_TIMx_RSTy_SRT (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxeef1_values HRTIM_TIMxEEF1 Values - * @ingroup hrtim_defines - * @{ - */ - -/** EExFLTR:25]: External Event x filter */ -#define HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x) ((x) * 6 - 5) -#define HRTIM_TIMx_EEF1_EExFLTR_MASK(x) (0xf << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) - -#define HRTIM_TIMx_EEF1_EExFLTR_NONE(x) ( 0 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_CMP1(x) ( 1 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_CMP2(x) ( 2 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_CMP3(x) ( 3 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_CMP4(x) ( 4 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR1(x) ( 5 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR2(x) ( 6 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR3(x) ( 7 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR4(x) ( 8 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR5(x) ( 9 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR6(x) (10 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR7(x) (11 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMFLTR8(x) (12 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_WND_CMP2(x) (13 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_WND_CMP3(x) (14 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF1_EExFLTR_TIMWIN(x) (15 << HRTIM_TIMx_EEF1_EExFLTR_SHIFT(x)) - -/** EExLTCH: External Event x latch */ -#define HRTIM_TIMx_EEF1_EExLTCH (1 << ((x) * 6 - 6)) - -/**@}*/ - -/** @defgroup hrtim_timxeef2_values HRTIM_TIMxEEF2 Values - * @ingroup hrtim_defines - * @{ - */ - -/** EExFLTR:25]: External Event x filter */ -#define HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x) (((x) - 6) * 6 + 1) -#define HRTIM_TIMx_EEF2_EExFLTR_MASK(x) (0xf << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) - -#define HRTIM_TIMx_EEF2_EExFLTR_NONE(x) ( 0 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_CMP1(x) ( 1 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_CMP2(x) ( 2 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_CMP3(x) ( 3 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_CMP4(x) ( 4 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR1(x) ( 5 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR2(x) ( 6 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR3(x) ( 7 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR4(x) ( 8 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR5(x) ( 9 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR6(x) (10 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR7(x) (11 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMFLTR8(x) (12 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_WND_CMP2(x) (13 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_WND_CMP3(x) (14 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) -#define HRTIM_TIMx_EEF2_EExFLTR_TIMWIN(x) (15 << HRTIM_TIMx_EEF2_EExFLTR_SHIFT(x)) - -/** EExLTCH: External Event x latch */ -#define HRTIM_TIMx_EEF2_EExLTCH (1 << (((x) - 6) * 6)) - -/**@}*/ - -/** @defgroup hrtim_timarst_values HRTIM_TIMA_RST Values - * @ingroup hrtim_defines - * Only bits 30:19 differ between TIMx_RST registers. - * @sa hrtim_timarst_values - * @sa hrtim_timbrst_values - * @sa hrtim_timcrst_values - * @sa hrtim_timdrst_values - * @sa hrtim_timerst_values - * @{ - */ - -/** TIMECMP4: Timer E Compare 4 */ -#define HRTIM_TIMA_RST_TIMECMP4 (1 << 30) - -/** TIMECMP2: Timer E Compare 2 */ -#define HRTIM_TIMA_RST_TIMECMP2 (1 << 29) - -/** TIMECMP1: Timer E Compare 1 */ -#define HRTIM_TIMA_RST_TIMECMP1 (1 << 28) - -/** TIMDCMP4: Timer D Compare 4 */ -#define HRTIM_TIMA_RST_TIMDCMP4 (1 << 27) - -/** TIMDCMP2: Timer D Compare 2 */ -#define HRTIM_TIMA_RST_TIMDCMP2 (1 << 26) - -/** TIMDCMP1: Timer D Compare 1 */ -#define HRTIM_TIMA_RST_TIMDCMP1 (1 << 25) - -/** TIMCCMP4: Timer C Compare 4 */ -#define HRTIM_TIMA_RST_TIMCCMP4 (1 << 24) - -/** TIMCCMP2: Timer C Compare 2 */ -#define HRTIM_TIMA_RST_TIMCCMP2 (1 << 23) - -/** TIMCCMP1: Timer C Compare 1 */ -#define HRTIM_TIMA_RST_TIMCCMP1 (1 << 22) - -/** TIMBCMP4: Timer B Compare 4 */ -#define HRTIM_TIMA_RST_TIMBCMP4 (1 << 21) - -/** TIMBCMP2: Timer B Compare 2 */ -#define HRTIM_TIMA_RST_TIMBCMP2 (1 << 20) - -/** TIMBCMP1: Timer B Compare 1 */ -#define HRTIM_TIMA_RST_TIMBCMP1 (1 << 19) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMA_RST_EXTEVNT10 (1 << 18) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMA_RST_EXTEVNT9 (1 << 17) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMA_RST_EXTEVNT8 (1 << 16) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMA_RST_EXTEVNT7 (1 << 15) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMA_RST_EXTEVNT6 (1 << 14) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMA_RST_EXTEVNT5 (1 << 13) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMA_RST_EXTEVNT4 (1 << 12) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMA_RST_EXTEVNT3 (1 << 11) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMA_RST_EXTEVNT2 (1 << 10) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMA_RST_EXTEVNT1 (1 << 9) - -/** MSTCMP4: Master compare 4 */ -#define HRTIM_TIMA_RST_MSTCMP4 (1 << 8) - -/** MSTCMP3: Master compare 3 */ -#define HRTIM_TIMA_RST_MSTCMP3 (1 << 7) - -/** MSTCMP2: Master compare 2 */ -#define HRTIM_TIMA_RST_MSTCMP2 (1 << 6) - -/** MSTCMP1: Master compare 1 */ -#define HRTIM_TIMA_RST_MSTCMP1 (1 << 5) - -/** MSTPER: Master timer Period */ -#define HRTIM_TIMA_RST_MSTPER (1 << 4) - -/** CMP4: Timer A compare 4 reset */ -#define HRTIM_TIMA_RST_CMP4 (1 << 3) - -/** CMP2: Timer A compare 2 reset */ -#define HRTIM_TIMA_RST_CMP2 (1 << 2) - -/** UPDT: Timer A Update reset */ -#define HRTIM_TIMA_RST_UPDT (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timbrst_values HRTIM_TIMB_RST Values - * @ingroup hrtim_defines - * Only bits 30:19 differ between TIMx_RST registers. - * @sa hrtim_timarst_values - * @sa hrtim_timbrst_values - * @sa hrtim_timcrst_values - * @sa hrtim_timdrst_values - * @sa hrtim_timerst_values - * @{ - */ - -/** TIMECMP4: Timer E Compare 4 */ -#define HRTIM_TIMB_RST_TIMECMP4 (1 << 30) - -/** TIMECMP2: Timer E Compare 2 */ -#define HRTIM_TIMB_RST_TIMECMP2 (1 << 29) - -/** TIMECMP1: Timer E Compare 1 */ -#define HRTIM_TIMB_RST_TIMECMP1 (1 << 28) - -/** TIMDCMP4: Timer D Compare 4 */ -#define HRTIM_TIMB_RST_TIMDCMP4 (1 << 27) - -/** TIMDCMP2: Timer D Compare 2 */ -#define HRTIM_TIMB_RST_TIMDCMP2 (1 << 26) - -/** TIMDCMP1: Timer D Compare 1 */ -#define HRTIM_TIMB_RST_TIMDCMP1 (1 << 25) - -/** TIMCCMP4: Timer C Compare 4 */ -#define HRTIM_TIMB_RST_TIMCCMP4 (1 << 24) - -/** TIMCCMP2: Timer C Compare 2 */ -#define HRTIM_TIMB_RST_TIMCCMP2 (1 << 23) - -/** TIMCCMP1: Timer C Compare 1 */ -#define HRTIM_TIMB_RST_TIMCCMP1 (1 << 22) - -/** TIMACMP4: Timer A Compare 4 */ -#define HRTIM_TIMB_RST_TIMACMP4 (1 << 21) - -/** TIMACMP2: Timer A Compare 2 */ -#define HRTIM_TIMB_RST_TIMACMP2 (1 << 20) - -/** TIMACMP1: Timer A Compare 1 */ -#define HRTIM_TIMB_RST_TIMACMP1 (1 << 19) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMB_RST_EXTEVNT10 (1 << 18) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMB_RST_EXTEVNT9 (1 << 17) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMB_RST_EXTEVNT8 (1 << 16) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMB_RST_EXTEVNT7 (1 << 15) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMB_RST_EXTEVNT6 (1 << 14) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMB_RST_EXTEVNT5 (1 << 13) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMB_RST_EXTEVNT4 (1 << 12) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMB_RST_EXTEVNT3 (1 << 11) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMB_RST_EXTEVNT2 (1 << 10) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMB_RST_EXTEVNT1 (1 << 9) - -/** MSTCMP4: Master compare 4 */ -#define HRTIM_TIMB_RST_MSTCMP4 (1 << 8) - -/** MSTCMP3: Master compare 3 */ -#define HRTIM_TIMB_RST_MSTCMP3 (1 << 7) - -/** MSTCMP2: Master compare 2 */ -#define HRTIM_TIMB_RST_MSTCMP2 (1 << 6) - -/** MSTCMP1: Master compare 1 */ -#define HRTIM_TIMB_RST_MSTCMP1 (1 << 5) - -/** MSTPER: Master timer Period */ -#define HRTIM_TIMB_RST_MSTPER (1 << 4) - -/** CMP4: Timer A compare 4 reset */ -#define HRTIM_TIMB_RST_CMP4 (1 << 3) - -/** CMP2: Timer A compare 2 reset */ -#define HRTIM_TIMB_RST_CMP2 (1 << 2) - -/** UPDT: Timer A Update reset */ -#define HRTIM_TIMB_RST_UPDT (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timcrst_values HRTIM_TIMC_RST Values - * @ingroup hrtim_defines - * Only bits 30:19 differ between TIMx_RST registers. - * @sa hrtim_timarst_values - * @sa hrtim_timbrst_values - * @sa hrtim_timcrst_values - * @sa hrtim_timdrst_values - * @sa hrtim_timerst_values - * @{ - */ - -/** TIMECMP4: Timer E Compare 4 */ -#define HRTIM_TIMC_RST_TIMECMP4 (1 << 30) - -/** TIMECMP2: Timer E Compare 2 */ -#define HRTIM_TIMC_RST_TIMECMP2 (1 << 29) - -/** TIMECMP1: Timer E Compare 1 */ -#define HRTIM_TIMC_RST_TIMECMP1 (1 << 28) - -/** TIMDCMP4: Timer D Compare 4 */ -#define HRTIM_TIMC_RST_TIMDCMP4 (1 << 27) - -/** TIMDCMP2: Timer D Compare 2 */ -#define HRTIM_TIMC_RST_TIMDCMP2 (1 << 26) - -/** TIMDCMP1: Timer D Compare 1 */ -#define HRTIM_TIMC_RST_TIMDCMP1 (1 << 25) - -/** TIMBCMP4: Timer B Compare 4 */ -#define HRTIM_TIMC_RST_TIMBCMP4 (1 << 24) - -/** TIMBCMP2: Timer B Compare 2 */ -#define HRTIM_TIMC_RST_TIMBCMP2 (1 << 23) - -/** TIMBCMP1: Timer B Compare 1 */ -#define HRTIM_TIMC_RST_TIMBCMP1 (1 << 22) - -/** TIMACMP4: Timer A Compare 4 */ -#define HRTIM_TIMC_RST_TIMACMP4 (1 << 21) - -/** TIMACMP2: Timer A Compare 2 */ -#define HRTIM_TIMC_RST_TIMACMP2 (1 << 20) - -/** TIMACMP1: Timer A Compare 1 */ -#define HRTIM_TIMC_RST_TIMACMP1 (1 << 19) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMC_RST_EXTEVNT10 (1 << 18) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMC_RST_EXTEVNT9 (1 << 17) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMC_RST_EXTEVNT8 (1 << 16) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMC_RST_EXTEVNT7 (1 << 15) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMC_RST_EXTEVNT6 (1 << 14) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMC_RST_EXTEVNT5 (1 << 13) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMC_RST_EXTEVNT4 (1 << 12) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMC_RST_EXTEVNT3 (1 << 11) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMC_RST_EXTEVNT2 (1 << 10) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMC_RST_EXTEVNT1 (1 << 9) - -/** MSTCMP4: Master compare 4 */ -#define HRTIM_TIMC_RST_MSTCMP4 (1 << 8) - -/** MSTCMP3: Master compare 3 */ -#define HRTIM_TIMC_RST_MSTCMP3 (1 << 7) - -/** MSTCMP2: Master compare 2 */ -#define HRTIM_TIMC_RST_MSTCMP2 (1 << 6) - -/** MSTCMP1: Master compare 1 */ -#define HRTIM_TIMC_RST_MSTCMP1 (1 << 5) - -/** MSTPER: Master timer Period */ -#define HRTIM_TIMC_RST_MSTPER (1 << 4) - -/** CMP4: Timer A compare 4 reset */ -#define HRTIM_TIMC_RST_CMP4 (1 << 3) - -/** CMP2: Timer A compare 2 reset */ -#define HRTIM_TIMC_RST_CMP2 (1 << 2) - -/** UPDT: Timer A Update reset */ -#define HRTIM_TIMC_RST_UPDT (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timdrst_values HRTIM_TIMD_RST Values - * @ingroup hrtim_defines - * Only bits 30:19 differ between TIMx_RST registers. - * @sa hrtim_timarst_values - * @sa hrtim_timbrst_values - * @sa hrtim_timcrst_values - * @sa hrtim_timdrst_values - * @sa hrtim_timerst_values - * @{ - */ - -/** TIMECMP4: Timer E Compare 4 */ -#define HRTIM_TIMD_RST_TIMECMP4 (1 << 30) - -/** TIMECMP2: Timer E Compare 2 */ -#define HRTIM_TIMD_RST_TIMECMP2 (1 << 29) - -/** TIMECMP1: Timer E Compare 1 */ -#define HRTIM_TIMD_RST_TIMECMP1 (1 << 28) - -/** TIMCCMP4: Timer C Compare 4 */ -#define HRTIM_TIMD_RST_TIMCCMP4 (1 << 27) - -/** TIMCCMP2: Timer C Compare 2 */ -#define HRTIM_TIMD_RST_TIMCCMP2 (1 << 26) - -/** TIMCCMP1: Timer C Compare 1 */ -#define HRTIM_TIMD_RST_TIMCCMP1 (1 << 25) - -/** TIMBCMP4: Timer B Compare 4 */ -#define HRTIM_TIMD_RST_TIMBCMP4 (1 << 24) - -/** TIMBCMP2: Timer B Compare 2 */ -#define HRTIM_TIMD_RST_TIMBCMP2 (1 << 23) - -/** TIMBCMP1: Timer B Compare 1 */ -#define HRTIM_TIMD_RST_TIMBCMP1 (1 << 22) - -/** TIMACMP4: Timer A Compare 4 */ -#define HRTIM_TIMD_RST_TIMACMP4 (1 << 21) - -/** TIMACMP2: Timer A Compare 2 */ -#define HRTIM_TIMD_RST_TIMACMP2 (1 << 20) - -/** TIMACMP1: Timer A Compare 1 */ -#define HRTIM_TIMD_RST_TIMACMP1 (1 << 19) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIMD_RST_EXTEVNT10 (1 << 18) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIMD_RST_EXTEVNT9 (1 << 17) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIMD_RST_EXTEVNT8 (1 << 16) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIMD_RST_EXTEVNT7 (1 << 15) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIMD_RST_EXTEVNT6 (1 << 14) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIMD_RST_EXTEVNT5 (1 << 13) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIMD_RST_EXTEVNT4 (1 << 12) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIMD_RST_EXTEVNT3 (1 << 11) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIMD_RST_EXTEVNT2 (1 << 10) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIMD_RST_EXTEVNT1 (1 << 9) - -/** MSTCMP4: Master compare 4 */ -#define HRTIM_TIMD_RST_MSTCMP4 (1 << 8) - -/** MSTCMP3: Master compare 3 */ -#define HRTIM_TIMD_RST_MSTCMP3 (1 << 7) - -/** MSTCMP2: Master compare 2 */ -#define HRTIM_TIMD_RST_MSTCMP2 (1 << 6) - -/** MSTCMP1: Master compare 1 */ -#define HRTIM_TIMD_RST_MSTCMP1 (1 << 5) - -/** MSTPER: Master timer Period */ -#define HRTIM_TIMD_RST_MSTPER (1 << 4) - -/** CMP4: Timer A compare 4 reset */ -#define HRTIM_TIMD_RST_CMP4 (1 << 3) - -/** CMP2: Timer A compare 2 reset */ -#define HRTIM_TIMD_RST_CMP2 (1 << 2) - -/** UPDT: Timer A Update reset */ -#define HRTIM_TIMD_RST_UPDT (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timerst_values HRTIM_TIME_RST Values - * @ingroup hrtim_defines - * Only bits 30:19 differ between TIMx_RST registers. - * @sa hrtim_timarst_values - * @sa hrtim_timbrst_values - * @sa hrtim_timcrst_values - * @sa hrtim_timdrst_values - * @sa hrtim_timerst_values - * @{ - */ - -/** TIMDCMP4: Timer D Compare 4 */ -#define HRTIM_TIME_RST_TIMDCMP4 (1 << 30) - -/** TIMDCMP2: Timer D Compare 2 */ -#define HRTIM_TIME_RST_TIMDCMP2 (1 << 29) - -/** TIMDCMP1: Timer D Compare 1 */ -#define HRTIM_TIME_RST_TIMDCMP1 (1 << 28) - -/** TIMCCMP4: Timer C Compare 4 */ -#define HRTIM_TIME_RST_TIMCCMP4 (1 << 27) - -/** TIMCCMP2: Timer C Compare 2 */ -#define HRTIM_TIME_RST_TIMCCMP2 (1 << 26) - -/** TIMCCMP1: Timer C Compare 1 */ -#define HRTIM_TIME_RST_TIMCCMP1 (1 << 25) - -/** TIMBCMP4: Timer B Compare 4 */ -#define HRTIM_TIME_RST_TIMBCMP4 (1 << 24) - -/** TIMBCMP2: Timer B Compare 2 */ -#define HRTIM_TIME_RST_TIMBCMP2 (1 << 23) - -/** TIMBCMP1: Timer B Compare 1 */ -#define HRTIM_TIME_RST_TIMBCMP1 (1 << 22) - -/** TIMACMP4: Timer A Compare 4 */ -#define HRTIM_TIME_RST_TIMACMP4 (1 << 21) - -/** TIMACMP2: Timer A Compare 2 */ -#define HRTIM_TIME_RST_TIMACMP2 (1 << 20) - -/** TIMACMP1: Timer A Compare 1 */ -#define HRTIM_TIME_RST_TIMACMP1 (1 << 19) - -/** EXTEVNT10: External Event 10 */ -#define HRTIM_TIME_RST_EXTEVNT10 (1 << 18) - -/** EXTEVNT9: External Event 9 */ -#define HRTIM_TIME_RST_EXTEVNT9 (1 << 17) - -/** EXTEVNT8: External Event 8 */ -#define HRTIM_TIME_RST_EXTEVNT8 (1 << 16) - -/** EXTEVNT7: External Event 7 */ -#define HRTIM_TIME_RST_EXTEVNT7 (1 << 15) - -/** EXTEVNT6: External Event 6 */ -#define HRTIM_TIME_RST_EXTEVNT6 (1 << 14) - -/** EXTEVNT5: External Event 5 */ -#define HRTIM_TIME_RST_EXTEVNT5 (1 << 13) - -/** EXTEVNT4: External Event 4 */ -#define HRTIM_TIME_RST_EXTEVNT4 (1 << 12) - -/** EXTEVNT3: External Event 3 */ -#define HRTIM_TIME_RST_EXTEVNT3 (1 << 11) - -/** EXTEVNT2: External Event 2 */ -#define HRTIM_TIME_RST_EXTEVNT2 (1 << 10) - -/** EXTEVNT1: External Event 1 */ -#define HRTIM_TIME_RST_EXTEVNT1 (1 << 9) - -/** MSTCMP4: Master compare 4 */ -#define HRTIM_TIME_RST_MSTCMP4 (1 << 8) - -/** MSTCMP3: Master compare 3 */ -#define HRTIM_TIME_RST_MSTCMP3 (1 << 7) - -/** MSTCMP2: Master compare 2 */ -#define HRTIM_TIME_RST_MSTCMP2 (1 << 6) - -/** MSTCMP1: Master compare 1 */ -#define HRTIM_TIME_RST_MSTCMP1 (1 << 5) - -/** MSTPER: Master timer Period */ -#define HRTIM_TIME_RST_MSTPER (1 << 4) - -/** CMP4: Timer A compare 4 reset */ -#define HRTIM_TIME_RST_CMP4 (1 << 3) - -/** CMP2: Timer A compare 2 reset */ -#define HRTIM_TIME_RST_CMP2 (1 << 2) - -/** UPDT: Timer A Update reset */ -#define HRTIM_TIME_RST_UPDT (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timxchp_values HRTIM_TIMxCHP Values - * @ingroup hrtim_defines - * @{ - */ - -/** STRTPW[10:7]: STRTPW */ -#define HRTIM_TIMx_CHP_STRTPW_SHIFT 7 -#define HRTIM_TIMx_CHP_STRTPW_MASK (0xf << HRTIM_TIMx_CHP_STRTPW_SHIFT) - -/** CHPDTY[6:4]: Timerx chopper duty cycle value */ -#define HRTIM_TIMx_CHP_CHPDTY_SHIFT 4 -#define HRTIM_TIMx_CHP_CHPDTY_MASK (0x7 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) - -#define HRTIM_TIMx_CHP_CHPDTY_0_8 (0 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_1_8 (1 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_2_8 (2 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_3_8 (3 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_4_8 (4 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_5_8 (5 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_6_8 (6 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) -#define HRTIM_TIMx_CHP_CHPDTY_7_8 (7 << HRTIM_TIMx_CHP_CHPDTY_SHIFT) - -/** CHPFRQ[3:0]: Timerx carrier frequency value */ -#define HRTIM_TIMx_CHP_CHPFRQ_SHIFT 0 -#define HRTIM_TIMx_CHP_CHPFRQ_MASK (0xf << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) - -#define HRTIM_TIMx_CHP_CHPFRQ_DIV16 ( 0 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV32 ( 1 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV48 ( 2 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV64 ( 3 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV80 ( 4 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV96 ( 5 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV112 ( 6 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV128 ( 7 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV144 ( 8 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV160 ( 9 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV176 (10 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV192 (11 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV208 (12 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV224 (13 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV240 (14 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) -#define HRTIM_TIMx_CHP_CHPFRQ_DIV256 (15 << HRTIM_TIMx_CHP_CHPFRQ_SHIFT) - -/**@}*/ - -/** @defgroup hrtim_timxcpt1_values HRTIM_TIMxCPT1 Values - * @ingroup hrtim_defines - * @{ - */ - -/** TECMP2: Timer E Compare 2 */ -#define HRTIM_TIMx_CPT1_TECMP2 (1 << 31) - -/** TECMP1: Timer E Compare 1 */ -#define HRTIM_TIMx_CPT1_TECMP1 (1 << 30) - -/** TE1RST: Timer E output 1 Reset */ -#define HRTIM_TIMx_CPT1_TE1RST (1 << 29) - -/** TE1SET: Timer E output 1 Set */ -#define HRTIM_TIMx_CPT1_TE1SET (1 << 28) - -/** TDCMP2: Timer D Compare 2 */ -#define HRTIM_TIMx_CPT1_TDCMP2 (1 << 27) - -/** TDCMP1: Timer D Compare 1 */ -#define HRTIM_TIMx_CPT1_TDCMP1 (1 << 26) - -/** TD1RST: Timer D output 1 Reset */ -#define HRTIM_TIMx_CPT1_TD1RST (1 << 25) - -/** TD1SET: Timer D output 1 Set */ -#define HRTIM_TIMx_CPT1_TD1SET (1 << 24) - -/** TCCMP2: Timer C Compare 2 */ -#define HRTIM_TIMx_CPT1_TCCMP2 (1 << 23) - -/** TCCMP1: Timer C Compare 1 */ -#define HRTIM_TIMx_CPT1_TCCMP1 (1 << 22) - -/** TC1RST: Timer C output 1 Reset */ -#define HRTIM_TIMx_CPT1_TC1RST (1 << 21) - -/** TC1SET: Timer C output 1 Set */ -#define HRTIM_TIMx_CPT1_TC1SET (1 << 20) - -/** TBCMP2: Timer B Compare 2 */ -#define HRTIM_TIMx_CPT1_TBCMP2 (1 << 19) - -/** TBCMP1: Timer B Compare 1 */ -#define HRTIM_TIMx_CPT1_TBCMP1 (1 << 18) - -/** TB1RST: Timer B output 1 Reset */ -#define HRTIM_TIMx_CPT1_TB1RST (1 << 17) - -/** TB1SET: Timer B output 1 Set */ -#define HRTIM_TIMx_CPT1_TB1SET (1 << 16) - -/** EXEV10CPT: External Event 10 Capture */ -#define HRTIM_TIMx_CPT1_EXEV10CPT (1 << 11) - -/** EXEV9CPT: External Event 9 Capture */ -#define HRTIM_TIMx_CPT1_EXEV9CPT (1 << 10) - -/** EXEV8CPT: External Event 8 Capture */ -#define HRTIM_TIMx_CPT1_EXEV8CPT (1 << 9) - -/** EXEV7CPT: External Event 7 Capture */ -#define HRTIM_TIMx_CPT1_EXEV7CPT (1 << 8) - -/** EXEV6CPT: External Event 6 Capture */ -#define HRTIM_TIMx_CPT1_EXEV6CPT (1 << 7) - -/** EXEV5CPT: External Event 5 Capture */ -#define HRTIM_TIMx_CPT1_EXEV5CPT (1 << 6) - -/** EXEV4CPT: External Event 4 Capture */ -#define HRTIM_TIMx_CPT1_EXEV4CPT (1 << 5) - -/** EXEV3CPT: External Event 3 Capture */ -#define HRTIM_TIMx_CPT1_EXEV3CPT (1 << 4) - -/** EXEV2CPT: External Event 2 Capture */ -#define HRTIM_TIMx_CPT1_EXEV2CPT (1 << 3) - -/** EXEV1CPT: External Event 1 Capture */ -#define HRTIM_TIMx_CPT1_EXEV1CPT (1 << 2) - -/** UDPCPT: Update Capture */ -#define HRTIM_TIMx_CPT1_UDPCPT (1 << 1) - -/** SWCPT: Software Capture */ -#define HRTIM_TIMx_CPT1_SWCPT (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxcpt2_values HRTIM_TIMxCPT2 Values - * @ingroup hrtim_defines - * @{ - */ - -/** TECMP2: Timer E Compare 2 */ -#define HRTIM_TIMx_CPT2_TECMP2 (1 << 31) - -/** TECMP1: Timer E Compare 1 */ -#define HRTIM_TIMx_CPT2_TECMP1 (1 << 30) - -/** TE1RST: Timer E output 1 Reset */ -#define HRTIM_TIMx_CPT2_TE1RST (1 << 29) - -/** TE1SET: Timer E output 1 Set */ -#define HRTIM_TIMx_CPT2_TE1SET (1 << 28) - -/** TDCMP2: Timer D Compare 2 */ -#define HRTIM_TIMx_CPT2_TDCMP2 (1 << 27) - -/** TDCMP1: Timer D Compare 1 */ -#define HRTIM_TIMx_CPT2_TDCMP1 (1 << 26) - -/** TD1RST: Timer D output 1 Reset */ -#define HRTIM_TIMx_CPT2_TD1RST (1 << 25) - -/** TD1SET: Timer D output 1 Set */ -#define HRTIM_TIMx_CPT2_TD1SET (1 << 24) - -/** TCCMP2: Timer C Compare 2 */ -#define HRTIM_TIMx_CPT2_TCCMP2 (1 << 23) - -/** TCCMP1: Timer C Compare 1 */ -#define HRTIM_TIMx_CPT2_TCCMP1 (1 << 22) - -/** TC1RST: Timer C output 1 Reset */ -#define HRTIM_TIMx_CPT2_TC1RST (1 << 21) - -/** TC1SET: Timer C output 1 Set */ -#define HRTIM_TIMx_CPT2_TC1SET (1 << 20) - -/** TBCMP2: Timer B Compare 2 */ -#define HRTIM_TIMx_CPT2_TBCMP2 (1 << 19) - -/** TBCMP1: Timer B Compare 1 */ -#define HRTIM_TIMx_CPT2_TBCMP1 (1 << 18) - -/** TB1RST: Timer B output 1 Reset */ -#define HRTIM_TIMx_CPT2_TB1RST (1 << 17) - -/** TB1SET: Timer B output 1 Set */ -#define HRTIM_TIMx_CPT2_TB1SET (1 << 16) - -/** EXEV10CPT: External Event 10 Capture */ -#define HRTIM_TIMx_CPT2_EXEV10CPT (1 << 11) - -/** EXEV9CPT: External Event 9 Capture */ -#define HRTIM_TIMx_CPT2_EXEV9CPT (1 << 10) - -/** EXEV8CPT: External Event 8 Capture */ -#define HRTIM_TIMx_CPT2_EXEV8CPT (1 << 9) - -/** EXEV7CPT: External Event 7 Capture */ -#define HRTIM_TIMx_CPT2_EXEV7CPT (1 << 8) - -/** EXEV6CPT: External Event 6 Capture */ -#define HRTIM_TIMx_CPT2_EXEV6CPT (1 << 7) - -/** EXEV5CPT: External Event 5 Capture */ -#define HRTIM_TIMx_CPT2_EXEV5CPT (1 << 6) - -/** EXEV4CPT: External Event 4 Capture */ -#define HRTIM_TIMx_CPT2_EXEV4CPT (1 << 5) - -/** EXEV3CPT: External Event 3 Capture */ -#define HRTIM_TIMx_CPT2_EXEV3CPT (1 << 4) - -/** EXEV2CPT: External Event 2 Capture */ -#define HRTIM_TIMx_CPT2_EXEV2CPT (1 << 3) - -/** EXEV1CPT: External Event 1 Capture */ -#define HRTIM_TIMx_CPT2_EXEV1CPT (1 << 2) - -/** UDPCPT: Update Capture */ -#define HRTIM_TIMx_CPT2_UDPCPT (1 << 1) - -/** SWCPT: Software Capture */ -#define HRTIM_TIMx_CPT2_SWCPT (1 << 0) - -/**@}*/ - -/** @defgroup hrtim_timxout_values HRTIM_TIMxOUT Values - * @ingroup hrtim_defines - * @{ - */ - -/** DIDL2: Output 2 Deadtime upon burst mode Idle entry */ -#define HRTIM_TIMx_OUT_DIDL2 (1 << 23) - -/** CHP2: Output 2 Chopper enable */ -#define HRTIM_TIMx_OUT_CHP2 (1 << 22) - -/** FAULT2[21:20]: Output 2 Fault state */ -#define HRTIM_TIMx_OUT_FAULT2_SHIFT 20 -#define HRTIM_TIMx_OUT_FAULT2_MASK (0x3 << HRTIM_TIMx_OUT_FAULT2_SHIFT) - -#define HRTIM_TIMx_OUT_FAULT2_NOOP (0 << HRTIM_TIMx_OUT_FAULT2_SHIFT) -#define HRTIM_TIMx_OUT_FAULT2_ACTIVE (1 << HRTIM_TIMx_OUT_FAULT2_SHIFT) -#define HRTIM_TIMx_OUT_FAULT2_INACTIVE (2 << HRTIM_TIMx_OUT_FAULT2_SHIFT) -#define HRTIM_TIMx_OUT_FAULT2_HIGHZ (3 << HRTIM_TIMx_OUT_FAULT2_SHIFT) - -/** IDLES2: Output 2 Idle State */ -#define HRTIM_TIMx_OUT_IDLES2 (1 << 19) - -/** IDLEM2: Output 2 Idle mode */ -#define HRTIM_TIMx_OUT_IDLEM2 (1 << 18) - -/** POL2: Output 2 polarity */ -#define HRTIM_TIMx_OUT_POL2 (1 << 17) - -/** DLYPRT[12:10]: Delayed Protection */ -#define HRTIM_TIMx_OUT_DLYPRT_SHIFT 10 -#define HRTIM_TIMx_OUT_DLYPRT_MASK (0x7 << HRTIM_TIMx_OUT_DLYPRT_SHIFT) - -/** DLYPRTEN: Delayed Protection Enable */ -#define HRTIM_TIMx_OUT_DLYPRTEN (1 << 9) - -/** DTEN: Deadtime enable */ -#define HRTIM_TIMx_OUT_DTEN (1 << 8) - -/** DIDL1: Output 1 Deadtime upon burst mode Idle entry */ -#define HRTIM_TIMx_OUT_DIDL1 (1 << 7) - -/** CHP1: Output 1 Chopper enable */ -#define HRTIM_TIMx_OUT_CHP1 (1 << 6) - -/** FAULT1[5:4]: Output 1 Fault state */ -#define HRTIM_TIMx_OUT_FAULT1_SHIFT 4 -#define HRTIM_TIMx_OUT_FAULT1_MASK (0x3 << HRTIM_TIMx_OUT_FAULT1_SHIFT) - -#define HRTIM_TIMx_OUT_FAULT1_NOOP (0 << HRTIM_TIMx_OUT_FAULT1_SHIFT) -#define HRTIM_TIMx_OUT_FAULT1_ACTIVE (1 << HRTIM_TIMx_OUT_FAULT1_SHIFT) -#define HRTIM_TIMx_OUT_FAULT1_INACTIVE (2 << HRTIM_TIMx_OUT_FAULT1_SHIFT) -#define HRTIM_TIMx_OUT_FAULT1_HIGHZ (3 << HRTIM_TIMx_OUT_FAULT1_SHIFT) - -/** IDLES1: Output 1 Idle State */ -#define HRTIM_TIMx_OUT_IDLES1 (1 << 3) - -/** IDLEM1: Output 1 Idle mode */ -#define HRTIM_TIMx_OUT_IDLEM1 (1 << 2) - -/** POL1: Output 1 polarity */ -#define HRTIM_TIMx_OUT_POL1 (1 << 1) - -/**@}*/ - -/** @defgroup hrtim_timxflt_values HRTIM_TIMxFLT Values - * @ingroup hrtim_defines - * @{ - */ - -/** FLTLCK: Fault sources Lock */ -#define HRTIM_TIMx_FLT_FLTLCK (1 << 31) - -/** FLT5EN: Fault 5 enable */ -#define HRTIM_TIMx_FLT_FLT5EN (1 << 4) - -/** FLT4EN: Fault 4 enable */ -#define HRTIM_TIMx_FLT_FLT4EN (1 << 3) - -/** FLT3EN: Fault 3 enable */ -#define HRTIM_TIMx_FLT_FLT3EN (1 << 2) - -/** FLT2EN: Fault 2 enable */ -#define HRTIM_TIMx_FLT_FLT2EN (1 << 1) - -/** FLT1EN: Fault 1 enable */ -#define HRTIM_TIMx_FLT_FLT1EN (1 << 0) -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -END_DECLS - -#endif -/** @cond */ -#else -#warning "hrtim_common_all.h should not be included explicitly, only via hrtim.h" -#endif -/** @endcond */ - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_v1.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_v1.h deleted file mode 100644 index 16c8982..0000000 --- a/libopencm3/include/libopencm3/stm32/common/i2c_common_v1.h +++ /dev/null @@ -1,435 +0,0 @@ -/** @addtogroup i2c_defines - * - * @author @htmlonly © @endhtmlonly 2010 Thomas Otto - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H -The order of header inclusion is important. i2c.h includes the device -specific memorymap.h header before including this header file.*/ - -/**@{*/ - -/** @cond */ -#ifdef LIBOPENCM3_I2C_H -/** @endcond */ -#ifndef LIBOPENCM3_I2C_COMMON_V1_H -#define LIBOPENCM3_I2C_COMMON_V1_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base addresses (for convenience) */ -/****************************************************************************/ -/** @defgroup i2c_reg_base I2C register base address -@ingroup i2c_defines - -@{*/ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE -#ifdef I2C3_BASE -#define I2C3 I2C3_BASE -#endif -/**@}*/ - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32((i2c_base) + 0x10) -#define I2C1_DR I2C_DR(I2C1) -#define I2C2_DR I2C_DR(I2C2) - -/* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32((i2c_base) + 0x14) -#define I2C1_SR1 I2C_SR1(I2C1) -#define I2C2_SR1 I2C_SR1(I2C2) - -/* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32((i2c_base) + 0x18) -#define I2C1_SR2 I2C_SR2(I2C1) -#define I2C2_SR2 I2C_SR2(I2C2) - -/* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32((i2c_base) + 0x1c) -#define I2C1_CCR I2C_CCR(I2C1) -#define I2C2_CCR I2C_CCR(I2C2) - -/* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32((i2c_base) + 0x20) -#define I2C1_TRISE I2C_TRISE(I2C1) -#define I2C2_TRISE I2C_TRISE(I2C2) - -/* Not all parts have i2c3 */ -#ifdef I2C3_BASE -#define I2C3_CR1 I2C_CR1(I2C3) -#define I2C3_CR2 I2C_CR2(I2C3) -#define I2C3_OAR1 I2C_OAR1(I2C3) -#define I2C3_OAR2 I2C_OAR2(I2C3) -#define I2C3_DR I2C_DR(I2C3) -#define I2C3_SR1 I2C_SR1(I2C3) -#define I2C3_SR2 I2C_SR2(I2C3) -#define I2C3_CCR I2C_CCR(I2C3) -#define I2C3_TRISE I2C_TRISE(I2C3) -#endif - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* SWRST: Software reset */ -#define I2C_CR1_SWRST (1 << 15) - -/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ - -/* ALERT: SMBus alert */ -#define I2C_CR1_ALERT (1 << 13) - -/* PEC: Packet error checking */ -#define I2C_CR1_PEC (1 << 12) - -/* POS: Acknowledge / PEC position */ -#define I2C_CR1_POS (1 << 11) - -/* ACK: Acknowledge enable */ -#define I2C_CR1_ACK (1 << 10) - -/* STOP: STOP generation */ -#define I2C_CR1_STOP (1 << 9) - -/* START: START generation */ -#define I2C_CR1_START (1 << 8) - -/* NOSTRETCH: Clock stretching disable (slave mode) */ -#define I2C_CR1_NOSTRETCH (1 << 7) - -/* ENGC: General call enable */ -#define I2C_CR1_ENGC (1 << 6) - -/* ENPEC: Enable PEC */ -#define I2C_CR1_ENPEC (1 << 5) - -/* ENARP: ARP enable */ -#define I2C_CR1_ENARP (1 << 4) - -/* SMBTYPE: SMBus type */ -#define I2C_CR1_SMBTYPE (1 << 3) - -/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ - -/* SMBUS: SMBus mode */ -#define I2C_CR1_SMBUS (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ - -/* LAST: DMA last transfer */ -#define I2C_CR2_LAST (1 << 12) - -/* DMAEN: DMA requests enable */ -#define I2C_CR2_DMAEN (1 << 11) - -/* ITBUFEN: Buffer interrupt enable */ -#define I2C_CR2_ITBUFEN (1 << 10) - -/* ITEVTEN: Event interrupt enable */ -#define I2C_CR2_ITEVTEN (1 << 9) - -/* ITERREN: Error interrupt enable */ -#define I2C_CR2_ITERREN (1 << 8) - -/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ - -/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz, 2-42 MHz for - * STM32F4 respectively) */ -/****************************************************************************/ -/** @defgroup i2c_clock I2C clock frequency settings -@ingroup i2c_defines - -@{*/ -#define I2C_CR2_FREQ_2MHZ 0x02 -#define I2C_CR2_FREQ_3MHZ 0x03 -#define I2C_CR2_FREQ_4MHZ 0x04 -#define I2C_CR2_FREQ_5MHZ 0x05 -#define I2C_CR2_FREQ_6MHZ 0x06 -#define I2C_CR2_FREQ_7MHZ 0x07 -#define I2C_CR2_FREQ_8MHZ 0x08 -#define I2C_CR2_FREQ_9MHZ 0x09 -#define I2C_CR2_FREQ_10MHZ 0x0a -#define I2C_CR2_FREQ_11MHZ 0x0b -#define I2C_CR2_FREQ_12MHZ 0x0c -#define I2C_CR2_FREQ_13MHZ 0x0d -#define I2C_CR2_FREQ_14MHZ 0x0e -#define I2C_CR2_FREQ_15MHZ 0x0f -#define I2C_CR2_FREQ_16MHZ 0x10 -#define I2C_CR2_FREQ_17MHZ 0x11 -#define I2C_CR2_FREQ_18MHZ 0x12 -#define I2C_CR2_FREQ_19MHZ 0x13 -#define I2C_CR2_FREQ_20MHZ 0x14 -#define I2C_CR2_FREQ_21MHZ 0x15 -#define I2C_CR2_FREQ_22MHZ 0x16 -#define I2C_CR2_FREQ_23MHZ 0x17 -#define I2C_CR2_FREQ_24MHZ 0x18 -#define I2C_CR2_FREQ_25MHZ 0x19 -#define I2C_CR2_FREQ_26MHZ 0x1a -#define I2C_CR2_FREQ_27MHZ 0x1b -#define I2C_CR2_FREQ_28MHZ 0x1c -#define I2C_CR2_FREQ_29MHZ 0x1d -#define I2C_CR2_FREQ_30MHZ 0x1e -#define I2C_CR2_FREQ_31MHZ 0x1f -#define I2C_CR2_FREQ_32MHZ 0x20 -#define I2C_CR2_FREQ_33MHZ 0x21 -#define I2C_CR2_FREQ_34MHZ 0x22 -#define I2C_CR2_FREQ_35MHZ 0x23 -#define I2C_CR2_FREQ_36MHZ 0x24 -#define I2C_CR2_FREQ_37MHZ 0x25 -#define I2C_CR2_FREQ_38MHZ 0x26 -#define I2C_CR2_FREQ_39MHZ 0x27 -#define I2C_CR2_FREQ_40MHZ 0x28 -#define I2C_CR2_FREQ_41MHZ 0x29 -#define I2C_CR2_FREQ_42MHZ 0x2a -/**@}*/ - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* ADDMODE: Addressing mode (slave mode) */ -#define I2C_OAR1_ADDMODE (1 << 15) -#define I2C_OAR1_ADDMODE_7BIT 0 -#define I2C_OAR1_ADDMODE_10BIT 1 - -/* Note: Bit 14 should always be kept at 1 by software! */ - -/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ - -/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ - -/* --- I2Cx_OAR2 values ---------------------------------------------------- */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ - -/* ENDUAL: Dual addressing mode enable */ -#define I2C_OAR2_ENDUAL (1 << 0) - -/* --- I2Cx_DR values ------------------------------------------------------ */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* DR[7:0] 8-bit data register */ - -/* --- I2Cx_SR1 values ----------------------------------------------------- */ - -/* SMBALERT: SMBus alert */ -#define I2C_SR1_SMBALERT (1 << 15) - -/* TIMEOUT: Timeout or Tlow Error */ -#define I2C_SR1_TIMEOUT (1 << 14) - -/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ - -/* PECERR: PEC Error in reception */ -#define I2C_SR1_PECERR (1 << 12) - -/* OVR: Overrun/Underrun */ -#define I2C_SR1_OVR (1 << 11) - -/* AF: Acknowledge failure */ -#define I2C_SR1_AF (1 << 10) - -/* ARLO: Arbitration lost (master mode) */ -#define I2C_SR1_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_SR1_BERR (1 << 8) - -/* TxE: Data register empty (transmitters) */ -#define I2C_SR1_TxE (1 << 7) - -/* RxNE: Data register not empty (receivers) */ -#define I2C_SR1_RxNE (1 << 6) - -/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ - -/* STOPF: STOP detection (slave mode) */ -#define I2C_SR1_STOPF (1 << 4) - -/* ADD10: 10-bit header sent (master mode) */ -#define I2C_SR1_ADD10 (1 << 3) - -/* BTF: Byte transfer finished */ -#define I2C_SR1_BTF (1 << 2) - -/* ADDR: Address sent (master mode) / address matched (slave mode) */ -#define I2C_SR1_ADDR (1 << 1) - -/* SB: Start bit (master mode) */ -#define I2C_SR1_SB (1 << 0) - -/* --- I2Cx_SR2 values ----------------------------------------------------- */ - -/* Bits [15:8]: PEC[7:0]: Packet error checking register */ - -/* DUALF: Dual flag (slave mode) */ -#define I2C_SR2_DUALF (1 << 7) - -/* SMBHOST: SMBus host header (slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) - -/* SMBDEFAULT: SMBus device default address (slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) - -/* GENCALL: General call address (slave mode) */ -#define I2C_SR2_GENCALL (1 << 4) - -/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ - -/* TRA: Transmitter / receiver */ -#define I2C_SR2_TRA (1 << 2) - -/* BUSY: Bus busy */ -#define I2C_SR2_BUSY (1 << 1) - -/* MSL: Master / slave */ -#define I2C_SR2_MSL (1 << 0) - -/* --- I2Cx_CCR values ----------------------------------------------------- */ - -/* F/S: I2C Master mode selection (fast / standard) */ -#define I2C_CCR_FS (1 << 15) - -/* DUTY: Fast Mode Duty Cycle */ -/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles -@ingroup i2c_defines - -@{*/ -#define I2C_CCR_DUTY (1 << 14) -#define I2C_CCR_DUTY_DIV2 0 -#define I2C_CCR_DUTY_16_DIV_9 1 -/**@}*/ - -/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [11:0]: - * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) - */ - -/* --- I2Cx_TRISE values --------------------------------------------------- */ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [5:0]: - * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) - */ - -/* --- I2C constant definitions -------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup i2c_rw I2C Read/Write bit -@ingroup i2c_defines - -@{*/ -#define I2C_WRITE 0 -#define I2C_READ 1 -/**@}*/ - -/* --- I2C function prototypes---------------------------------------------- */ - -/** - * I2C speed modes. - */ -enum i2c_speeds { - i2c_speed_sm_100k, - i2c_speed_fm_400k, - i2c_speed_fmp_1m, - i2c_speed_unknown -}; - -BEGIN_DECLS - -void i2c_reset(uint32_t i2c); -void i2c_peripheral_enable(uint32_t i2c); -void i2c_peripheral_disable(uint32_t i2c); -void i2c_send_start(uint32_t i2c); -void i2c_send_stop(uint32_t i2c); -void i2c_clear_stop(uint32_t i2c); -void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); -void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); -void i2c_set_own_7bit_slave_address_two(uint32_t i2c, uint8_t slave); -void i2c_enable_dual_addressing_mode(uint32_t i2c); -void i2c_disable_dual_addressing_mode(uint32_t i2c); -void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); -void i2c_send_data(uint32_t i2c, uint8_t data); -void i2c_set_fast_mode(uint32_t i2c); -void i2c_set_standard_mode(uint32_t i2c); -void i2c_set_ccr(uint32_t i2c, uint16_t freq); -void i2c_set_trise(uint32_t i2c, uint16_t trise); -void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite); -uint8_t i2c_get_data(uint32_t i2c); -void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); -void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); -void i2c_enable_ack(uint32_t i2c); -void i2c_disable_ack(uint32_t i2c); -void i2c_nack_next(uint32_t i2c); -void i2c_nack_current(uint32_t i2c); -void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle); -void i2c_enable_dma(uint32_t i2c); -void i2c_disable_dma(uint32_t i2c); -void i2c_set_dma_last_transfer(uint32_t i2c); -void i2c_clear_dma_last_transfer(uint32_t i2c); -void i2c_transfer7(uint32_t i2c, uint8_t addr, uint8_t *w, size_t wn, uint8_t *r, size_t rn); -void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "i2c_common_v1.h should not be included explicitly, only via i2c.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_v2.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_v2.h deleted file mode 100644 index ad4846b..0000000 --- a/libopencm3/include/libopencm3/stm32/common/i2c_common_v2.h +++ /dev/null @@ -1,459 +0,0 @@ -/** @addtogroup i2c_defines - * - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H -The order of header inclusion is important. i2c.h includes the device -specific memorymap.h header before including this header file.*/ - -/**@{*/ - -/** @cond */ -#ifdef LIBOPENCM3_I2C_H -/** @endcond */ -#ifndef LIBOPENCM3_I2C_COMMON_V2_H -#define LIBOPENCM3_I2C_COMMON_V2_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base addresses (for convenience) */ -/*****************************************************************************/ -/** @defgroup i2c_reg_base I2C register base address - * @ingroup i2c_defines - * @{*/ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE -#ifdef I2C3_BASE -#define I2C3 I2C3_BASE -#endif -#ifdef I2C4_BASE -#define I2C4 I2C4_BASE -#endif -/**@}*/ - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Timing register (I2Cx_TIMINGR) */ -#define I2C_TIMINGR(i2c_base) MMIO32((i2c_base) + 0x10) -#define I2C1_TIMINGR I2C_TIMINGR(I2C1) -#define I2C2_TIMINGR I2C_TIMINGR(I2C2) - -/* Timeout register (I2Cx_TIMEOUTR) */ -#define I2C_TIMEOUTR(i2c_base) MMIO32((i2c_base) + 0x14) -#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) -#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) - -/* Interrupt and Status register (I2Cx_ISR) */ -#define I2C_ISR(i2c_base) MMIO32((i2c_base) + 0x18) -#define I2C1_ISR I2C_ISR(I2C1) -#define I2C2_ISR I2C_ISR(I2C2) - -/* Interrupt clear register (I2Cx_ICR) */ -#define I2C_ICR(i2c_base) MMIO32((i2c_base) + 0x1C) -#define I2C1_ICR I2C_ICR(I2C1) -#define I2C2_ICR I2C_ICR(I2C2) - -/* PEC register (I2Cx_PECR) */ -#define I2C_PECR(i2c_base) MMIO32((i2c_base) + 0x20) -#define I2C1_PECR I2C_PECR(I2C1) -#define I2C2_PECR I2C_PECR(I2C2) - -/* Receive data register (I2Cx_RXDR) */ -#define I2C_RXDR(i2c_base) MMIO32((i2c_base) + 0x24) -#define I2C1_RXDR I2C_RXDR(I2C1) -#define I2C2_RXDR I2C_RXDR(I2C2) - -/* Transmit data register (I2Cx_TXDR) */ -#define I2C_TXDR(i2c_base) MMIO32((i2c_base) + 0x28) -#define I2C1_TXDR I2C_TXDR(I2C1) -#define I2C2_TXDR I2C_TXDR(I2C2) - -/* Not all parts have i2c3 */ -#ifdef I2C3_BASE -#define I2C3_CR1 I2C_CR1(I2C3) -#define I2C3_CR2 I2C_CR2(I2C3) -#define I2C3_OAR1 I2C_OAR1(I2C3) -#define I2C3_OAR2 I2C_OAR2(I2C3) -#define I2C3_DR I2C_DR(I2C3) -#define I2C3_SR1 I2C_SR1(I2C3) -#define I2C3_SR2 I2C_SR2(I2C3) -#define I2C3_CCR I2C_CCR(I2C3) -#define I2C3_TRISE I2C_TRISE(I2C3) -#endif - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* PECEN: PEC enable */ -#define I2C_CR1_PECEN (1 << 23) - -/* ALERTEN: SMBus alert enable */ -#define I2C_CR1_ALERTEN (1 << 22) - -/* SMBDEN: SMBus Device Default address enable */ -#define I2C_CR1_SMBDEN (1 << 21) - -/* SMBHEN: SMBus Host address enable */ -#define I2C_CR1_SMBHEN (1 << 20) - -/* GCEN: General call enable */ -#define I2C_CR1_GCEN (1 << 19) - -/* WUPEN: Wakeup from STOP enable */ -#define I2C_CR1_WUPEN (1 << 18) - -/* NOSTRETCH: Clock stretching disable */ -#define I2C_CR1_NOSTRETCH (1 << 17) - -/* SBC: Slave byte control */ -#define I2C_CR1_SBC (1 << 16) - -/* RXDMAEN: DMA reception requests enable */ -#define I2C_CR1_RXDMAEN (1 << 15) - -/* TXDMAEN: DMA transmission requests enable */ -#define I2C_CR1_TXDMAEN (1 << 14) - -/* ANFOFF: Analog noise filter OFF */ -#define I2C_CR1_ANFOFF (1 << 12) - -/** DNF[3:0]: Digital noise filter. */ -#define I2C_CR1_DNF_MASK 0xF -#define I2C_CR1_DNF_SHIFT 8 - -/* ERRIE: Error interrupts enable */ -#define I2C_CR1_ERRIE (1 << 7) - -/* TCIE: Transfer Complete interrupt enable */ -#define I2C_CR1_TCIE (1 << 6) - -/* STOPIE: STOP detection Interrupt enable */ -#define I2C_CR1_STOPIE (1 << 5) - -/* NACKIE: Not acknowledge received Interrupt enable */ -#define I2C_CR1_NACKIE (1 << 4) - -/* ADDRIE: Address match Interrupt enable (slave only) */ -#define I2C_CR1_ADDRIE (1 << 3) - -/* RXIE: RX Interrupt enable */ -#define I2C_CR1_RXIE (1 << 2) - -/* TXIE: TX Interrupt enable */ -#define I2C_CR1_TXIE (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* PECBYTE: Packet error checking byte */ -#define I2C_CR2_PECBYTE (1 << 26) - -/* AUTOEND: Automatic end mode (master mode) */ -#define I2C_CR2_AUTOEND (1 << 25) - -/* RELOAD: NBYTES reload mode */ -#define I2C_CR2_RELOAD (1 << 24) - -/* NBYTES[7:0]: Number of bytes (23,16) */ -#define I2C_CR2_NBYTES_SHIFT 16 -#define I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT) - -/* NACK: NACK generation (slave mode) */ -#define I2C_CR2_NACK (1 << 15) - -/* STOP: Stop generation (master mode) */ -#define I2C_CR2_STOP (1 << 14) - -/* START: Start generation */ -#define I2C_CR2_START (1 << 13) - -/* HEAD10R: 10-bit address header only read direction (master receiver mode) */ -#define I2C_CR2_HEAD10R (1 << 12) - -/* ADD10: 10-bit addressing mode (master mode) */ -#define I2C_CR2_ADD10 (1 << 11) - -/* RD_WRN: Transfer direction (master mode) */ -#define I2C_CR2_RD_WRN (1 << 10) - -#define I2C_CR2_SADD_7BIT_SHIFT 1 -#define I2C_CR2_SADD_10BIT_SHIFT 0 -#define I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT) -#define I2C_CR2_SADD_10BIT_MASK 0x3FF - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* OA1EN: Own Address 1 enable */ -#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) -#define I2C_OAR1_OA1EN_ENABLE (0x1 << 15) - -/* OA1MODE Own Address 1 10-bit mode */ -#define I2C_OAR1_OA1MODE (1 << 10) -#define I2C_OAR1_OA1MODE_7BIT 0 -#define I2C_OAR1_OA1MODE_10BIT 1 - -/* OA1[9:8]: Interface address */ - -/* OA1[7:1]: Interface address */ - -/* OA1[0]: Interface address */ -#define I2C_OAR1_OA1 (1 << 10) -#define I2C_OAR1_OA1_7BIT 0 -#define I2C_OAR1_OA1_10BIT 1 - -/* --- I2Cx_OAR2 values ---------------------------------------------------- */ - -/* OA2EN: Own Address 2 enable */ -#define I2C_OAR2_OA2EN (1 << 15) - -/* OA2MSK[2:0]: Own Address 2 masks */ -#define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8) -#define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8) -#define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8) -#define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8) -#define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8) -#define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8) -#define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8) -#define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8) - -/* OA2[7:1]: Interface address */ - -/* --- I2Cx_TIMINGR values ------------------------------------------------- */ - -/* PRESC[3:0]: Timing prescaler (31,28) */ -#define I2C_TIMINGR_PRESC_SHIFT 28 -#define I2C_TIMINGR_PRESC_MASK (0xF << 28) - -/* SCLDEL[3:0]: Data setup time (23,20) */ -#define I2C_TIMINGR_SCLDEL_SHIFT 20 -#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT) - -/* SDADEL[3:0]: Data hold time (19,16) */ -#define I2C_TIMINGR_SDADEL_SHIFT 16 -#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT) - -/* SCLH[7:0]: SCL high period (master mode) (15,8) */ -#define I2C_TIMINGR_SCLH_SHIFT 8 -#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT) - -/* SCLL[7:0]: SCL low period (master mode) (7,0) */ -#define I2C_TIMINGR_SCLL_SHIFT 0 -#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) - -/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */ - -/* TEXTEN: Extended clock timeout enable */ -#define I2C_TIEMOUTR_TEXTEN (1 << 31) - -/* XXX: Not clear yet. */ -/* TIMEOUTB[11:0]: Bus timeout B */ - -/* TIMOUTEN: Clock timeout enable */ -#define I2C_TIEMOUTR_TIMOUTEN (1 << 15) - -/* TIDLE: Idle clock timeout detection */ -#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) -#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) - -/* XXX: Not clear yet. */ -/* TIMEOUTA[11:0]: Bus Timeout A */ - -/* --- I2Cx_ISR values ----------------------------------------------------- */ - -/* Bits 31:24 Reserved, must be kept at reset value */ - -/* XXX: Not clear yet. */ -/* ADDCODE[6:0]: Address match code (Slave mode) */ - -/* DIR: Transfer direction (Slave mode) */ -#define I2C_ISR_DIR_READ (0x1 << 16) -#define I2C_ISR_DIR_WRITE (0x0 << 16) - -/* BUSY: Bus busy */ -#define I2C_ISR_BUSY (1 << 15) - -/* ALERT: SMBus alert */ -#define I2C_ISR_ALERT (1 << 13) - -/* TIMEOUT: Timeout or tLOW detection flag */ -#define I2C_ISR_TIMEOUT (1 << 12) - -/* PECERR: PEC Error in reception */ -#define I2C_ISR_PECERR (1 << 11) - -/* OVR: Overrun/Underrun (slave mode) */ -#define I2C_ISR_OVR (1 << 10) - -/* ARLO: Arbitration lost */ -#define I2C_ISR_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_ISR_BERR (1 << 8) - -/* TCR: Transfer Complete Reload */ -#define I2C_ISR_TCR (1 << 7) - -/* TC: Transfer Complete (master mode) */ -#define I2C_ISR_TC (1 << 6) - -/* STOPF: Stop detection flag */ -#define I2C_ISR_STOPF (1 << 5) - -/* NACKF: Not Acknowledge received flag */ -#define I2C_ISR_NACKF (1 << 4) - -/* ADDR: Address matched (slave mode) */ -#define I2C_ISR_ADDR (1 << 3) - -/* RXNE: Receive data register not empty (receivers) */ -#define I2C_ISR_RXNE (1 << 2) - -/* TXIS: Transmit interrupt status (transmitters) */ -#define I2C_ISR_TXIS (1 << 1) - -/* TXE: Transmit data register empty (transmitters) */ -#define I2C_ISR_TXE (1 << 0) - -/* --- I2Cx_ICR values ----------------------------------------------------- */ - -/* ALERTCF: Alert flag clear */ -#define I2C_ICR_ALERTCF (1 << 13) - -/* TIMOUTCF: Timeout detection flag clear */ -#define I2C_ICR_TIMOUTCF (1 << 12) - -/* PECCF: PEC Error flag clear */ -#define I2C_ICR_PECCF (1 << 11) - -/* OVRCF: Overrun/Underrun flag clear */ -#define I2C_ICR_OVRCF (1 << 10) - -/* ARLOCF: Arbitration Lost flag clear */ -#define I2C_ICR_ARLOCF (1 << 9) - -/* BERRCF: Bus error flag clear */ -#define I2C_ICR_BERRCF (1 << 8) - -/* STOPCF: Stop detection flag clear */ -#define I2C_ICR_STOPCF (1 << 5) - -/* NACKCF: Not Acknowledge flag clear */ -#define I2C_ICR_NACKCF (1 << 4) - -/* ADDRCF: Address Matched flag clear */ -#define I2C_ICR_ADDRCF (1 << 3) - -/* --- I2Cx_PECR values ---------------------------------------------------- */ - -/* PEC[7:0] Packet error checking register */ - -/* --- I2C function prototypes---------------------------------------------- */ - -/** - * I2C speed modes. - */ -enum i2c_speeds { - i2c_speed_sm_100k, - i2c_speed_fm_400k, - i2c_speed_fmp_1m, - i2c_speed_unknown -}; - -BEGIN_DECLS - -void i2c_reset(uint32_t i2c); -void i2c_peripheral_enable(uint32_t i2c); -void i2c_peripheral_disable(uint32_t i2c); -void i2c_send_start(uint32_t i2c); -void i2c_send_stop(uint32_t i2c); -void i2c_clear_stop(uint32_t i2c); -void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); -void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); -void i2c_send_data(uint32_t i2c, uint8_t data); -uint8_t i2c_get_data(uint32_t i2c); - -void i2c_enable_analog_filter(uint32_t i2c); -void i2c_disable_analog_filter(uint32_t i2c); -void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting); -void i2c_set_prescaler(uint32_t i2c, uint8_t presc); -void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time); -void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time); -void i2c_set_scl_high_period(uint32_t i2c, uint8_t period); -void i2c_set_scl_low_period(uint32_t i2c, uint8_t period); -void i2c_enable_stretching(uint32_t i2c); -void i2c_disable_stretching(uint32_t i2c); -void i2c_set_7bit_addr_mode(uint32_t i2c); -void i2c_set_10bit_addr_mode(uint32_t i2c); -void i2c_set_7bit_address(uint32_t i2c, uint8_t addr); -void i2c_set_10bit_address(uint32_t i2c, uint16_t addr); -void i2c_set_write_transfer_dir(uint32_t i2c); -void i2c_set_read_transfer_dir(uint32_t i2c); -void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes); -bool i2c_is_start(uint32_t i2c); -void i2c_enable_autoend(uint32_t i2c); -void i2c_disable_autoend(uint32_t i2c); -bool i2c_nack(uint32_t i2c); -bool i2c_busy(uint32_t i2c); -bool i2c_transmit_int_status(uint32_t i2c); -bool i2c_transfer_complete(uint32_t i2c); -bool i2c_received_data(uint32_t i2c); -void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); -void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); -void i2c_enable_rxdma(uint32_t i2c); -void i2c_disable_rxdma(uint32_t i2c); -void i2c_enable_txdma(uint32_t i2c); -void i2c_disable_txdma(uint32_t i2c); -void i2c_transfer7(uint32_t i2c, uint8_t addr, uint8_t *w, size_t wn, uint8_t *r, size_t rn); -void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "i2c_common_v2.h should not be included explicitly, only via i2c.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h b/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h deleted file mode 100644 index d7430b5..0000000 --- a/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h +++ /dev/null @@ -1,121 +0,0 @@ -/** @addtogroup iwdg_defines - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H -The order of header inclusion is important. iwdg.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_IWDG_H -/** @endcond */ -#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H -#define LIBOPENCM3_IWDG_COMMON_ALL_H - -/**@{*/ - -/* --- IWDG registers ------------------------------------------------------ */ - -/** Key Register (IWDG_KR) */ -#define IWDG_KR MMIO32(IWDG_BASE + 0x00) - -/** Prescaler register (IWDG_PR) */ -#define IWDG_PR MMIO32(IWDG_BASE + 0x04) - -/** Reload register (IWDG_RLR) */ -#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) - -/** Status register (IWDG_SR) */ -#define IWDG_SR MMIO32(IWDG_BASE + 0x0c) - -/* --- IWDG_KR values ------------------------------------------------------ */ - -/* Bits [31:16]: Reserved. */ - -/* KEY[15:0]: Key value (write-only, reads as 0x0000) */ -/** @defgroup iwdg_key IWDG Key Values -@ingroup iwdg_defines - -@{*/ -#define IWDG_KR_RESET 0xaaaa -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_START 0xcccc -/**@}*/ - -/* --- IWDG_PR values ------------------------------------------------------ */ - -/* Bits [31:3]: Reserved. */ - -/* PR[2:0]: Prescaler divider */ -#define IWDG_PR_LSB 0 -/** @defgroup iwdg_prediv IWDG prescaler divider -@ingroup iwdg_defines - -@{*/ -#define IWDG_PR_DIV4 0x0 -#define IWDG_PR_DIV8 0x1 -#define IWDG_PR_DIV16 0x2 -#define IWDG_PR_DIV32 0x3 -#define IWDG_PR_DIV64 0x4 -#define IWDG_PR_DIV128 0x5 -#define IWDG_PR_DIV256 0x6 -/**@}*/ -/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ -/* #define IWDG_PR_DIV256 0x7 */ - -/* --- IWDG_RLR values ----------------------------------------------------- */ - -/* Bits [31:12]: Reserved. */ - -/* RL[11:0]: Watchdog counter reload value */ - -/** @defgroup iwdg_sr_values IWDG Status Register Values -@ingroup iwdg_defines -@{*/ -/** RVU: Watchdog counter reload value update */ -#define IWDG_SR_RVU (1 << 1) - -/** PVU: Watchdog prescaler value update */ -#define IWDG_SR_PVU (1 << 0) -/*@}*/ - -/* --- IWDG function prototypes---------------------------------------------- */ - -BEGIN_DECLS - -void iwdg_start(void); -void iwdg_set_period_ms(uint32_t period); -bool iwdg_reload_busy(void); -bool iwdg_prescaler_busy(void); -void iwdg_reset(void); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/iwdg_common_v2.h b/libopencm3/include/libopencm3/stm32/common/iwdg_common_v2.h deleted file mode 100644 index 2b7ade5..0000000 --- a/libopencm3/include/libopencm3/stm32/common/iwdg_common_v2.h +++ /dev/null @@ -1,80 +0,0 @@ -/** @addtogroup iwdg_defines - - @author @htmlonly © @endhtmlonly 2018 Guillame Revaillot - - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2018 Guillaume Revaillot - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H -The order of header inclusion is important. iwdg.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_IWDG_H -/** @endcond */ -#pragma once - -/**@{*/ - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/** Window Register (IWDG_WINR) */ -#define IWDG_WINR MMIO32(IWDG_BASE + 0x10) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @addtogroup iwdg_sr_values -@{*/ -/** WVU: Watchdog counter window value update */ -#define IWDG_SR_WVU (1 << 2) -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -/** @cond */ -#else -#warning "iwdg_common_v2.h should not be included explicitly, only via iwdg.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/lptimer_common_all.h b/libopencm3/include/libopencm3/stm32/common/lptimer_common_all.h deleted file mode 100644 index 37ea10f..0000000 --- a/libopencm3/include/libopencm3/stm32/common/lptimer_common_all.h +++ /dev/null @@ -1,296 +0,0 @@ -/** @addtogroup lptimer_defines - * - * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski - * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/** @cond */ -#if defined(LIBOPENCM3_LPTIMER_H) -/** @endcond */ -#ifndef LIBOPENCM3_LPTIMER_COMMON_H -#define LIBOPENCM3_LPTIMER_COMMON_H - -/* --- LPTIM (low power timer) ------------------------------------------- */ - -#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) -#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) -#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) -#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) -#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) -#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) -#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) -#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) - -#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) -#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) -#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) -#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) -#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) -#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) -#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) -#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) - -#if defined(LPTIM2_BASE) -#define LPTIM2_ISR LPTIM_ISR(LPTIM2_BASE) -#define LPTIM2_ICR LPTIM_ICR(LPTIM2_BASE) -#define LPTIM2_IER LPTIM_IER(LPTIM2_BASE) -#define LPTIM2_CFGR LPTIM_CFGR(LPTIM2_BASE) -#define LPTIM2_CR LPTIM_CR(LPTIM2_BASE) -#define LPTIM2_CMP LPTIM_CMP(LPTIM2_BASE) -#define LPTIM2_ARR LPTIM_ARR(LPTIM2_BASE) -#define LPTIM2_CNT LPTIM_CNT(LPTIM2_BASE) -#endif - -/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register -@{*/ - -/** LPTIM_ISR_CMPM Compare match */ -#define LPTIM_ISR_CMPM (1 << 0) - -/** LPTIM_ISR_ARRM Autoreload match */ -#define LPTIM_ISR_ARRM (1 << 1) - -/** LPTIM_ISR_EXTTRIG External trigger edge event */ -#define LPTIM_ISR_EXTTRIG (1 << 2) - -/** LPTIM_ISR_CMPOK Compare register update OK */ -#define LPTIM_ISR_CMPOK (1 << 3) - -/** LPTIM_ISR_ARROK Autoreload register update OK */ -#define LPTIM_ISR_ARROK (1 << 4) - -/** LPTIM_ISR_UP Counter direction change down to up */ -#define LPTIM_ISR_UP (1 << 5) - -/** LPTIM_ISR_DOWN Counter direction change up to down */ -#define LPTIM_ISR_DOWN (1 << 6) - -/**@}*/ - -/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register -@{*/ - -/** LPTIM_ICR_CMPMCF compare match Clear Flag */ -#define LPTIM_ICR_CMPMCF (1 << 0) - -/** LPTIM_ICR_ARRMCF Autoreload match Clear Flag */ -#define LPTIM_ICR_ARRMCF (1 << 1) - -/** LPTIM_ICR_EXTTRIGCF External trigger valid edge Clear Flag */ -#define LPTIM_ICR_EXTTRIGCF (1 << 2) - -/** LPTIM_ICR_CMPOKCF Compare register update OK Clear Flag */ -#define LPTIM_ICR_CMPOKCF (1 << 3) - -/** LPTIM_ICR_ARROKCF Autoreload register update OK Clear Flag */ -#define LPTIM_ICR_ARROKCF (1 << 4) - -/** LPTIM_ICR_UPCF Direction change to UP Clear Flag */ -#define LPTIM_ICR_UPCF (1 << 5) - -/** LPTIM_ICR_DOWNCF Direction change to down Clear Flag */ -#define LPTIM_ICR_DOWNCF (1 << 6) - -/**@}*/ - -/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register -@{*/ - -/** LPTIM_IER_CMPMIE Compare match Interrupt Enable */ -#define LPTIM_IER_CMPMIE (1 << 0) - -/** LPTIM_IER_ARRMIE Autoreload match Interrupt Enable */ -#define LPTIM_IER_ARRMIE (1 << 1) - -/** LPTIM_IER_EXTTRIGIE External trigger valid edge Interrupt Enable */ -#define LPTIM_IER_EXTTRIGIE (1 << 2) - -/** LPTIM_IER_CMPOKIE Compare register update OK Interrupt Enable */ -#define LPTIM_IER_CMPOKIE (1 << 3) - -/** LPTIM_IER_ARROKIE Autoreload register update OK Interrupt Enable */ -#define LPTIM_IER_ARROKIE (1 << 4) - -/** LPTIM_IER_UPIE Direction change to UP Interrupt Enable */ -#define LPTIM_IER_UPIE (1 << 5) - -/** LPTIM_IER_DOWNIE Direction change to down Interrupt Enable */ -#define LPTIM_IER_DOWNIE (1 << 6) - -/**@}*/ - -/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register -@{*/ - -/** CKSEL: Select internal (0) or external clock source (1) */ -#define LPTIM_CFGR_CKSEL (1 << 0) - -#define LPTIM_CFGR_CKPOL_SHIFT 1 -#define LPTIM_CFGR_CKPOL_MASK 0x03 -#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) -/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity -@{*/ -#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_CKFLT_SHIFT 3 -#define LPTIM_CFGR_CKFLT_MASK 0x03 -#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) -/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock -@{*/ -#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRGFLT_SHIFT 6 -#define LPTIM_CFGR_TRGFLT_MASK 0x03 -#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) -/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger -@{*/ -#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_PRESC_SHIFT 9 -#define LPTIM_CFGR_PRESC_MASK 0x07 -#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) -/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler -@{*/ -#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRIGSEL_SHIFT 13 -#define LPTIM_CFGR_TRIGSEL_MASK 0x07 -#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector -@{*/ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) -/* 5 is reserved */ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRIGEN_SHIFT 17 -#define LPTIM_CFGR_TRIGEN_MASK 0x07 -#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) -/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity -@{*/ -#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) -/**@}*/ - -/** TIMOUT: Timeout enable */ -#define LPTIM_CFGR_TIMOUT (1 << 19) - -/** WAVE: Waveform shape */ -#define LPTIM_CFGR_WAVE (1 << 20) - -/** WAVPOL: Waveform shape polarity */ -#define LPTIM_CFGR_WAVPOL (1 << 21) - -/** PRELOAD: Register update mode */ -#define LPTIM_CFGR_PRELOAD (1 << 22) - -/** COUNTMODE: Counter mode enable */ -#define LPTIM_CFGR_COUNTMODE (1 << 23) - -/** ENC: Encoder mode enable */ -#define LPTIM_CFGR_ENC (1 << 24) - -/**@}*/ - -/** @defgroup lptim_cr LPTIM_CR Control Register -@{*/ - -/** ENABLE: LPTIM Enable */ -#define LPTIM_CR_ENABLE (1 << 0) - -/** SNGSTRT: Start in Single Mode */ -#define LPTIM_CR_SNGSTRT (1 << 1) - -/** CNGSTRT: Start in Continuous Mode */ -#define LPTIM_CR_CNTSTRT (1 << 2) - -/**@}*/ - -/* --- LPTIM function prototypes --------------------------------------------- */ - -BEGIN_DECLS - -void lptimer_enable(uint32_t timer_peripheral); -void lptimer_disable(uint32_t timer_peripheral); - -void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode); -void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count); -uint16_t lptimer_get_counter(uint32_t timer_peripheral); -void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value); -void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value); -void lptimer_enable_preload(uint32_t lptimer_peripheral); -void lptimer_disable_preload(uint32_t lptimer_peripheral); -void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral); -void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral); - -void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); -void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen); -void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source); -void lptimer_set_internal_clock_source(uint32_t timer_peripheral); -void lptimer_set_external_clock_source(uint32_t timer_peripheral); - -void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag); -bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag); -void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq); -void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq); - - -END_DECLS - -#endif -/** @cond */ -#else -#warning "lptimer_common_all.h should not be included directly, only via lptimer.h" -#endif -/** @endcond */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/ltdc_common_f47.h b/libopencm3/include/libopencm3/stm32/common/ltdc_common_f47.h deleted file mode 100644 index d938d6c..0000000 --- a/libopencm3/include/libopencm3/stm32/common/ltdc_common_f47.h +++ /dev/null @@ -1,535 +0,0 @@ -/** @addtogroup ltdc_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Oliver Meier - * - * @date 5 December 2014 - * - * This library supports the LCD TFT display controller (LTDC) in the STM32F4xx - * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Oliver Meier - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -/** @cond */ -#ifndef LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ -/** @endcond */ -#define LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ - - -#include -#include - -/** - * LTDC - */ - - -#define LTDC_SSCR (MMIO32(LTDC_BASE + 0x08)) -#define LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C)) -#define LTDC_AWCR (MMIO32(LTDC_BASE + 0x10)) -#define LTDC_TWCR (MMIO32(LTDC_BASE + 0x14)) -#define LTDC_GCR (MMIO32(LTDC_BASE + 0x18)) -#define LTDC_SRCR (MMIO32(LTDC_BASE + 0x24)) -#define LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C)) -#define LTDC_IER (MMIO32(LTDC_BASE + 0x34)) -#define LTDC_ISR (MMIO32(LTDC_BASE + 0x38)) -#define LTDC_ICR (MMIO32(LTDC_BASE + 0x3C)) -#define LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40)) -#define LTDC_CPSR (MMIO32(LTDC_BASE + 0x44)) -#define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) - -/* x == LTDC_LAYER_x */ -#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) -#define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) -#define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) - -#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) -#define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) -#define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) - -#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) -#define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) -#define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) - -#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) -#define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) -#define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) - -#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) -#define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) -#define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) - -#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) -#define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) -#define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) - -#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) -#define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) -#define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) - -#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) -#define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) -#define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) - -#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) -#define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) -#define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) - -#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) -#define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) -#define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) - -#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) -#define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) -#define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) - -#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) -#define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) -#define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) - - -#define LTDC_LAYER_1 1 -#define LTDC_LAYER_2 2 - -/* --- LTDC_SSCR values ---------------------------------------------------- */ - -/* Horizontal Synchronization Width */ -#define LTDC_SSCR_HSW_SHIFT 16 -#define LTDC_SSCR_HSW_MASK 0xfff - -/* Vertical Synchronization Height */ -#define LTDC_SSCR_VSH_SHIFT 0 -#define LTDC_SSCR_VSH_MASK 0x7ff - -/* --- LTDC_BPCR values ---------------------------------------------------- */ - -/* Accumulated Horizontal Back Porch */ -#define LTDC_BPCR_AHBP_SHIFT 16 -#define LTDC_BPCR_AHBP_MASK 0xfff - -/* Accumulated Vertical Back Porch */ -#define LTDC_BPCR_AVBP_SHIFT 0 -#define LTDC_BPCR_AVBP_MASK 0x7FF - -/* --- LTDC_AWCR values ---------------------------------------------------- */ - -/* Accumulated Active Width */ -#define LTDC_AWCR_AAW_SHIFT 16 -#define LTDC_AWCR_AAW_MASK 0xfff - -/* Accumulated Active Height */ -#define LTDC_AWCR_AAH_SHIFT 0 -#define LTDC_AWCR_AAH_MASK 0x7ff - -/* --- LTDC_TWCR values ---------------------------------------------------- */ - -/* Total Width */ -#define LTDC_TWCR_TOTALW_SHIFT 16 -#define LTDC_TWCR_TOTALW_MASK 0xfff - -/* Total Height */ -#define LTDC_TWCR_TOTALH_SHIFT 0 -#define LTDC_TWCR_TOTALH_MASK 0x7ff - -/* GCR - control register */ -#define LTDC_GCR_LTDC_ENABLE (1<<0) -#define LTDC_GCR_DITHER_ENABLE (1<<16) - -#define LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28) -#define LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28) - -#define LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29) -#define LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29) - -#define LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30) -#define LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30) - -#define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) -#define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) - -/* GCR - register bit defines (no semantics) */ -#define LTDC_GCR_HSPOL (1 << 31) -#define LTDC_GCR_VSPOL (1 << 30) -#define LTDC_GCR_DEPOL (1 << 29) -#define LTDC_GCR_PCPOL (1 << 28) -#define LTDC_GCR_DITHER (1 << 16) -#define LTDC_GCR_LTDCEN (1 << 0) - -/* --- LTDC_SRCR values ---------------------------------------------------- */ - -/* Vertical Blanking Reload */ -#define LTDC_SRCR_VBR (1 << 1) - -/* Immediate Reload */ -#define LTDC_SRCR_IMR (1 << 0) - -/* LTDC_BCCR - reload control */ -#define LTDC_SRCR_RELOAD_IMR (1<<0) -#define LTDC_SRCR_RELOAD_VBR (1<<1) - -/* --- LTDC_IER values ----------------------------------------------------- */ - -/* Register Reload Interrupt Enable */ -#define LTDC_IER_RRIE (1 << 3) - -/* Transfer Error Interrupt Enable */ -#define LTDC_IER_TERRIE (1 << 2) - -/* FIFO Underrun Interrupt Enable */ -#define LTDC_IER_FUIE (1 << 1) - -/* Line Interrupt Enable */ -#define LTDC_IER_LIE (1 << 0) - -/* --- LTDC_ISR values ----------------------------------------------------- */ - -/* Register Reload Interrupt Flag */ -#define LTDC_ISR_RRIF (1 << 3) - -/* Transfer Error Interrupt Flag */ -#define LTDC_ISR_TERRIF (1 << 2) - -/* FIFO Underrun Interrupt Flag */ -#define LTDC_ISR_FUIF (1 << 1) - -/* Line Interrupt Flag */ -#define LTDC_ISR_LIF (1 << 0) - -/* --- LTDC_ICR values ----------------------------------------------------- */ - -/* Clears Register Reload Interrupt Flag */ -#define LTDC_ICR_CRRIF (1 << 3) - -/* Clears Transfer Error Interrupt Flag */ -#define LTDC_ICR_CTERRIF (1 << 2) - -/* Clears FIFO Underrun Interrupt Flag */ -#define LTDC_ICR_CFUIF (1 << 1) - -/* Clears Line Interrupt Flag */ -#define LTDC_ICR_CLIF (1 << 0) - -/* --- LTDC_LIPCR values --------------------------------------------------- */ - -/* Line Interrupt Position */ -#define LTDC_LIPCR_LIPOS_SHIFT 0 -#define LTDC_LIPCR_LIPOS_MASK 0x7ff - -/* --- LTDC_CPSR values ---------------------------------------------------- */ - -/* Current X Position */ -#define LTDC_CPSR_CXPOS_SHIFT 16 -#define LTDC_CPSR_CXPOS_MASK 0xffff - -/* Current Y Position */ -#define LTDC_CPSR_CYPOS_SHIFT 0 -#define LTDC_CPSR_CYPOS_MASK 0xffff - -/* LTDC_CDSR - display status register */ -#define LTDC_CDSR_VDES (1<<0) -#define LTDC_CDSR_HDES (1<<1) -#define LTDC_CDSR_VSYNCS (1<<2) -#define LTDC_CDSR_HSYNCS (1<<3) - -/* LTDC_LxCR - layer control */ -#define LTDC_LxCR_LAYER_ENABLE (1<<0) -#define LTDC_LxCR_COLKEY_ENABLE (1<<1) -#define LTDC_LxCR_COLTAB_ENABLE (1<<4) - -/* --- LTDC_LxWHPCR values ------------------------------------------------- */ - -/* Window Horizontal Stop Position */ -#define LTDC_LxWHPCR_WHSPPOS_SHIFT 16 -#define LTDC_LxWHPCR_WHSPPOS_MASK 0xfff - -/* Window Horizontal Start Position */ -#define LTDC_LxWHPCR_WHSTPOS_SHIFT 0 -#define LTDC_LxWHPCR_WHSTPOS_MASK 0xfff - -/* --- LTDC_LxWVPCR values ------------------------------------------------- */ - -/* Window Vertical Stop Position */ -#define LTDC_LxWVPCR_WVSPPOS_SHIFT 16 -#define LTDC_LxWVPCR_WVSPPOS_MASK 0x7ff - -/* Window Vertical Start Position */ -#define LTDC_LxWVPCR_WVSTPOS_SHIFT 0 -#define LTDC_LxWVPCR_WVSTPOS_MASK 0x7ff - -/* --- LTDC_LxCKCR values -------------------------------------------------- */ - -/* Color Key Red */ -#define LTDC_LxCKCR_CKRED_SHIFT 16 -#define LTDC_LxCKCR_CKRED_MASK 0xff - -/* Color Key Green */ -#define LTDC_LxCKCR_CKGREEN_SHIFT 16 -#define LTDC_LxCKCR_CKGREEN_MASK 0xff - -/* Color Key Blue */ -#define LTDC_LxCKCR_CKBLUE_SHIFT 16 -#define LTDC_LxCKCR_CKBLUE_MASK 0xff - -/* LTDC_LxPFCR - Pixel formats */ -#define LTDC_LxPFCR_ARGB8888 (0b000) -#define LTDC_LxPFCR_RGB888 (0b001) -#define LTDC_LxPFCR_RGB565 (0b010) -#define LTDC_LxPFCR_ARGB1555 (0b011) -#define LTDC_LxPFCR_ARGB4444 (0b100) -#define LTDC_LxPFCR_L8 (0b101) -#define LTDC_LxPFCR_AL44 (0b110) -#define LTDC_LxPFCR_AL88 (0b111) - -/* --- LTDC_LxCACR values -------------------------------------------------- */ - -/* Constant Alpha */ -#define LTDC_LxCACR_CONSTA_SHIFT 0 -#define LTDC_LxCACR_CONSTA_MASK 0xff - -/* --- LTDC_LxDCCR values -------------------------------------------------- */ - -/* Default Color Alpha */ -#define LTDC_LxDCCR_DCALPHA_SHIFT 24 -#define LTDC_LxDCCR_DCALPHA_MASK 1 - -/* Default Color Red */ -#define LTDC_LxDCCR_DCRED_SHIFT 16 -#define LTDC_LxDCCR_DCRED_MASK 1 - -/* Default Color Green */ -#define LTDC_LxDCCR_DCGREEN_SHIFT 8 -#define LTDC_LxDCCR_DCGREEN_MASK 1 - -/* Default Color Blue */ -#define LTDC_LxDCCR_DCBLUE_SHIFT 0 -#define LTDC_LxDCCR_DCBLUE_MASK 1 - -/* LTDC_LxBFCR - Blending factors - BF1 */ -#define LTDC_LxBFCR_BF1_CONST_ALPHA (0b100) -#define LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110) -/* LTDC_LxBFCR - Blending factors - BF2 */ -#define LTDC_LxBFCR_BF2_CONST_ALPHA (0b101) -#define LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111) - -/* --- LTDC_LxCFBAR values ------------------------------------------------- */ - -/* Color Frame Buffer Start Address */ -#define LTDC_LxCFBAR_CFBAR_SHIFT 0 -#define LTDC_LxCFBAR_CFBAR_MASK 0xffffffff - -/* --- LTDC_LxCFBLR values ------------------------------------------------- */ - -/* Color Frame Buffer Pitch */ -#define LTDC_LxCFBLR_CFBP_SHIFT 16 -#define LTDC_LxCFBLR_CFBP_MASK 0x1fff - -/* Color Frame Buffer Line Length */ -#define LTDC_LxCFBLR_CFBLL_SHIFT 0 -#define LTDC_LxCFBLR_CFBLL_MASK 0x1fff - -/* --- LTDC_LxCFBLNR values ------------------------------------------------ */ - -/* Frame Buffer Line Number */ -#define LTDC_LxCFBLNR_CFBLNBR_SHIFT 0 -#define LTDC_LxCFBLNR_CFBLNBR_MASK 0x3ff - -/* --- LTDC_LxCLUTWR values ------------------------------------------------ */ - -/* CLUT Address */ -#define LTDC_LxCLUTWR_CLUTADD_SHIFT 24 -#define LTDC_LxCLUTWR_CLUTADD_MASK 0xff - -/* Red */ -#define LTDC_LxCLUTWR_RED_SHIFT 16 -#define LTDC_LxCLUTWR_RED_MASK 0xff - -/* Green */ -#define LTDC_LxCLUTWR_GREEN_SHIFT 8 -#define LTDC_LxCLUTWR_GREEN_MASK 0xff - -/* Blue */ -#define LTDC_LxCLUTWR_BLUE_SHIFT 0 -#define LTDC_LxCLUTWR_BLUE_MASK 0xff - -/** - * simple helper macros - */ - -/* global */ -static inline void ltdc_ctrl_enable(uint32_t ctrl_flags) -{ - LTDC_GCR |= ctrl_flags; -} - -static inline void ltdc_ctrl_disable(uint32_t ctrl_flags) -{ - LTDC_GCR &= ~(ctrl_flags); -} - -static inline void ltdc_reload(uint32_t reload_flags) -{ - LTDC_SRCR = reload_flags; -} - -static inline void ltdc_set_background_color(uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_BCCR = (((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0); -} - -static inline void ltdc_get_current_position(uint16_t *x, uint16_t *y) -{ - uint32_t tmp = LTDC_CPSR; - *x = tmp >> 16; - *y = tmp &= 0xFFFF; -} - -static inline uint16_t ltdc_get_current_position_x(void) -{ - return LTDC_CPSR >> 16; -} - -static inline uint16_t ltdc_get_current_position_y(void) -{ - return LTDC_CPSR & 0xffff; -} - -static inline uint32_t ltdc_get_display_status(uint32_t status_flags) -{ - return LTDC_CDSR & status_flags; -} - -/* layers */ -static inline void ltdc_layer_ctrl_enable(uint32_t layer, uint32_t ctrl_flags) -{ - LTDC_LxCR(layer) |= ctrl_flags; -} - -static inline void ltdc_layer_ctrl_disable(uint32_t layer, uint32_t ctrl_flags) -{ - LTDC_LxCR(layer) &= ~(ctrl_flags); -} - -static inline void ltdc_set_color_key(uint32_t layer, - uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_LxCKCR(layer) = ((((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0)); -} - -static inline void ltdc_set_pixel_format(uint32_t layer, uint32_t format) -{ - LTDC_LxPFCR(layer) = format; -} - -static inline void ltdc_set_constant_alpha(uint32_t layer, uint8_t alpha) -{ - LTDC_LxCACR(layer) = ((alpha)&255); -} - -static inline void ltdc_set_default_colors(uint32_t layer, - uint8_t a, - uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_LxDCCR(layer) = ((((a)&255)<<24) | - (((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0)); -} - -static inline void ltdc_set_blending_factors(uint32_t layer, - uint8_t bf1, uint8_t bf2) -{ - LTDC_LxBFCR(layer) = ((bf1)<<8) | ((bf2)<<0); -} - -static inline void ltdc_set_fbuffer_address(uint32_t layer, uint32_t address) -{ - LTDC_LxCFBAR(layer) = (uint32_t)address; -} - -static inline uint32_t ltdc_get_fbuffer_address(uint32_t layer) -{ - return LTDC_LxCFBAR(layer); -} - -static inline void ltdc_set_fb_line_length(uint32_t layer, - uint16_t len, uint16_t pitch) -{ - LTDC_LxCFBLR(layer) = ((((pitch)&0x1FFF)<<16) | (((len)&0x1FFF)<<0)); -} - -static inline void ltdc_set_fb_line_count(uint32_t layer, uint16_t linecount) -{ - LTDC_LxCFBLNR(layer) = (((linecount)&0x3FF)<<0); -} - -/** - * more complicated helper functions - */ -void ltdc_set_tft_sync_timings( - uint16_t sync_width, uint16_t sync_height, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height, - uint16_t h_front_porch, uint16_t v_front_porch -); -void ltdc_setup_windowing( - uint8_t layer_number, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height -); - - - -/** - * Helper function to wait for SRCR reload to complete or so - */ - -static inline bool LTDC_SRCR_IS_RELOADING(void) -{ - return (LTDC_SRCR & (LTDC_SRCR_RELOAD_VBR | - LTDC_SRCR_RELOAD_IMR)) != 0; -} - -/** - * color conversion helper function - * (simulate the ltdc color conversion) - */ - -static inline uint32_t ltdc_get_rgb888_from_rgb565(uint16_t rgb565) -{ - uint32_t rgb565_32 = (uint32_t)rgb565; - return ((((rgb565_32) & 0xF800) >> (11-8))/31)<<16 - | ((((rgb565_32) & 0x07E0) << (8-5))/63)<<8 - | ((((rgb565_32) & 0x001F) << (8-0))/31)<<0; -} - -/** @cond */ -#endif /* LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ */ -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/pwr_common_v1.h b/libopencm3/include/libopencm3/stm32/common/pwr_common_v1.h deleted file mode 100644 index 524455d..0000000 --- a/libopencm3/include/libopencm3/stm32/common/pwr_common_v1.h +++ /dev/null @@ -1,132 +0,0 @@ -/** @addtogroup pwr_defines - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H -The order of header inclusion is important. pwr.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_PWR_H -/** @endcond */ -#ifndef LIBOPENCM3_PWR_COMMON_V1_H -#define LIBOPENCM3_PWR_COMMON_V1_H - -/**@{*/ - -/* --- PWR registers ------------------------------------------------------- */ - -/** Power control register (PWR_CR) */ -#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) - -/** Power control/status register (PWR_CSR) */ -#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* Bits [31:9]: Reserved, must be kept at reset value. */ - -/** DBP: Disable backup domain write protection */ -#define PWR_CR_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR_PLS_LSB 5 -/** @defgroup pwr_pls PVD level selection -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) -/**@}*/ -#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) - -/** PVDE: Power voltage detector enable */ -#define PWR_CR_PVDE (1 << 4) - -/** CSBF: Clear standby flag */ -#define PWR_CR_CSBF (1 << 3) - -/** CWUF: Clear wakeup flag */ -#define PWR_CR_CWUF (1 << 2) - -/** PDDS: Power down deepsleep */ -#define PWR_CR_PDDS (1 << 1) - -/** LPDS: Low-power deepsleep */ -#define PWR_CR_LPDS (1 << 0) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* Bits [31:9]: Reserved, must be kept at reset value. */ - -/** EWUP: Enable WKUP pin */ -#define PWR_CSR_EWUP (1 << 8) - -/* Bits [7:3]: Reserved, must be kept at reset value. */ - -/** PVDO: PVD output */ -#define PWR_CSR_PVDO (1 << 2) - -/** SBF: Standby flag */ -#define PWR_CSR_SBF (1 << 1) - -/** WUF: Wakeup flag */ -#define PWR_CSR_WUF (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -BEGIN_DECLS - -void pwr_disable_backup_domain_write_protect(void); -void pwr_enable_backup_domain_write_protect(void); -void pwr_enable_power_voltage_detect(uint32_t pvd_level); -void pwr_disable_power_voltage_detect(void); -void pwr_clear_standby_flag(void); -void pwr_clear_wakeup_flag(void); -void pwr_set_standby_mode(void); -void pwr_set_stop_mode(void); -void pwr_voltage_regulator_on_in_stop(void); -void pwr_voltage_regulator_low_power_in_stop(void); -void pwr_enable_wakeup_pin(void); -void pwr_disable_wakeup_pin(void); -bool pwr_voltage_high(void); -bool pwr_get_standby_flag(void); -bool pwr_get_wakeup_flag(void); - -END_DECLS - -/**@}*/ -#endif -/** @cond */ -#else -#warning "pwr_common_v1.h should not be included explicitly, only via pwr.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/pwr_common_v2.h b/libopencm3/include/libopencm3/stm32/common/pwr_common_v2.h deleted file mode 100644 index cd797fa..0000000 --- a/libopencm3/include/libopencm3/stm32/common/pwr_common_v2.h +++ /dev/null @@ -1,98 +0,0 @@ -/** @addtogroup pwr_defines - -@author @htmlonly © @endhtmlonly 2011 Stephen Caudle -@author @htmlonly © @endhtmlonly 2012 Karl Palsson - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Stephen Caudle - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_COMMON_V2_H -#define LIBOPENCM3_PWR_COMMON_V2_H - -#include - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* Bits [31:15]: Reserved */ - -/* LPRUN: Low power run mode */ -#define PWR_CR_LPRUN (1 << 14) - -/* VOS[12:11]: Regulator voltage scaling output selection */ -#define PWR_CR_VOS_LSB 11 -/** @defgroup pwr_vos Voltage Scaling Output level selection -@ingroup pwr_defines - -@{*/ -#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) -/**@}*/ -#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) - -/* FWU: Fast wakeup */ -#define PWR_CR_FWU (1 << 10) - -/* ULP: Ultralow power mode */ -#define PWR_CR_ULP (1 << 9) - -/* LPSDSR: Low-power deepsleep/sleep/low power run */ -#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */ - -/* --- PWR_CSR values ------------------------------------------------------- */ - -/* EWUP2: Enable WKUP2 pin */ -#define PWR_CSR_EWUP2 (1 << 9) - -/* EWUP1: Enable WKUP1 pin */ -#define PWR_CSR_EWUP1 PWR_CSR_EWUP - -/* REGLPF : Regulator LP flag */ -#define PWR_CSR_REGLPF (1 << 5) - -/* VOSF: Voltage Scaling select flag */ -#define PWR_CSR_VOSF (1 << 4) - -/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ -#define PWR_CSR_VREFINTRDYF (1 << 3) - - - -/* --- Function prototypes ------------------------------------------------- */ - -/** Voltage scales for internal regulator - */ -enum pwr_vos_scale { - /** high performance, highest voltage */ - PWR_SCALE1, - /** medium performance, flash operational but slow */ - PWR_SCALE2, - /** low performance, no flash erase/program */ - PWR_SCALE3, -}; - -BEGIN_DECLS - -void pwr_set_vos_scale(enum pwr_vos_scale scale); - -END_DECLS - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h b/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h deleted file mode 100644 index 4983713..0000000 --- a/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h +++ /dev/null @@ -1,79 +0,0 @@ -/** @addtogroup rcc_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RCC.H - * The order of header inclusion is important. rcc.h defines the device - * specific enumerations before including this header file. - */ - -/** @cond */ -#ifdef LIBOPENCM3_RCC_H -/** @endcond */ - -#ifndef LIBOPENCM3_RCC_COMMON_ALL_H -#define LIBOPENCM3_RCC_COMMON_ALL_H - -/**@{*/ - -BEGIN_DECLS - -void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); -void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); -void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); -void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); - -void rcc_periph_clock_enable(enum rcc_periph_clken clken); -void rcc_periph_clock_disable(enum rcc_periph_clken clken); -void rcc_periph_reset_pulse(enum rcc_periph_rst rst); -void rcc_periph_reset_hold(enum rcc_periph_rst rst); -void rcc_periph_reset_release(enum rcc_periph_rst rst); - -void rcc_set_mco(uint32_t mcosrc); -void rcc_osc_bypass_enable(enum rcc_osc osc); -void rcc_osc_bypass_disable(enum rcc_osc osc); - -/** - * Is the given oscillator ready? - * @param osc Oscillator ID - * @return true if the hardware indicates the oscillator is ready. - */ -bool rcc_is_osc_ready(enum rcc_osc osc); - -/** - * Wait for Oscillator Ready. - * Block until the hardware indicates that the Oscillator is ready. - * @param osc Oscillator ID - */ -void rcc_wait_for_osc_ready(enum rcc_osc osc); - -END_DECLS -/**@}*/ - -#endif -/** @cond */ -#else -#warning "rcc_common_all.h should not be included explicitly, only via rcc.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/rng_common_v1.h b/libopencm3/include/libopencm3/stm32/common/rng_common_v1.h deleted file mode 100644 index 66f725a..0000000 --- a/libopencm3/include/libopencm3/stm32/common/rng_common_v1.h +++ /dev/null @@ -1,93 +0,0 @@ -/** @addtogroup rng_file - */ -/* - * This file is part of the libopencm3 project. - * - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H -The order of header inclusion is important. rng.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_RNG_H -/** @endcond */ -#ifndef LIBOPENCM3_RNG_V1_H -#define LIBOPENCM3_RNG_V1_H - -#include -#include - -/**@{*/ - -/* --- Random number generator registers ----------------------------------- */ - -/* Control register */ -#define RNG_CR MMIO32(RNG_BASE + 0x00) - -/* Status register */ -#define RNG_SR MMIO32(RNG_BASE + 0x04) - -/* Data register */ -#define RNG_DR MMIO32(RNG_BASE + 0x08) - -/* --- RNG_CR values ------------------------------------------------------- */ - -/* RNG ENABLE */ -#define RNG_CR_RNGEN (1 << 2) - -/* RNG interrupt enable */ -#define RNG_CR_IE (1 << 3) - -/* --- RNG_SR values ------------------------------------------------------- */ - -/* Data ready */ -#define RNG_SR_DRDY (1 << 0) - -/* Clock error current status */ -#define RNG_SR_CECS (1 << 1) - -/* Seed error current status */ -#define RNG_SR_SECS (1 << 2) - -/* Clock error interrupt status */ -#define RNG_SR_CEIS (1 << 5) - -/* Seed error interrupt status */ -#define RNG_SR_SEIS (1 << 6) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void rng_enable(void); -void rng_disable(void); -void rng_interrupt_enable(void); -void rng_interrupt_disable(void); -bool rng_get_random(uint32_t *rand_nr); -uint32_t rng_get_random_blocking(void); - -END_DECLS - -/**@}*/ - -#endif -/** @cond */ -#else -#warning "rng_common_v1.h should not be included explicitly, only via rng.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h b/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h deleted file mode 100644 index d854320..0000000 --- a/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h +++ /dev/null @@ -1,449 +0,0 @@ -/** @addtogroup rtc_defines - -@author @htmlonly © @endhtmlonly 2012 Karl Palsson - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This covers the "version 2" RTC peripheral. This is completely different - * to the v1 RTC periph on the F1 series devices. It has BCD counters, with - * automatic leapyear corrections and daylight savings support. - * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some - * only support a subset. - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H -The order of header inclusion is important. rtc.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_RTC_H -/** @endcond */ -#ifndef LIBOPENCM3_RTC2_H -#define LIBOPENCM3_RTC2_H - -/** @defgroup rtc_registers RTC Registers - * @ingroup rtc_defines - * @brief Real Time Clock registers -@{*/ - -/** RTC time register (RTC_TR) */ -#define RTC_TR MMIO32(RTC_BASE + 0x00) - -/** RTC date register (RTC_DR) */ -#define RTC_DR MMIO32(RTC_BASE + 0x04) - -/** RTC control register (RTC_CR) */ -#define RTC_CR MMIO32(RTC_BASE + 0x08) - -/** RTC initialization and status register (RTC_ISR) */ -#define RTC_ISR MMIO32(RTC_BASE + 0x0c) - -/** RTC prescaler register (RTC_PRER) */ -#define RTC_PRER MMIO32(RTC_BASE + 0x10) - -/** RTC wakeup timer register (RTC_WUTR) */ -#define RTC_WUTR MMIO32(RTC_BASE + 0x14) - -/** RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */ -#define RTC_CALIBR MMIO32(RTC_BASE + 0x18) - -/** RTC alarm X register (RTC_ALRMxR) */ -#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c) -#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20) - -/** RTC write protection register (RTC_WPR)*/ -#define RTC_WPR MMIO32(RTC_BASE + 0x24) - -/** RTC sub second register (RTC_SSR) (high and med+ only) */ -#define RTC_SSR MMIO32(RTC_BASE + 0x28) - -/** RTC shift control register (RTC_SHIFTR) (high and med+ only) */ -#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c) - -/** RTC time stamp time register (RTC_TSTR) */ -#define RTC_TSTR MMIO32(RTC_BASE + 0x30) -/** RTC time stamp date register (RTC_TSDR) */ -#define RTC_TSDR MMIO32(RTC_BASE + 0x34) -/** RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */ -#define RTC_TSSSR MMIO32(RTC_BASE + 0x38) - -/** RTC calibration register (RTC_CALR) (high and med+ only) */ -#define RTC_CALR MMIO32(RTC_BASE + 0x3c) - -/** RTC tamper and alternate function configuration register (RTC_TAFCR) */ -#define RTC_TAFCR MMIO32(RTC_BASE + 0x40) - -/** RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */ -#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44) -#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48) - -#define RTC_BKP_BASE (RTC_BASE + 0x50) -/** RTC backup registers (RTC_BKPxR) */ -#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg))) - -/*@}*/ - - -/** @defgroup rtc_tr_values RTC Time register (RTC_TR) values - * @ingroup rtc_registers - * Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. -@{*/ -/** AM/PM notation */ -#define RTC_TR_PM (1 << 22) -/** Hour tens in BCD format shift */ -#define RTC_TR_HT_SHIFT (20) -/** Hour tens in BCD format mask */ -#define RTC_TR_HT_MASK (0x3) -/** Hour units in BCD format shift */ -#define RTC_TR_HU_SHIFT (16) -/** Hour units in BCD format mask */ -#define RTC_TR_HU_MASK (0xf) -/** Minute tens in BCD format shift */ -#define RTC_TR_MNT_SHIFT (12) -/** Minute tens in BCD format mask */ -#define RTC_TR_MNT_MASK (0x7) -/** Minute units in BCD format shift */ -#define RTC_TR_MNU_SHIFT (8) -/** Minute units in BCD format mask */ -#define RTC_TR_MNU_MASK (0xf) -/** Second tens in BCD format shift */ -#define RTC_TR_ST_SHIFT (4) -/** Second tens in BCD format mask */ -#define RTC_TR_ST_MASK (0x7) -/** Second units in BCD format shift */ -#define RTC_TR_SU_SHIFT (0) -/** Second units in BCD format mask */ -#define RTC_TR_SU_MASK (0xf) -/*@}*/ - -/** @defgroup rtc_dr_values RTC Date register (RTC_DR) values - * @ingroup rtc_registers - * Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. -@{*/ -/** Year tens in BCD format shift */ -#define RTC_DR_YT_SHIFT (20) -/** Year tens in BCD format mask */ -#define RTC_DR_YT_MASK (0xf) -/** Year units in BCD format shift */ -#define RTC_DR_YU_SHIFT (16) -/** Year units in BCD format mask */ -#define RTC_DR_YU_MASK (0xf) -/** Weekday units shift */ -#define RTC_DR_WDU_SHIFT (13) -/** Weekday units mask */ -#define RTC_DR_WDU_MASK (0x7) -/** Month tens in BCD format shift */ -#define RTC_DR_MT_SHIFT (12) -/** Month tens in BCD format mask */ -#define RTC_DR_MT_MASK (1) -/** Month units in BCD format shift */ -#define RTC_DR_MU_SHIFT (8) -/** Month units in BCD format mask */ -#define RTC_DR_MU_MASK (0xf) -/** Date tens in BCD format shift */ -#define RTC_DR_DT_SHIFT (4) -/** Date tens in BCD format mask */ -#define RTC_DR_DT_MASK (0x3) -/** Date units in BCD format shift */ -#define RTC_DR_DU_SHIFT (0) -/** Date units in BCD format mask */ -#define RTC_DR_DU_MASK (0xf) -/*@}*/ - -/** @defgroup rtc_cr_values RTC control register (RTC_CR) values - * @ingroup rtc_registers - * Note: Bits [31:24] are reserved, and must be kept at reset value. - * Note: Bits 7, 6 and 4 of this register can be written in initialization mode - * only (RTC_ISR/INITF = 1). -@{*/ -/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit - * = 0 and RTC_ISR WUTWF bit = 1. - */ -/** Calibration output enable */ -#define RTC_CR_COE (1<<23) - -#define RTC_CR_OSEL_SHIFT 21 -#define RTC_CR_OSEL_MASK (0x3) -/** @defgroup rtc_cr_osel RTC_CR_OSEL: Output selection values - * @ingroup rtc_cr_values - * These bits are used to select the flag to be routed to AFO_ALARM RTC output -@{*/ -#define RTC_CR_OSEL_DISABLED (0x0) -#define RTC_CR_OSEL_ALARMA (0x1) -#define RTC_CR_OSEL_ALARMB (0x2) -#define RTC_CR_OSEL_WAKEUP (0x3) -/*@}*/ - -/** Output polarity */ -#define RTC_CR_POL (1<<20) -/** Calibration output selection */ -#define RTC_CR_COSEL (1<<19) -/** Backup */ -#define RTC_CR_BKP (1<<18) -/** Subtract 1 hour (winter time change) */ -#define RTC_CR_SUB1H (1<<17) -/** Add 1 hour (summer time change) */ -#define RTC_CR_ADD1H (1<<16) -/** Timestamp interrupt enable */ -#define RTC_CR_TSIE (1<<15) -/** Wakeup timer interrupt enable */ -#define RTC_CR_WUTIE (1<<14) -/** Alarm B interrupt enable */ -#define RTC_CR_ALRBIE (1<<13) -/** Alarm A interrupt enable */ -#define RTC_CR_ALRAIE (1<<12) -/** Time stamp enable */ -#define RTC_CR_TSE (1<<11) -/** Wakeup timer enable */ -#define RTC_CR_WUTE (1<<10) -/** Alarm B enable */ -#define RTC_CR_ALRBE (1<<9) -/** Alarm A enable */ -#define RTC_CR_ALRAE (1<<8) -/** Course digital calibration enable */ -#define RTC_CR_DCE (1<<7) -/** Hour format */ -#define RTC_CR_FMT (1<<6) -/** Bypass the shadow registers */ -#define RTC_CR_BYPSHAD (1<<5) -/** Reference clock detection enable */ -#define RTC_CR_REFCKON (1<<4) -/** Timestamp event active edge */ -#define RTC_CR_TSEDGE (1<<3) - -/* RTC_CR_WUCKSEL: Wakeup clock selection */ -#define RTC_CR_WUCLKSEL_SHIFT (0) -#define RTC_CR_WUCLKSEL_MASK (0x7) -#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0) -#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1) -#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2) -#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3) -#define RTC_CR_WUCLKSEL_SPRE (0x4) -#define RTC_CR_WUCLKSEL_SPRE_216 (0x6) -/*@}*/ - -/** @defgroup rtc_isr_values RTC initialization and status register (RTC_ISR) values - * @ingroup rtc_registers - * Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. - * Note: This register is write protected (except for RTC_ISR[13:8] bits). -@{*/ -/** RECALPF: Recalib pending flag */ -#define RTC_ISR_RECALPF (1<<16) -/** TAMP3F: TAMPER3 detection flag (not on F4)*/ -#define RTC_ISR_TAMP3F (1<<15) -/** TAMP2F: TAMPER2 detection flag */ -#define RTC_ISR_TAMP2F (1<<14) -/** TAMP1F: TAMPER detection flag */ -#define RTC_ISR_TAMP1F (1<<13) -/** TSOVF: Timestamp overflow flag */ -#define RTC_ISR_TSOVF (1<<12) -/** TSF: Timestamp flag */ -#define RTC_ISR_TSF (1<<11) -/** WUTF: Wakeup timer flag */ -#define RTC_ISR_WUTF (1<<10) -/** ALRBF: Alarm B flag */ -#define RTC_ISR_ALRBF (1<<9) -/** ALRAF: Alarm A flag */ -#define RTC_ISR_ALRAF (1<<8) -/** INIT: Initialization mode */ -#define RTC_ISR_INIT (1<<7) -/** INITF: Initialization flag */ -#define RTC_ISR_INITF (1<<6) -/** RSF: Registers sync flag */ -#define RTC_ISR_RSF (1<<5) -/** INITS: Init status flag */ -#define RTC_ISR_INITS (1<<4) -/** SHPF: Shift operation pending */ -#define RTC_ISR_SHPF (1<<3) -/** WUTWF: Wakeup timer write flag */ -#define RTC_ISR_WUTWF (1<<2) -/** ALRBWF: Alarm B write flag */ -#define RTC_ISR_ALRBWF (1<<1) -/** ALRAWF: Alarm A write flag */ -#define RTC_ISR_ALRAWF (1<<0) -/*@}*/ - -/** @defgroup rtc_prer_values RTC prescaler register (RTC_PRER) values - * @ingroup rtc_registers -@{*/ -/** Async prescaler factor shift */ -#define RTC_PRER_PREDIV_A_SHIFT (16) -/** Async prescaler factor mask */ -#define RTC_PRER_PREDIV_A_MASK (0x7f) -/** Sync prescaler factor shift */ -#define RTC_PRER_PREDIV_S_SHIFT (0) -/** Sync prescaler factor mask */ -#define RTC_PRER_PREDIV_S_MASK (0x7fff) -/*@}*/ - -/* RTC calibration register (RTC_CALIBR) ------------------------ */ -#define RTC_CALIBR_DCS (1 << 7) - -#define RTC_CALIBR_DC_SHIFT (0) -#define RTC_CALIBR_DC_MASK (0x1f) - -/** @defgroup rtc_alarm_values RTC Alarm register values - * @ingroup rtc_registers - * Applies to RTC_ALRMAR and RTC_ALRMBR -@{*/ -#define RTC_ALRMXR_MSK4 (1<<31) -#define RTC_ALRMXR_WDSEL (1<<30) -#define RTC_ALRMXR_DT_SHIFT (28) -#define RTC_ALRMXR_DT_MASK (0x3) -#define RTC_ALRMXR_DU_SHIFT (24) -#define RTC_ALRMXR_DU_MASK (0xf) -#define RTC_ALRMXR_MSK3 (1<<23) -#define RTC_ALRMXR_PM (1<<22) -#define RTC_ALRMXR_HT_SHIFT (20) -#define RTC_ALRMXR_HT_MASK (0x3) -#define RTC_ALRMXR_HU_SHIFT (16) -#define RTC_ALRMXR_HU_MASK (0xf) -#define RTC_ALRMXR_MSK2 (1<<15) -#define RTC_ALRMXR_MNT_SHIFT (12) -#define RTC_ALRMXR_MNT_MASK (0x7) -#define RTC_ALRMXR_MNU_SHIFT (8) -#define RTC_ALRMXR_MNU_MASK (0xf) -#define RTC_ALRMXR_MSK1 (1<<7) -#define RTC_ALRMXR_ST_SHIFT (4) -#define RTC_ALRMXR_ST_MASK (0x7) -#define RTC_ALRMXR_SU_SHIFT (0) -#define RTC_ALRMXR_SU_MASK (0xf) -/*@}*/ - -/* RTC shift control register (RTC_SHIFTR) ---------------------- */ -#define RTC_SHIFTR_ADD1S (31) - -#define RTC_SHIFTR_SUBFS_SHIFT (0) -#define RTC_SHIFTR_SUBFS_MASK (0x7fff) - -/** @defgroup rtc_tstr_values RTC time stamp time register (RTC_TSTR) values - * @ingroup rtc_registers -@{*/ -#define RTC_TSTR_PM (1<<22) -#define RTC_TSTR_HT_SHIFT (20) -#define RTC_TSTR_HT_MASK (0x3) -#define RTC_TSTR_HU_SHIFT (16) -#define RTC_TSTR_HU_MASK (0xf) -#define RTC_TSTR_MNT_SHIFT (12) -#define RTC_TSTR_MNT_MASK (0x7) -#define RTC_TSTR_MNU_SHIFT (8) -#define RTC_TSTR_MNU_MASK (0xf) -#define RTC_TSTR_ST_SHIFT (4) -#define RTC_TSTR_ST_MASK (0x7) -#define RTC_TSTR_SU_SHIFT (0) -#define RTC_TSTR_SU_MASK (0xf) -/*@}*/ - -/** @defgroup rtc_tsdr_values RTC time stamp date register (RTC_TSDR) values - * @ingroup rtc_registers -@{*/ -#define RTC_TSDR_WDU_SHIFT (13) -#define RTC_TSDR_WDU_MASK (0x7) -#define RTC_TSDR_MT (1<<12) -#define RTC_TSDR_MU_SHIFT (8) -#define RTC_TSDR_MU_MASK (0xf) -#define RTC_TSDR_DT_SHIFT (4) -#define RTC_TSDR_DT_MASK (0x3) -#define RTC_TSDR_DU_SHIFT (0) -#define RTC_TSDR_DU_MASK (0xf) -/*@}*/ - -/** @defgroup rtc_calr_values RTC calibration register (RTC_CALR) values - * @ingroup rtc_registers -@{*/ -#define RTC_CALR_CALP (1 << 15) -#define RTC_CALR_CALW8 (1 << 14) -#define RTC_CALR_CALW16 (1 << 13) -#define RTC_CALR_CALM_SHIFT (0) -#define RTC_CALR_CALM_MASK (0x1ff) -/*@}*/ - -/** @defgroup rtc_tafcr_values RTC tamper and alternate function configuration register (RTC_TAFCR) values - * @ingroup rtc_registers -@{*/ -#define RTC_TAFCR_ALARMOUTTYPE (1<<18) -#define RTC_TAFCR_TAMPPUDIS (1<<15) - -#define RTC_TAFCR_TAMPPRCH_SHIFT (13) -#define RTC_TAFCR_TAMPPRCH_MASK (0x3) -#define RTC_TAFCR_TAMPPRCH_1RTC (0x0) -#define RTC_TAFCR_TAMPPRCH_2RTC (0x1) -#define RTC_TAFCR_TAMPPRCH_4RTC (0x2) -#define RTC_TAFCR_TAMPPRCH_8RTC (0x3) - -#define RTC_TAFCR_TAMPFLT_SHIFT (11) -#define RTC_TAFCR_TAMPFLT_MASK (0x3) -#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0) -#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1) -#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2) -#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3) - -#define RTC_TAFCR_TAMPFREQ_SHIFT (8) -#define RTC_TAFCR_TAMPFREQ_MASK (0x7) -#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0) -#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1) -#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2) -#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3) -#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4) -#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5) -#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6) -#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7) - -#define RTC_TAFCR_TAMPTS (1<<7) -#define RTC_TAFCR_TAMP3TRG (1<<6) -#define RTC_TAFCR_TAMP3E (1<<5) -#define RTC_TAFCR_TAMP2TRG (1<<4) -#define RTC_TAFCR_TAMP2E (1<<3) -#define RTC_TAFCR_TAMPIE (1<<2) -#define RTC_TAFCR_TAMP1TRG (1<<1) -#define RTC_TAFCR_TAMP1E (1<<0) -/*@}*/ - -/* RTC alarm X sub second register ------------------------------ */ -/* Note: Applies to RTC_ALRMASSR and RTC_ALRMBSSR */ -#define RTC_ALRMXSSR_MASKSS_SHIFT (24) -#define RTC_ALARXSSR_MASKSS_MASK (0xf) - -#define RTC_ALRMXSSR_SS_SHIFT (0) -#define RTC_ALARXSSR_SS_MASK (0x7fff) - - -BEGIN_DECLS - -void rtc_set_prescaler(uint32_t sync, uint32_t async); -void rtc_wait_for_synchro(void); -void rtc_lock(void); -void rtc_unlock(void); -void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel); -void rtc_clear_wakeup_flag(void); - -END_DECLS -/**@}*/ - -#endif /* RTC2_H */ -/** @cond */ -#else -#warning "rtc_common_l1f024.h should not be included explicitly, only via rtc.h" -#endif -/** @endcond */ - - diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_all.h b/libopencm3/include/libopencm3/stm32/common/spi_common_all.h deleted file mode 100644 index da19e62..0000000 --- a/libopencm3/include/libopencm3/stm32/common/spi_common_all.h +++ /dev/null @@ -1,402 +0,0 @@ -/** @addtogroup spi_defines - * - * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H -The order of header inclusion is important. spi.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_SPI_H) -/** @endcond */ -#ifndef LIBOPENCM3_SPI_COMMON_ALL_H -#define LIBOPENCM3_SPI_COMMON_ALL_H - -/**@{*/ - -/* Registers can be accessed as 16bit or 32bit values. */ - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup spi_reg_base SPI Register base address -@ingroup spi_defines - -@{*/ -#define SPI1 SPI1_BASE -#define SPI2 SPI2_BASE -#define SPI3 SPI3_BASE -#define SPI4 SPI4_BASE -#define SPI5 SPI5_BASE -#define SPI6 SPI6_BASE -/**@}*/ - -/* --- SPI registers ------------------------------------------------------- */ - -/* Control register 1 (SPIx_CR1) */ -/* Note: Not used in I2S mode. */ -#define SPI_CR1(spi_base) MMIO32((spi_base) + 0x00) -#define SPI1_CR1 SPI_CR1(SPI1_BASE) -#define SPI2_CR1 SPI_CR1(SPI2_BASE) -#define SPI3_CR1 SPI_CR1(SPI3_BASE) - -/* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32((spi_base) + 0x04) -#define SPI1_CR2 SPI_CR2(SPI1_BASE) -#define SPI2_CR2 SPI_CR2(SPI2_BASE) -#define SPI3_CR2 SPI_CR2(SPI3_BASE) - -/* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32((spi_base) + 0x08) -#define SPI1_SR SPI_SR(SPI1_BASE) -#define SPI2_SR SPI_SR(SPI2_BASE) -#define SPI3_SR SPI_SR(SPI3_BASE) - -/* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32((spi_base) + 0x0c) -#define SPI1_DR SPI_DR(SPI1_BASE) -#define SPI2_DR SPI_DR(SPI2_BASE) -#define SPI3_DR SPI_DR(SPI3_BASE) - -/* CRC polynomial register (SPIx_CRCPR) */ -/* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10) -#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) -#define SPI2_CRCPR SPI_CRCPR(SPI2_BASE) -#define SPI3_CRCPR SPI_CRCPR(SPI3_BASE) - -/* RX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14) -#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) -#define SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE) -#define SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE) - -/* TX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18) -#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) -#define SPI2_TXCRCR SPI_TXCRCR(SPI2_BASE) -#define SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE) - -/* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c) -#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) -#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE) -#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE) - -/* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20) -#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) -#define SPI2_I2SPR SPI_I2SPR(SPI2_BASE) -#define SPI3_I2SPR SPI_I2SPR(SPI3_BASE) - -/* --- SPI_CR1 values ------------------------------------------------------ */ - -/* Note: None of the CR1 bits are used in I2S mode. */ - -/* BIDIMODE: Bidirectional data mode enable */ -#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) -#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) -#define SPI_CR1_BIDIMODE (1 << 15) - -/* BIDIOE: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIOE (1 << 14) - -/* CRCEN: Hardware CRC calculation enable */ -#define SPI_CR1_CRCEN (1 << 13) - -/* CRCNEXT: Transmit CRC next */ -#define SPI_CR1_CRCNEXT (1 << 12) - -/* RXONLY: Receive only */ -#define SPI_CR1_RXONLY (1 << 10) - -/* SSM: Software slave management */ -#define SPI_CR1_SSM (1 << 9) - -/* SSI: Internal slave select */ -#define SPI_CR1_SSI (1 << 8) - -/* LSBFIRST: Frame format */ -/****************************************************************************/ -/** @defgroup spi_lsbfirst SPI lsb/msb first -@ingroup spi_defines - -@{*/ -#define SPI_CR1_MSBFIRST (0 << 7) -#define SPI_CR1_LSBFIRST (1 << 7) -/**@}*/ - -/* SPE: SPI enable */ -#define SPI_CR1_SPE (1 << 6) - -/* BR[2:0]: Baud rate control */ -/****************************************************************************/ -/** @defgroup spi_baudrate SPI peripheral baud rates -@ingroup spi_defines - -@{*/ -#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) -/**@}*/ -/****************************************************************************/ -/** @defgroup spi_br_pre SPI peripheral baud rate prescale values -@ingroup spi_defines - -@{*/ -#define SPI_CR1_BR_FPCLK_DIV_2 0x0 -#define SPI_CR1_BR_FPCLK_DIV_4 0x1 -#define SPI_CR1_BR_FPCLK_DIV_8 0x2 -#define SPI_CR1_BR_FPCLK_DIV_16 0x3 -#define SPI_CR1_BR_FPCLK_DIV_32 0x4 -#define SPI_CR1_BR_FPCLK_DIV_64 0x5 -#define SPI_CR1_BR_FPCLK_DIV_128 0x6 -#define SPI_CR1_BR_FPCLK_DIV_256 0x7 -/**@}*/ - -/* MSTR: Master selection */ -#define SPI_CR1_MSTR (1 << 2) - -/* CPOL: Clock polarity */ -/****************************************************************************/ -/** @defgroup spi_cpol SPI clock polarity -@ingroup spi_defines - -@{*/ -#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) -#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) -/**@}*/ -#define SPI_CR1_CPOL (1 << 1) - -/* CPHA: Clock phase */ -/****************************************************************************/ -/** @defgroup spi_cpha SPI clock phase -@ingroup spi_defines - -@{*/ -#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) -#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) -/**@}*/ -#define SPI_CR1_CPHA (1 << 0) - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ - -/* TXEIE: Tx buffer empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) - -/* RXNEIE: Rx buffer not empty interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) - -/* ERRIE: Error interrupt enable */ -#define SPI_CR2_ERRIE (1 << 5) - -/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ - -/* SSOE: SS output enable */ -/* Note: Not used in I2S mode. */ -#define SPI_CR2_SSOE (1 << 2) - -/* TXDMAEN: Tx buffer DMA enable */ -#define SPI_CR2_TXDMAEN (1 << 1) - -/* RXDMAEN: Rx buffer DMA enable */ -#define SPI_CR2_RXDMAEN (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ - -/* BSY: Busy flag */ -#define SPI_SR_BSY (1 << 7) - -/* OVR: Overrun flag */ -#define SPI_SR_OVR (1 << 6) - -/* MODF: Mode fault */ -/* Note: Not used in I2S mode. */ -#define SPI_SR_MODF (1 << 5) - -/* CRCERR: CRC error flag */ -/* Note: Not used in I2S mode. */ -#define SPI_SR_CRCERR (1 << 4) - -/* UDR: Underrun flag */ -/* Note: Not used in SPI mode. */ -#define SPI_SR_UDR (1 << 3) - -/* CHSIDE: Channel side */ -/* Note: Not used in SPI mode. No meaning in PCM mode. */ -#define SPI_SR_CHSIDE (1 << 2) - -/* TXE: Transmit buffer empty */ -#define SPI_SR_TXE (1 << 1) - -/* RXNE: Receive buffer not empty */ -#define SPI_SR_RXNE (1 << 0) - -/* --- SPI_DR values ------------------------------------------------------- */ - -/* SPI_DR[15:0]: Data Register. */ - -/* --- SPI_CRCPR values ---------------------------------------------------- */ - -/* Note: Not used in I2S mode. */ -/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ - -/* --- SPI_RXCRCR values --------------------------------------------------- */ - -/* Note: Not used in I2S mode. */ -/* SPI_RXCRCR [15:0]: RX CRC Register. */ - -/* --- SPI_TXCRCR values --------------------------------------------------- */ - -/* Note: Not used in I2S mode. */ -/* SPI_TXCRCR [15:0]: TX CRC Register. */ - -/* --- SPI_I2SCFGR values -------------------------------------------------- */ - -/* Note: None of these bits are used in SPI mode. */ - -/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ - -/* I2SMOD: I2S mode selection */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) - -/* I2SE: I2S enable */ -#define SPI_I2SCFGR_I2SE (1 << 10) - -/* I2SCFG[9:8]: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_LSB 8 -#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 -#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 -#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 -#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 - -/* PCMSYNC: PCM frame synchronization */ -#define SPI_I2SCFGR_PCMSYNC (1 << 7) - -/* Bit 6: Reserved. Forced to 0 by hardware. */ - -/* I2SSTD[5:4]: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_LSB 4 -#define SPI_I2SCFGR_I2SSTD_I2S_PHILIPS 0x0 -#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 -#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 -#define SPI_I2SCFGR_I2SSTD_PCM 0x3 - -/* CKPOL: Steady state clock polarity */ -#define SPI_I2SCFGR_CKPOL (1 << 3) - -/* DATLEN[2:1]: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_LSB 1 -#define SPI_I2SCFGR_DATLEN_16BIT 0x0 -#define SPI_I2SCFGR_DATLEN_24BIT 0x1 -#define SPI_I2SCFGR_DATLEN_32BIT 0x2 - -/* CHLEN: Channel length */ -#define SPI_I2SCFGR_CHLEN (1 << 0) - -/* --- SPI_I2SPR values ---------------------------------------------------- */ - -/* Note: None of these bits are used in SPI mode. */ - -/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ - -/* MCKOE: Master clock output enable */ -#define SPI_I2SPR_MCKOE (1 << 9) - -/* ODD: Odd factor for the prescaler */ -#define SPI_I2SPR_ODD (1 << 8) - -/* I2SDIV[7:0]: I2S linear prescaler */ -/* 0 and 1 are forbidden values */ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void spi_reset(uint32_t spi_peripheral); -void spi_enable(uint32_t spi); -void spi_disable(uint32_t spi); -uint16_t spi_clean_disable(uint32_t spi); -void spi_write(uint32_t spi, uint16_t data); -void spi_send(uint32_t spi, uint16_t data); -uint16_t spi_read(uint32_t spi); -uint16_t spi_xfer(uint32_t spi, uint16_t data); -void spi_set_bidirectional_mode(uint32_t spi); -void spi_set_unidirectional_mode(uint32_t spi); -void spi_set_bidirectional_receive_only_mode(uint32_t spi); -void spi_set_bidirectional_transmit_only_mode(uint32_t spi); -void spi_enable_crc(uint32_t spi); -void spi_disable_crc(uint32_t spi); -void spi_set_next_tx_from_buffer(uint32_t spi); -void spi_set_next_tx_from_crc(uint32_t spi); -void spi_set_full_duplex_mode(uint32_t spi); -void spi_set_receive_only_mode(uint32_t spi); -void spi_disable_software_slave_management(uint32_t spi); -void spi_enable_software_slave_management(uint32_t spi); -void spi_set_nss_high(uint32_t spi); -void spi_set_nss_low(uint32_t spi); -void spi_send_lsb_first(uint32_t spi); -void spi_send_msb_first(uint32_t spi); -void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate); -void spi_set_master_mode(uint32_t spi); -void spi_set_slave_mode(uint32_t spi); -void spi_set_clock_polarity_1(uint32_t spi); -void spi_set_clock_polarity_0(uint32_t spi); -void spi_set_clock_phase_1(uint32_t spi); -void spi_set_clock_phase_0(uint32_t spi); -void spi_enable_tx_buffer_empty_interrupt(uint32_t spi); -void spi_disable_tx_buffer_empty_interrupt(uint32_t spi); -void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi); -void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi); -void spi_enable_error_interrupt(uint32_t spi); -void spi_disable_error_interrupt(uint32_t spi); -void spi_enable_ss_output(uint32_t spi); -void spi_disable_ss_output(uint32_t spi); -void spi_enable_tx_dma(uint32_t spi); -void spi_disable_tx_dma(uint32_t spi); -void spi_enable_rx_dma(uint32_t spi); -void spi_disable_rx_dma(uint32_t spi); -void spi_set_standard_mode(uint32_t spi, uint8_t mode); - -END_DECLS - -/**@}*/ - -#endif -/** @cond */ -#else -#warning "spi_common_all.h should not be included explicitly, only via spi.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_v1.h b/libopencm3/include/libopencm3/stm32/common/spi_common_v1.h deleted file mode 100644 index 2ce31b8..0000000 --- a/libopencm3/include/libopencm3/stm32/common/spi_common_v1.h +++ /dev/null @@ -1,69 +0,0 @@ -/** @addtogroup spi_defines - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H -The order of header inclusion is important. spi.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_SPI_H -/** @endcond */ -#pragma once - -/**@{*/ - -#include - -/* DFF: Data frame format */ -/****************************************************************************/ -/** @defgroup spi_dff SPI data frame format -@ingroup spi_defines - -@{*/ - -#define SPI_CR1_DFF_8BIT (0 << 11) -#define SPI_CR1_DFF_16BIT (1 << 11) - -/**@}*/ - -#define SPI_CR1_DFF (1 << 11) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, - uint32_t dff, uint32_t lsbfirst); -void spi_set_dff_8bit(uint32_t spi); -void spi_set_dff_16bit(uint32_t spi); - -END_DECLS - -/** @cond */ -#else -#warning "spi_common_v1.h should not be included explicitly, only via spi.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_v1_frf.h b/libopencm3/include/libopencm3/stm32/common/spi_common_v1_frf.h deleted file mode 100644 index 18453a3..0000000 --- a/libopencm3/include/libopencm3/stm32/common/spi_common_v1_frf.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @addtogroup spi_defines - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H -The order of header inclusion is important. spi.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_SPI_H -/** @endcond */ -#pragma once - -/**@{*/ - -#include - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* FRF: Frame format */ -/* Note: Not used in I2S mode. */ -#define SPI_CR2_FRF (1 << 4) -#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) -#define SPI_CR2_FRF_TI_MODE (1 << 4) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* FRE / TIFRFE: TI frame format error */ -#define SPI_SR_TIFRFE (1 << 8) //F2 -#define SPI_SR_FRE (1 << 8) //others - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void spi_set_frf_ti(uint32_t spi); -void spi_set_frf_motorola(uint32_t spi); - -END_DECLS - -/** @cond */ -#else -#warning "spi_common_v1_frf.h should not be included explicitly, only via spi.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_v2.h b/libopencm3/include/libopencm3/stm32/common/spi_common_v2.h deleted file mode 100644 index dd81b6c..0000000 --- a/libopencm3/include/libopencm3/stm32/common/spi_common_v2.h +++ /dev/null @@ -1,132 +0,0 @@ -/** @addtogroup spi_defines - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H -The order of header inclusion is important. spi.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_SPI_H -/** @endcond */ -#pragma once - -/**@{*/ - -#include - -#define SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c) -#define SPI1_DR8 SPI_DR8(SPI1_BASE) -#define SPI2_DR8 SPI_DR8(SPI2_BASE) -#define SPI3_DR8 SPI_DR8(SPI3_BASE) - -/* CRCL: CRC Length */ -/****************************************************************************/ -/** @defgroup spi_crcl SPI crc length - * @ingroup spi_defines - * - * @{*/ - -#define SPI_CR1_CRCL_8BIT (0 << 11) -#define SPI_CR1_CRCL_16BIT (1 << 11) -/**@}*/ -#define SPI_CR1_CRCL (1 << 11) - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* LDMA_TX: Last DMA transfer for transmission */ -#define SPI_CR2_LDMA_TX (1 << 14) - -/* LDMA_RX: Last DMA transfer for reception */ -#define SPI_CR2_LDMA_RX (1 << 13) - -/* FRXTH: FIFO reception threshold */ -#define SPI_CR2_FRXTH (1 << 12) - -/* FRF: Frame format */ -/* Note: Not used in I2S mode. */ -#define SPI_CR2_FRF (1 << 4) -#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) -#define SPI_CR2_FRF_TI_MODE (1 << 4) - -/* DS: Data size */ -/****************************************************************************/ -/** @defgroup spi_ds SPI data size - * @ingroup spi_defines - * - * @{*/ -#define SPI_CR2_DS_4BIT (0x3 << 8) -#define SPI_CR2_DS_5BIT (0x4 << 8) -#define SPI_CR2_DS_6BIT (0x5 << 8) -#define SPI_CR2_DS_7BIT (0x6 << 8) -#define SPI_CR2_DS_8BIT (0x7 << 8) -#define SPI_CR2_DS_9BIT (0x8 << 8) -#define SPI_CR2_DS_10BIT (0x9 << 8) -#define SPI_CR2_DS_11BIT (0xA << 8) -#define SPI_CR2_DS_12BIT (0xB << 8) -#define SPI_CR2_DS_13BIT (0xC << 8) -#define SPI_CR2_DS_14BIT (0xD << 8) -#define SPI_CR2_DS_15BIT (0xE << 8) -#define SPI_CR2_DS_16BIT (0xF << 8) -/**@}*/ -#define SPI_CR2_DS_MASK (0xF << 8) - -/* NSSP: NSS pulse management */ -#define SPI_CR2_NSSP (1 << 3) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* FTLVL[1:0]: FIFO Transmission Level */ -#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) -#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) -#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) -#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) - -/* FRLVL[1:0]: FIFO Reception Level */ -#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) -#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) -#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) -#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) - -/* FRE : TI frame format error */ -#define SPI_SR_FRE (1 << 8) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS -int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, - uint32_t lsbfirst); -void spi_set_crcl_8bit(uint32_t spi); -void spi_set_crcl_16bit(uint32_t spi); -void spi_set_data_size(uint32_t spi, uint16_t data_s); -void spi_fifo_reception_threshold_8bit(uint32_t spi); -void spi_fifo_reception_threshold_16bit(uint32_t spi); -void spi_i2s_mode_spi_mode(uint32_t spi); -void spi_send8(uint32_t spi, uint8_t data); -uint8_t spi_read8(uint32_t spi); - -END_DECLS - -/** @cond */ -#else -#warning "spi_common_v2.h should not be included explicitly, only via spi.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/st_usbfs_common.h b/libopencm3/include/libopencm3/stm32/common/st_usbfs_common.h deleted file mode 100644 index 874aa50..0000000 --- a/libopencm3/include/libopencm3/stm32/common/st_usbfs_common.h +++ /dev/null @@ -1,302 +0,0 @@ -/** @defgroup usb_defines USB Defines - -@brief Defined Constants and Types for the STM32F* USB drivers - -@ingroup STM32Fx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 -Piotr Esden-Tempski - -@date 11 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -/**@{*/ - -/** @cond */ -#ifdef LIBOPENCM3_ST_USBFS_H -/** @endcond */ -#ifndef LIBOPENCM3_ST_USBFS_COMMON_H -#define LIBOPENCM3_ST_USBFS_COMMON_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/* --- USB general registers ----------------------------------------------- */ - -/* USB Control register */ -#define USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40)) -/* USB Interrupt status register */ -#define USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44)) -/* USB Frame number register */ -#define USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48)) -/* USB Device address register */ -#define USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C)) -/* USB Buffer table address register */ -#define USB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50)) - -/* USB EP register */ -#define USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP)) - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- USB control register masks / bits ----------------------------------- */ - -/* Interrupt mask bits, set to 1 to enable interrupt generation */ -#define USB_CNTR_CTRM 0x8000 -#define USB_CNTR_PMAOVRM 0x4000 -#define USB_CNTR_ERRM 0x2000 -#define USB_CNTR_WKUPM 0x1000 -#define USB_CNTR_SUSPM 0x0800 -#define USB_CNTR_RESETM 0x0400 -#define USB_CNTR_SOFM 0x0200 -#define USB_CNTR_ESOFM 0x0100 - -/* Request/Force bits */ -#define USB_CNTR_RESUME 0x0010 /* Resume request */ -#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ -#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ -#define USB_CNTR_PWDN 0x0002 /* Power down */ -#define USB_CNTR_FRES 0x0001 /* Force reset */ - -/* --- USB interrupt status register masks / bits -------------------------- */ - -#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ -#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ -#define USB_ISTR_ERR 0x2000 /* Error */ -#define USB_ISTR_WKUP 0x1000 /* Wake up */ -#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ -#define USB_ISTR_RESET 0x0400 /* USB RESET request */ -#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ -#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ -#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ -#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ - -/* --- USB interrupt status register manipulators -------------------------- */ - -/* Note: CTR is read only! */ -#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) -#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) -#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) -#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) -#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) -#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) -#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) - -/* --- USB Frame Number Register bits -------------------------------------- */ - -#define USB_FNR_RXDP (1 << 15) -#define USB_FNR_RXDM (1 << 14) -#define USB_FNR_LCK (1 << 13) - -#define USB_FNR_LSOF_SHIFT 11 -#define USB_FNR_LSOF (3 << USB_FNR_LSOF_SHIFT) - -#define USB_FNR_FN (0x7FF << 0) - -/* --- USB device address register masks / bits ---------------------------- */ - -#define USB_DADDR_EF (1 << 7) -#define USB_DADDR_ADDR 0x007F - -/* USB_BTABLE Values ------------------------------------------------------- */ - -#define USB_BTABLE_BTABLE 0xFFF8 - -/* --- USB device address register manipulators ---------------------------- */ - -/* --- USB endpoint register offsets --------------------------------------- */ - -#define USB_EP0 0 -#define USB_EP1 1 -#define USB_EP2 2 -#define USB_EP3 3 -#define USB_EP4 4 -#define USB_EP5 5 -#define USB_EP6 6 -#define USB_EP7 7 - -/* --- USB endpoint register masks / bits ---------------------------------- */ - -/* Masks and toggle bits */ -#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ -#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ -#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ - -#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ -#define USB_EP_TYPE 0x0600 /* Endpoint type */ -#define USB_EP_KIND 0x0100 /* Endpoint kind. - * When set and type=bulk -> double buffer - * When set and type=control -> status out - */ - -#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ -#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ -#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ - -#define USB_EP_ADDR 0x000F /* Endpoint Address */ - -/* Masking all toggle bits */ -#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ - USB_EP_SETUP | \ - USB_EP_TYPE | \ - USB_EP_KIND | \ - USB_EP_TX_CTR | \ - USB_EP_ADDR) - -/* All non toggle bits plus EP_RX toggle bits */ -#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) -/* All non toggle bits plus EP_TX toggle bits */ -#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) - -/* Endpoint status bits for USB_EP_RX_STAT bit field */ -#define USB_EP_RX_STAT_DISABLED 0x0000 -#define USB_EP_RX_STAT_STALL 0x1000 -#define USB_EP_RX_STAT_NAK 0x2000 -#define USB_EP_RX_STAT_VALID 0x3000 - -/* Endpoint status bits for USB_EP_TX_STAT bit field */ -#define USB_EP_TX_STAT_DISABLED 0x0000 -#define USB_EP_TX_STAT_STALL 0x0010 -#define USB_EP_TX_STAT_NAK 0x0020 -#define USB_EP_TX_STAT_VALID 0x0030 - -/* Endpoint type bits for USB_EP_TYPE bit field */ -#define USB_EP_TYPE_BULK 0x0000 -#define USB_EP_TYPE_CONTROL 0x0200 -#define USB_EP_TYPE_ISO 0x0400 -#define USB_EP_TYPE_INTERRUPT 0x0600 - -/* --- USB endpoint register manipulators ---------------------------------- */ - -/* - * Set USB endpoint tx/rx status. - * - * USB status field is changed using an awkward toggle mechanism, that - * is why we use some helper macros for that. - */ -#define USB_SET_EP_RX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), \ - USB_EP_RX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR) - -#define USB_SET_EP_TX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), \ - USB_EP_TX_STAT_TOG_MSK, STAT, USB_EP_RX_CTR | USB_EP_TX_CTR) - -/* - * Macros for clearing and setting USB endpoint register bits that do - * not use the toggle mechanism. - * - * Because the register contains some bits that use the toggle - * mechanism we need a helper macro here. Otherwise the code gets really messy. - */ -#define USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, BIT, EXTRA_BITS) \ - CLR_REG_BIT_MSK_AND_SET(USB_EP_REG(EP), \ - USB_EP_NTOGGLE_MSK, BIT, EXTRA_BITS) - -#define USB_CLR_EP_RX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_RX_CTR, USB_EP_TX_CTR) - -#define USB_CLR_EP_TX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT_AND_SET(EP, USB_EP_TX_CTR, USB_EP_RX_CTR) - - -#define USB_SET_EP_TYPE(EP, TYPE) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_TYPE))) | TYPE) - -#define USB_SET_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_KIND))) | USB_EP_KIND) - -#define USB_CLR_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) - -#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) -#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) - -#define USB_SET_EP_ADDR(EP, ADDR) \ - SET_REG(USB_EP_REG(EP), \ - ((GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_ADDR))) | ADDR)) - -/* Macros for clearing DTOG bits */ -#define USB_CLR_EP_TX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) - -#define USB_CLR_EP_RX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) - - -/* --- USB BTABLE registers ------------------------------------------------ */ - -#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) - -/* --- USB BTABLE manipulators --------------------------------------------- */ - -#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) -#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) -#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) -#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) -#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) -#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) -#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) -#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) - - - -/**@}*/ - -#endif -/** @cond */ -#else -#error "st_usbfs_common.h should not be included explicitly, only via st_usbfs.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/st_usbfs_v1.h b/libopencm3/include/libopencm3/stm32/common/st_usbfs_v1.h deleted file mode 100644 index 7a5a045..0000000 --- a/libopencm3/include/libopencm3/stm32/common/st_usbfs_v1.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @addtogroup usb_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - * - * Additional definitions for F1, F3, L1 devices: - * -F102, F103 (RM0008) - * -F302x{B,C}; *NOT* F302x{6,8,D,E} !! (USB_BTABLE access issues) (RM0365) - * -F303x{B,C}; *NOT* F303x{D,E} !! (USB_BTABLE access issues) (RM0316) - * -F37x (RM0313) - * -L1xx (RM0038) - */ - -/** @cond */ -#ifdef LIBOPENCM3_ST_USBFS_H -/** @endcond */ -#ifndef LIBOPENCM3_ST_USBFS_V1_H -#define LIBOPENCM3_ST_USBFS_V1_H - -#include - -/* --- USB BTABLE Registers ------------------------------------------------ */ - -#define USB_EP_TX_ADDR(EP) \ - ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) - -#define USB_EP_TX_COUNT(EP) \ - ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) - -#define USB_EP_RX_ADDR(EP) \ - ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) - -#define USB_EP_RX_COUNT(EP) \ - ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) - -/* --- USB BTABLE manipulators --------------------------------------------- */ - -#define USB_GET_EP_TX_BUFF(EP) \ - (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2)) - -#define USB_GET_EP_RX_BUFF(EP) \ - (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2)) - -#endif -/** @cond */ -#else -#error "st_usbfs_v1.h should not be included directly, only via st_usbfs.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/st_usbfs_v2.h b/libopencm3/include/libopencm3/stm32/common/st_usbfs_v2.h deleted file mode 100644 index d85f442..0000000 --- a/libopencm3/include/libopencm3/stm32/common/st_usbfs_v2.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @addtogroup usb_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - * - * Additional definitions for F0 devices : - * -F0x0 (RM0360), - * -F04x, F0x2, F0x8 (RM0091) - */ - -/** @cond */ -#ifdef LIBOPENCM3_ST_USBFS_H -/** @endcond */ -#ifndef LIBOPENCM3_ST_USBFS_V2_H -#define LIBOPENCM3_ST_USBFS_V2_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define USB_LPMCSR_REG (&MMIO32(USB_DEV_FS_BASE + 0x54)) -#define USB_BCDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x58)) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- USB control register masks / bits ----------------------------------- */ - -#define USB_CNTR_L1REQM (1 << 7) -#define USB_CNTR_L1RESUME (1 << 5) - -/* --- USB interrupt status register masks / bits -------------------------- */ - -#define USB_ISTR_L1REQ (1 << 7) - -/* --- LPM control and status register USB_LPMCSR Values --------------------*/ - -#define USB_LPMCSR_BESL_SHIFT 4 -#define USB_LPMCSR_BESL (15 << USB_LPMCSR_BESL_SHIFT) - -#define USB_LPMCSR_REMWAKE (1 << 3) -#define USB_LPMCSR_LPMACK (1 << 1) -#define USB_LPMCSR_LPMEN (1 << 0) - -/* --- Battery Charging Detector Values ----------------------------------------------------------*/ - -#define USB_BCDR_DPPU (1 << 15) -#define USB_BCDR_PS2DET (1 << 7) -#define USB_BCDR_SDET (1 << 6) -#define USB_BCDR_PDET (1 << 5) -#define USB_BCDR_DCDET (1 << 4) -#define USB_BCDR_SDEN (1 << 3) -#define USB_BCDR_PDEN (1 << 2) -#define USB_BCDR_DCDEN (1 << 1) -#define USB_BCDR_BCDEN (1 << 0) - -/* --- USB BTABLE registers ------------------------------------------------ */ - -#define USB_EP_TX_ADDR(ep) \ - ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 0) * 1)) - -#define USB_EP_TX_COUNT(ep) \ - ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 2) * 1)) - -#define USB_EP_RX_ADDR(ep) \ - ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 4) * 1)) - -#define USB_EP_RX_COUNT(ep) \ - ((uint16_t *)(USB_PMA_BASE + (USB_GET_BTABLE + (ep) * 8 + 6) * 1)) - -/* --- USB BTABLE manipulators --------------------------------------------- */ - -#define USB_GET_EP_TX_BUFF(ep) \ - (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(ep) * 1)) - -#define USB_GET_EP_RX_BUFF(ep) \ - (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(ep) * 1)) - -#endif -/** @cond */ -#else -#error "st_usbfs_v2.h should not be included directly, only via st_usbfs.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h deleted file mode 100644 index 5e7f2d4..0000000 --- a/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h +++ /dev/null @@ -1,65 +0,0 @@ -/** @addtogroup syscfg_defines - * - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SYSCFG.H -The order of header inclusion is important. syscfg.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_SYSCFG_H) -/** @endcond */ -#ifndef LIBOPENCM3_SYSCFG_COMMON_L1F234_H -#define LIBOPENCM3_SYSCFG_COMMON_L1F234_H - -/**@{*/ - -/* --- SYSCFG registers ---------------------------------------------------- */ - -#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) - -#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) - -/* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) -#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) -#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) -#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) -#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) - -#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) - -/* --- SYSCFG_EXTICR Values -------------------------------------------------*/ - -#define SYSCFG_EXTICR_FIELDSIZE 4 - -#endif -/**@}*/ - -/** @cond */ -#else -#warning "syscfg_common_l1f234.h should not be included explicitly," -#warning "only via syscfg.h" -#endif -/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_all.h b/libopencm3/include/libopencm3/stm32/common/timer_common_all.h deleted file mode 100644 index c4f8d93..0000000 --- a/libopencm3/include/libopencm3/stm32/common/timer_common_all.h +++ /dev/null @@ -1,1251 +0,0 @@ -/** @addtogroup timer_defines - * - * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H -The order of header inclusion is important. timer.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_TIMER_H) -/** @endcond */ -#ifndef LIBOPENCM3_TIMER_COMMON_H -#define LIBOPENCM3_TIMER_COMMON_H - -/* --- Convenience macros -------------------------------------------------- */ - -/* Timer register base addresses (for convenience) */ -/****************************************************************************/ -/** @defgroup tim_reg_base Timer register base addresses -@{*/ -#define TIM1 TIM1_BASE -#define TIM2 TIM2_BASE -#define TIM3 TIM3_BASE -#if defined(TIM4_BASE) -#define TIM4 TIM4_BASE -#endif -#define TIM5 TIM5_BASE -#define TIM6 TIM6_BASE -#define TIM7 TIM7_BASE -#if defined(TIM8_BASE) -# define TIM8 TIM8_BASE -#endif -#if defined(TIM9_BASE) -# define TIM9 TIM9_BASE -#endif -#if defined(TIM10_BASE) -# define TIM10 TIM10_BASE -#endif -#if defined(TIM11_BASE) -# define TIM11 TIM11_BASE -#endif -#if defined(TIM12_BASE) -# define TIM12 TIM12_BASE -#endif -#if defined(TIM13_BASE) -# define TIM13 TIM13_BASE -#endif -#if defined(TIM14_BASE) -# define TIM14 TIM14_BASE -#endif -#if defined(TIM15_BASE) -# define TIM15 TIM15_BASE -#endif -#if defined(TIM16_BASE) -# define TIM16 TIM16_BASE -#endif -#if defined(TIM17_BASE) -# define TIM17 TIM17_BASE -#endif -#if defined(TIM21_BASE) -# define TIM21 TIM21_BASE -#endif -#if defined(TIM22_BASE) -# define TIM22 TIM22_BASE -#endif -/**@}*/ - -/* --- Timer registers ----------------------------------------------------- */ - -/* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32((tim_base) + 0x00) -#define TIM1_CR1 TIM_CR1(TIM1) -#define TIM2_CR1 TIM_CR1(TIM2) -#define TIM3_CR1 TIM_CR1(TIM3) -#define TIM4_CR1 TIM_CR1(TIM4) -#define TIM5_CR1 TIM_CR1(TIM5) -#define TIM6_CR1 TIM_CR1(TIM6) -#define TIM7_CR1 TIM_CR1(TIM7) -#define TIM8_CR1 TIM_CR1(TIM8) -#define TIM9_CR1 TIM_CR1(TIM9) -#define TIM10_CR1 TIM_CR1(TIM10) -#define TIM11_CR1 TIM_CR1(TIM11) -#define TIM12_CR1 TIM_CR1(TIM12) -#define TIM13_CR1 TIM_CR1(TIM13) -#define TIM14_CR1 TIM_CR1(TIM14) -#define TIM15_CR1 TIM_CR1(TIM15) -#define TIM16_CR1 TIM_CR1(TIM16) -#define TIM17_CR1 TIM_CR1(TIM17) - -/* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32((tim_base) + 0x04) -#define TIM1_CR2 TIM_CR2(TIM1) -#define TIM2_CR2 TIM_CR2(TIM2) -#define TIM3_CR2 TIM_CR2(TIM3) -#define TIM4_CR2 TIM_CR2(TIM4) -#define TIM5_CR2 TIM_CR2(TIM5) -#define TIM6_CR2 TIM_CR2(TIM6) -#define TIM7_CR2 TIM_CR2(TIM7) -#define TIM8_CR2 TIM_CR2(TIM8) -#define TIM15_CR2 TIM_CR2(TIM15) -#define TIM16_CR2 TIM_CR2(TIM16) -#define TIM17_CR2 TIM_CR2(TIM17) - -/* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08) -#define TIM1_SMCR TIM_SMCR(TIM1) -#define TIM2_SMCR TIM_SMCR(TIM2) -#define TIM3_SMCR TIM_SMCR(TIM3) -#define TIM4_SMCR TIM_SMCR(TIM4) -#define TIM5_SMCR TIM_SMCR(TIM5) -#define TIM8_SMCR TIM_SMCR(TIM8) -#define TIM9_SMCR TIM_SMCR(TIM9) -#define TIM12_SMCR TIM_SMCR(TIM12) -#define TIM15_SMCR TIM_SMCR(TIM15) - -/* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C) -#define TIM1_DIER TIM_DIER(TIM1) -#define TIM2_DIER TIM_DIER(TIM2) -#define TIM3_DIER TIM_DIER(TIM3) -#define TIM4_DIER TIM_DIER(TIM4) -#define TIM5_DIER TIM_DIER(TIM5) -#define TIM6_DIER TIM_DIER(TIM6) -#define TIM7_DIER TIM_DIER(TIM7) -#define TIM8_DIER TIM_DIER(TIM8) -#define TIM9_DIER TIM_DIER(TIM9) -#define TIM10_DIER TIM_DIER(TIM10) -#define TIM11_DIER TIM_DIER(TIM11) -#define TIM12_DIER TIM_DIER(TIM12) -#define TIM13_DIER TIM_DIER(TIM13) -#define TIM14_DIER TIM_DIER(TIM14) -#define TIM15_DIER TIM_DIER(TIM15) -#define TIM16_DIER TIM_DIER(TIM16) -#define TIM17_DIER TIM_DIER(TIM17) - -/* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32((tim_base) + 0x10) -#define TIM1_SR TIM_SR(TIM1) -#define TIM2_SR TIM_SR(TIM2) -#define TIM3_SR TIM_SR(TIM3) -#define TIM4_SR TIM_SR(TIM4) -#define TIM5_SR TIM_SR(TIM5) -#define TIM6_SR TIM_SR(TIM6) -#define TIM7_SR TIM_SR(TIM7) -#define TIM8_SR TIM_SR(TIM8) -#define TIM9_SR TIM_SR(TIM9) -#define TIM10_SR TIM_SR(TIM10) -#define TIM11_SR TIM_SR(TIM11) -#define TIM12_SR TIM_SR(TIM12) -#define TIM13_SR TIM_SR(TIM13) -#define TIM14_SR TIM_SR(TIM14) -#define TIM15_SR TIM_SR(TIM15) -#define TIM16_SR TIM_SR(TIM16) -#define TIM17_SR TIM_SR(TIM17) - -/* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32((tim_base) + 0x14) -#define TIM1_EGR TIM_EGR(TIM1) -#define TIM2_EGR TIM_EGR(TIM2) -#define TIM3_EGR TIM_EGR(TIM3) -#define TIM4_EGR TIM_EGR(TIM4) -#define TIM5_EGR TIM_EGR(TIM5) -#define TIM6_EGR TIM_EGR(TIM6) -#define TIM7_EGR TIM_EGR(TIM7) -#define TIM8_EGR TIM_EGR(TIM8) -#define TIM9_EGR TIM_EGR(TIM9) -#define TIM10_EGR TIM_EGR(TIM10) -#define TIM11_EGR TIM_EGR(TIM11) -#define TIM12_EGR TIM_EGR(TIM12) -#define TIM13_EGR TIM_EGR(TIM13) -#define TIM14_EGR TIM_EGR(TIM14) -#define TIM15_EGR TIM_EGR(TIM15) -#define TIM16_EGR TIM_EGR(TIM16) -#define TIM17_EGR TIM_EGR(TIM17) - -/* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18) -#define TIM1_CCMR1 TIM_CCMR1(TIM1) -#define TIM2_CCMR1 TIM_CCMR1(TIM2) -#define TIM3_CCMR1 TIM_CCMR1(TIM3) -#define TIM4_CCMR1 TIM_CCMR1(TIM4) -#define TIM5_CCMR1 TIM_CCMR1(TIM5) -#define TIM8_CCMR1 TIM_CCMR1(TIM8) -#define TIM9_CCMR1 TIM_CCMR1(TIM9) -#define TIM10_CCMR1 TIM_CCMR1(TIM10) -#define TIM11_CCMR1 TIM_CCMR1(TIM11) -#define TIM12_CCMR1 TIM_CCMR1(TIM12) -#define TIM13_CCMR1 TIM_CCMR1(TIM13) -#define TIM14_CCMR1 TIM_CCMR1(TIM14) -#define TIM15_CCMR1 TIM_CCMR1(TIM15) -#define TIM16_CCMR1 TIM_CCMR1(TIM16) -#define TIM17_CCMR1 TIM_CCMR1(TIM17) - -/* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C) -#define TIM1_CCMR2 TIM_CCMR2(TIM1) -#define TIM2_CCMR2 TIM_CCMR2(TIM2) -#define TIM3_CCMR2 TIM_CCMR2(TIM3) -#define TIM4_CCMR2 TIM_CCMR2(TIM4) -#define TIM5_CCMR2 TIM_CCMR2(TIM5) -#define TIM8_CCMR2 TIM_CCMR2(TIM8) - -/* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32((tim_base) + 0x20) -#define TIM1_CCER TIM_CCER(TIM1) -#define TIM2_CCER TIM_CCER(TIM2) -#define TIM3_CCER TIM_CCER(TIM3) -#define TIM4_CCER TIM_CCER(TIM4) -#define TIM5_CCER TIM_CCER(TIM5) -#define TIM8_CCER TIM_CCER(TIM8) -#define TIM9_CCER TIM_CCER(TIM9) -#define TIM10_CCER TIM_CCER(TIM10) -#define TIM11_CCER TIM_CCER(TIM11) -#define TIM12_CCER TIM_CCER(TIM12) -#define TIM13_CCER TIM_CCER(TIM13) -#define TIM14_CCER TIM_CCER(TIM14) -#define TIM15_CCER TIM_CCER(TIM15) -#define TIM16_CCER TIM_CCER(TIM16) -#define TIM17_CCER TIM_CCER(TIM17) - -/* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32((tim_base) + 0x24) -#define TIM1_CNT TIM_CNT(TIM1) -#define TIM2_CNT TIM_CNT(TIM2) -#define TIM3_CNT TIM_CNT(TIM3) -#define TIM4_CNT TIM_CNT(TIM4) -#define TIM5_CNT TIM_CNT(TIM5) -#define TIM6_CNT TIM_CNT(TIM6) -#define TIM7_CNT TIM_CNT(TIM7) -#define TIM8_CNT TIM_CNT(TIM8) -#define TIM9_CNT TIM_CNT(TIM9) -#define TIM10_CNT TIM_CNT(TIM10) -#define TIM11_CNT TIM_CNT(TIM11) -#define TIM12_CNT TIM_CNT(TIM12) -#define TIM13_CNT TIM_CNT(TIM13) -#define TIM14_CNT TIM_CNT(TIM14) -#define TIM15_CNT TIM_CNT(TIM15) -#define TIM16_CNT TIM_CNT(TIM16) -#define TIM17_CNT TIM_CNT(TIM17) - -/* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32((tim_base) + 0x28) -#define TIM1_PSC TIM_PSC(TIM1) -#define TIM2_PSC TIM_PSC(TIM2) -#define TIM3_PSC TIM_PSC(TIM3) -#define TIM4_PSC TIM_PSC(TIM4) -#define TIM5_PSC TIM_PSC(TIM5) -#define TIM6_PSC TIM_PSC(TIM6) -#define TIM7_PSC TIM_PSC(TIM7) -#define TIM8_PSC TIM_PSC(TIM8) -#define TIM9_PSC TIM_PSC(TIM9) -#define TIM10_PSC TIM_PSC(TIM10) -#define TIM11_PSC TIM_PSC(TIM11) -#define TIM12_PSC TIM_PSC(TIM12) -#define TIM13_PSC TIM_PSC(TIM13) -#define TIM14_PSC TIM_PSC(TIM14) -#define TIM15_PSC TIM_PSC(TIM15) -#define TIM16_PSC TIM_PSC(TIM16) -#define TIM17_PSC TIM_PSC(TIM17) - -/* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C) -#define TIM1_ARR TIM_ARR(TIM1) -#define TIM2_ARR TIM_ARR(TIM2) -#define TIM3_ARR TIM_ARR(TIM3) -#define TIM4_ARR TIM_ARR(TIM4) -#define TIM5_ARR TIM_ARR(TIM5) -#define TIM6_ARR TIM_ARR(TIM6) -#define TIM7_ARR TIM_ARR(TIM7) -#define TIM8_ARR TIM_ARR(TIM8) -#define TIM9_ARR TIM_ARR(TIM9) -#define TIM10_ARR TIM_ARR(TIM10) -#define TIM11_ARR TIM_ARR(TIM11) -#define TIM12_ARR TIM_ARR(TIM12) -#define TIM13_ARR TIM_ARR(TIM13) -#define TIM14_ARR TIM_ARR(TIM14) -#define TIM15_ARR TIM_ARR(TIM15) -#define TIM16_ARR TIM_ARR(TIM16) -#define TIM17_ARR TIM_ARR(TIM17) - -/* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32((tim_base) + 0x30) -#define TIM1_RCR TIM_RCR(TIM1) -#define TIM8_RCR TIM_RCR(TIM8) -#define TIM15_RCR TIM_RCR(TIM15) -#define TIM16_RCR TIM_RCR(TIM16) -#define TIM17_RCR TIM_RCR(TIM17) - -/* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34) -#define TIM1_CCR1 TIM_CCR1(TIM1) -#define TIM2_CCR1 TIM_CCR1(TIM2) -#define TIM3_CCR1 TIM_CCR1(TIM3) -#define TIM4_CCR1 TIM_CCR1(TIM4) -#define TIM5_CCR1 TIM_CCR1(TIM5) -#define TIM8_CCR1 TIM_CCR1(TIM8) -#define TIM9_CCR1 TIM_CCR1(TIM9) -#define TIM10_CCR1 TIM_CCR1(TIM10) -#define TIM11_CCR1 TIM_CCR1(TIM11) -#define TIM12_CCR1 TIM_CCR1(TIM12) -#define TIM13_CCR1 TIM_CCR1(TIM13) -#define TIM14_CCR1 TIM_CCR1(TIM14) -#define TIM15_CCR1 TIM_CCR1(TIM15) -#define TIM16_CCR1 TIM_CCR1(TIM16) -#define TIM17_CCR1 TIM_CCR1(TIM17) - -/* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38) -#define TIM1_CCR2 TIM_CCR2(TIM1) -#define TIM2_CCR2 TIM_CCR2(TIM2) -#define TIM3_CCR2 TIM_CCR2(TIM3) -#define TIM4_CCR2 TIM_CCR2(TIM4) -#define TIM5_CCR2 TIM_CCR2(TIM5) -#define TIM8_CCR2 TIM_CCR2(TIM8) -#define TIM9_CCR2 TIM_CCR2(TIM9) -#define TIM12_CCR2 TIM_CCR2(TIM12) -#define TIM15_CCR2 TIM_CCR2(TIM15) - -/* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C) -#define TIM1_CCR3 TIM_CCR3(TIM1) -#define TIM2_CCR3 TIM_CCR3(TIM2) -#define TIM3_CCR3 TIM_CCR3(TIM3) -#define TIM4_CCR3 TIM_CCR3(TIM4) -#define TIM5_CCR3 TIM_CCR3(TIM5) -#define TIM8_CCR3 TIM_CCR3(TIM8) - -/* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40) -#define TIM1_CCR4 TIM_CCR4(TIM1) -#define TIM2_CCR4 TIM_CCR4(TIM2) -#define TIM3_CCR4 TIM_CCR4(TIM3) -#define TIM4_CCR4 TIM_CCR4(TIM4) -#define TIM5_CCR4 TIM_CCR4(TIM5) -#define TIM8_CCR4 TIM_CCR4(TIM8) - -/* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44) -#define TIM1_BDTR TIM_BDTR(TIM1) -#define TIM8_BDTR TIM_BDTR(TIM8) -#define TIM15_BDTR TIM_BDTR(TIM15) -#define TIM16_BDTR TIM_BDTR(TIM16) -#define TIM17_BDTR TIM_BDTR(TIM17) - -/* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32((tim_base) + 0x48) -#define TIM1_DCR TIM_DCR(TIM1) -#define TIM2_DCR TIM_DCR(TIM2) -#define TIM3_DCR TIM_DCR(TIM3) -#define TIM4_DCR TIM_DCR(TIM4) -#define TIM5_DCR TIM_DCR(TIM5) -#define TIM8_DCR TIM_DCR(TIM8) -#define TIM15_DCR TIM_DCR(TIM15) -#define TIM16_DCR TIM_DCR(TIM16) -#define TIM17_DCR TIM_DCR(TIM17) - -/* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C) -#define TIM1_DMAR TIM_DMAR(TIM1) -#define TIM2_DMAR TIM_DMAR(TIM2) -#define TIM3_DMAR TIM_DMAR(TIM3) -#define TIM4_DMAR TIM_DMAR(TIM4) -#define TIM5_DMAR TIM_DMAR(TIM5) -#define TIM8_DMAR TIM_DMAR(TIM8) -#define TIM15_DMAR TIM_DMAR(TIM15) -#define TIM16_DMAR TIM_DMAR(TIM16) -#define TIM17_DMAR TIM_DMAR(TIM17) - -/* --- TIMx_CR1 values ----------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@{*/ -/* CKD[1:0]: Clock division */ -#define TIM_CR1_CKD_CK_INT (0x0 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) -#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) -/**@}*/ - -/* ARPE: Auto-reload preload enable */ -#define TIM_CR1_ARPE (1 << 7) - -/* CMS[1:0]: Center-aligned mode selection */ -/****************************************************************************/ -/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@{*/ -#define TIM_CR1_CMS_EDGE (0x0 << 5) -#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) -#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) -#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) -#define TIM_CR1_CMS_MASK (0x3 << 5) -/**@}*/ - -/* DIR: Direction */ -/****************************************************************************/ -/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@{*/ -#define TIM_CR1_DIR_UP (0 << 4) -#define TIM_CR1_DIR_DOWN (1 << 4) -/**@}*/ - -/* OPM: One pulse mode */ -#define TIM_CR1_OPM (1 << 3) - -/* URS: Update request source */ -#define TIM_CR1_URS (1 << 2) - -/* UDIS: Update disable */ -#define TIM_CR1_UDIS (1 << 1) - -/* CEN: Counter enable */ -#define TIM_CR1_CEN (1 << 0) - -/* --- TIMx_CR2 values ----------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@{*/ -/* OIS4:*//** Output idle state 4 (OC4 output) */ -#define TIM_CR2_OIS4 (1 << 14) - -/* OIS3N:*//** Output idle state 3 (OC3N output) */ -#define TIM_CR2_OIS3N (1 << 13) - -/* OIS3:*//** Output idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3 (1 << 12) - -/* OIS2N:*//** Output idle state 2 (OC2N output) */ -#define TIM_CR2_OIS2N (1 << 11) - -/* OIS2:*//** Output idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2 (1 << 10) - -/* OIS1N:*//** Output idle state 1 (OC1N output) */ -#define TIM_CR2_OIS1N (1 << 9) - -/* OIS1:*//** Output idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1 (1 << 8) -#define TIM_CR2_OIS_MASK (0x7f << 8) -/**@}*/ - -/* TI1S: TI1 selection */ -#define TIM_CR2_TI1S (1 << 7) - -/* MMS[2:0]: Master mode selection */ -/****************************************************************************/ -/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@{*/ -#define TIM_CR2_MMS_RESET (0x0 << 4) -#define TIM_CR2_MMS_ENABLE (0x1 << 4) -#define TIM_CR2_MMS_UPDATE (0x2 << 4) -#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) -#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) -#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) -#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) -#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIM_CR2_MMS_MASK (0x7 << 4) -/**@}*/ - -/* CCDS: Capture/compare DMA selection */ -#define TIM_CR2_CCDS (1 << 3) - -/* CCUS: Capture/compare control update selection */ -#define TIM_CR2_CCUS (1 << 2) - -/* CCPC: Capture/compare preload control */ -#define TIM_CR2_CCPC (1 << 0) - -/* --- TIMx_SMCR values ---------------------------------------------------- */ - -/* ETP: External trigger polarity */ -#define TIM_SMCR_ETP (1 << 15) - -/* ECE: External clock enable */ -#define TIM_SMCR_ECE (1 << 14) - -/* ETPS[1:0]: External trigger prescaler */ -#define TIM_SMCR_ETPS_OFF (0x0 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) -#define TIM_SMCR_ETPS_MASK (0X3 << 12) - -/* ETF[3:0]: External trigger filter */ -#define TIM_SMCR_ETF_OFF (0x0 << 8) -#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) -#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) -#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) -#define TIM_SMCR_ETF_MASK (0xF << 8) - -/* MSM: Master/slave mode */ -#define TIM_SMCR_MSM (1 << 7) - -/* TS[2:0]: Trigger selection */ -/** @defgroup tim_ts TIMx_SMCR TS Trigger selection -@{*/ -/** Internal Trigger 0 (ITR0) */ -#define TIM_SMCR_TS_ITR0 (0x0 << 4) -/** Internal Trigger 1 (ITR1) */ -#define TIM_SMCR_TS_ITR1 (0x1 << 4) -/** Internal Trigger 2 (ITR2) */ -#define TIM_SMCR_TS_ITR2 (0x2 << 4) -/** Internal Trigger 3 (ITR3) */ -#define TIM_SMCR_TS_ITR3 (0x3 << 4) -/** TI1 Edge Detector (TI1F_ED) */ -#define TIM_SMCR_TS_TI1F_ED (0x4 << 4) -/** Filtered Timer Input 1 (TI1FP1) */ -#define TIM_SMCR_TS_TI1FP1 (0x5 << 4) -/** Filtered Timer Input 2 (TI2FP2) */ -#define TIM_SMCR_TS_TI2FP2 (0x6 << 4) -/** External Trigger input (ETRF) */ -#define TIM_SMCR_TS_ETRF (0x7 << 4) -#define TIM_SMCR_TS_MASK (0x7 << 4) -/**@}*/ - -/* SMS[2:0]: Slave mode selection */ -/** @defgroup tim_sms TIMx_SMCR SMS Slave mode selection -@{*/ -/** Slave mode disabled */ -#define TIM_SMCR_SMS_OFF (0x0 << 0) -/** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 -level. */ -#define TIM_SMCR_SMS_EM1 (0x1 << 0) -/** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 -level. */ -#define TIM_SMCR_SMS_EM2 (0x2 << 0) -/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges -depending on the level of the complementary input. */ -#define TIM_SMCR_SMS_EM3 (0x3 << 0) -/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes - * the counter and generates an update of the registers. - */ -#define TIM_SMCR_SMS_RM (0x4 << 0) -/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is - * high. - */ -#define TIM_SMCR_SMS_GM (0x5 << 0) -/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */ -#define TIM_SMCR_SMS_TM (0x6 << 0) -/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock - * the counter. - */ -#define TIM_SMCR_SMS_ECM1 (0x7 << 0) -#define TIM_SMCR_SMS_MASK (0x7 << 0) -/**@}*/ - -/* --- TIMx_DIER values ---------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@{*/ -/* TDE:*//** Trigger DMA request enable */ -#define TIM_DIER_TDE (1 << 14) - -/* COMDE:*//** COM DMA request enable */ -#define TIM_DIER_COMDE (1 << 13) - -/* CC4DE:*//** Capture/Compare 4 DMA request enable */ -#define TIM_DIER_CC4DE (1 << 12) - -/* CC3DE:*//** Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC3DE (1 << 11) - -/* CC2DE:*//** Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC2DE (1 << 10) - -/* CC1DE:*//** Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC1DE (1 << 9) - -/* UDE*//**: Update DMA request enable */ -#define TIM_DIER_UDE (1 << 8) - -/* BIE:*//** Break interrupt enable */ -#define TIM_DIER_BIE (1 << 7) - -/* TIE:*//** Trigger interrupt enable */ -#define TIM_DIER_TIE (1 << 6) - -/* COMIE:*//** COM interrupt enable */ -#define TIM_DIER_COMIE (1 << 5) - -/* CC4IE:*//** Capture/compare 4 interrupt enable */ -#define TIM_DIER_CC4IE (1 << 4) - -/* CC3IE:*//** Capture/compare 3 interrupt enable */ -#define TIM_DIER_CC3IE (1 << 3) - -/* CC2IE:*//** Capture/compare 2 interrupt enable */ -#define TIM_DIER_CC2IE (1 << 2) - -/* CC1IE:*//** Capture/compare 1 interrupt enable */ -#define TIM_DIER_CC1IE (1 << 1) - -/* UIE:*//** Update interrupt enable */ -#define TIM_DIER_UIE (1 << 0) -/**@}*/ - -/* --- TIMx_SR values ------------------------------------------------------ */ -/****************************************************************************/ -/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@{*/ - -/* CC4OF:*//** Capture/compare 4 overcapture flag */ -#define TIM_SR_CC4OF (1 << 12) - -/* CC3OF:*//** Capture/compare 3 overcapture flag */ -#define TIM_SR_CC3OF (1 << 11) - -/* CC2OF:*//** Capture/compare 2 overcapture flag */ -#define TIM_SR_CC2OF (1 << 10) - -/* CC1OF:*//** Capture/compare 1 overcapture flag */ -#define TIM_SR_CC1OF (1 << 9) - -/* BIF:*//** Break interrupt flag */ -#define TIM_SR_BIF (1 << 7) - -/* TIF:*//** Trigger interrupt flag */ -#define TIM_SR_TIF (1 << 6) - -/* COMIF:*//** COM interrupt flag */ -#define TIM_SR_COMIF (1 << 5) - -/* CC4IF:*//** Capture/compare 4 interrupt flag */ -#define TIM_SR_CC4IF (1 << 4) - -/* CC3IF:*//** Capture/compare 3 interrupt flag */ -#define TIM_SR_CC3IF (1 << 3) - -/* CC2IF:*//** Capture/compare 2 interrupt flag */ -#define TIM_SR_CC2IF (1 << 2) - -/* CC1IF:*//** Capture/compare 1 interrupt flag */ -#define TIM_SR_CC1IF (1 << 1) - -/* UIF:*//** Update interrupt flag */ -#define TIM_SR_UIF (1 << 0) -/**@}*/ - -/* --- TIMx_EGR values ----------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@{*/ - -/* BG:*//** Break generation */ -#define TIM_EGR_BG (1 << 7) - -/* TG:*//** Trigger generation */ -#define TIM_EGR_TG (1 << 6) - -/* COMG:*//** Capture/compare control update generation */ -#define TIM_EGR_COMG (1 << 5) - -/* CC4G:*//** Capture/compare 4 generation */ -#define TIM_EGR_CC4G (1 << 4) - -/* CC3G:*//** Capture/compare 3 generation */ -#define TIM_EGR_CC3G (1 << 3) - -/* CC2G:*//** Capture/compare 2 generation */ -#define TIM_EGR_CC2G (1 << 2) - -/* CC1G:*//** Capture/compare 1 generation */ -#define TIM_EGR_CC1G (1 << 1) - -/* UG:*//** Update generation */ -#define TIM_EGR_UG (1 << 0) -/**@}*/ - -/* --- TIMx_CCMR1 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC2CE: Output compare 2 clear enable */ -#define TIM_CCMR1_OC2CE (1 << 15) - -/* OC2M[2:0]: Output compare 2 mode */ -#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) -#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) -#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) -#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) -#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) -#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) -#define TIM_CCMR1_OC2M_MASK (0x7 << 12) - -/* OC2PE: Output compare 2 preload enable */ -#define TIM_CCMR1_OC2PE (1 << 11) - -/* OC2FE: Output compare 2 fast enable */ -#define TIM_CCMR1_OC2FE (1 << 10) - -/* CC2S[1:0]: Capture/compare 2 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC2S_OUT (0x0 << 8) -#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) -#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) -#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) -#define TIM_CCMR1_CC2S_MASK (0x3 << 8) - -/* OC1CE: Output compare 1 clear enable */ -#define TIM_CCMR1_OC1CE (1 << 7) - -/* OC1M[2:0]: Output compare 1 mode */ -#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) -#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) -#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) -#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) -#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) -#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) -#define TIM_CCMR1_OC1M_MASK (0x7 << 4) - -/* OC1PE: Output compare 1 preload enable */ -#define TIM_CCMR1_OC1PE (1 << 3) - -/* OC1FE: Output compare 1 fast enable */ -#define TIM_CCMR1_OC1FE (1 << 2) - -/* CC1S[1:0]: Capture/compare 1 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC1S_OUT (0x0 << 0) -#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) -#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) -#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) -#define TIM_CCMR1_CC1S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC2F[3:0]: Input capture 2 filter */ -#define TIM_CCMR1_IC2F_OFF (0x0 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR1_IC2F_MASK (0xF << 12) - -/* IC2PSC[1:0]: Input capture 2 prescaler */ -#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) -#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) -#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) -#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) -#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) - -/* IC1F[3:0]: Input capture 1 filter */ -#define TIM_CCMR1_IC1F_OFF (0x0 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR1_IC1F_MASK (0xF << 4) - -/* IC1PSC[1:0]: Input capture 1 prescaler */ -#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) -#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) -#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) -#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) -#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) - -/* --- TIMx_CCMR2 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC4CE: Output compare 4 clear enable */ -#define TIM_CCMR2_OC4CE (1 << 15) - -/* OC4M[2:0]: Output compare 4 mode */ -#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) -#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) -#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) -#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) -#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) -#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) -#define TIM_CCMR2_OC4M_MASK (0x7 << 12) - -/* OC4PE: Output compare 4 preload enable */ -#define TIM_CCMR2_OC4PE (1 << 11) - -/* OC4FE: Output compare 4 fast enable */ -#define TIM_CCMR2_OC4FE (1 << 10) - -/* CC4S[1:0]: Capture/compare 4 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC4S_OUT (0x0 << 8) -#define TIM_CCMR2_CC4S_IN_TI4 (0x1 << 8) -#define TIM_CCMR2_CC4S_IN_TI3 (0x2 << 8) -#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) -#define TIM_CCMR2_CC4S_MASK (0x3 << 8) - -/* OC3CE: Output compare 3 clear enable */ -#define TIM_CCMR2_OC3CE (1 << 7) - -/* OC3M[2:0]: Output compare 3 mode */ -#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) -#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) -#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) -#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) -#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) -#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) -#define TIM_CCMR2_OC3M_MASK (0x7 << 4) - -/* OC3PE: Output compare 3 preload enable */ -#define TIM_CCMR2_OC3PE (1 << 3) - -/* OC3FE: Output compare 3 fast enable */ -#define TIM_CCMR2_OC3FE (1 << 2) - -/* CC3S[1:0]: Capture/compare 3 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC3S_OUT (0x0 << 0) -#define TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0) -#define TIM_CCMR2_CC3S_IN_TI4 (0x2 << 0) -#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) -#define TIM_CCMR2_CC3S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC4F[3:0]: Input capture 4 filter */ -#define TIM_CCMR2_IC4F_OFF (0x0 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR2_IC4F_MASK (0xF << 12) - -/* IC4PSC[1:0]: Input capture 4 prescaler */ -#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) -#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) -#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) -#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) -#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) - -/* IC3F[3:0]: Input capture 3 filter */ -#define TIM_CCMR2_IC3F_OFF (0x0 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR2_IC3F_MASK (0xF << 4) - -/* IC3PSC[1:0]: Input capture 3 prescaler */ -#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) -#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) -#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) -#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) -#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) - -/* --- TIMx_CCER values ---------------------------------------------------- */ - -/* CC4NP: Capture/compare 4 complementary output polarity */ -#define TIM_CCER_CC4NP (1 << 15) - -/* CC4P: Capture/compare 4 output polarity */ -#define TIM_CCER_CC4P (1 << 13) - -/* CC4E: Capture/compare 4 output enable */ -#define TIM_CCER_CC4E (1 << 12) - -/* CC3NP: Capture/compare 3 complementary output polarity */ -#define TIM_CCER_CC3NP (1 << 11) - -/* CC3NE: Capture/compare 3 complementary output enable */ -#define TIM_CCER_CC3NE (1 << 10) - -/* CC3P: Capture/compare 3 output polarity */ -#define TIM_CCER_CC3P (1 << 9) - -/* CC3E: Capture/compare 3 output enable */ -#define TIM_CCER_CC3E (1 << 8) - -/* CC2NP: Capture/compare 2 complementary output polarity */ -#define TIM_CCER_CC2NP (1 << 7) - -/* CC2NE: Capture/compare 2 complementary output enable */ -#define TIM_CCER_CC2NE (1 << 6) - -/* CC2P: Capture/compare 2 output polarity */ -#define TIM_CCER_CC2P (1 << 5) - -/* CC2E: Capture/compare 2 output enable */ -#define TIM_CCER_CC2E (1 << 4) - -/* CC1NP: Capture/compare 1 complementary output polarity */ -#define TIM_CCER_CC1NP (1 << 3) - -/* CC1NE: Capture/compare 1 complementary output enable */ -#define TIM_CCER_CC1NE (1 << 2) - -/* CC1P: Capture/compare 1 output polarity */ -#define TIM_CCER_CC1P (1 << 1) - -/* CC1E: Capture/compare 1 output enable */ -#define TIM_CCER_CC1E (1 << 0) - -/* --- TIMx_CNT values ----------------------------------------------------- */ - -/* CNT[15:0]: Counter value */ - -/* --- TIMx_PSC values ----------------------------------------------------- */ - -/* PSC[15:0]: Prescaler value */ - -/* --- TIMx_ARR values ----------------------------------------------------- */ - -/* ARR[15:0]: Prescaler value */ - -/* --- TIMx_RCR values ----------------------------------------------------- */ - -/* REP[15:0]: Repetition counter value */ - -/* --- TIMx_CCR1 values ---------------------------------------------------- */ - -/* CCR1[15:0]: Capture/compare 1 value */ - -/* --- TIMx_CCR2 values ---------------------------------------------------- */ - -/* CCR2[15:0]: Capture/compare 2 value */ - -/* --- TIMx_CCR3 values ---------------------------------------------------- */ - -/* CCR3[15:0]: Capture/compare 3 value */ - -/* --- TIMx_CCR4 values ---------------------------------------------------- */ - -/* CCR4[15:0]: Capture/compare 4 value */ - -/* --- TIMx_BDTR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM_BDTR_MOE (1 << 15) - -/* AOE: Automatic output enable */ -#define TIM_BDTR_AOE (1 << 14) - -/* BKP: Break polarity */ -#define TIM_BDTR_BKP (1 << 13) - -/* BKE: Break enable */ -#define TIM_BDTR_BKE (1 << 12) - -/* OSSR: Off-state selection of run mode */ -#define TIM_BDTR_OSSR (1 << 11) - -/* OSSI: Off-state selection of idle mode */ -#define TIM_BDTR_OSSI (1 << 10) - -/* LOCK[1:0]: Lock configuration */ -/****************************************************************************/ -/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@{*/ -#define TIM_BDTR_LOCK_OFF (0x0 << 8) -#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) -#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) -#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) -#define TIM_BDTR_LOCK_MASK (0x3 << 8) -/**@}*/ - -/* DTG[7:0]: Dead-time generator set-up */ -#define TIM_BDTR_DTG_MASK 0x00FF - -/* --- TIMx_DCR values ----------------------------------------------------- */ - -/* DBL[4:0]: DMA burst length */ -#define TIM_BDTR_DBL_MASK (0x1F << 8) - -/* DBA[4:0]: DMA base address */ -#define TIM_BDTR_DBA_MASK (0x1F << 0) - -/* --- TIMx_DMAR values ---------------------------------------------------- */ - -/* DMAB[15:0]: DMA register for burst accesses */ - -/* --- TIMx convenience defines -------------------------------------------- */ - -/** Output Compare channel designators */ -enum tim_oc_id { - TIM_OC1 = 0, - TIM_OC1N, - TIM_OC2, - TIM_OC2N, - TIM_OC3, - TIM_OC3N, - TIM_OC4, -}; - -/** Output Compare mode designators */ -enum tim_oc_mode { - TIM_OCM_FROZEN, - TIM_OCM_ACTIVE, - TIM_OCM_INACTIVE, - TIM_OCM_TOGGLE, - TIM_OCM_FORCE_LOW, - TIM_OCM_FORCE_HIGH, - TIM_OCM_PWM1, - TIM_OCM_PWM2, -}; - -/** Input Capture channel designators */ -enum tim_ic_id { - TIM_IC1, - TIM_IC2, - TIM_IC3, - TIM_IC4, -}; - -/** Input Capture input filter. The frequency used to sample the -input and the number of events needed to validate an output transition. - -TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency -(DTF), filter length x -TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x - */ -enum tim_ic_filter { - TIM_IC_OFF, - TIM_IC_CK_INT_N_2, - TIM_IC_CK_INT_N_4, - TIM_IC_CK_INT_N_8, - TIM_IC_DTF_DIV_2_N_6, - TIM_IC_DTF_DIV_2_N_8, - TIM_IC_DTF_DIV_4_N_6, - TIM_IC_DTF_DIV_4_N_8, - TIM_IC_DTF_DIV_8_N_6, - TIM_IC_DTF_DIV_8_N_8, - TIM_IC_DTF_DIV_16_N_5, - TIM_IC_DTF_DIV_16_N_6, - TIM_IC_DTF_DIV_16_N_8, - TIM_IC_DTF_DIV_32_N_5, - TIM_IC_DTF_DIV_32_N_6, - TIM_IC_DTF_DIV_32_N_8, -}; - -/** Input Capture input prescaler. - -TIM_IC_PSC_x Input capture is done every x events*/ -enum tim_ic_psc { - TIM_IC_PSC_OFF, - TIM_IC_PSC_2, - TIM_IC_PSC_4, - TIM_IC_PSC_8, -}; - -/** Input Capture input source. - -The direction of the channel (input/output) as well as the input used. - */ -enum tim_ic_input { - TIM_IC_OUT = 0, - TIM_IC_IN_TI1 = 1, - TIM_IC_IN_TI2 = 2, - TIM_IC_IN_TRC = 3, - TIM_IC_IN_TI3 = 5, - TIM_IC_IN_TI4 = 6, -}; - -/** Slave external trigger polarity */ -enum tim_et_pol { - TIM_ET_RISING, - TIM_ET_FALLING, -}; - -/* --- TIM function prototypes --------------------------------------------- */ - -BEGIN_DECLS - -void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq); -void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq); -bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag); -bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag); -void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag); -void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, - uint32_t alignment, uint32_t direction); -void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div); -void timer_enable_preload(uint32_t timer_peripheral); -void timer_disable_preload(uint32_t timer_peripheral); -void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment); -void timer_direction_up(uint32_t timer_peripheral); -void timer_direction_down(uint32_t timer_peripheral); -void timer_one_shot_mode(uint32_t timer_peripheral); -void timer_continuous_mode(uint32_t timer_peripheral); -void timer_update_on_any(uint32_t timer_peripheral); -void timer_update_on_overflow(uint32_t timer_peripheral); -void timer_enable_update_event(uint32_t timer_peripheral); -void timer_disable_update_event(uint32_t timer_peripheral); -void timer_enable_counter(uint32_t timer_peripheral); -void timer_disable_counter(uint32_t timer_peripheral); -void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); -void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); -void timer_set_ti1_ch123_xor(uint32_t timer_peripheral); -void timer_set_ti1_ch1(uint32_t timer_peripheral); -void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode); -void timer_set_dma_on_compare_event(uint32_t timer_peripheral); -void timer_set_dma_on_update_event(uint32_t timer_peripheral); -void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral); -void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral); -void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral); -void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral); -void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value); -void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value); -void timer_set_period(uint32_t timer_peripheral, uint32_t period); -void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, - enum tim_oc_mode oc_mode); -void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_high(uint32_t timer_peripheral, - enum tim_oc_id oc_id); -void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_set(uint32_t timer_peripheral, - enum tim_oc_id oc_id); -void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, - enum tim_oc_id oc_id); -void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, - uint32_t value); -void timer_enable_break_main_output(uint32_t timer_peripheral); -void timer_disable_break_main_output(uint32_t timer_peripheral); -void timer_enable_break_automatic_output(uint32_t timer_peripheral); -void timer_disable_break_automatic_output(uint32_t timer_peripheral); -void timer_set_break_polarity_high(uint32_t timer_peripheral); -void timer_set_break_polarity_low(uint32_t timer_peripheral); -void timer_enable_break(uint32_t timer_peripheral); -void timer_disable_break(uint32_t timer_peripheral); -void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral); -void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral); -void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral); -void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral); -void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock); -void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime); -void timer_generate_event(uint32_t timer_peripheral, uint32_t event); -uint32_t timer_get_counter(uint32_t timer_peripheral); -uint32_t timer_get_ic_value(uint32_t timer_peripheral, enum tim_ic_id ic_id); -void timer_set_counter(uint32_t timer_peripheral, uint32_t count); - -void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, - enum tim_ic_filter flt); -void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, - enum tim_ic_psc psc); -void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, - enum tim_ic_input in); -void timer_ic_enable(uint32_t timer, enum tim_ic_id ic); -void timer_ic_disable(uint32_t timer, enum tim_ic_id ic); - -void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt); -void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc); -void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol); -void timer_slave_set_mode(uint32_t timer, uint8_t mode); -void timer_slave_set_trigger(uint32_t timer, uint8_t trigger); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "timer_common_all.h should not be included directly, only via timer.h" -#endif -/** @endcond */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h b/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h deleted file mode 100644 index 6f483d8..0000000 --- a/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h +++ /dev/null @@ -1,114 +0,0 @@ -/** @addtogroup timer_defines - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H -The order of header inclusion is important. timer.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_TIMER_H -/** @endcond */ -#ifndef LIBOPENCM3_TIMER_COMMON_F24_H -#define LIBOPENCM3_TIMER_COMMON_F24_H - -#include - -/* - * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: - * CNT, ARR, CCR1, CCR2, CCR3, CCR4 - */ - -/* Timer 2/5 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) -#define TIM2_OR TIM_OR(TIM2) -#define TIM5_OR TIM_OR(TIM5) - -/* --- TIM2_OR values ---------------------------------------------------- */ - -/* ITR1_RMP */ -/****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal -Trigger 1 Remap - -Only available in F2 and F4 series. -@ingroup timer_defines - -@{*/ -/** Internal Trigger 1 remapped to timer 8 trigger out */ -#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10) -/** Internal Trigger 1 remapped to PTP trigger out */ -#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) -/** Internal Trigger 1 remapped to USB OTG FS SOF */ -#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) -/** Internal Trigger 1 remapped to USB OTG HS SOF */ -#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) -/**@}*/ -#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) - -/* --- TIM5_OR values ---------------------------------------------------- */ - -/* ITR4_RMP */ -/****************************************************************************/ -/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap - -Only available in F2 and F4 series. -@ingroup timer_defines - -@{*/ -/** Internal Trigger 4 remapped to GPIO (see reference manual) */ -#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) -/** Internal Trigger 4 remapped to LSI internal clock */ -#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) -/** Internal Trigger 4 remapped to LSE internal clock */ -#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) -/** Internal Trigger 4 remapped to RTC output event */ -#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) -/**@}*/ -#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) - -/** Input Capture input polarity */ -enum tim_ic_pol { - TIM_IC_RISING, - TIM_IC_FALLING, - TIM_IC_BOTH, -}; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void timer_set_option(uint32_t timer_peripheral, uint32_t option); -void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, - enum tim_ic_pol pol); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "timer_common_f24.h should not be included directly, only via timer.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_all.h b/libopencm3/include/libopencm3/stm32/common/usart_common_all.h deleted file mode 100644 index a39d683..0000000 --- a/libopencm3/include/libopencm3/stm32/common/usart_common_all.h +++ /dev/null @@ -1,136 +0,0 @@ -/** @addtogroup usart_defines - * - * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H -The order of header inclusion is important. usart.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_USART_H) -/** @endcond */ -#ifndef LIBOPENCM3_USART_COMMON_ALL_H -#define LIBOPENCM3_USART_COMMON_ALL_H - - -/* --- Convenience defines ------------------------------------------------- */ - -/* CR1_PCE / CR1_PS combined values */ -/****************************************************************************/ -/** @defgroup usart_cr1_parity USART Parity Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_PARITY_NONE 0x00 -#define USART_PARITY_EVEN USART_CR1_PCE -#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) -/**@}*/ -#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) - -/* CR1_TE/CR1_RE combined values */ -/****************************************************************************/ -/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_MODE_RX USART_CR1_RE -#define USART_MODE_TX USART_CR1_TE -#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) -/**@}*/ -#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) - -/****************************************************************************/ -/** @defgroup usart_cr2_stopbits USART Stop Bit Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */ -#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/ -/**@}*/ - -/* STOP[13:12]: STOP bits */ -#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ -#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ -#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ -#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ -#define USART_CR2_STOPBITS_MASK (0x03 << 12) -#define USART_CR2_STOPBITS_SHIFT 12 - - -/* CR3_CTSE/CR3_RTSE combined values */ -/****************************************************************************/ -/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection -@ingroup STM32F_usart_defines - -@{*/ -#define USART_FLOWCONTROL_NONE 0x00 -#define USART_FLOWCONTROL_RTS USART_CR3_RTSE -#define USART_FLOWCONTROL_CTS USART_CR3_CTSE -#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -/**@}*/ -#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void usart_set_baudrate(uint32_t usart, uint32_t baud); -void usart_set_databits(uint32_t usart, uint32_t bits); -void usart_set_stopbits(uint32_t usart, uint32_t stopbits); -void usart_set_parity(uint32_t usart, uint32_t parity); -void usart_set_mode(uint32_t usart, uint32_t mode); -void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); -void usart_enable(uint32_t usart); -void usart_disable(uint32_t usart); -void usart_send(uint32_t usart, uint16_t data); -uint16_t usart_recv(uint32_t usart); -void usart_wait_send_ready(uint32_t usart); -void usart_wait_recv_ready(uint32_t usart); -void usart_send_blocking(uint32_t usart, uint16_t data); -uint16_t usart_recv_blocking(uint32_t usart); -void usart_enable_rx_dma(uint32_t usart); -void usart_disable_rx_dma(uint32_t usart); -void usart_enable_tx_dma(uint32_t usart); -void usart_disable_tx_dma(uint32_t usart); -void usart_enable_rx_interrupt(uint32_t usart); -void usart_disable_rx_interrupt(uint32_t usart); -void usart_enable_tx_interrupt(uint32_t usart); -void usart_disable_tx_interrupt(uint32_t usart); -void usart_enable_error_interrupt(uint32_t usart); -void usart_disable_error_interrupt(uint32_t usart); -bool usart_get_flag(uint32_t usart, uint32_t flag); - -END_DECLS - -#endif -/** @cond */ -#else -#warning "usart_common_all.h should not be included directly, only via usart.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h deleted file mode 100644 index cd5c712..0000000 --- a/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h +++ /dev/null @@ -1,309 +0,0 @@ -/** @addtogroup usart_defines - -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H -The order of header inclusion is important. usart.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#if defined(LIBOPENCM3_USART_H) -/** @endcond */ -#ifndef LIBOPENCM3_USART_COMMON_F124_H -#define LIBOPENCM3_USART_COMMON_F124_H - -#include - - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -/**@}*/ - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32((usart_base) + 0x00) -#define USART1_SR USART_SR(USART1_BASE) -#define USART2_SR USART_SR(USART2_BASE) -#define USART3_SR USART_SR(USART3_BASE) -#define UART4_SR USART_SR(UART4_BASE) -#define UART5_SR USART_SR(UART5_BASE) - -/* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32((usart_base) + 0x04) -#define USART1_DR USART_DR(USART1_BASE) -#define USART2_DR USART_DR(USART2_BASE) -#define USART3_DR USART_DR(USART3_BASE) -#define UART4_DR USART_DR(UART4_BASE) -#define UART5_DR USART_DR(UART5_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32((usart_base) + 0x08) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32((usart_base) + 0x0c) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32((usart_base) + 0x10) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32((usart_base) + 0x14) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x18) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) - -/** @defgroup usart_convenience_flags U(S)ART convenience Flags - * @ingroup STM32F_usart_defines - * We define the "common" lower flag bits using a standard name, - * allowing them to be used regardless of which usart peripheral - * version you have. - * @{ - */ -#define USART_FLAG_PE USART_SR_PE -#define USART_FLAG_FE USART_SR_FE -#define USART_FLAG_NF USART_SR_NF -#define USART_FLAG_ORE USART_SR_ORE -#define USART_FLAG_IDLE USART_SR_IDLE -#define USART_FLAG_RXNE USART_SR_RXNE -#define USART_FLAG_TC USART_SR_TC -#define USART_FLAG_TXE USART_SR_TXE -/**@}*/ - -/* --- USART_SR values ----------------------------------------------------- */ -/****************************************************************************/ -/** @defgroup usart_sr_flags USART Status register Flags -@ingroup STM32F_usart_defines - -@{*/ - -/** CTS: CTS flag */ -/** @note: undefined on UART4 and UART5 */ -#define USART_SR_CTS (1 << 9) - -/** LBD: LIN break detection flag */ -#define USART_SR_LBD (1 << 8) - -/** TXE: Transmit data buffer empty */ -#define USART_SR_TXE (1 << 7) - -/** TC: Transmission complete */ -#define USART_SR_TC (1 << 6) - -/** RXNE: Read data register not empty */ -#define USART_SR_RXNE (1 << 5) - -/** IDLE: Idle line detected */ -#define USART_SR_IDLE (1 << 4) - -/** ORE: Overrun error */ -#define USART_SR_ORE (1 << 3) - -/** NE: Noise error flag */ -#define USART_SR_NE (1 << 2) - -/** FE: Framing error */ -#define USART_SR_FE (1 << 1) - -/** PE: Parity error */ -#define USART_SR_PE (1 << 0) -/**@}*/ - -/* --- USART_DR values ----------------------------------------------------- */ - -/* USART_DR[8:0]: DR[8:0]: Data value */ -#define USART_DR_MASK 0x1FF - -/* --- USART_BRR values ---------------------------------------------------- */ - -/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ -#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) -/* DIV_Fraction[3:0]: fraction of USARTDIV */ -#define USART_BRR_DIV_FRACTION_MASK 0xF - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* UE: USART enable */ -#define USART_CR1_UE (1 << 13) - -/* M: Word length */ -#define USART_CR1_M (1 << 12) - -/* WAKE: Wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/* PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/* PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/* PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/* TXEIE: TXE interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/* TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/* RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/* IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/* TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/* RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/* RWU: Receiver wakeup */ -#define USART_CR1_RWU (1 << 1) - -/* SBK: Send break */ -#define USART_CR1_SBK (1 << 0) - -/* --- USART_CR2 values ---------------------------------------------------- */ - -/* LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/* CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/* CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/* CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/* LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/* LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/* LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/* ADD[3:0]: Address of the usart node */ -#define USART_CR2_ADD_MASK 0xF - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* CTSIE: CTS interrupt enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSIE (1 << 10) - -/* CTSE: CTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSE (1 << 9) - -/* RTSE: RTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_RTSE (1 << 8) - -/* DMAT: DMA enable transmitter */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAT (1 << 7) - -/* DMAR: DMA enable receiver */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAR (1 << 6) - -/* SCEN: Smartcard mode enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_SCEN (1 << 5) - -/* NACK: Smartcard NACK enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_NACK (1 << 4) - -/* HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/* IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/* IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/* EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/* --- USART_GTPR values --------------------------------------------------- */ - -/* GT[7:0]: Guard time value */ -/* Note: N/A on UART4 & UART5 */ -#define USART_GTPR_GT_MASK (0xFF << 8) - -/* PSC[7:0]: Prescaler value */ -/* Note: N/A on UART4/5 */ -#define USART_GTPR_PSC_MASK 0xFF - -/* TODO */ /* Note to Uwe: what needs to be done here? */ - -#endif -/** @cond */ -#else -#warning "usart_common_all.h should not be included directly, only via usart.h" -#endif -/** @endcond */ -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h deleted file mode 100644 index 9edb640..0000000 --- a/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h +++ /dev/null @@ -1,103 +0,0 @@ -/** @addtogroup usart_defines - -@author @htmlonly © @endhtmlonly 2011 Uwe Hermann -@author @htmlonly © @endhtmlonly 2011 Stephen Caudle - -*/ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H -The order of header inclusion is important. usart.h includes the device -specific memorymap.h header before including this header file.*/ - -/** @cond */ -#ifdef LIBOPENCM3_USART_H -/** @endcond */ -#ifndef LIBOPENCM3_USART_COMMON_F24_H -#define LIBOPENCM3_USART_COMMON_F24_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/** @addtogroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART6 USART6_BASE -#define UART7 UART7_BASE -#define UART8 UART8_BASE -/**@}*/ - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART6_SR USART_SR(USART6_BASE) -#define UART7_SR USART_SR(UART7) -#define UART8_SR USART_SR(UART8) - -/* Data register (USARTx_DR) */ -#define USART6_DR USART_DR(USART6_BASE) -#define UART7_DR USART_DR(UART7) -#define UART8_DR USART_DR(UART8) - -/* Baud rate register (USARTx_BRR) */ -#define USART6_BRR USART_BRR(USART6_BASE) -#define UART7_BRR USART_BRR(UART7) -#define UART8_BRR USART_BRR(UART8) - -/* Control register 1 (USARTx_CR1) */ -#define USART6_CR1 USART_CR1(USART6_BASE) -#define UART7_CR1 USART_CR1(UART7) -#define UART8_CR1 USART_CR1(UART8) - -/* Control register 2 (USARTx_CR2) */ -#define USART6_CR2 USART_CR2(USART6_BASE) -#define UART7_CR2 USART_CR2(UART7) -#define UART8_CR2 USART_CR2(UART8) - -/* Control register 3 (USARTx_CR3) */ -#define USART6_CR3 USART_CR3(USART6_BASE) -#define UART7_CR3 USART_CR3(UART7) -#define UART8_CR3 USART_CR3(UART8) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART6_GTPR USART_GTPR(USART6_BASE) -#define UART7_GTPR USART_GTPR(UART7) -#define UART8_GTPR USART_GTPR(UART8) - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* OVER8: Oversampling mode */ -#define USART_CR1_OVER8 (1 << 15) - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) - -#endif -/** @cond */ -#else -#warning "usart_common_f24.h should not be included directly, only via usart.h" -#endif -/** @endcond */ - diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_fifos.h b/libopencm3/include/libopencm3/stm32/common/usart_common_fifos.h deleted file mode 100644 index 5eb5d37..0000000 --- a/libopencm3/include/libopencm3/stm32/common/usart_common_fifos.h +++ /dev/null @@ -1,164 +0,0 @@ -/** @addtogroup usart_defines - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Brian Viele - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#ifndef LIBOPENCM3_STM32_COMMON_USART_COMMON_FIFOS_H_ -#define LIBOPENCM3_STM32_COMMON_USART_COMMON_FIFOS_H_ - -#include -#include -#include - -/** @addtogroup usart_registers -@{*/ -#define USART_PRESC(usart_base) MMIO32((usart_base) + 0x2C) -/**@}*/ - -/** @addtogroup usart_cr1_values -@{*/ -/** RX FIFO Full Interrupt Enable. */ -#define USART_CR1_RXFFIE BIT31 -/** TX FIFO Empty Interrupt Enable. */ -#define USART_CR1_TXFEIE BIT30 -/** FIFO Enable bit. */ -#define USART_CR1_FIFOEN BIT29 -/**@}*/ - -/** @addtogroup usart_cr3_values -@{*/ -/** FIFO Threshold definitions. */ -typedef enum { - USART_FIFO_THRESH_EIGTH = 0x0, - USART_FIFO_THRESH_QUARTER = 0x1, - USART_FIFO_THRESH_HALF = 0x2, - USART_FIFO_THRESH_THREEQTR = 0x3, - USART_FIFO_THRESH_SEVENEIGTH = 0x4, - USART_FIFO_THRESH_TX_EMPTY = 0x5, - USART_FIFO_THRESH_RX_FULL = 0x5, - USART_FIFO_THRESH_MASK = 0x7 -} usart_fifo_threshold_t; - -/** TX FIFO Threshold Configuration bits. */ -#define USART_CR3_TXFTCFG_SHIFT 29 -/** RX FIFO THreshold Interrupt Enable. */ -#define USART_CR3_RXFTIE BIT28 -/** RX FIFO Threshold Configuration bits. */ -#define USART_CR3_RXFTCFG_SHIFT 25 -/** Transmission Complete Before Guard Time Enable bit. */ -#define USART_CR3_TCBGTIE BIT24 -/** TX FIFO THreshold Interrupt Enable. */ -#define USART_CR3_TXFTIE BIT23 -/**@}*/ - -/** @addtogroup usart_isr_values -@{*/ -/** TX FIFO Threshold Interrupt Flag. */ -#define USART_ISR_TXFT BIT27 -/** RX FIFO Threshold Interrupt Flag. */ -#define USART_ISR_RXFT BIT26 -/** Transmission Complete before Guard Time Interrupt Flag. */ -#define USART_ISR_TCBGT BIT25 -/** RX FIFO Full Flag. */ -#define USART_ISR_RXFF BIT24 -/** TX FIFO Empty Flag. */ -#define USART_ISR_TXFE BIT23 -/** SPI Slave Underrun Flag. */ -#define USART_ISR_UDR BIT13 -/**@}*/ - -/** @addtogroup usart_icr_values -@{*/ -/** SPI Slave Underrun Clear Flag. */ -#define USART_ICR_UDR BIT13 -/** TX FIFO Empty Clear Flag. */ -#define USART_ICR_TXFECF BIT5 -/**@}*/ - -BEGIN_DECLS - -/** @addtogroup usart_file -@{*/ -/** - * Enable FIFOs on the specified USART. - * @param[in] usart Base address of USART to configure FIFOs. - */ -void usart_enable_fifos(uint32_t usart); -/** - * Disable FIFOs on the specified USART. - * @param[in] usart Base address of USART to configure FIFOs. - */ -void usart_disable_fifos(uint32_t usart); -/** - * Enable TX FIFO empty interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_enable_tx_fifo_empty_interrupt(uint32_t usart); -/** - * Disable TX FIFO empty interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_disable_tx_fifo_empty_interrupt(uint32_t usart); -/** - * Enable TX FIFO empty interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_enable_tx_fifo_threshold_interrupt(uint32_t usart); -/** - * Disable TX FIFO empty interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_disable_tx_fifo_threshold_interrupt(uint32_t usart); -/** - * Configure TX FIFO threshold on specified UART. - * @param[in] usart Base address of USART to configure FIFO. - * @param[in] threshold Threshold value to set for TX FIFO. - */ -void usart_set_tx_fifo_threshold(uint32_t usart, - usart_fifo_threshold_t threshold); -/** - * Enable RX FIFO full interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_enable_rx_fifo_full_interrupt(uint32_t usart); -/** - * Disable RX FIFO full interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_disable_rx_fifo_full_interrupt(uint32_t usart); -/** - * Enable RX FIFO threshold interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_enable_rx_fifo_threshold_interrupt(uint32_t usart); -/** - * Disable RX FIFO threshold interrupt on the specified USART. - * @param[in] usart Base address of USART to configure FIFO interrupt. - */ -void usart_disable_rx_fifo_threshold_interrupt(uint32_t usart); -/** - * Configure RX FIFO threshold on specified UART. - * @param[in] usart Base address of USART to configure FIFO. - * @param[in] threshold Threshold value to set for RX FIFO. - */ -void usart_set_rx_fifo_threshold(uint32_t usart, - usart_fifo_threshold_t threshold); -/**@}*/ -END_DECLS - -#endif /* LIBOPENCM3_STM32_COMMON_USART_COMMON_FIFOS_H_ */ diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_v2.h b/libopencm3/include/libopencm3/stm32/common/usart_common_v2.h deleted file mode 100644 index b0bcea7..0000000 --- a/libopencm3/include/libopencm3/stm32/common/usart_common_v2.h +++ /dev/null @@ -1,633 +0,0 @@ -/** @addtogroup usart_defines - - @author @htmlonly © @endhtmlonly 2016 Cem Basoglu - - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Cem Basoglu - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -/** @defgroup usart_registers USART Registers -@ingroup usart_defines -@{*/ - -/** Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_CR1 USART_CR1(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) -#endif - -/** Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_CR2 USART_CR2(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) -#endif - -/** Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_CR3 USART_CR3(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) -#endif - -/** Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0C) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_BRR USART_BRR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) -#endif - -/** Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_GTPR USART_GTPR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) -#endif - -/** Receiver timeout register (USART_RTOR) */ -#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) -#define USART1_RTOR USART_RTOR(USART1_BASE) -#define USART2_RTOR USART_RTOR(USART2_BASE) -#define USART3_RTOR USART_RTOR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_RTOR USART_RTOR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_RTOR USART_RTOR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_RTOR USART_RTOR(UART5_BASE) -#endif - -/** Request register (USART_RQR) */ -#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18) -#define USART1_RQR USART_RQR(USART1_BASE) -#define USART2_RQR USART_RQR(USART2_BASE) -#define USART3_RQR USART_RQR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_RQR USART_RQR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_RQR USART_RQR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_RQR USART_RQR(UART5_BASE) -#endif - -/** Interrupt & status register (USART_ISR) */ -#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1C) -#define USART1_ISR USART_ISR(USART1_BASE) -#define USART2_ISR USART_ISR(USART2_BASE) -#define USART3_ISR USART_ISR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_ISR USART_ISR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_ISR USART_ISR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_ISR USART_ISR(UART5_BASE) -#endif - -/** Interrupt flag clear register (USART_ICR) */ -#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20) -#define USART1_ICR USART_ICR(USART1_BASE) -#define USART2_ICR USART_ICR(USART2_BASE) -#define USART3_ICR USART_ICR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_ICR USART_ICR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_ICR USART_ICR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_ICR USART_ICR(UART5_BASE) -#endif - -/** Receive data register (USART_RDR) */ -#define USART_RDR(usart_base) MMIO32((usart_base) + 0x24) -#define USART1_RDR USART_RDR(USART1_BASE) -#define USART2_RDR USART_RDR(USART2_BASE) -#define USART3_RDR USART_RDR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_RDR USART_RDR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_RDR USART_RDR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_RDR USART_RDR(UART5_BASE) -#endif - -/** Transmit data register (USART_TDR) */ -#define USART_TDR(usart_base) MMIO32((usart_base) + 0x28) -#define USART1_TDR USART_TDR(USART1_BASE) -#define USART2_TDR USART_TDR(USART2_BASE) -#define USART3_TDR USART_TDR(USART3_BASE) -#if defined(USART4_BASE) -#define USART4_TDR USART_TDR(USART4_BASE) -#endif -#if defined(UART4_BASE) -#define UART4_TDR USART_TDR(UART4_BASE) -#endif -#if defined(UART5_BASE) -#define UART5_TDR USART_TDR(UART5_BASE) -#endif - -/**@}*/ - -/** @defgroup usart_convenience_flags U(S)ART convenience Flags - * @ingroup usart_defines - * We define the "common" lower flag bits using a standard name, - * allowing them to be used regardless of which usart peripheral - * version you have. - * @{ - */ -#define USART_FLAG_PE USART_ISR_PE -#define USART_FLAG_FE USART_ISR_FE -#define USART_FLAG_NF USART_ISR_NF -#define USART_FLAG_ORE USART_ISR_ORE -#define USART_FLAG_IDLE USART_ISR_IDLE -#define USART_FLAG_RXNE USART_ISR_RXNE -#define USART_FLAG_TC USART_ISR_TC -#define USART_FLAG_TXE USART_ISR_TXE -/**@}*/ - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @defgroup usart_cr1_values USART_CR1 Values -@ingroup usart_defines -@{*/ - -/** M1: Wordlength. @sa M0 */ -#define USART_CR1_M1 (1 << 28) /* F07x */ - -/** EOBIE: End of Block interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) - -/** RTOIE: Receiver timeout interrupt enable */ -#define USART_CR1_RTOIE (1 << 26) - -#define USART_CR1_DEAT_SHIFT 21 -#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) -/** DEAT[4:0]: Driver Enable assertion time */ -#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) - -#define USART_CR1_DEDT_SHIFT 16 -#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) -/** DEDT[4:0]: Driver Enable deassertion time */ -#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) - -/** OVER8: Oversampling mode */ -#define USART_CR1_OVER8 (1 << 15) - -/** CMIE: Character match interrupt enable */ -#define USART_CR1_CMIE (1 << 14) - -/** MME: Mute mode enable */ -#define USART_CR1_MME (1 << 13) - -/** M0: Word length */ -#define USART_CR1_M0 (1 << 12) -/** @deprecated alias for M0.*/ -#define USART_CR1_M USART_CR1_M0 - -/** WAKE: Receiver wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/** PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/** PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/** PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/** TXEIE: Interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/** TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/** RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/** IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/** TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/** RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/** UESM: USART enable in Stop mode */ -#define USART_CR1_UESM (1 << 1) - -/** UE: USART enable */ -#define USART_CR1_UE (1 << 0) -/**@}*/ - -/*------------------------------------------------*/ -/** @defgroup usart_cr2_values USART_CR2 Values -@ingroup usart_defines -@{*/ - -/** ADD[7:0]: Address of the USART node. */ -#define USART_CR2_ADD_SHIFT 24 -#define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT) -#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT) - -#define USART_CR2_ABRMOD_MASK 3 -#define USART_CR2_ABRMOD_SHIFT 21 -/** ABRMOD[1:0]: Auto baud rate mode - * @defgroup usart_cr2_abrmod Auto baud rate mode - * @ingroup usart_defines - * @{ - */ -#define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) -#define USART_CR2_ABRMOD_FALL_EDGE (0x1 << USART_CR2_ABRMOD_SHIFT) -#define USART_CR2_ABRMOD_FRAME_0x7F (0x2 << USART_CR2_ABRMOD_SHIFT) -#define USART_CR2_ABRMOD_FRAME_0x55 (0x3 << USART_CR2_ABRMOD_SHIFT) -/**@}*/ - -/** RTOEN: Receiver timeout enable */ -#define USART_CR2_RTOEN (1 << 23) - -/** ABREN: Auto baud rate enable */ -#define USART_CR2_ABREN (1 << 20) - -/** MSBFIRST: Most significant bit first */ -#define USART_CR2_MSBFIRST (1 << 19) - -/** DATAINV: Binary data inversion */ -#define USART_CR2_DATAINV (1 << 18) - -/** TXINV: TX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) - -/** RXINV: RX pin active level inversion */ -#define USART_CR2_RXINV (1 << 16) - -/** SWAP: Swap TX/RX pins */ -#define USART_CR2_SWAP (1 << 15) - -/** LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/** CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/** CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/** CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/** LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/** LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/** LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/** ADDM7:7-bit Address Detection/4-bit Address Detection */ -#define USART_CR2_ADDM7 (1 << 4) - -/**@}*/ - -/*------------------------------------------------*/ -/** @defgroup usart_cr3_values USART_CR3 Values -@ingroup usart_defines -@{*/ -/** WUFIE: Wakeup from Stop mode interrupt enable */ -#define USART_CR3_WUFIE (1 << 22) - -/** WUS[1:0]: Wakeup from Stop mode interrupt flag selection */ -#define USART_CR3_WUS_ADDRMATCH (0x0 << 20) -#define USART_CR3_WUS_START_BIT (0x2 << 20) -#define USART_CR3_WUS_RXNE (0x3 << 20) - -#define USART_CR3_SCARCNT_SHIFT 17 -#define USART_CR3_SCARCNT_MASK 0x7 -/** SCARCNT[2:0]: Smartcard auto retry count */ -#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT) - -/** DEP: Driver enable polarity selection */ -#define USART_CR3_DEP (1 << 15) - -/** DEM: Driver enable mode */ -#define USART_CR3_DEM (1 << 14) - -/** DDRE: DMA Disable on Reception Error */ -#define USART_CR3_DDRE (1 << 13) - -/** OVRDIS: Overrun Disable */ -#define USART_CR3_OVRDIS (1 << 12) - -/** ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) - -/** CTSIE: CTS interrupt enable. Not on UARTs */ -#define USART_CR3_CTSIE (1 << 10) - -/** CTSE: CTS enable. Not on UARTS */ -#define USART_CR3_CTSE (1 << 9) - -/** RTSE: RTS enable. Not on UARTs */ -#define USART_CR3_RTSE (1 << 8) - -/** DMAT: DMA enable transmitter. Not on UARTs */ -#define USART_CR3_DMAT (1 << 7) - -/** DMAR: DMA enable receiver. Not on UARTS */ -#define USART_CR3_DMAR (1 << 6) - -/** SCEN: Smartcard mode enable. Not on UARTs */ -#define USART_CR3_SCEN (1 << 5) - -/** NACK: Smartcard NACK enable. Not UARTs */ -#define USART_CR3_NACK (1 << 4) - -/** HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/** IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/** IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/** EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/**@}*/ - -/** @defgroup usart_gtpr_values USART_GTPR Values - * @ingroup usart_defines - * @{ - */ -#define USART_GTPR_GT_SHIFT 8 -#define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT) -#define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT) - -#define USART_GTPR_PSC_SHIFT 0 -#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT) -/**@}*/ - -/* ------------------------------------------------------ */ -/** @defgroup usart_rtor_values USART_RTOR Values - * @ingroup usart_defines - * @{ - */ -/** BLEN[7:0]: Block Length */ -#define USART_RTOR_BLEN_SHIFT 24 -#define USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT) -#define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT) - -/** RTO[23:0]: Receiver timeout value */ -#define USART_RTOR_RTO_SHIFT 0 -#define USART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT) - -/**@}*/ - -/* ------------------------------------------------------ */ -/** @defgroup usart_rqr_values USART_RQR Values - * @ingroup usart_defines - * @{ - */ -/** TXFRQ: Transmit data flush request */ -#define USART_RQR_TXFRQ (1 << 4) - -/** RXFRQ: Receive data flush request */ -#define USART_RQR_RXFRQ (1 << 3) - -/** MMRQ: Mute mode request */ -#define USART_RQR_MMRQ (1 << 2) - -/** SBKRQ: Send break request */ -#define USART_RQR_SBKRQ (1 << 1) - -/** ABRRQ: Auto baud rate request */ -#define USART_RQR_ABKRQ (1 << 0) - -/**@}*/ - -/* ------------------------------------------------------ */ -/** @defgroup usart_isr_values USART_ISR Values - * @ingroup usart_defines - * @{ - */ - -/** REACK: Receive enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) - -/** TEACK: Transmit enable acknowledge flag */ -#define USART_ISR_TEACK (1 << 21) - -/** WUF: Wakeup from Stop mode flag */ -#define USART_ISR_WUF (1 << 20) - -/** RWU: Receiver wakeup from Mute mode */ -#define USART_ISR_RWU (1 << 19) - -/** SBKF: Send break flag */ -#define USART_ISR_SBKF (1 << 18) - -/** CMF: Character match flag */ -#define USART_ISR_CMF (1 << 17) - -/** BUSY: Busy flag */ -#define USART_ISR_BUSY (1 << 16) - -/** ABRF: Auto baud rate flag */ -#define USART_ISR_ABRF (1 << 15) - -/** ABRE: Auto baud rate error */ -#define USART_ISR_ABRE (1 << 14) - -/** EOBF: End of block flag */ -#define USART_ISR_EOBF (1 << 12) - -/** RTOF: Receiver timeout */ -#define USART_ISR_RTOF (1 << 11) - -/** CTS: CTS flag */ -#define USART_ISR_CTS (1 << 10) - -/** CTSIF: CTS interrupt flag */ -#define USART_ISR_CTSIF (1 << 9) - -/** LBDF: LIN break detection flag */ -#define USART_ISR_LBDF (1 << 8) - -/** TXE: Transmit data register empty */ -#define USART_ISR_TXE (1 << 7) - -/** TC: Transmission complete */ -#define USART_ISR_TC (1 << 6) - -/** RXNE: Read data register not empty */ -#define USART_ISR_RXNE (1 << 5) - -/** IDLE: Idle line detected */ -#define USART_ISR_IDLE (1 << 4) - -/** ORE: Overrun error */ -#define USART_ISR_ORE (1 << 3) - -/** NF: Noise detected flag */ -#define USART_ISR_NF (1 << 2) - -/** FE: Framing error */ -#define USART_ISR_FE (1 << 1) - -/** PE: Parity error */ -#define USART_ISR_PE (1 << 0) - -/**@}*/ - -/* ------------------------------------------------------ */ -/** @defgroup usart_icr_values USART_ICR Values - * @ingroup usart_defines - * @{ - */ - -/** WUCF: Wakeup from Stop mode clear flag */ -#define USART_ICR_WUCF (1 << 20) - -/** CMCF: Character match clear flag */ -#define USART_ICR_CMCF (1 << 17) - -/** EOBCF: End of timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) - -/** RTOCF: Receiver timeout clear flag */ -#define USART_ICR_RTOCF (1 << 11) - -/** CTSCF: CTS clear flag */ -#define USART_ICR_CTSCF (1 << 9) - -/** LBDCF: LIN break detection clear flag */ -#define USART_ICR_LBDCF (1 << 8) - -/** TCCF: Transmission complete clear flag */ -#define USART_ICR_TCCF (1 << 6) - -/** IDLECF: Idle line detected clear flag */ -#define USART_ICR_IDLECF (1 << 4) - -/** ORECF: Overrun error clear flag */ -#define USART_ICR_ORECF (1 << 3) - -/** NCF: Noise detected clear flag */ -#define USART_ICR_NCF (1 << 2) - -/** FECF: Framing error clear flag */ -#define USART_ICR_FECF (1 << 1) - -/** PECF: Parity error clear flag */ -#define USART_ICR_PECF (1 << 0) - -/**@}*/ - -/** @defgroup usart_dr_values USART_RDR/TDR Values - * @ingroup usart_defines - * @{ - */ -/** RDR[8:0]: Receive data value */ -#define USART_RDR_MASK (0x1FF << 0) -/** TDR[8:0]: Transmit data value */ -#define USART_TDR_MASK (0x1FF << 0) -/**@}*/ - - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void usart_enable_data_inversion(uint32_t usart); -void usart_disable_data_inversion(uint32_t usart); -void usart_enable_tx_inversion(uint32_t usart); -void usart_disable_tx_inversion(uint32_t usart); -void usart_enable_rx_inversion(uint32_t usart); -void usart_disable_rx_inversion(uint32_t usart); -void usart_enable_halfduplex(uint32_t usart); -void usart_disable_halfduplex(uint32_t usart); - -void usart_set_rx_timeout_value(uint32_t usart, uint32_t value); -void usart_enable_rx_timeout(uint32_t usart); -void usart_disable_rx_timeout(uint32_t usart); -void usart_enable_rx_timeout_interrupt(uint32_t usart); -void usart_disable_rx_timeout_interrupt(uint32_t usart); - -END_DECLS diff --git a/libopencm3/include/libopencm3/stm32/comparator.h b/libopencm3/include/libopencm3/stm32/comparator.h deleted file mode 100644 index b188c79..0000000 --- a/libopencm3/include/libopencm3/stm32/comparator.h +++ /dev/null @@ -1,29 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F3) -# include -#else -# error "stm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/stm32/crc.h b/libopencm3/include/libopencm3/stm32/crc.h deleted file mode 100644 index 0749866..0000000 --- a/libopencm3/include/libopencm3/stm32/crc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/crs.h b/libopencm3/include/libopencm3/stm32/crs.h deleted file mode 100644 index 69858bc..0000000 --- a/libopencm3/include/libopencm3/stm32/crs.h +++ /dev/null @@ -1,32 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L4) -# include -#else -# error "stm32 family not defined or not supported for this peripheral" -#endif - diff --git a/libopencm3/include/libopencm3/stm32/crypto.h b/libopencm3/include/libopencm3/stm32/crypto.h deleted file mode 100644 index edce6a1..0000000 --- a/libopencm3/include/libopencm3/stm32/crypto.h +++ /dev/null @@ -1,30 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "CRYPTO processor is supported only" \ - "in stm32f2xx, stm32f41xx, stm32f42xx and stm32f43xx family." -#endif diff --git a/libopencm3/include/libopencm3/stm32/dac.h b/libopencm3/include/libopencm3/stm32/dac.h deleted file mode 100644 index 196d2e8..0000000 --- a/libopencm3/include/libopencm3/stm32/dac.h +++ /dev/null @@ -1,44 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/dbgmcu.h b/libopencm3/include/libopencm3/stm32/dbgmcu.h deleted file mode 100644 index cb4c5f6..0000000 --- a/libopencm3/include/libopencm3/stm32/dbgmcu.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_DBGMCU_H -#define LIBOPENCM3_STM32_DBGMCU_H - -#include -#include - -/* --- DBGMCU registers ---------------------------------------------------- */ - -/* Debug MCU IDCODE register (DBGMCU_IDCODE) */ -#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) - -/* Debug MCU configuration register (DBGMCU_CR) */ -/* Note: Only 32bit access supported. */ -#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) - -/* --- DBGMCU_IDCODE values ------------------------------------------------ */ - -#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff -#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 - -/* --- DBGMCU_CR values ---------------------------------------------------- */ - -/* Bit 31: Reserved. */ - -/* Bits [24:22]: Reserved, must be kept cleared. */ - -/* Bits [4:3]: Reserved. */ - -#define DBGMCU_CR_SLEEP 0x00000001 -#define DBGMCU_CR_STOP 0x00000002 -#define DBGMCU_CR_STANDBY 0x00000004 -#define DBGMCU_CR_TRACE_IOEN 0x00000020 -#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 -#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 -#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 -#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 -#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 -#define DBGMCU_CR_IWDG_STOP 0x00000100 -#define DBGMCU_CR_WWDG_STOP 0x00000200 -#define DBGMCU_CR_TIM1_STOP 0x00000400 -#define DBGMCU_CR_TIM2_STOP 0x00000800 -#define DBGMCU_CR_TIM3_STOP 0x00001000 -#define DBGMCU_CR_TIM4_STOP 0x00002000 -#define DBGMCU_CR_CAN1_STOP 0x00004000 -#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 -#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 -#define DBGMCU_CR_TIM8_STOP 0x00020000 -#define DBGMCU_CR_TIM5_STOP 0x00040000 -#define DBGMCU_CR_TIM6_STOP 0x00080000 -#define DBGMCU_CR_TIM7_STOP 0x00100000 -#define DBGMCU_CR_CAN2_STOP 0x00200000 - -#endif diff --git a/libopencm3/include/libopencm3/stm32/dcmi.h b/libopencm3/include/libopencm3/stm32/dcmi.h deleted file mode 100644 index ac9cb02..0000000 --- a/libopencm3/include/libopencm3/stm32/dcmi.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/desig.h b/libopencm3/include/libopencm3/stm32/desig.h deleted file mode 100644 index c24d64c..0000000 --- a/libopencm3/include/libopencm3/stm32/desig.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DESIG_H -#define LIBOPENCM3_DESIG_H - -#include -#include - -/* --- Device Electronic Signature -------------------------------- */ - -BEGIN_DECLS - -/** - * Read the on board flash size - * @return flash size in KB - */ -uint16_t desig_get_flash_size(void); - -/** - * Read the full 96 bit unique identifier - * Note: ST specifies that bits 31..16 are _also_ reserved for future use - * @param result pointer to at least 3xuint32_ts (96 bits) - */ -void desig_get_unique_id(uint32_t *result); - -/** - * Read the full 96 bit unique identifier and return it as a - * zero-terminated string - * @param string memory region to write the result to - * @param string_len the size of string in bytes - */ -void desig_get_unique_id_as_string(char *string, - unsigned int string_len); - -/** - * Generate the same serial number from the unique id registers as - * the DFU bootloader. - * - * This document: http://www.usb.org/developers/docs/devclass_docs/usbmassbulk_10.pdf - * says that the serial number has to be at least 12 digits long and that - * the last 12 digits need to be unique. It also stipulates that the valid - * character set is that of upper-case hexadecimal digits. - * The onboard DFU bootloader produces a 12-digit serial based on the - * 96-bit unique ID. Show the serial with ```dfu-util -l``` while the - * MCU is in DFU mode. - * @see https://my.st.com/52d187b7 for the algorithim used. - * @param string pointer to store serial in, must be at least 13 bytes - */ -void desig_get_unique_id_as_dfu(char *string); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/dma.h b/libopencm3/include/libopencm3/stm32/dma.h deleted file mode 100644 index f914cf0..0000000 --- a/libopencm3/include/libopencm3/stm32/dma.h +++ /dev/null @@ -1,46 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/dma2d.h b/libopencm3/include/libopencm3/stm32/dma2d.h deleted file mode 100644 index ab4e1f2..0000000 --- a/libopencm3/include/libopencm3/stm32/dma2d.h +++ /dev/null @@ -1,30 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#else -# error "dma2d.h not available for this family." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/dmamux.h b/libopencm3/include/libopencm3/stm32/dmamux.h deleted file mode 100644 index 291bc7d..0000000 --- a/libopencm3/include/libopencm3/stm32/dmamux.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/dsi.h b/libopencm3/include/libopencm3/stm32/dsi.h deleted file mode 100644 index b811f10..0000000 --- a/libopencm3/include/libopencm3/stm32/dsi.h +++ /dev/null @@ -1,27 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#if defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#else -# error "dsi.h not available for this family." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/exti.h b/libopencm3/include/libopencm3/stm32/exti.h deleted file mode 100644 index 0a6df03..0000000 --- a/libopencm3/include/libopencm3/stm32/exti.h +++ /dev/null @@ -1,50 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f0/adc.h b/libopencm3/include/libopencm3/stm32/f0/adc.h deleted file mode 100644 index bc88a57..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/adc.h +++ /dev/null @@ -1,198 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the STM32F0xx Analog to Digital - * Converter - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/** @defgroup adc_reg_base ADC register base addresses - * @ingroup adc_defines - * - *@{*/ -#define ADC ADC_BASE -#define ADC1 ADC_BASE/* for API compatibility */ -/**@}*/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define ADC1_ISR ADC_ISR(ADC) -#define ADC1_IER ADC_IER(ADC) -#define ADC1_CR ADC_CR(ADC) -#define ADC1_CFGR1 ADC_CFGR1(ADC) -#define ADC1_CFGR2 ADC_CFGR2(ADC) -#define ADC1_SMPR1 ADC_SMPR1(ADC) -#define ADC_SMPR(adc) ADC_SMPR1(adc) /* Compatibility */ -#define ADC1_SMPR ADC_SMPR1(ADC) /* Compatibility */ -#define ADC1_TR1 ADC_TR1(ADC) -#define ADC_TR(adc) ADC_TR1(adc) /* Compatibility */ -#define ADC1_TR ADC1_TR(ADC) /* Compatibility */ -#define ADC1_CHSELR ADC_CHSELR(ADC) -#define ADC1_DR ADC_DR(ADC) -#define ADC1_CCR ADC_CCR(ADC) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* ADC_CFGR2 Values ---------------------------------------------------------*/ - -#define ADC_CFGR2_CKMODE_SHIFT 30 -#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT) - -/* ADC_SMPR Values ----------------------------------------------------------*/ - -#define ADC_SMPR_SMP_SHIFT 0 -#define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT) -#define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT) - - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/** @defgroup adc_api_res ADC resolutions - * @ingroup adc_defines - * - *@{*/ -#define ADC_RESOLUTION_12BIT ADC_CFGR1_RES_12_BIT -#define ADC_RESOLUTION_10BIT ADC_CFGR1_RES_10_BIT -#define ADC_RESOLUTION_8BIT ADC_CFGR1_RES_8_BIT -#define ADC_RESOLUTION_6BIT ADC_CFGR1_RES_6_BIT -/**@}*/ - -/** @defgroup adc_api_smptime ADC sampling time - * @ingroup adc_defines - * - *@{*/ -#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMP_001DOT5 -#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMP_007DOT5 -#define ADC_SMPTIME_013DOT5 ADC_SMPR_SMP_013DOT5 -#define ADC_SMPTIME_028DOT5 ADC_SMPR_SMP_028DOT5 -#define ADC_SMPTIME_041DOT5 ADC_SMPR_SMP_041DOT5 -#define ADC_SMPTIME_055DOT5 ADC_SMPR_SMP_055DOT5 -#define ADC_SMPTIME_071DOT5 ADC_SMPR_SMP_071DOT5 -#define ADC_SMPTIME_239DOT5 ADC_SMPR_SMP_239DOT5 -/**@}*/ - -/** @defgroup adc_api_clksource ADC clock source - * @ingroup adc_defines - * - *@{*/ -#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_CK_ADC -#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2 -#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4 -/**@}*/ - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_TEMP 16 -#define ADC_CHANNEL_VREF 17 -#define ADC_CHANNEL_VBAT 18 -/**@}*/ - -/** @defgroup adc_api_opmode ADC Operation Modes - * @ingroup adc_defines - * - *@{*/ -enum adc_opmode { - ADC_MODE_SEQUENTIAL, - ADC_MODE_SCAN, - ADC_MODE_SCAN_INFINITE, -}; -/**@}*/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - - -BEGIN_DECLS - -/* Operation mode API */ -void adc_enable_discontinuous_mode(uint32_t adc); -void adc_disable_discontinuous_mode(uint32_t adc); -void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode); - -/* Trigger API */ -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_disable_external_trigger_regular(uint32_t adc); - -/* Interrupt configuration */ -void adc_enable_watchdog_interrupt(uint32_t adc); -void adc_disable_watchdog_interrupt(uint32_t adc); -bool adc_get_watchdog_flag(uint32_t adc); -void adc_clear_watchdog_flag(uint32_t adc); -void adc_enable_eoc_sequence_interrupt(uint32_t adc); -void adc_disable_eoc_sequence_interrupt(uint32_t adc); -bool adc_get_eoc_sequence_flag(uint32_t adc); -void adc_clear_eoc_sequence_flag(uint32_t adc); - -/* Basic configuration */ -void adc_set_clk_source(uint32_t adc, uint32_t source); -void adc_enable_vbat_sensor(void); -void adc_disable_vbat_sensor(void); -void adc_calibrate_start(uint32_t adc) - LIBOPENCM3_DEPRECATED("see adc_calibrate/_async"); -void adc_calibrate_wait_finish(uint32_t adc) - LIBOPENCM3_DEPRECATED("see adc_is_calibrating"); - -/* Analog Watchdog */ -void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); -void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan); -void adc_disable_analog_watchdog(uint32_t adc); -void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); -void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/cec.h b/libopencm3/include/libopencm3/stm32/f0/cec.h deleted file mode 100644 index 2193a97..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/cec.h +++ /dev/null @@ -1,125 +0,0 @@ -/** @defgroup CEC_defines CEC Defines - * - * @brief Defined Constants and Types for the STM32F0xx HDMI-CEC - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CEC_H -#define LIBOPENCM3_CEC_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -#define CEC CEC_BASE - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define CEC_CR MMIO32(CEC_BASE + 0x00) -#define CEC_CFGR MMIO32(CEC_BASE + 0x04) -#define CEC_TXDR MMIO32(CEC_BASE + 0x08) -#define CEC_RXDR MMIO32(CEC_BASE + 0x0c) -#define CEC_ISR MMIO32(CEC_BASE + 0x10) -#define CEC_IER MMIO32(CEC_BASE + 0x14) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* CEC_CR Values ------------------------------------------------------------*/ - -#define CEC_CR_TXEOM (1 << 2) -#define CEC_CR_TXSOM (1 << 1) -#define CEC_CR_CECEN (1 << 0) - -/* CEC_CFGR Values ----------------------------------------------------------*/ - -#define CEC_CFGR_LSTN (1 << 31) - -#define CEC_CFGR_OAR_SHIFT 16 -#define CEC_CFGR_OAR (0x3FFF << CEC_CFGR_OAR_SHIFT) - -#define CEC_CFGR_SFTOPT (1 << 8) -#define CEC_CFGR_BRDNOGEN (1 << 7) -#define CEC_CFGR_LBPEGEN (1 << 6) -#define CEC_CFGR_BREGEN (1 << 5) -#define CEC_CFGR_BRESTP (1 << 4) -#define CEC_CFGR_RXTOL (1 << 3) - -#define CEC_CFGR_SFT_SHIFT 0 -#define CEC_CFGR_SFT (7 >> CEC_CFGR_SFT_SHIFT) - -/* CEC_ISR Values -----------------------------------------------------------*/ - -#define CEC_ISR_TXACKE (1 << 12) -#define CEC_ISR_TXERR (1 << 11) -#define CEC_ISR_TXUDR (1 << 10) -#define CEC_ISR_TXEND (1 << 9) -#define CEC_ISR_TXBR (1 << 8) -#define CEC_ISR_ARBLST (1 << 7) -#define CEC_ISR_RXACKE (1 << 6) -#define CEC_ISR_LBPE (1 << 5) -#define CEC_ISR_SBPE (1 << 4) -#define CEC_ISR_BRE (1 << 3) -#define CEC_ISR_RXOVR (1 << 2) -#define CEC_ISR_RXEND (1 << 1) -#define CEC_ISR_RXBR (1 << 0) - -/* CEC_IER Values -----------------------------------------------------------*/ - -#define CEC_IER_TXACKIE (1 << 12) -#define CEC_IER_TXERRIE (1 << 11) -#define CEC_IER_TXUDRIE (1 << 10) -#define CEC_IER_TXENDIE (1 << 9) -#define CEC_IER_TXBRIE (1 << 8) -#define CEC_IER_ARBLSTIE (1 << 7) -#define CEC_IER_RXACKIE (1 << 6) -#define CEC_IER_LBPEIE (1 << 5) -#define CEC_IER_SBPEIE (1 << 4) -#define CEC_IER_BREIE (1 << 3) -#define CEC_IER_RXOVRIE (1 << 2) -#define CEC_IER_RXENDIE (1 << 1) -#define CEC_IER_RXBRIE (1 << 0) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/comparator.h b/libopencm3/include/libopencm3/stm32/f0/comparator.h deleted file mode 100644 index 78db9cf..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/comparator.h +++ /dev/null @@ -1,124 +0,0 @@ -/** @defgroup comp_defines COMP Defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F0xx - * Comparator module - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 29 Jun 2013 - * - *LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_COMP_H -#define LIBOPENCM3_COMP_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -#define COMP1 0 -#define COMP2 1 - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define COMP_CSR(i) MMIO16(SYSCFG_COMP_BASE + 0x1c + (i)*2) -#define COMP_CSR1 COMP_CSR(COMP1) -#define COMP_CSR2 COMP_CSR(COMP2) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* COMP_CSR Values ----------------------------------------------------------*/ - -#define COMP_CSR_LOCK (1 << 15) -#define COMP_CSR_OUT (1 << 14) - -#define COMP_CSR_HYST_SHIFT 12 -#define COMP_CSR_HYST (3 << COMP_CSR_HYST_SHIFT) -#define COMP_CSR_HYST_NO (0 << COMP_CSR_HYST_SHIFT) -#define COMP_CSR_HYST_LOW (1 << COMP_CSR_HYST_SHIFT) -#define COMP_CSR_HYST_MED (2 << COMP_CSR_HYST_SHIFT) -#define COMP_CSR_HYST_HIGH (3 << COMP_CSR_HYST_SHIFT) - -#define COMP_CSR_POL (1 << 11) - -#define COMP_CSR_OUTSEL_SHIFT 8 -#define COMP_CSR_OUTSEL (7 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_NONE (0 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM1_BRK (1 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM1_IC1 (2 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM1_OCRCLR (3 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM2_IC4 (4 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM2_OCRCLR (5 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM3_IC1 (6 << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_TIM3_OCRCLR (7 << COMP_CSR_OUTSEL_SHIFT) - -#define COMP_CSR_WINDWEN (1 << 23) - -#define COMP_CSR_INSEL_SHIFT 4 -#define COMP_CSR_INSEL (7 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_1_4_VREFINT (0 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_2_4_VREFINT (1 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_3_4_VREFINT (2 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_4_4_VREFINT (3 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_VREFINT (3 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_INM4 (4 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_INM5 (5 << COMP_CSR_INSEL_SHIFT) -#define COMP_CSR_INSEL_INM6 (6 << COMP_CSR_INSEL_SHIFT) - -#define COMP_CSR_SPEED_SHIFT 2 -#define COMP_CSR_SPEED (3 << COMP_CSR_SPEED_SHIFT) -#define COMP_CSR_SPEED_HIGH (0 << COMP_CSR_SPEED_SHIFT) -#define COMP_CSR_SPEED_MED (1 << COMP_CSR_SPEED_SHIFT) -#define COMP_CSR_SPEED_LOW (2 << COMP_CSR_SPEED_SHIFT) -#define COMP_CSR_SPEED_VERYLOW (3 << COMP_CSR_SPEED_SHIFT) - -#define COMP_CSR_SW1 (1 << 1) -#define COMP_CSR_EN (1 << 0) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -void comp_enable(uint8_t id); -void comp_disable(uint8_t id); -void comp_select_input(uint8_t id, uint32_t input); -void comp_select_output(uint8_t id, uint32_t output); -void comp_select_hyst(uint8_t id, uint32_t hyst); -void comp_select_speed(uint8_t id, uint32_t speed); - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/crc.h b/libopencm3/include/libopencm3/stm32/f0/crc.h deleted file mode 100644 index fb8ff8f..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F1xx CRC - * Generator - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 29 Jun 2013 - * - *LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/dac.h b/libopencm3/include/libopencm3/stm32/f0/dac.h deleted file mode 100644 index 7f54484..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/dac.h +++ /dev/null @@ -1,117 +0,0 @@ -/** @defgroup dac_defines DAC Defines - * - * @brief Defined Constants and Types for the STM32F0xx Digital to Analog - * Converter - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -#define DAC DAC_BASE - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define DAC_CR MMIO32(DAC_BASE + 0x00) -#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) -#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) -#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) -#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) -#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) -#define DAC_SR MMIO32(DAC_BASE + 0x34) - - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* DAC_CR Values ------------------------------------------------------------*/ - -#define DAC_CR_DMAUDRIE1 (1 << 13) -#define DAC_CR_DMAEN1 (1 << 12) - -#define DAC_CR_TSEL1_SHIFT 3 -#define DAC_CR_TSEL1 (7 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM6_TRGO (0 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM8_TRGO (1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM7_TRGO (2 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM5_TRGO (3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM2_TRGO (4 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_TIM4_TRGO (5 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_EXT_9 (6 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_SWTRG (7 << DAC_CR_TSEL1_SHIFT) - -#define DAC_CR_TEN1 (1 << 2) -#define DAC_CR_BOFF1 (1 << 1) -#define DAC_CR_EN1 (1 << 0) - -/* DAC_SWTRIGR Values -------------------------------------------------------*/ - -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) - -/* DAC_DHR12R1 Values -------------------------------------------------------*/ - -#define DAC_DHR12R1_DACC1DHR 0xFFF - -/* DAC_DHR12L1 Values -------------------------------------------------------*/ - -#define DAC_DHR12L1_DACC1DHR (0xFFF << 4) - -/* DAC_DHR8R1 Values --------------------------------------------------------*/ - -#define DAC_DHR8R1_DACC1DHR 0xFF - -/* DAC_DOR1 Values ----------------------------------------------------------*/ - -#define DAC_DOR1_DACC1DOR 0xFFF - -/* DAC_SR Values ------------------------------------------------------------*/ - -#define DAC_SR_DMAUDR1 (1 << 13) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/dma.h b/libopencm3/include/libopencm3/stm32/f0/dma.h deleted file mode 100644 index d309bf7..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/dma.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32F0xx_defines - * - * @brief Defined Constants and Types for the STM32F0xx DMA Controller - * - * @version 1.0.0 - * - * @date 10 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h b/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h deleted file mode 100644 index 84d2fa0..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32F0 - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * API documentation for ST Microelectronics STM32F0 Cortex M0 series. - * - * LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F0xx STM32F0xx - * Libraries for ST Microelectronics STM32F0xx series. - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/** @defgroup STM32F0xx_defines STM32F0xx Defines - * - * @brief Defined Constants and Types for the STM32F0xx series - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - diff --git a/libopencm3/include/libopencm3/stm32/f0/exti.h b/libopencm3/include/libopencm3/stm32/f0/exti.h deleted file mode 100644 index 0a3aeba..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/exti.h +++ /dev/null @@ -1,43 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F0xx External Interrupts - * - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H -/**@{*/ - -#include -#include - - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/flash.h b/libopencm3/include/libopencm3/stm32/f0/flash.h deleted file mode 100644 index 818e5f2..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/flash.h +++ /dev/null @@ -1,120 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @brief Defined Constants and Types for the STM32F0xx Flash memory - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H -/**@{*/ - -#include -#include -#include - -/* --- FLASH_OPTION values ------------------------------------------------- */ - -/** @defgroup flash_options Option Byte Addresses -@ingroup flash_defines -@{*/ -#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0) -#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1) -#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2) -#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3) -#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4) -#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5) -/**@}*/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY_000_024MHZ 0 -#define FLASH_ACR_LATENCY_024_048MHZ 1 -#define FLASH_ACR_LATENCY_0WS 0 -#define FLASH_ACR_LATENCY_1WS 1 -/**@}*/ - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_EOP (1 << 5) -#define FLASH_SR_WRPRTERR (1 << 4) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_OBL_LAUNCH (1 << 13) - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -#define FLASH_OBR_DATA1_SHIFT 24 -#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT) -#define FLASH_OBR_DATA0_SHIFT 16 -#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT) - -#define FLASH_OBR_BOOT_SEL (1 << 15) -#define FLASH_OBR_RAM_PARITY_CHECK (1 << 14) -#define FLASH_OBR_VDDA_MONITOR (1 << 13) -#define FLASH_OBR_NBOOT1 (1 << 12) -#define FLASH_OBR_NBOOT0 (1 << 11) -#define FLASH_OBR_NRST_STDBY (1 << 10) -#define FLASH_OBR_NRST_STOP (1 << 9) -#define FLASH_OBR_WDG_SW (1 << 8) -#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT) -#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/* Read protection option byte protection level setting */ -#define FLASH_RDP_L0 ((uint8_t)0xaa) -#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */ -#define FLASH_RDP_L2 ((uint8_t)0xcc) - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/gpio.h b/libopencm3/include/libopencm3/stm32/f0/gpio.h deleted file mode 100644 index a5a2236..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/gpio.h +++ /dev/null @@ -1,75 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the STM32F0xx General Purpose I/O - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 1 July 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define GPIO_BRR(port) MMIO32((port) + 0x28) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOF_BRR GPIO_BRR(GPIOF) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @defgroup gpio_speed GPIO Output Pin Speed -@ingroup gpio_defines -@{*/ -#define GPIO_OSPEED_LOW 0x0 -#define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x3 -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/i2c.h b/libopencm3/include/libopencm3/stm32/f0/i2c.h deleted file mode 100644 index d105a2f..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/i2c.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the STM32F0xx I2C - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f0/irq.json b/libopencm3/include/libopencm3/stm32/f0/irq.json deleted file mode 100644 index ab7c9f8..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/irq.json +++ /dev/null @@ -1,39 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "rtc", - "flash", - "rcc", - "exti0_1", - "exti2_3", - "exti4_15", - "tsc", - "dma1_channel1", - "dma1_channel2_3_dma2_channel1_2", - "dma1_channel4_7_dma2_channel3_5", - "adc_comp", - "tim1_brk_up_trg_com", - "tim1_cc", - "tim2", - "tim3", - "tim6_dac", - "tim7", - "tim14", - "tim15", - "tim16", - "tim17", - "i2c1", - "i2c2", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3_4", - "cec_can", - "usb" - ], - "partname_humanreadable": "STM32 F0 series", - "partname_doxygen": "STM32F0", - "includeguard": "LIBOPENCM3_STM32_F0_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f0/iwdg.h b/libopencm3/include/libopencm3/stm32/f0/iwdg.h deleted file mode 100644 index be7b6e9..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/iwdg.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @brief Defined Constants and Types for the STM32F0xx Independent Watchdog - * Timer - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/memorymap.h b/libopencm3/include/libopencm3/stm32/f0/memorymap.h deleted file mode 100644 index 12e6c58..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/memorymap.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * .. based on file from F4. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all buses */ -#define FLASH_BASE (0x08000000U) -#define PERIPH_BASE (0x40000000U) -#define INFO_BASE (0x1ffff000U) -#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000) -#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB + 0x0400) - -#define TIM6_BASE (PERIPH_BASE_APB + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB + 0x1400) - -#define TIM14_BASE (PERIPH_BASE_APB + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB + 0x3000) -/* PERIPH_BASE_APB + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB + 0x3800) -/* PERIPH_BASE_APB + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB + 0x4800) -#define USART4_BASE (PERIPH_BASE_APB + 0x4C00) -#define USART5_BASE (PERIPH_BASE_APB + 0x5000) - -#define I2C1_BASE (PERIPH_BASE_APB + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB + 0x5C00) -#define USB_PMA_BASE (PERIPH_BASE_APB + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB + 0x6400) - -#define CRS_BASE (PERIPH_BASE_APB + 0x6C00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB + 0x7400) -#define CEC_BASE (PERIPH_BASE_APB + 0x7800) - -#define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000) -#define EXTI_BASE (PERIPH_BASE_APB + 0x10400) - -#define USART6_BASE (PERIPH_BASE_APB + 0x11400) -#define USART7_BASE (PERIPH_BASE_APB + 0x11800) -#define USART8_BASE (PERIPH_BASE_APB + 0x11C00) - -#define ADC_BASE (PERIPH_BASE_APB + 0x12400) -#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) -#define SPI1_BASE (PERIPH_BASE_APB + 0x13000) - -#define USART1_BASE (PERIPH_BASE_APB + 0x13800) -#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) -#define TIM16_BASE (PERIPH_BASE_APB + 0x14400) -#define TIM17_BASE (PERIPH_BASE_APB + 0x14800) - -#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) - -/* AHB1 */ -#define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000) -/* DMA is the name in the F0 refman, but all other stm32's use DMA1 */ -#define DMA1_BASE DMA_BASE -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) - -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) - -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) - -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) - -#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) - -/* AHB2 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU) -#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - -/* ST provided factory calibration values @ 3.3V */ -#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA) -#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8) -#define ST_TSENSE_CAL2_110C MMIO16(0x1FFFF7C2) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/pwr.h b/libopencm3/include/libopencm3/stm32/f0/pwr.h deleted file mode 100644 index c01c7d3..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/pwr.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - * - * @brief Defined Constants and Types for the STM32F0xx PWR Control - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* EWUP: Enable WKUP2 pin */ -#define PWR_CSR_EWUP2 (1 << 9) - -/* EWUP: Enable WKUP1 pin */ -#define PWR_CSR_EWUP1 (1 << 8) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f0/rcc.h b/libopencm3/include/libopencm3/stm32/f0/rcc.h deleted file mode 100644 index 3bd4f58..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/rcc.h +++ /dev/null @@ -1,587 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F0xx Reset and Clock -Control - * - * @ingroup STM32F0xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @version 1.0.0 - * - * @date 29 Jun 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) -#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) -#define RCC_CR2 MMIO32(RCC_BASE + 0x34) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSICAL_SHIFT 8 -#define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT) -#define RCC_CR_HSITRIM_SHIFT 3 -#define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT) -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -#define RCC_CFGR_PLLNODIV (1 << 31) - -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) -#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) - -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf -#define RCC_CFGR_MCO_NOCLK 0 -#define RCC_CFGR_MCO_HSI14 1 -#define RCC_CFGR_MCO_LSI 2 -#define RCC_CFGR_MCO_LSE 3 -#define RCC_CFGR_MCO_SYSCLK 4 -#define RCC_CFGR_MCO_HSI 5 -#define RCC_CFGR_MCO_HSE 6 -#define RCC_CFGR_MCO_PLL 7 -#define RCC_CFGR_MCO_HSI48 8 - -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) -/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor - * @{ - */ -#define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL5 (0x03 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL6 (0x04 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL7 (0x05 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL8 (0x06 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL9 (0x07 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL10 (0x08 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL11 (0x09 << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL12 (0x0A << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL13 (0x0B << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL14 (0x0C << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL15 (0x0D << RCC_CFGR_PLLMUL_SHIFT) -#define RCC_CFGR_PLLMUL_MUL16 (0x0E << RCC_CFGR_PLLMUL_SHIFT) -/**@}*/ - -#define RCC_CFGR_PLLXTPRE (1<<17) -/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL source - * @{ - */ -#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 -#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 -/**@}*/ - -#define RCC_CFGR_PLLSRC (1<<16) -/** @defgroup rcc_cfgr_pcs PLLSRC: PLL Clock source - * @{ - */ -#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -/**@}*/ - -#define RCC_CFGR_PLLSRC0 (1<<15) -#define RCC_CFGR_ADCPRE (1<<14) - -#define RCC_CFGR_PPRE_SHIFT 8 -#define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) -/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB prescale Factors -@{*/ -#define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT) -#define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT) -#define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT) -#define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT) -#define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT) -/**@}*/ - -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT) -/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors -@{*/ -#define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV8 (0xa << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV16 (0xb << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV64 (0xc << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT) -#define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT) -/**@}*/ - -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) -#define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) -#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) -#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) -#define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) - -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) -#define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) -#define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) -#define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) -#define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) - -/* --- RCC_CIR values ------------------------------------------------------ */ - -#define RCC_CIR_CSSC (1 << 23) -#define RCC_CIR_HSI48RDYC (1 << 22) -#define RCC_CIR_HSI14RDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) -#define RCC_CIR_HSI48RDYIE (1 << 14) -#define RCC_CIR_HSI14RDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) -#define RCC_CIR_CSSF (1 << 7) -#define RCC_CIR_HSI48RDYF (1 << 6) -#define RCC_CIR_HSI14RDYF (1 << 5) -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_DBGMCURST (1 << 22) -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_ADCRST (1 << 9) -#define RCC_APB2RSTR_USART8RST (1 << 7) -#define RCC_APB2RSTR_USART7RST (1 << 6) -#define RCC_APB2RSTR_USART6RST (1 << 5) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_CECRST (1 << 30) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_CRSRST (1 << 27) -#define RCC_APB1RSTR_CANRST (1 << 25) -#define RCC_APB1RSTR_USBRST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART5RST (1 << 20) -#define RCC_APB1RSTR_USART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM14RST (1 << 8) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values -@{*/ -#define RCC_AHBENR_TSCEN (1 << 24) -#define RCC_AHBENR_GPIOFEN (1 << 22) -#define RCC_AHBENR_GPIOEEN (1 << 21) -#define RCC_AHBENR_GPIODEN (1 << 20) -#define RCC_AHBENR_GPIOCEN (1 << 19) -#define RCC_AHBENR_GPIOBEN (1 << 18) -#define RCC_AHBENR_GPIOAEN (1 << 17) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLTFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) -#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1EN /* compatibility alias */ -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values -@{*/ -#define RCC_APB2ENR_DBGMCUEN (1 << 22) -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADCEN (1 << 9) -#define RCC_APB2ENR_USART8EN (1 << 7) -#define RCC_APB2ENR_USART7EN (1 << 6) -#define RCC_APB2ENR_USART6EN (1 << 5) -#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_CECEN (1 << 30) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_CRSEN (1 << 27) -#define RCC_APB1ENR_CANEN (1 << 25) -#define RCC_APB1ENR_USBEN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART5EN (1 << 20) -#define RCC_APB1ENR_USART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM14EN (1 << 8) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT) -#define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) -#define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) -#define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) -#define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT) -#define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) -#define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) -#define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) -#define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF) -#define RCC_CSR_V18PWRRSTF (1 << 23) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values -@{*/ -#define RCC_AHBRSTR_TSCRST (1 << 24) -#define RCC_AHBRSTR_IOPFRST (1 << 22) -#define RCC_AHBRSTR_IOPERST (1 << 21) -#define RCC_AHBRSTR_IOPDRST (1 << 20) -#define RCC_AHBRSTR_IOPCRST (1 << 19) -#define RCC_AHBRSTR_IOPBRST (1 << 18) -#define RCC_AHBRSTR_IOPARST (1 << 17) -/**@}*/ - - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -#define RCC_CFGR2_PREDIV 0xf -/** @defgroup rcc_cfgr2_prediv PLL source predividers -@ingroup rcc_defines -@{*/ -#define RCC_CFGR2_PREDIV_NODIV 0x0 -#define RCC_CFGR2_PREDIV_DIV2 0x1 -#define RCC_CFGR2_PREDIV_DIV3 0x2 -#define RCC_CFGR2_PREDIV_DIV4 0x3 -#define RCC_CFGR2_PREDIV_DIV5 0x4 -#define RCC_CFGR2_PREDIV_DIV6 0x5 -#define RCC_CFGR2_PREDIV_DIV7 0x6 -#define RCC_CFGR2_PREDIV_DIV8 0x7 -#define RCC_CFGR2_PREDIV_DIV9 0x8 -#define RCC_CFGR2_PREDIV_DIV10 0x9 -#define RCC_CFGR2_PREDIV_DIV11 0xa -#define RCC_CFGR2_PREDIV_DIV12 0xb -#define RCC_CFGR2_PREDIV_DIV13 0xc -#define RCC_CFGR2_PREDIV_DIV14 0xd -#define RCC_CFGR2_PREDIV_DIV15 0xe -#define RCC_CFGR2_PREDIV_DIV16 0xf -/**@}*/ - -/* --- RCC_CFGR3 values ---------------------------------------------------- */ - -#define RCC_CFGR3_USART2SW_SHIFT 16 -#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) -#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) - -#define RCC_CFGR3_ADCSW (1 << 8) -#define RCC_CFGR3_USBSW (1 << 7) -#define RCC_CFGR3_CECSW (1 << 6) -#define RCC_CFGR3_I2C1SW (1 << 4) - -#define RCC_CFGR3_USART1SW_SHIFT 0 -#define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT) -#define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) -#define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) -#define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) -#define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) - -/* --- RCC_CFGR3 values ---------------------------------------------------- */ - -#define RCC_CR2_HSI48CAL_SHIFT 24 -#define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT) -#define RCC_CR2_HSI48RDY (1 << 17) -#define RCC_CR2_HSI48ON (1 << 16) -#define RCC_CR2_HSI14CAL_SHIFT 8 -#define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT) -#define RCC_CR2_HSI14TRIM_SHIFT 3 -#define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT) -#define RCC_CR2_HSI14DIS (1 << 2) -#define RCC_CR2_HSI14RDY (1 << 1) -#define RCC_CR2_HSI14ON (1 << 0) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -/** F0 doens't _realllly_ have apb2, but it has a bunch of things - * enabled via the "APB2" enable register. Fake it out. - */ -#define rcc_apb2_frequency rcc_apb1_frequency - -enum rcc_osc { - RCC_HSI14, RCC_HSI, RCC_HSE, RCC_PLL, RCC_LSI, RCC_LSE, RCC_HSI48 -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB peripherals */ - RCC_DMA = _REG_BIT(0x14, 0), - RCC_DMA1 = _REG_BIT(0x14, 0), /* Compatibility alias */ - RCC_DMA2 = _REG_BIT(0x14, 1), - RCC_SRAM = _REG_BIT(0x14, 2), - RCC_FLTIF = _REG_BIT(0x14, 4), - RCC_CRC = _REG_BIT(0x14, 6), - RCC_GPIOA = _REG_BIT(0x14, 17), - RCC_GPIOB = _REG_BIT(0x14, 18), - RCC_GPIOC = _REG_BIT(0x14, 19), - RCC_GPIOD = _REG_BIT(0x14, 20), - RCC_GPIOE = _REG_BIT(0x14, 21), - RCC_GPIOF = _REG_BIT(0x14, 22), - RCC_TSC = _REG_BIT(0x14, 24), - - /* APB2 peripherals */ - RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), - RCC_USART6 = _REG_BIT(0x18, 5), - RCC_USART7 = _REG_BIT(0x18, 6), - RCC_USART8 = _REG_BIT(0x18, 7), - RCC_ADC = _REG_BIT(0x18, 9), - RCC_ADC1 = _REG_BIT(0x18, 9), /* Compatibility alias */ - RCC_TIM1 = _REG_BIT(0x18, 11), - RCC_SPI1 = _REG_BIT(0x18, 12), - RCC_USART1 = _REG_BIT(0x18, 14), - RCC_TIM15 = _REG_BIT(0x18, 16), - RCC_TIM16 = _REG_BIT(0x18, 17), - RCC_TIM17 = _REG_BIT(0x18, 18), - RCC_DBGMCU = _REG_BIT(0x18, 22), - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x1C, 0), - RCC_TIM3 = _REG_BIT(0x1C, 1), - RCC_TIM6 = _REG_BIT(0x1C, 4), - RCC_TIM7 = _REG_BIT(0x1C, 5), - RCC_TIM14 = _REG_BIT(0x1C, 8), - RCC_WWDG = _REG_BIT(0x1C, 11), - RCC_SPI2 = _REG_BIT(0x1C, 14), - RCC_USART2 = _REG_BIT(0x1C, 17), - RCC_USART3 = _REG_BIT(0x1C, 18), - RCC_USART4 = _REG_BIT(0x1C, 19), - RCC_USART5 = _REG_BIT(0x1C, 20), - RCC_I2C1 = _REG_BIT(0x1C, 21), - RCC_I2C2 = _REG_BIT(0x1C, 22), - RCC_USB = _REG_BIT(0x1C, 23), - RCC_CAN = _REG_BIT(0x1C, 25), - RCC_CAN1 = _REG_BIT(0x1C, 25), /* Compatibility alias */ - RCC_CRS = _REG_BIT(0x1C, 27), - RCC_PWR = _REG_BIT(0x1C, 28), - RCC_DAC = _REG_BIT(0x1C, 29), - RCC_DAC1 = _REG_BIT(0x1C, 29), /* Compatibility alias */ - RCC_CEC = _REG_BIT(0x1C, 30), - - /* Advanced peripherals */ - RCC_RTC = _REG_BIT(0x20, 15),/* BDCR[15] */ -}; - -enum rcc_periph_rst { - /* APB2 peripherals */ - RST_SYSCFG = _REG_BIT(0x0C, 0), - RST_ADC = _REG_BIT(0x0C, 9), - RST_ADC1 = _REG_BIT(0x0C, 9), /* Compatibility alias */ - RST_TIM1 = _REG_BIT(0x0C, 11), - RST_SPI1 = _REG_BIT(0x0C, 12), - RST_USART1 = _REG_BIT(0x0C, 14), - RST_TIM15 = _REG_BIT(0x0C, 16), - RST_TIM16 = _REG_BIT(0x0C, 17), - RST_TIM17 = _REG_BIT(0x0C, 18), - RST_DBGMCU = _REG_BIT(0x0C, 22), - - /* APB1 peripherals */ - RST_TIM2 = _REG_BIT(0x10, 0), - RST_TIM3 = _REG_BIT(0x10, 1), - RST_TIM6 = _REG_BIT(0x10, 4), - RST_TIM7 = _REG_BIT(0x10, 5), - RST_TIM14 = _REG_BIT(0x10, 8), - RST_WWDG = _REG_BIT(0x10, 11), - RST_SPI2 = _REG_BIT(0x10, 14), - RST_USART2 = _REG_BIT(0x10, 17), - RST_USART3 = _REG_BIT(0x10, 18), - RST_USART4 = _REG_BIT(0x10, 19), - RST_I2C1 = _REG_BIT(0x10, 21), - RST_I2C2 = _REG_BIT(0x10, 22), - RST_USB = _REG_BIT(0x10, 23), - RST_CAN = _REG_BIT(0x10, 25), - RST_CAN1 = _REG_BIT(0x10, 25), /* Compatibility alias */ - RST_CRS = _REG_BIT(0x10, 27), - RST_PWR = _REG_BIT(0x10, 28), - RST_DAC = _REG_BIT(0x10, 29), - RST_DAC1 = _REG_BIT(0x10, 29), /* Compatibility alias */ - RST_CEC = _REG_BIT(0x10, 30), - - /* Advanced peripherals */ - RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */ - - /* AHB peripherals */ - RST_GPIOA = _REG_BIT(0x28, 17), - RST_GPIOB = _REG_BIT(0x28, 18), - RST_GPIOC = _REG_BIT(0x28, 19), - RST_GPIOD = _REG_BIT(0x28, 20), - RST_GPIOE = _REG_BIT(0x28, 21), - RST_GPIOF = _REG_BIT(0x28, 22), - RST_TSC = _REG_BIT(0x28, 24), -}; -#undef _REG_BIT - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_set_sysclk_source(enum rcc_osc clk); -void rcc_set_usbclk_source(enum rcc_osc clk); -void rcc_set_rtc_clock_source(enum rcc_osc clk); -void rcc_enable_rtc_clock(void); -void rcc_disable_rtc_clock(void); -void rcc_set_pll_multiplication_factor(uint32_t mul); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_pllxtpre(uint32_t pllxtpre); -void rcc_set_ppre(uint32_t ppre); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_prediv(uint32_t prediv); -enum rcc_osc rcc_system_clock_source(void); -void rcc_set_i2c_clock_hsi(uint32_t i2c); -void rcc_set_i2c_clock_sysclk(uint32_t i2c); -uint32_t rcc_get_i2c_clocks(void); -enum rcc_osc rcc_usb_clock_source(void); -void rcc_clock_setup_in_hse_8mhz_out_48mhz(void); -void rcc_clock_setup_in_hsi_out_48mhz(void); -void rcc_clock_setup_in_hsi48_out_48mhz(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f0/rtc.h b/libopencm3/include/libopencm3/stm32/f0/rtc.h deleted file mode 100644 index 8a99c24..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the STM32F0xx RTC - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/spi.h b/libopencm3/include/libopencm3/stm32/f0/spi.h deleted file mode 100644 index b956336..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/spi.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup spi_defines SPI Defines - * - * @brief Defined Constants and Types for the STM32F0xx SPI - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/st_usbfs.h b/libopencm3/include/libopencm3/stm32/f0/st_usbfs.h deleted file mode 100644 index 7b65d2b..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/syscfg.h b/libopencm3/include/libopencm3/stm32/f0/syscfg.h deleted file mode 100644 index fcfb74a..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/syscfg.h +++ /dev/null @@ -1,121 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @brief Defined Constants and Types for the STM32F0xx System Config - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00) -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4) -#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) -#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) -#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) -#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) -#define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/ - -#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0 -#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) - -#define SYSCFG_CFGR1_PA11_PA12_RMP (1 << 4) -#define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8) -#define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9) -#define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10) -#define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11) -#define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12) -#define SYSCFG_CFGR1_TIM16_DMA_RMP2 (1 << 13) -#define SYSCFG_CFGR1_TIM17_DMA_RMP2 (1 << 14) - -#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) -#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) -#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) -#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) -#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) -#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) -#define SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22) -#define SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23) -#define SYSCFG_CFGR1_SPI2_DMA_RMP (1 << 24) -#define SYSCFG_CFGR1_USART2_DMA_RMP (1 << 25) -#define SYSCFG_CFGR1_USART3_DMA_RMP (1 << 26) -#define SYSCFG_CFGR1_I2C1_DMA_RMP (1 << 27) -#define SYSCFG_CFGR1_TIM1_DMA_RMP (1 << 28) -#define SYSCFG_CFGR1_TIM2_DMA_RMP (1 << 29) -#define SYSCFG_CFGR1_TIM3_DMA_RMP (1 << 30) - -/* SYSCFG_EXTICR Values -- --------------------------------------------------*/ - -#define SYSCFG_EXTICR_FIELDSIZE 4 -#define SYSCFG_EXTICR_GPIOA 0 -#define SYSCFG_EXTICR_GPIOB 1 -#define SYSCFG_EXTICR_GPIOC 2 -#define SYSCFG_EXTICR_GPIOD 3 -#define SYSCFG_EXTICR_GPIOF 5 - -/* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/ - -#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0) -#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1) -#define SYSCFG_CFGR2_PVD_LOCK (1 << 2) -#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/timer.h b/libopencm3/include/libopencm3/stm32/f0/timer.h deleted file mode 100644 index 5f59816..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/timer.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup timer_defines Timers Defines - * - * @brief Defined Constants and Types for the STM32F0xx Timers - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/tsc.h b/libopencm3/include/libopencm3/stm32/f0/tsc.h deleted file mode 100644 index 989451f..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/tsc.h +++ /dev/null @@ -1,159 +0,0 @@ -/** @defgroup tsc_defines TSC Defines - * - * @brief Defined Constants and Types for the STM32F0xx Touch Sensor - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TSC_H -#define LIBOPENCM3_TSC_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -#define TSC TSC_BASE - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define TSC_CR MMIO32(TSC_BASE + 0x00) -#define TSC_IER MMIO32(TSC_BASE + 0x04) -#define TSC_ICR MMIO32(TSC_BASE + 0x08) -#define TSC_ISR MMIO32(TSC_BASE + 0x0c) -#define TSC_IOHCR MMIO32(TSC_BASE + 0x10) -#define TSC_IOASCR MMIO32(TSC_BASE + 0x18) -#define TSC_IOSCR MMIO32(TSC_BASE + 0x20) -#define TSC_IOCCR MMIO32(TSC_BASE + 0x28) -#define TSC_IOGCSR MMIO32(TSC_BASE + 0x30) -#define TSC_IOGxCR(x) MMIO32(TSC_BASE + 0x34 + ((x)-1)*4) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* TSC_CR Values ------------------------------------------------------------*/ - -#define TSC_CR_CTPH_SHIFT 28 -#define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT) - -#define TSC_CR_CTPL_SHIFT 24 -#define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT) - -#define TSC_CR_SSD_SHIFT 17 -#define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT) - -#define TSC_CR_SSE (1 << 16) -#define TSC_CR_SSPSC (1 << 15) - -#define TSC_CR_PGPSC_SHIFT 12 -#define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT) - -#define TSC_CR_MCV_SHIFT 5 -#define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT) - -#define TSC_CR_IODEF (1 << 4) -#define TSC_CR_SYNCPOL (1 << 3) -#define TSC_CR_AM (1 << 2) -#define TSC_CR_START (1 << 1) -#define TSC_CR_TSCE (1 << 0) - -/* TSC_IER Values -----------------------------------------------------------*/ - -#define TSC_IER_MCEIE (1 << 1) -#define TSC_IER_EOAIE (1 << 0) - -/* TSC_ICR Values -----------------------------------------------------------*/ - -#define TSC_ICR_MCEIC (1 << 1) -#define TSC_ICR_EOAIC (1 << 0) - -/* TSC_ISR Values -----------------------------------------------------------*/ - -#define TSC_ISR_MCEF (1 << 1) -#define TSC_ISR_EOAF (1 << 0) - -/* TSC_IOHCR Values ---------------------------------------------------------*/ - -/* Bit helper g = [1..6] io = [1..4] */ -#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4)) - -#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io) -#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io) -#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io) -#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io) -#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io) -#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io) - -/* TSC_IOASCR Values --------------------------------------------------------*/ - -#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io) -#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io) -#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io) -#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io) -#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io) -#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io) - -/* TSC_IOSCR Values ---------------------------------------------------------*/ - -#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io) -#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io) -#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io) -#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io) -#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io) -#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io) - -/* TSC_IOCCR Values ---------------------------------------------------------*/ - -#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io) -#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io) -#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io) -#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io) -#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io) -#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io) - -/* TSC_IOGCSR Values --------------------------------------------------------*/ - -#define TSC_IOGCSR_GxE(x) (1 << ((x)-1)) -#define TSC_IOGCSR_GxS(x) (1 << ((x)+15)) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/usart.h b/libopencm3/include/libopencm3/stm32/f0/usart.h deleted file mode 100644 index 869f484..0000000 --- a/libopencm3/include/libopencm3/stm32/f0/usart.h +++ /dev/null @@ -1,72 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32F0xx USART - * - * @ingroup STM32F0xx_defines - * - * @version 1.0.0 - * - * @date 2 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define USART4 USART4_BASE -#define USART5 USART5_BASE -#define USART6 USART6_BASE -#define USART7 USART7_BASE -#define USART8 USART8_BASE -/**@}*/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/adc.h b/libopencm3/include/libopencm3/stm32/f1/adc.h deleted file mode 100644 index 3941036..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/adc.h +++ /dev/null @@ -1,425 +0,0 @@ -/** @defgroup adc_defines ADC Defines - -@brief Defined Constants and Types for the STM32F1xx Analog to Digital -Converters - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2009 -Edward Cheeseman - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Edward Cheeseman - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32((block) + 0x14) -#define ADC_JOFR2(block) MMIO32((block) + 0x18) -#define ADC_JOFR3(block) MMIO32((block) + 0x1c) -#define ADC_JOFR4(block) MMIO32((block) + 0x20) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32((block) + 0x24) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32((block) + 0x28) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32((block) + 0x2c) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32((block) + 0x30) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32((block) + 0x34) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32((block) + 0x38) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32((block) + 0x3c) -#define ADC_JDR2(block) MMIO32((block) + 0x40) -#define ADC_JDR3(block) MMIO32((block) + 0x44) -#define ADC_JDR4(block) MMIO32((block) + 0x48) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32((block) + 0x4c) - - -/* --- ADC_CR1 values ------------------------------------------------------ */ - -/* Note: Bits [21:20] are reserved, and must be kept at reset value. */ - -/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */ -/* Legend: - * IND: Independent mode. - * CRSISM: Combined regular simultaneous + injected simultaneous mode. - * CRSATM: Combined regular simultaneous + alternate trigger mode. - * CISFIM: Combined injected simultaneous + fast interleaved mode. - * CISSIM: Combined injected simultaneous + slow interleaved mode. - * ISM: Injected simultaneous mode only. - * RSM: Regular simultaneous mode only. - * FIM: Fast interleaved mode only. - * SIM: Slow interleaved mode only. - * ATM: Alternate trigger mode only. - */ -/****************************************************************************/ -/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */ -/** @defgroup adc_cr1_dualmod ADC Mode Selection -@ingroup adc_defines - -@{*/ -/** Independent (non-dual) mode */ -#define ADC_CR1_DUALMOD_IND (0x0 << 16) -/** Combined regular simultaneous + injected simultaneous mode. */ -#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16) -/** Combined regular simultaneous + alternate trigger mode. */ -#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16) -/** Combined injected simultaneous + fast interleaved mode. */ -#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16) -/** Combined injected simultaneous + slow interleaved mode. */ -#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16) -/** Injected simultaneous mode only. */ -#define ADC_CR1_DUALMOD_ISM (0x5 << 16) -/** Regular simultaneous mode only. */ -#define ADC_CR1_DUALMOD_RSM (0x6 << 16) -/** Fast interleaved mode only. */ -#define ADC_CR1_DUALMOD_FIM (0x7 << 16) -/** Slow interleaved mode only. */ -#define ADC_CR1_DUALMOD_SIM (0x8 << 16) -/** Alternate trigger mode only. */ -#define ADC_CR1_DUALMOD_ATM (0x9 << 16) -/**@}*/ -#define ADC_CR1_DUALMOD_MASK (0xF << 16) -#define ADC_CR1_DUALMOD_SHIFT 16 - -#define ADC_CR1_AWDCH_MAX 17 - -/* --- ADC_CR2 values ------------------------------------------------------ */ - -/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */ -#define ADC_CR2_TSVREFE (1 << 23) - -/* SWSTART: */ /** Start conversion of regular channels. */ -#define ADC_CR2_SWSTART (1 << 22) - -/* JSWSTART: */ /** Start conversion of injected channels. */ -#define ADC_CR2_JSWSTART (1 << 21) - -/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */ -#define ADC_CR2_EXTTRIG (1 << 20) - -/* EXTSEL[2:0]: External event select for regular group. */ -/* The following are only valid for ADC1 and ADC2. */ -/****************************************************************************/ -/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */ -/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2 -@ingroup adc_defines - -@{*/ -/** Timer 1 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17) -/** Timer 1 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17) -/** Timer 1 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) -/** Timer 2 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17) -/** Timer 3 Trigger Output */ -#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17) -/** Timer 4 Compare Output 4 */ -#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17) -/** External Interrupt 11 */ -#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17) -/** Software Trigger */ -#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17) -/**@}*/ - -/* The following are only valid for ADC3 */ -/****************************************************************************/ -/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */ -/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3 -@ingroup adc_defines - -@{*/ -/** Timer 2 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17) -/** Timer 2 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17) -/** Timer 1 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) -/** Timer 8 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17) -/** Timer 8 Trigger Output */ -#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17) -/** Timer 5 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17) -/** Timer 5 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17) -/**@}*/ - -#define ADC_CR2_EXTSEL_MASK (0x7 << 17) -#define ADC_CR2_EXTSEL_SHIFT 17 - -/* Note: Bit 16 is reserved, must be kept at reset value. */ - -/* JEXTTRIG: External trigger conversion mode for injected channels. */ -#define ADC_CR2_JEXTTRIG (1 << 15) - -/* JEXTSEL[2:0]: External event selection for injected group. */ -/* The following are only valid for ADC1 and ADC2. */ -/****************************************************************************/ -/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */ -/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 -and ADC2 -@ingroup adc_defines - -@{*/ -/** Timer 1 Trigger Output */ -#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) -/** Timer 1 Compare Output 4 */ -#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) -/** Timer 2 Trigger Output */ -#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12) -/** Timer 2 Compare Output 1 */ -#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12) -/** Timer 3 Compare Output 4 */ -#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12) -/** Timer 4 Trigger Output */ -#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12) -/** External Interrupt 15 */ -#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12) -/** Injected Software Trigger */ -#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ -/**@}*/ - -/* The following are the different meanings for ADC3 only. */ -/****************************************************************************/ -/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */ -/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3 -@ingroup adc_defines - -@{*/ -/** Timer 1 Trigger Output */ -#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) -/** Timer 1 Compare Output 4 */ -#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) -/** Timer 4 Compare Output 3 */ -#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12) -/** Timer 8 Compare Output 2 */ -#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12) -/** Timer 8 Compare Output 4 */ -#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) -/** Timer 5 Trigger Output */ -#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) -/** Timer 5 Compare Output 4 */ -#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) -/** Injected Software Trigger */ -#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ -/**@}*/ - -#define ADC_CR2_JEXTSEL_MASK (0x7 << 12) -#define ADC_CR2_JEXTSEL_SHIFT 12 - -/* ALIGN: Data alignment. */ -#define ADC_CR2_ALIGN_RIGHT (0 << 11) -#define ADC_CR2_ALIGN_LEFT (1 << 11) -#define ADC_CR2_ALIGN (1 << 11) - -/* Note: Bits [10:9] are reserved and must be kept at reset value. */ - -/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ -#define ADC_CR2_DMA (1 << 8) - -/* Note: Bits [7:4] are reserved and must be kept at reset value. */ - -/* RSTCAL: Reset calibration. */ -#define ADC_CR2_RSTCAL (1 << 3) - -/* CAL: A/D Calibration. */ -#define ADC_CR2_CAL (1 << 2) - -/* CONT: Continuous conversion. */ -#define ADC_CR2_CONT (1 << 1) - -/* ADON: A/D converter On/Off. */ -/* Note: If any other bit in this register apart from ADON is changed at the - * same time, then conversion is not triggered. This is to prevent triggering - * an erroneous conversion. - * Conclusion: Must be separately written. - */ -#define ADC_CR2_ADON (1 << 0) - -/* --- ADC_SMPR1 values ---------------------------------------------------- */ -#define ADC_SMPR1_SMP17_LSB 21 -#define ADC_SMPR1_SMP16_LSB 18 -#define ADC_SMPR1_SMP15_LSB 15 -#define ADC_SMPR1_SMP14_LSB 12 -#define ADC_SMPR1_SMP13_LSB 9 -#define ADC_SMPR1_SMP12_LSB 6 -#define ADC_SMPR1_SMP11_LSB 3 -#define ADC_SMPR1_SMP10_LSB 0 -#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMPR1_SMP17_LSB) -#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMPR1_SMP16_LSB) -#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMPR1_SMP15_LSB) -#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMPR1_SMP14_LSB) -#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMPR1_SMP13_LSB) -#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMPR1_SMP12_LSB) -#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMPR1_SMP11_LSB) -#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMPR1_SMP10_LSB) - -/* --- ADC_SMPR2 values ---------------------------------------------------- */ - -#define ADC_SMPR2_SMP9_LSB 27 -#define ADC_SMPR2_SMP8_LSB 24 -#define ADC_SMPR2_SMP7_LSB 21 -#define ADC_SMPR2_SMP6_LSB 18 -#define ADC_SMPR2_SMP5_LSB 15 -#define ADC_SMPR2_SMP4_LSB 12 -#define ADC_SMPR2_SMP3_LSB 9 -#define ADC_SMPR2_SMP2_LSB 6 -#define ADC_SMPR2_SMP1_LSB 3 -#define ADC_SMPR2_SMP0_LSB 0 -#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMPR2_SMP9_LSB) -#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMPR2_SMP8_LSB) -#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMPR2_SMP7_LSB) -#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMPR2_SMP6_LSB) -#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMPR2_SMP5_LSB) -#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMPR2_SMP4_LSB) -#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMPR2_SMP3_LSB) -#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMPR2_SMP2_LSB) -#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMPR2_SMP1_LSB) -#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMPR2_SMP0_LSB) - -/* --- ADC_SMPRx values --------------------------------------------------- */ -/****************************************************************************/ -/* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_1DOT5CYC 0x0 -#define ADC_SMPR_SMP_7DOT5CYC 0x1 -#define ADC_SMPR_SMP_13DOT5CYC 0x2 -#define ADC_SMPR_SMP_28DOT5CYC 0x3 -#define ADC_SMPR_SMP_41DOT5CYC 0x4 -#define ADC_SMPR_SMP_55DOT5CYC 0x5 -#define ADC_SMPR_SMP_71DOT5CYC 0x6 -#define ADC_SMPR_SMP_239DOT5CYC 0x7 -/**@}*/ - - -/* --- ADC_SQR1 values ----------------------------------------------------- */ - -#define ADC_SQR_MAX_CHANNELS_REGULAR 16 - -#define ADC_SQR1_SQ16_LSB 15 -#define ADC_SQR1_SQ15_LSB 10 -#define ADC_SQR1_SQ14_LSB 5 -#define ADC_SQR1_SQ13_LSB 0 -#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) - -/* --- ADC_SQR2 values ----------------------------------------------------- */ - -#define ADC_SQR2_SQ12_LSB 25 -#define ADC_SQR2_SQ11_LSB 20 -#define ADC_SQR2_SQ10_LSB 15 -#define ADC_SQR2_SQ9_LSB 10 -#define ADC_SQR2_SQ8_LSB 5 -#define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) - -/* --- ADC_SQR3 values ----------------------------------------------------- */ - -#define ADC_SQR3_SQ6_LSB 25 -#define ADC_SQR3_SQ5_LSB 20 -#define ADC_SQR3_SQ4_LSB 15 -#define ADC_SQR3_SQ3_LSB 10 -#define ADC_SQR3_SQ2_LSB 5 -#define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) - -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) -#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) - /* ADC1 only (dual mode) */ - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_TEMP 16 -#define ADC_CHANNEL_VREF 17 -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void adc_start_conversion_direct(uint32_t adc); -void adc_set_dual_mode(uint32_t mode); -void adc_enable_temperature_sensor(void); -void adc_disable_temperature_sensor(void); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger); -void adc_reset_calibration(uint32_t adc); -void adc_calibration(uint32_t adc) - LIBOPENCM3_DEPRECATED("see adc_calibrate/_async"); -void adc_calibrate_async(uint32_t adc); -bool adc_is_calibrating(uint32_t adc); -void adc_calibrate(uint32_t adc); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f1/bkp.h b/libopencm3/include/libopencm3/stm32/f1/bkp.h deleted file mode 100644 index 577c6c2..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/bkp.h +++ /dev/null @@ -1,211 +0,0 @@ -/** - * @defgroup bkp_defines BKP Defines - * @ingroup STM32F1xx_defines - * @brief Defined Constants and Types for the Backup Registers - * - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_BKP_H -#define LIBOPENCM3_BKP_H - -/** @defgroup BKP_registers BKP Registers - * @ingroup bkp_defines -@{*/ -/* Backup data register 1 (BKP_DR1) */ -#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) - -/* Backup data register 2 (BKP_DR2) */ -#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) - -/* Backup data register 3 (BKP_DR3) */ -#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) - -/* Backup data register 4 (BKP_DR4) */ -#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) - -/* Backup data register 5 (BKP_DR5) */ -#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) - -/* Backup data register 6 (BKP_DR6) */ -#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) - -/* Backup data register 7 (BKP_DR7) */ -#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) - -/* Backup data register 8 (BKP_DR8) */ -#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) - -/* Backup data register 9 (BKP_DR9) */ -#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) - -/* Backup data register 10 (BKP_DR10) */ -#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) - -/** RTC clock calibration register (BKP_RTCCR) */ -#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) - -/** Backup control register (BKP_CR) */ -#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) - -/** Backup control/status register (BKP_CSR) */ -#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) - -/* Backup data register 11 (BKP_DR11) */ -#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) - -/* Backup data register 12 (BKP_DR12) */ -#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) - -/* Backup data register 13 (BKP_DR13) */ -#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) - -/* Backup data register 14 (BKP_DR14) */ -#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) - -/* Backup data register 15 (BKP_DR15) */ -#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) - -/* Backup data register 16 (BKP_DR16) */ -#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) - -/* Backup data register 17 (BKP_DR17) */ -#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) - -/* Backup data register 18 (BKP_DR18) */ -#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) - -/* Backup data register 19 (BKP_DR19) */ -#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) - -/* Backup data register 20 (BKP_DR20) */ -#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) - -/* Backup data register 21 (BKP_DR21) */ -#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) - -/* Backup data register 22 (BKP_DR22) */ -#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) - -/* Backup data register 23 (BKP_DR23) */ -#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) - -/* Backup data register 24 (BKP_DR24) */ -#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) - -/* Backup data register 25 (BKP_DR25) */ -#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) - -/* Backup data register 26 (BKP_DR26) */ -#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) - -/* Backup data register 27 (BKP_DR27) */ -#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) - -/* Backup data register 28 (BKP_DR28) */ -#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) - -/* Backup data register 29 (BKP_DR29) */ -#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) - -/* Backup data register 30 (BKP_DR30) */ -#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) - -/* Backup data register 31 (BKP_DR31) */ -#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) - -/* Backup data register 32 (BKP_DR32) */ -#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) - -/* Backup data register 33 (BKP_DR33) */ -#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) - -/* Backup data register 34 (BKP_DR34) */ -#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) - -/* Backup data register 35 (BKP_DR35) */ -#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) - -/* Backup data register 36 (BKP_DR36) */ -#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) - -/* Backup data register 37 (BKP_DR37) */ -#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) - -/* Backup data register 38 (BKP_DR38) */ -#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) - -/* Backup data register 39 (BKP_DR39) */ -#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) - -/* Backup data register 40 (BKP_DR40) */ -#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) - -/* Backup data register 41 (BKP_DR41) */ -#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) - -/* Backup data register 42 (BKP_DR42) */ -#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) -/*@}*/ - -/** @defgroup BKP_RTCCR_Values BKP_RTCCR Values - * @ingroup bkp_defines -@{*/ -/** ASOS: Alarm or second output selection */ -#define BKP_RTCCR_ASOS (1 << 9) - -/** ASOE: Alarm or second output enable */ -#define BKP_RTCCR_ASOE (1 << 8) - -/** CCO: Calibration clock output */ -#define BKP_RTCCR_CCO (1 << 7) - -/** CAL[6:0]: Calibration value */ -#define BKP_RTCCR_CAL_LSB 0 -/*@}*/ - -/** @defgroup BKP_CR_Values BKP_CR Values - * @ingroup bkp_defines -@{*/ -/** TPAL: TAMPER pin active level */ -#define BKP_CR_TPAL (1 << 1) - -/** TPE: TAMPER pin enable */ -#define BKP_CR_TPE (1 << 0) -/*@}*/ - -/** @defgroup BKP_CSR_Values BKP_CSR Values - * @ingroup bkp_defines -@{*/ -/** TIF: Tamper interrupt flag */ -#define BKP_CSR_TIF (1 << 9) - -/** TEF: Tamper event flag */ -#define BKP_CSR_TEF (1 << 8) - -/** TPIE: TAMPER pin interrupt enable */ -#define BKP_CSR_TPIE (1 << 2) - -/** CTI: Clear tamper interrupt */ -#define BKP_CSR_CTI (1 << 1) - -/** CTE: Clear tamper event */ -#define BKP_CSR_CTE (1 << 0) -/*@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/crc.h b/libopencm3/include/libopencm3/stm32/f1/crc.h deleted file mode 100644 index a35bf49..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup crc_defines CRC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F1xx CRC -Generator - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/dac.h b/libopencm3/include/libopencm3/stm32/f1/dac.h deleted file mode 100644 index 145df73..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/dac.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32F1xx DAC - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/dma.h b/libopencm3/include/libopencm3/stm32/f1/dma.h deleted file mode 100644 index ac73090..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/dma.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dma_defines DMA Defines - -@ingroup STM32F1xx_defines - -@brief Defined Constants and Types for the STM32F1xx DMA Controller - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h b/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h deleted file mode 100644 index 55c9b9f..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32F1 - -@version 1.0.0 - -@date 7 September 2012 - -API documentation for ST Microelectronics STM32F1 Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F1xx STM32F1xx -Libraries for ST Microelectronics STM32F1xx series. - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32F1xx_defines STM32F1xx Defines - -@brief Defined Constants and Types for the STM32F1xx series - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/f1/exti.h b/libopencm3/include/libopencm3/stm32/f1/exti.h deleted file mode 100644 index 8fe1862..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/exti.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F1xx External Interrupts - * - * - * @ingroup STM32F1xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Piotr Esden-Tempski - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/flash.h b/libopencm3/include/libopencm3/stm32/f1/flash.h deleted file mode 100644 index d14df2b..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/flash.h +++ /dev/null @@ -1,121 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32F1xx_defines - * - * @brief Defined Constants and Types for the STM32F1xx FLASH Memory - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * For details see: - * PM0075 programming manual: STM32F10xxx Flash programming - * August 2010, Doc ID 17863 Rev 1 - * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/CD00283419.pdf - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -/**@{*/ - -#include -#include -#include - -/* --- FLASH_OPTION bytes ------------------------------------------------- */ - -/** @defgroup flash_options Option Byte Addresses -@ingroup flash_defines -@{*/ -#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0) -#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1) -#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2) -#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3) -#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4) -#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5) -#define FLASH_OPTION_BYTE_6 FLASH_OPTION_BYTE(6) -#define FLASH_OPTION_BYTE_7 FLASH_OPTION_BYTE(7) -/**@}*/ - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -#define FLASH_ACR_LATENCY_2WS 0x02 -/**@}*/ -#define FLASH_ACR_HLFCYA (1 << 3) - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_EOP (1 << 5) -#define FLASH_SR_WRPRTERR (1 << 4) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -/* FLASH_OBR[25:18]: Data1 */ -/* FLASH_OBR[17:10]: Data0 */ -#define FLASH_OBR_NRST_STDBY (1 << 4) -#define FLASH_OBR_NRST_STOP (1 << 3) -#define FLASH_OBR_WDG_SW (1 << 2) -#define FLASH_OBR_RDPRT_EN (1 << FLASH_OBR_RDPRT_SHIFT) - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/* Read protection option byte protection enable key */ -#define FLASH_RDP_KEY ((uint16_t)0x00a5) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_halfcycle_enable(void); -void flash_halfcycle_disable(void); -void flash_unlock_upper(void); -void flash_lock_upper(void); -void flash_clear_pgerr_flag_upper(void); -void flash_clear_eop_flag_upper(void); -void flash_clear_wrprterr_flag_upper(void); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/gpio.h b/libopencm3/include/libopencm3/stm32/f1/gpio.h deleted file mode 100644 index e8b4250..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/gpio.h +++ /dev/null @@ -1,979 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32F1xx General Purpose I/O - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 Piotr Esden-Tempski - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -/** @defgroup gpio_port_id GPIO Port IDs -@ingroup gpio_defines - -@{*/ -/* GPIO port base addresses (for convenience) */ -#define GPIOA GPIO_PORT_A_BASE -#define GPIOB GPIO_PORT_B_BASE -#define GPIOC GPIO_PORT_C_BASE -#define GPIOD GPIO_PORT_D_BASE -#define GPIOE GPIO_PORT_E_BASE -#define GPIOF GPIO_PORT_F_BASE -#define GPIOG GPIO_PORT_G_BASE -/**@}*/ - -/* --- Alternate function GPIOs -------------------------------------------- */ - -/* Default alternate functions of some pins (with and without remapping) */ - -/* CAN1 / CAN GPIO */ -#define GPIO_CAN1_RX GPIO11 /* PA11 */ -#define GPIO_CAN1_TX GPIO12 /* PA12 */ -#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ -#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ - -#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ -#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ -#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ -#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ - -#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ -#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ -#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ -#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ - -/* CAN1 / CAN BANK */ -#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */ -#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */ -#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */ -#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */ - -#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */ -#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */ -#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */ -#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */ - -#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */ -#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */ -#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */ -#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */ - -/* CAN2 GPIO */ -#define GPIO_CAN2_RX GPIO12 /* PB12 */ -#define GPIO_CAN2_TX GPIO13 /* PB13 */ - -#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ -#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ - -/* CAN2 BANK */ -#define GPIO_BANK_CAN2_RX GPIOB /* PB12 */ -#define GPIO_BANK_CAN2_TX GPIOB /* PB13 */ - -#define GPIO_BANK_CAN2_RE_RX GPIOB /* PB5 */ -#define GPIO_BANK_CAN2_RE_TX GPIOB /* PB6 */ - -/* JTAG/SWD GPIO */ -#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ -#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ -#define GPIO_JTDI GPIO15 /* PA15 */ -#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ -#define GPIO_JNTRST GPIO4 /* PB4 */ -#define GPIO_TRACECK GPIO2 /* PE2 */ -#define GPIO_TRACED0 GPIO3 /* PE3 */ -#define GPIO_TRACED1 GPIO4 /* PE4 */ -#define GPIO_TRACED2 GPIO5 /* PE5 */ -#define GPIO_TRACED3 GPIO6 /* PE6 */ - -/* JTAG/SWD BANK */ -#define GPIO_BANK_JTMS_SWDIO GPIOA /* PA13 */ -#define GPIO_BANK_JTCK_SWCLK GPIOA /* PA14 */ -#define GPIO_BANK_JTDI GPIOA /* PA15 */ -#define GPIO_BANK_JTDO_TRACESWO GPIOB /* PB3 */ -#define GPIO_BANK_JNTRST GPIOB /* PB4 */ -#define GPIO_BANK_TRACECK GPIOE /* PE2 */ -#define GPIO_BANK_TRACED0 GPIOE /* PE3 */ -#define GPIO_BANK_TRACED1 GPIOE /* PE4 */ -#define GPIO_BANK_TRACED2 GPIOE /* PE5 */ -#define GPIO_BANK_TRACED3 GPIOE /* PE6 */ - -/* Timer5 GPIO */ -#define GPIO_TIM5_CH1 GPIO0 /* PA0 */ -#define GPIO_TIM5_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM5_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ - -/* Timer5 BANK */ -#define GPIO_BANK_TIM5_CH1 GPIOA /* PA0 */ -#define GPIO_BANK_TIM5_CH2 GPIOA /* PA1 */ -#define GPIO_BANK_TIM5_CH3 GPIOA /* PA2 */ -#define GPIO_BANK_TIM5_CH4 GPIOA /* PA3 */ -#define GPIO_BANK_TIM5 GPIOA - -/* Timer4 GPIO */ -#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ -#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ -#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ -#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ - -#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ -#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ -#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ -#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ - -/* Timer4 BANK */ -#define GPIO_BANK_TIM4_CH1 GPIOB /* PB6 */ -#define GPIO_BANK_TIM4_CH2 GPIOB /* PB7 */ -#define GPIO_BANK_TIM4_CH3 GPIOB /* PB8 */ -#define GPIO_BANK_TIM4_CH4 GPIOB /* PB9 */ -#define GPIO_BANK_TIM4 GPIOB - -#define GPIO_BANK_TIM4_RE_CH1 GPIOD /* PD12 */ -#define GPIO_BANK_TIM4_RE_CH2 GPIOD /* PD13 */ -#define GPIO_BANK_TIM4_RE_CH3 GPIOD /* PD14 */ -#define GPIO_BANK_TIM4_RE_CH4 GPIOD /* PD15 */ -#define GPIO_BANK_TIM4_RE GPIOD - -/* Timer3 GPIO */ -#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ -#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ -#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ -#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ -#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ -#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ -#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ -#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ - -/* Timer3 BANK */ -#define GPIO_BANK_TIM3_CH1 GPIOA /* PA6 */ -#define GPIO_BANK_TIM3_CH2 GPIOA /* PA7 */ -#define GPIO_BANK_TIM3_CH3 GPIOB /* PB0 */ -#define GPIO_BANK_TIM3_CH4 GPIOB /* PB1 */ -#define GPIO_BANK_TIM3_CH12 GPIOA -#define GPIO_BANK_TIM3_CH34 GPIOB - -#define GPIO_BANK_TIM3_PR_CH1 GPIOB /* PB4 */ -#define GPIO_BANK_TIM3_PR_CH2 GPIOB /* PB5 */ -#define GPIO_BANK_TIM3_PR_CH3 GPIOB /* PB0 */ -#define GPIO_BANK_TIM3_PR_CH4 GPIOB /* PB1 */ -#define GPIO_BANK_TIM3_PR GPIOB - -#define GPIO_BANK_TIM3_FR_CH1 GPIOC /* PC6 */ -#define GPIO_BANK_TIM3_FR_CH2 GPIOC /* PC7 */ -#define GPIO_BANK_TIM3_FR_CH3 GPIOC /* PC8 */ -#define GPIO_BANK_TIM3_FR_CH4 GPIOC /* PC9 */ -#define GPIO_BANK_TIM3_FR GPIOC - -/* Timer2 GPIO */ -#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ - -#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ - -/* Timer2 BANK */ -#define GPIO_BANK_TIM2_CH1_ETR GPIOA /* PA0 */ -#define GPIO_BANK_TIM2_CH2 GPIOA /* PA1 */ -#define GPIO_BANK_TIM2_CH3 GPIOA /* PA2 */ -#define GPIO_BANK_TIM2_CH4 GPIOA /* PA3 */ -#define GPIO_BANK_TIM2 GPIOA - -#define GPIO_BANK_TIM2_PR1_CH1_ETR GPIOA /* PA15 */ -#define GPIO_BANK_TIM2_PR1_CH2 GPIOB /* PB3 */ -#define GPIO_BANK_TIM2_PR1_CH3 GPIOA /* PA2 */ -#define GPIO_BANK_TIM2_PR1_CH4 GPIOA /* PA3 */ -#define GPIO_BANK_TIM2_PR1_CH134 GPIOA - -#define GPIO_BANK_TIM2_PR2_CH1_ETR GPIOA /* PA0 */ -#define GPIO_BANK_TIM2_PR2_CH2 GPIOA /* PA1 */ -#define GPIO_BANK_TIM2_PR2_CH3 GPIOB /* PB10 */ -#define GPIO_BANK_TIM2_PR2_CH4 GPIOB /* PB11 */ -#define GPIO_BANK_TIM2_PR2_CH12 GPIOA -#define GPIO_BANK_TIM2_PR2_CH34 GPIOB - -#define GPIO_BANK_TIM2_FR_CH1_ETR GPIOA /* PA15 */ -#define GPIO_BANK_TIM2_FR_CH2 GPIOB /* PB3 */ -#define GPIO_BANK_TIM2_FR_CH3 GPIOB /* PB10 */ -#define GPIO_BANK_TIM2_FR_CH4 GPIOB /* PB11 */ -#define GPIO_BANK_TIM2_FR_CH234 GPIOB - -/* Timer1 GPIO */ -#define GPIO_TIM1_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ -#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ -#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ -#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ - -#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ -#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ -#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ -#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ - -#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ -#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ -#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ -#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ -#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ -#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ -#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ -#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ -#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ - -/* Timer1 BANK */ -#define GPIO_BANK_TIM1_ETR GPIOA /* PA12 */ -#define GPIO_BANK_TIM1_CH1 GPIOA /* PA8 */ -#define GPIO_BANK_TIM1_CH2 GPIOA /* PA9 */ -#define GPIO_BANK_TIM1_CH3 GPIOA /* PA10 */ -#define GPIO_BANK_TIM1_CH4 GPIOA /* PA11 */ -#define GPIO_BANK_TIM1_BKIN GPIOB /* PB12 */ -#define GPIO_BANK_TIM1_CH1N GPIOB /* PB13 */ -#define GPIO_BANK_TIM1_CH2N GPIOB /* PB14 */ -#define GPIO_BANK_TIM1_CH3N GPIOB /* PB15 */ -#define GPIO_BANK_TIM1_ETR_CH1234 GPIOA -#define GPIO_BANK_TIM1_BKIN_CH123N GPIOB - -#define GPIO_BANK_TIM1_PR_ETR GPIOA /* PA12 */ -#define GPIO_BANK_TIM1_PR_CH1 GPIOA /* PA8 */ -#define GPIO_BANK_TIM1_PR_CH2 GPIOA /* PA9 */ -#define GPIO_BANK_TIM1_PR_CH3 GPIOA /* PA10 */ -#define GPIO_BANK_TIM1_PR_CH4 GPIOA /* PA11 */ -#define GPIO_BANK_TIM1_PR_BKIN GPIOA /* PA6 */ -#define GPIO_BANK_TIM1_PR_CH1N GPIOA /* PA7 */ -#define GPIO_BANK_TIM1_PR_CH2N GPIOB /* PB0 */ -#define GPIO_BANK_TIM1_PR_CH3N GPIOB /* PB1 */ -#define GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N GPIOA -#define GPIO_BANK_TIM1_PR_CH23N GPIOB - -#define GPIO_BANK_TIM1_FR_ETR GPIOE /* PE7 */ -#define GPIO_BANK_TIM1_FR_CH1 GPIOE /* PE9 */ -#define GPIO_BANK_TIM1_FR_CH2 GPIOE /* PE11 */ -#define GPIO_BANK_TIM1_FR_CH3 GPIOE /* PE13 */ -#define GPIO_BANK_TIM1_FR_CH4 GPIOE /* PE14 */ -#define GPIO_BANK_TIM1_FR_BKIN GPIOE /* PE15 */ -#define GPIO_BANK_TIM1_FR_CH1N GPIOE /* PE8 */ -#define GPIO_BANK_TIM1_FR_CH2N GPIOE /* PE10 */ -#define GPIO_BANK_TIM1_FR_CH3N GPIOE /* PE12 */ -#define GPIO_BANK_TIM1_FR GPIOE - -/* UART5 GPIO */ -#define GPIO_UART5_TX GPIO12 /* PC12 */ -#define GPIO_UART5_RX GPIO2 /* PD2 */ - -/* UART5 BANK */ -#define GPIO_BANK_UART5_TX GPIOC /* PC12 */ -#define GPIO_BANK_UART5_RX GPIOD /* PD2 */ - -/* UART4 GPIO */ -#define GPIO_UART4_TX GPIO10 /* PC10 */ -#define GPIO_UART4_RX GPIO11 /* PC11 */ - -/* UART4 BANK */ -#define GPIO_BANK_UART4_TX GPIOC /* PC10 */ -#define GPIO_BANK_UART4_RX GPIOC /* PC11 */ - -/* USART3 GPIO */ -#define GPIO_USART3_TX GPIO10 /* PB10 */ -#define GPIO_USART3_RX GPIO11 /* PB11 */ -#define GPIO_USART3_CK GPIO12 /* PB12 */ -#define GPIO_USART3_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ -#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ -#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ -#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ -#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ -#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ -#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ -#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ - -/* USART3 BANK */ -#define GPIO_BANK_USART3_TX GPIOB /* PB10 */ -#define GPIO_BANK_USART3_RX GPIOB /* PB11 */ -#define GPIO_BANK_USART3_CK GPIOB /* PB12 */ -#define GPIO_BANK_USART3_CTS GPIOB /* PB13 */ -#define GPIO_BANK_USART3_RTS GPIOB /* PB14 */ - -#define GPIO_BANK_USART3_PR_TX GPIOC /* PC10 */ -#define GPIO_BANK_USART3_PR_RX GPIOC /* PC11 */ -#define GPIO_BANK_USART3_PR_CK GPIOC /* PC12 */ -#define GPIO_BANK_USART3_PR_CTS GPIOB /* PB13 */ -#define GPIO_BANK_USART3_PR_RTS GPIOB /* PB14 */ - -#define GPIO_BANK_USART3_FR_TX GPIOD /* PD8 */ -#define GPIO_BANK_USART3_FR_RX GPIOD /* PD9 */ -#define GPIO_BANK_USART3_FR_CK GPIOD /* PD10 */ -#define GPIO_BANK_USART3_FR_CTS GPIOD /* PD11 */ -#define GPIO_BANK_USART3_FR_RTS GPIOD /* PD12 */ - -/* USART2 GPIO */ -#define GPIO_USART2_CTS GPIO0 /* PA0 */ -#define GPIO_USART2_RTS GPIO1 /* PA1 */ -#define GPIO_USART2_TX GPIO2 /* PA2 */ -#define GPIO_USART2_RX GPIO3 /* PA3 */ -#define GPIO_USART2_CK GPIO4 /* PA4 */ - -#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ -#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ -#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ -#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ -#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ - -/* USART2 BANK */ -#define GPIO_BANK_USART2_CTS GPIOA /* PA0 */ -#define GPIO_BANK_USART2_RTS GPIOA /* PA1 */ -#define GPIO_BANK_USART2_TX GPIOA /* PA2 */ -#define GPIO_BANK_USART2_RX GPIOA /* PA3 */ -#define GPIO_BANK_USART2_CK GPIOA /* PA4 */ - -#define GPIO_BANK_USART2_RE_CTS GPIOD /* PD3 */ -#define GPIO_BANK_USART2_RE_RTS GPIOD /* PD4 */ -#define GPIO_BANK_USART2_RE_TX GPIOD /* PD5 */ -#define GPIO_BANK_USART2_RE_RX GPIOD /* PD6 */ -#define GPIO_BANK_USART2_RE_CK GPIOD /* PD7 */ - -/* USART1 GPIO */ -#define GPIO_USART1_TX GPIO9 /* PA9 */ -#define GPIO_USART1_RX GPIO10 /* PA10 */ - -#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ -#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ - -/* USART1 BANK */ -#define GPIO_BANK_USART1_TX GPIOA /* PA9 */ -#define GPIO_BANK_USART1_RX GPIOA /* PA10 */ - -#define GPIO_BANK_USART1_RE_TX GPIOB /* PB6 */ -#define GPIO_BANK_USART1_RE_RX GPIOB /* PB7 */ - -/* I2C1 GPIO */ -#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_SCL GPIO6 /* PB6 */ -#define GPIO_I2C1_SDA GPIO7 /* PB7 */ - -#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ -#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ - -/* I2C1 BANK */ -#define GPIO_BANK_I2C1_SMBAI GPIOB /* PB5 */ -#define GPIO_BANK_I2C1_SCL GPIOB /* PB6 */ -#define GPIO_BANK_I2C1_SDA GPIOB /* PB7 */ - -#define GPIO_BANK_I2C1_RE_SMBAI GPIOB /* PB5 */ -#define GPIO_BANK_I2C1_RE_SCL GPIOB /* PB8 */ -#define GPIO_BANK_I2C1_RE_SDA GPIOB /* PB9 */ - -/* I2C2 GPIO */ -#define GPIO_I2C2_SCL GPIO10 /* PB10 */ -#define GPIO_I2C2_SDA GPIO11 /* PB11 */ -#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ - -/* I2C2 BANK */ -#define GPIO_BANK_I2C2_SCL GPIOB /* PB10 */ -#define GPIO_BANK_I2C2_SDA GPIOB /* PB11 */ -#define GPIO_BANK_I2C2_SMBAI GPIOB /* PB12 */ - -/* SPI1 GPIO */ -#define GPIO_SPI1_NSS GPIO4 /* PA4 */ -#define GPIO_SPI1_SCK GPIO5 /* PA5 */ -#define GPIO_SPI1_MISO GPIO6 /* PA6 */ -#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ - -#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ -#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ -#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ -#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ - -/* SPI1 BANK */ -#define GPIO_BANK_SPI1_NSS GPIOA /* PA4 */ -#define GPIO_BANK_SPI1_SCK GPIOA /* PA5 */ -#define GPIO_BANK_SPI1_MISO GPIOA /* PA6 */ -#define GPIO_BANK_SPI1_MOSI GPIOA /* PA7 */ - -#define GPIO_BANK_SPI1_RE_NSS GPIOA /* PA15 */ -#define GPIO_BANK_SPI1_RE_SCK GPIOB /* PB3 */ -#define GPIO_BANK_SPI1_RE_MISO GPIOB /* PB4 */ -#define GPIO_BANK_SPI1_RE_MOSI GPIOB /* PB5 */ - -/* SPI2 GPIO */ -#define GPIO_SPI2_NSS GPIO12 /* PB12 */ -#define GPIO_SPI2_SCK GPIO13 /* PB13 */ -#define GPIO_SPI2_MISO GPIO14 /* PB14 */ -#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ - -/* SPI2 BANK */ -#define GPIO_BANK_SPI2_NSS GPIOB /* PB12 */ -#define GPIO_BANK_SPI2_SCK GPIOB /* PB13 */ -#define GPIO_BANK_SPI2_MISO GPIOB /* PB14 */ -#define GPIO_BANK_SPI2_MOSI GPIOB /* PB15 */ - -/* SPI3 GPIO */ -#define GPIO_SPI3_NSS GPIO15 /* PA15 */ -#define GPIO_SPI3_SCK GPIO3 /* PB3 */ -#define GPIO_SPI3_MISO GPIO4 /* PB4 */ -#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ - -#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ -#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ -#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ -#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ - -/* SPI3 BANK */ -#define GPIO_BANK_SPI3_NSS GPIOA /* PA15 */ -#define GPIO_BANK_SPI3_SCK GPIOB /* PB3 */ -#define GPIO_BANK_SPI3_MISO GPIOB /* PB4 */ -#define GPIO_BANK_SPI3_MOSI GPIOB /* PB5 */ - -#define GPIO_BANK_SPI3_RE_NSS GPIOA /* PA4 */ -#define GPIO_BANK_SPI3_RE_SCK GPIOC /* PC10 */ -#define GPIO_BANK_SPI3_RE_MISO GPIOC /* PC11 */ -#define GPIO_BANK_SPI3_RE_MOSI GPIOC /* PC12 */ - -/* ETH GPIO */ -#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ -#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ -#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ -#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ -#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ - -#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ -#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ -#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ -#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ -#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ - -/* ETH BANK */ -#define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */ -#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ -#define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */ -#define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */ -#define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */ - -#define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */ -#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ -#define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */ -#define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */ -#define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */ - -/* --- GPIO registers ------------------------------------------------------ */ - -/* Port configuration register low (GPIOx_CRL) */ -#define GPIO_CRL(port) MMIO32((port) + 0x00) -#define GPIOA_CRL GPIO_CRL(GPIOA) -#define GPIOB_CRL GPIO_CRL(GPIOB) -#define GPIOC_CRL GPIO_CRL(GPIOC) -#define GPIOD_CRL GPIO_CRL(GPIOD) -#define GPIOE_CRL GPIO_CRL(GPIOE) -#define GPIOF_CRL GPIO_CRL(GPIOF) -#define GPIOG_CRL GPIO_CRL(GPIOG) - -/* Port configuration register low (GPIOx_CRH) */ -#define GPIO_CRH(port) MMIO32((port) + 0x04) -#define GPIOA_CRH GPIO_CRH(GPIOA) -#define GPIOB_CRH GPIO_CRH(GPIOB) -#define GPIOC_CRH GPIO_CRH(GPIOC) -#define GPIOD_CRH GPIO_CRH(GPIOD) -#define GPIOE_CRH GPIO_CRH(GPIOE) -#define GPIOF_CRH GPIO_CRH(GPIOF) -#define GPIOG_CRH GPIO_CRH(GPIOG) - -/* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32((port) + 0x08) -#define GPIOA_IDR GPIO_IDR(GPIOA) -#define GPIOB_IDR GPIO_IDR(GPIOB) -#define GPIOC_IDR GPIO_IDR(GPIOC) -#define GPIOD_IDR GPIO_IDR(GPIOD) -#define GPIOE_IDR GPIO_IDR(GPIOE) -#define GPIOF_IDR GPIO_IDR(GPIOF) -#define GPIOG_IDR GPIO_IDR(GPIOG) - -/* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32((port) + 0x0c) -#define GPIOA_ODR GPIO_ODR(GPIOA) -#define GPIOB_ODR GPIO_ODR(GPIOB) -#define GPIOC_ODR GPIO_ODR(GPIOC) -#define GPIOD_ODR GPIO_ODR(GPIOD) -#define GPIOE_ODR GPIO_ODR(GPIOE) -#define GPIOF_ODR GPIO_ODR(GPIOF) -#define GPIOG_ODR GPIO_ODR(GPIOG) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32((port) + 0x10) -#define GPIOA_BSRR GPIO_BSRR(GPIOA) -#define GPIOB_BSRR GPIO_BSRR(GPIOB) -#define GPIOC_BSRR GPIO_BSRR(GPIOC) -#define GPIOD_BSRR GPIO_BSRR(GPIOD) -#define GPIOE_BSRR GPIO_BSRR(GPIOE) -#define GPIOF_BSRR GPIO_BSRR(GPIOF) -#define GPIOG_BSRR GPIO_BSRR(GPIOG) - -/* Port bit reset register (GPIOx_BRR) */ -#define GPIO_BRR(port) MMIO16((port) + 0x14) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) -#define GPIOG_BRR GPIO_BRR(GPIOG) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32((port) + 0x18) -#define GPIOA_LCKR GPIO_LCKR(GPIOA) -#define GPIOB_LCKR GPIO_LCKR(GPIOB) -#define GPIOC_LCKR GPIO_LCKR(GPIOC) -#define GPIOD_LCKR GPIO_LCKR(GPIOD) -#define GPIOE_LCKR GPIO_LCKR(GPIOE) -#define GPIOF_LCKR GPIO_LCKR(GPIOF) -#define GPIOG_LCKR GPIO_LCKR(GPIOG) - -/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ - -/** @defgroup gpio_cnf GPIO Pin Configuration -@ingroup gpio_defines -If mode specifies input, configuration can be -@li Analog input -@li Floating input -@li Pull up/down input - -If mode specifies output, configuration can be -@li Digital push-pull -@li Digital open drain -@li Alternate function push-pull or analog output -@li Alternate function open drain or analog output -@{*/ -/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ -/** Analog Input */ -#define GPIO_CNF_INPUT_ANALOG 0x00 -/** Digital Input Floating */ -#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ -/** Digital Input Pull Up and Down */ -#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 -/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ -/** Digital Output Pushpull */ -#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 -/** Digital Output Open Drain */ -#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 -/** Alternate Function Output Pushpull */ -#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 -/** Alternate Function Output Open Drain */ -#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 -/**@}*/ - -/* Pin mode (MODE[1:0]) values */ -/** @defgroup gpio_mode GPIO Pin Mode -@ingroup gpio_defines -@li Input (default after reset) -@li Output mode at 10 MHz maximum speed -@li Output mode at 2 MHz maximum speed -@li Output mode at 50 MHz maximum speed -@{*/ -#define GPIO_MODE_INPUT 0x00 /* Default */ -#define GPIO_MODE_OUTPUT_10_MHZ 0x01 -#define GPIO_MODE_OUTPUT_2_MHZ 0x02 -#define GPIO_MODE_OUTPUT_50_MHZ 0x03 -/**@}*/ - -/* --- GPIO_IDR values ----------------------------------------------------- */ - -/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ - -/* --- GPIO_ODR values ----------------------------------------------------- */ - -/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ - -/* --- GPIO_BSRR values ---------------------------------------------------- */ - -/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ -/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ - -/* --- GPIO_BRR values ----------------------------------------------------- */ - -/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ - -/* --- AFIO registers ------------------------------------------------------ */ - -/* Event control register (AFIO_EVCR) */ -#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) - -/* AF remap and debug I/O configuration register (AFIO_MAPR) */ -#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) - -/* External interrupt configuration register [0..3] (AFIO_EXTICR[1..4])*/ -#define AFIO_EXTICR(i) MMIO32(AFIO_BASE + 0x08 + (i)*4) -#define AFIO_EXTICR1 AFIO_EXTICR(0) -#define AFIO_EXTICR2 AFIO_EXTICR(1) -#define AFIO_EXTICR3 AFIO_EXTICR(2) -#define AFIO_EXTICR4 AFIO_EXTICR(3) - -/* AF remap and debug I/O configuration register (AFIO_MAPR) */ -#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C) - -/* --- AFIO_EVCR values ---------------------------------------------------- */ - -/* EVOE: Event output enable */ -#define AFIO_EVCR_EVOE (1 << 7) - -/* PORT[2:0]: Port selection */ -/** @defgroup afio_evcr_port EVENTOUT Port selection -@ingroup gpio_defines - -@{*/ -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) -/**@}*/ - -/* PIN[3:0]: Pin selection */ -/** @defgroup afio_evcr_pin EVENTOUT Pin selection -@ingroup gpio_defines - -@{*/ -#define AFIO_EVCR_PIN_Px0 (0x0 << 0) -#define AFIO_EVCR_PIN_Px1 (0x1 << 0) -#define AFIO_EVCR_PIN_Px2 (0x2 << 0) -#define AFIO_EVCR_PIN_Px3 (0x3 << 0) -#define AFIO_EVCR_PIN_Px4 (0x4 << 0) -#define AFIO_EVCR_PIN_Px5 (0x5 << 0) -#define AFIO_EVCR_PIN_Px6 (0x6 << 0) -#define AFIO_EVCR_PIN_Px7 (0x7 << 0) -#define AFIO_EVCR_PIN_Px8 (0x8 << 0) -#define AFIO_EVCR_PIN_Px9 (0x9 << 0) -#define AFIO_EVCR_PIN_Px10 (0xA << 0) -#define AFIO_EVCR_PIN_Px11 (0xB << 0) -#define AFIO_EVCR_PIN_Px12 (0xC << 0) -#define AFIO_EVCR_PIN_Px13 (0xD << 0) -#define AFIO_EVCR_PIN_Px14 (0xE << 0) -#define AFIO_EVCR_PIN_Px15 (0xF << 0) -/**@}*/ - -/* --- AFIO_MAPR values ---------------------------------------------------- */ - -/* 31 reserved */ - -/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity -Line Devices only -@ingroup gpio_defines - -@{*/ -/* PTP_PPS_REMAP: */ -/** Ethernet PTP PPS remapping (only connectivity line devices) */ -#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) - -/* TIM2ITR1_IREMAP: */ -/** TIM2 internal trigger 1 remapping (only connectivity line devices) */ -#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) - -/* SPI3_REMAP: */ -/** SPI3/I2S3 remapping (only connectivity line devices) */ -#define AFIO_MAPR_SPI3_REMAP (1 << 28) - -/* MII_REMAP: */ -/** MII or RMII selection (only connectivity line devices) */ -#define AFIO_MAPR_MII_RMII_SEL (1 << 23) - -/* CAN2_REMAP: */ -/** CAN2 I/O remapping (only connectivity line devices) */ -#define AFIO_MAPR_CAN2_REMAP (1 << 22) - -/* ETH_REMAP: */ -/** Ethernet MAC I/O remapping (only connectivity line devices) */ -#define AFIO_MAPR_ETH_REMAP (1 << 21) - -/**@}*/ - -/* 27 reserved */ - -/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ -/** @defgroup afio_swj_disable Serial Wire JTAG disables -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_SWJ_MASK (0x7 << 24) -/** Full Serial Wire JTAG capability */ -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -/** Full Serial Wire JTAG capability without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) -/** JTAG-DP disabled with SW-DP enabled */ -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) -/** JTAG-DP disabled and SW-DP disabled */ -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) -/**@}*/ - -/** @defgroup afio_remap Alternate Function Remap Controls -@ingroup gpio_defines - -@{*/ -/* ADC2_ETRGREG_REMAP: */ -/** - * ADC2 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-density devices) - */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) - -/* ADC2_ETRGINJ_REMAP: */ -/** - * ADC2 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-density devices) - */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) - -/* ADC1_ETRGREG_REMAP: */ -/** - * ADC1 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-density devices) - */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) - -/* ADC1_ETRGINJ_REMAP: */ -/** - * ADC1 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-density devices) - */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) - -/* TIM5CH4_IREMAP: */ -/** TIM5 channel 4 internal remap */ -#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) - -/* PD01_REMAP: */ -/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_PD01_REMAP (1 << 15) - -/* TIM4_REMAP: */ -/** TIM4 remapping */ -#define AFIO_MAPR_TIM4_REMAP (1 << 12) - -/* USART2_REMAP[1:0]: */ -/** USART2 remapping */ -#define AFIO_MAPR_USART2_REMAP (1 << 3) - -/* USART1_REMAP[1:0]: */ -/** USART1 remapping */ -#define AFIO_MAPR_USART1_REMAP (1 << 2) - -/* I2C1_REMAP[1:0]: */ -/** I2C1 remapping */ -#define AFIO_MAPR_I2C1_REMAP (1 << 1) - -/* SPI1_REMAP[1:0]: */ -/** SPI1 remapping */ -#define AFIO_MAPR_SPI1_REMAP (1 << 0) -/**@}*/ - -/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ -/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1 -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) -#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */ -#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) -/**@}*/ - -/* TIM3_REMAP[1:0]: TIM3 remapping */ -/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3 -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) -/**@}*/ - -/* TIM2_REMAP[1:0]: TIM2 remapping */ -/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2 -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) -/**@}*/ - -/* TIM1_REMAP[1:0]: TIM1 remapping */ -/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1 -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) -/**@}*/ - -/* USART3_REMAP[1:0]: USART3 remapping */ -/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3 -@ingroup gpio_defines - -@{*/ -#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) -/**@}*/ - -/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set -@ingroup gpio_defines - -@{*/ -/** various remaps, dma/dac/timer triggers (HD only) */ -#define AFIO_MAPR2_MISC_REMAP (1 << 13) - -/** TIM12_CH1 and TIM12_CH2 remapping (HD only) */ -#define AFIO_MAPR2_TIM12_REMAP (1 << 12) - -/** TIM76_DAC_DMA remap to DMA1/DMA2 */ -#define AFIO_MAPR2_TIM76_DAC_DMA_REMAPE (1 << 11) - -/* FSMC_NADV_DISCONNECT: */ -/** The NADV is disconnected from its allocated pin */ -#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10) - -/* TIM14_REMAP: */ -/** TIM14 remapping */ -#define AFIO_MAPR2_TIM14_REMAP (1 << 9) - -/* TIM13_REMAP: */ -/** TIM13 remapping */ -#define AFIO_MAPR2_TIM13_REMAP (1 << 8) - -/* TIM11_REMAP: */ -/** TIM11 remapping */ -#define AFIO_MAPR2_TIM11_REMAP (1 << 7) - -/* TIM10_REMAP: */ -/** TIM10 remapping */ -#define AFIO_MAPR2_TIM10_REMAP (1 << 6) - -/* TIM9_REMAP: */ -/** TIM9 remapping */ -#define AFIO_MAPR2_TIM9_REMAP (1 << 5) - -/** TIM1_DMA channel 1/2 remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP (1 << 4) - -/** CEC remapping (PB8 vs PB10) */ -#define AFIO_MAPR2_CEC_REMAP (1 << 3) - -/** TIM17 remapping (PB9 vs PB7) */ -#define AFIO_MAPR2_TIM17_REMAP (1 << 2) - -/** TIM16 remapping (PB8 vs PB6) */ -#define AFIO_MAPR2_TIM16_REMAP (1 << 1) - -/** TIM15 remapping channels 1/2 */ -#define AFIO_MAPR1_TIM16_REMAP (1 << 0) - -/**@}*/ - -/* --- AFIO_EXTICRx values ------------------------------------------------- */ - -/** EXTICR port selection bits */ -#define AFIO_EXTICR_FIELDSIZE 4 - -/** @defgroup afio_exti Alternate Function EXTI pin number -@ingroup gpio_defines - -@{*/ - -#define AFIO_EXTI0 0 -#define AFIO_EXTI1 1 -#define AFIO_EXTI2 2 -#define AFIO_EXTI3 3 -#define AFIO_EXTI4 4 -#define AFIO_EXTI5 5 -#define AFIO_EXTI6 6 -#define AFIO_EXTI7 7 -#define AFIO_EXTI8 8 -#define AFIO_EXTI9 9 -#define AFIO_EXTI10 10 -#define AFIO_EXTI11 11 -#define AFIO_EXTI12 12 -#define AFIO_EXTI13 13 -#define AFIO_EXTI14 14 -#define AFIO_EXTI15 15 - -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, - uint16_t gpios); -void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin); -void gpio_primary_remap(uint32_t swjenable, uint32_t maps); -void gpio_secondary_remap(uint32_t maps); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f1/i2c.h b/libopencm3/include/libopencm3/stm32/f1/i2c.h deleted file mode 100644 index f7e25f7..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/i2c.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32F1xx I2C - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/irq.json b/libopencm3/include/libopencm3/stm32/f1/irq.json deleted file mode 100644 index 20bf00c..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/irq.json +++ /dev/null @@ -1,75 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "tamper", - "rtc", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_channel1", - "dma1_channel2", - "dma1_channel3", - "dma1_channel4", - "dma1_channel5", - "dma1_channel6", - "dma1_channel7", - "adc1_2", - "usb_hp_can_tx", - "usb_lp_can_rx0", - "can_rx1", - "can_sce", - "exti9_5", - "tim1_brk", - "tim1_up", - "tim1_trg_com", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_wakeup", - "tim8_brk", - "tim8_up", - "tim8_trg_com", - "tim8_cc", - "adc3", - "fsmc", - "sdio", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6", - "tim7", - "dma2_channel1", - "dma2_channel2", - "dma2_channel3", - "dma2_channel4_5", - "dma2_channel5", - "eth", - "eth_wkup", - "can2_tx", - "can2_rx0", - "can2_rx1", - "can2_sce", - "otg_fs" - ], - "partname_humanreadable": "STM32 F1 series", - "partname_doxygen": "STM32F1", - "includeguard": "LIBOPENCM3_STM32_F1_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f1/iwdg.h b/libopencm3/include/libopencm3/stm32/f1/iwdg.h deleted file mode 100644 index cdb5115..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/iwdg.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - -@brief Defined Constants and Types for the STM32F1xx Independent Watchdog -Timer - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/memorymap.h b/libopencm3/include/libopencm3/stm32/f1/memorymap.h deleted file mode 100644 index cbc04f4..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/memorymap.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all buses */ -#define FLASH_BASE (0x08000000U) -#define PERIPH_BASE (0x40000000U) -#define INFO_BASE (0x1ffff000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ -#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) -/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) -#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) -#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) -#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) -#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) -#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) -#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) -#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) -/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ - -/* AHB */ -#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) -/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) -#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) -/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) -/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) -#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) -/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) -/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* FSMC */ -#define FSMC_BASE (PERIPH_BASE + 0x60000000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) -#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8) -/* Ignore the "reserved for future use" half of the first word */ -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/pwr.h b/libopencm3/include/libopencm3/stm32/f1/pwr.h deleted file mode 100644 index 27e899b..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/pwr.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32F1xx PWR Control - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/rcc.h b/libopencm3/include/libopencm3/stm32/f1/rcc.h deleted file mode 100644 index 3b066f1..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/rcc.h +++ /dev/null @@ -1,726 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F1xx Reset and Clock - * Control - * - * @ingroup STM32F1xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ -/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/ -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/ - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ -#define RCC_CR_PLL3ON (1 << 28) /* (**) */ -#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ -#define RCC_CR_PLL2ON (1 << 26) /* (**) */ -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -#define RCC_CFGR_OTGFSPRE (1 << 22) /* Connectivity line */ -#define RCC_CFGR_USBPRE (1 << 22) /* LD,MD, HD, XL */ - -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLMUL (0xF << RCC_CFGR_PLLMUL_SHIFT) - -#define RCC_CFGR_PLLXTPRE (1 << 17) -#define RCC_CFGR_PLLSRC (1 << 16) - -#define RCC_CFGR_ADCPRE_SHIFT 14 -#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT) - -#define RCC_CFGR_PPRE2_SHIFT 11 -#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT) - -#define RCC_CFGR_PPRE1_SHIFT 8 -#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT) - -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT) - -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) - -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) - -/* MCO: Microcontroller clock output */ -/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x4 -#define RCC_CFGR_MCO_HSI 0x5 -#define RCC_CFGR_MCO_HSE 0x6 -#define RCC_CFGR_MCO_PLL_DIV2 0x7 -#define RCC_CFGR_MCO_PLL2 0x8 /* (**) */ -#define RCC_CFGR_MCO_PLL3_DIV2 0x9 /* (**) */ -#define RCC_CFGR_MCO_XT1 0xa /* (**) */ -#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ -/**@}*/ - -/* USBPRE: USB prescaler (RCC_CFGR[22]) */ -/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 -#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 -/**@}*/ - -/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 - -/* PLLMUL: PLL multiplication factor */ -/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. - line */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ -/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */ -/**@}*/ - -/* TODO: conn. line differs. */ -/* PLLXTPRE: HSE divider for PLL entry */ -/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 -#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 -/**@}*/ - -/* PLLSRC: PLL entry clock source */ -/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ -/**@}*/ - -/* ADCPRE: ADC prescaler */ -/****************************************************************************/ -/** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 -/**@}*/ - -/* PPRE2: APB high-speed prescaler (APB2) */ -/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -/**@}*/ - -/* PPRE1: APB low-speed prescaler (APB1) */ -/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 -/**@}*/ - -/* HPRE: AHB prescaler */ -/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf -/**@}*/ - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 - -/* SW: System clock switch */ -/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 -/**@}*/ - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ -#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ -#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ -#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_ADC2RST (1 << 10) -#define RCC_APB2RSTR_ADC1RST (1 << 9) -#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ -#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ -#define RCC_APB2RSTR_IOPERST (1 << 6) -#define RCC_APB2RSTR_IOPDRST (1 << 5) -#define RCC_APB2RSTR_IOPCRST (1 << 4) -#define RCC_APB2RSTR_IOPBRST (1 << 3) -#define RCC_APB2RSTR_IOPARST (1 << 2) -#define RCC_APB2RSTR_AFIORST (1 << 0) -/**@}*/ - -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_BKPRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ -#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for - CAN1RST */ -#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/* --- RCC_AHBENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_AHBENR_ETHMACENRX (1 << 16) -#define RCC_AHBENR_ETHMACENTX (1 << 15) -#define RCC_AHBENR_ETHMACEN (1 << 14) -#define RCC_AHBENR_OTGFSEN (1 << 12) -#define RCC_AHBENR_SDIOEN (1 << 10) -#define RCC_AHBENR_FSMCEN (1 << 8) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) -/**@}*/ - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADC2EN (1 << 10) -#define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ -#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ -#define RCC_APB2ENR_IOPEEN (1 << 6) -#define RCC_APB2ENR_IOPDEN (1 << 5) -#define RCC_APB2ENR_IOPCEN (1 << 4) -#define RCC_APB2ENR_IOPBEN (1 << 3) -#define RCC_APB2ENR_IOPAEN (1 << 2) -#define RCC_APB2ENR_AFIOEN (1 << 0) -/**@}*/ - -/* --- RCC_APB1ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_BKPEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ -#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for - CAN1EN */ -#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values -@ingroup STM32F1xx_rcc_defines - -@{*/ -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) -/**@}*/ - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -/* I2S3SRC: I2S3 clock source */ -#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 - -/* I2S2SRC: I2S2 clock source */ -#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 -#define RCC_CFGR2_I2S2SRC (1 << 17) - -/* PREDIV1SRC: PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 -#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 -#define RCC_CFGR2_PREDIV1SRC (1 << 16) - -#define RCC_CFGR2_PLL3MUL_SHIFT 12 -#define RCC_CFGR2_PLL3MUL (0xF << RCC_CFGR2_PLL3MUL_SHIFT) - -#define RCC_CFGR2_PLL2MUL_SHIFT 8 -#define RCC_CFGR2_PLL2MUL (0xF << RCC_CFGR2_PLL2MUL_SHIFT) - -#define RCC_CFGR2_PREDIV2_SHIFT 4 -#define RCC_CFGR2_PREDIV2 (0xF << RCC_CFGR2_PREDIV2_SHIFT) - -#define RCC_CFGR2_PREDIV1_SHIFT 0 -#define RCC_CFGR2_PREDIV1 (0xF << RCC_CFGR2_PREDIV1_SHIFT) - -/* PLL3MUL: PLL3 multiplication factor */ -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf - -/* PLL2MUL: PLL2 multiplication factor */ -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf - -/* PREDIV: PREDIV division factor */ -#define RCC_CFGR2_PREDIV_NODIV 0x0 -#define RCC_CFGR2_PREDIV_DIV2 0x1 -#define RCC_CFGR2_PREDIV_DIV3 0x2 -#define RCC_CFGR2_PREDIV_DIV4 0x3 -#define RCC_CFGR2_PREDIV_DIV5 0x4 -#define RCC_CFGR2_PREDIV_DIV6 0x5 -#define RCC_CFGR2_PREDIV_DIV7 0x6 -#define RCC_CFGR2_PREDIV_DIV8 0x7 -#define RCC_CFGR2_PREDIV_DIV9 0x8 -#define RCC_CFGR2_PREDIV_DIV10 0x9 -#define RCC_CFGR2_PREDIV_DIV11 0xa -#define RCC_CFGR2_PREDIV_DIV12 0xb -#define RCC_CFGR2_PREDIV_DIV13 0xc -#define RCC_CFGR2_PREDIV_DIV14 0xd -#define RCC_CFGR2_PREDIV_DIV15 0xe -#define RCC_CFGR2_PREDIV_DIV16 0xf - -/* PREDIV2: PREDIV2 division factor */ -#define RCC_CFGR2_PREDIV2_NODIV 0x0 -#define RCC_CFGR2_PREDIV2_DIV2 0x1 -#define RCC_CFGR2_PREDIV2_DIV3 0x2 -#define RCC_CFGR2_PREDIV2_DIV4 0x3 -#define RCC_CFGR2_PREDIV2_DIV5 0x4 -#define RCC_CFGR2_PREDIV2_DIV6 0x5 -#define RCC_CFGR2_PREDIV2_DIV7 0x6 -#define RCC_CFGR2_PREDIV2_DIV8 0x7 -#define RCC_CFGR2_PREDIV2_DIV9 0x8 -#define RCC_CFGR2_PREDIV2_DIV10 0x9 -#define RCC_CFGR2_PREDIV2_DIV11 0xa -#define RCC_CFGR2_PREDIV2_DIV12 0xb -#define RCC_CFGR2_PREDIV2_DIV13 0xc -#define RCC_CFGR2_PREDIV2_DIV14 0xd -#define RCC_CFGR2_PREDIV2_DIV15 0xe -#define RCC_CFGR2_PREDIV2_DIV16 0xf - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_osc { - RCC_PLL, RCC_PLL2, RCC_PLL3, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -/* V = value line F100 - * N = standard line F101, F102, F103 - * C = communication line F105, F107 - */ -enum rcc_periph_clken { - - /* AHB peripherals */ - RCC_DMA1 = _REG_BIT(0x14, 0),/*VNC*/ - RCC_DMA2 = _REG_BIT(0x14, 1),/*VNC*/ - RCC_SRAM = _REG_BIT(0x14, 2),/*VNC*/ - RCC_FLTF = _REG_BIT(0x14, 4),/*VNC*/ - RCC_CRC = _REG_BIT(0x14, 6),/*VNC*/ - RCC_FSMC = _REG_BIT(0x14, 8),/*VN-*/ - RCC_SDIO = _REG_BIT(0x14, 10),/*-N-*/ - RCC_OTGFS = _REG_BIT(0x14, 12),/*--C*/ - RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/ - RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/ - RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/ - - /* APB2 peripherals */ - RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/ - RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/ - RCC_GPIOB = _REG_BIT(0x18, 3),/*VNC*/ - RCC_GPIOC = _REG_BIT(0x18, 4),/*VNC*/ - RCC_GPIOD = _REG_BIT(0x18, 5),/*VNC*/ - RCC_GPIOE = _REG_BIT(0x18, 6),/*VNC*/ - RCC_GPIOF = _REG_BIT(0x18, 7),/*VN-*/ - RCC_GPIOG = _REG_BIT(0x18, 8),/*VN-*/ - RCC_ADC1 = _REG_BIT(0x18, 9),/*VNC*/ - RCC_ADC2 = _REG_BIT(0x18, 10),/*-NC*/ - RCC_TIM1 = _REG_BIT(0x18, 11),/*VNC*/ - RCC_SPI1 = _REG_BIT(0x18, 12),/*VNC*/ - RCC_TIM8 = _REG_BIT(0x18, 13),/*-N-*/ - RCC_USART1 = _REG_BIT(0x18, 14),/*VNC*/ - RCC_ADC3 = _REG_BIT(0x18, 15),/*-N-*/ - RCC_TIM15 = _REG_BIT(0x18, 16),/*V--*/ - RCC_TIM16 = _REG_BIT(0x18, 17),/*V--*/ - RCC_TIM17 = _REG_BIT(0x18, 18),/*V--*/ - RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/ - RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/ - RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/ - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/ - RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/ - RCC_TIM4 = _REG_BIT(0x1C, 2),/*VNC*/ - RCC_TIM5 = _REG_BIT(0x1C, 3),/*VNC*/ - RCC_TIM6 = _REG_BIT(0x1C, 4),/*VNC*/ - RCC_TIM7 = _REG_BIT(0x1C, 5),/*VNC*/ - RCC_TIM12 = _REG_BIT(0x1C, 6),/*VN-*/ - RCC_TIM13 = _REG_BIT(0x1C, 7),/*VN-*/ - RCC_TIM14 = _REG_BIT(0x1C, 8),/*VN-*/ - RCC_WWDG = _REG_BIT(0x1C, 11),/*VNC*/ - RCC_SPI2 = _REG_BIT(0x1C, 14),/*VNC*/ - RCC_SPI3 = _REG_BIT(0x1C, 15),/*VNC*/ - RCC_USART2 = _REG_BIT(0x1C, 17),/*VNC*/ - RCC_USART3 = _REG_BIT(0x1C, 18),/*VNC*/ - RCC_UART4 = _REG_BIT(0x1C, 19),/*VNC*/ - RCC_UART5 = _REG_BIT(0x1C, 20),/*VNC*/ - RCC_I2C1 = _REG_BIT(0x1C, 21),/*VNC*/ - RCC_I2C2 = _REG_BIT(0x1C, 22),/*VNC*/ - RCC_USB = _REG_BIT(0x1C, 23),/*-N-*/ - RCC_CAN = _REG_BIT(0x1C, 25),/*-N-*/ - RCC_CAN1 = _REG_BIT(0x1C, 25),/*--C*/ - RCC_CAN2 = _REG_BIT(0x1C, 26),/*--C*/ - RCC_BKP = _REG_BIT(0x1C, 27),/*VNC*/ - RCC_PWR = _REG_BIT(0x1C, 28),/*VNC*/ - RCC_DAC = _REG_BIT(0x1C, 29),/*VNC*/ - RCC_CEC = _REG_BIT(0x1C, 30),/*V--*/ -}; - -enum rcc_periph_rst { - - /* AHB peripherals */ - RST_OTGFS = _REG_BIT(0x28, 12),/*--C*/ - RST_ETHMAC = _REG_BIT(0x28, 14),/*--C*/ - - /* APB2 peripherals */ - RST_AFIO = _REG_BIT(0x0c, 0),/*VNC*/ - RST_GPIOA = _REG_BIT(0x0c, 2),/*VNC*/ - RST_GPIOB = _REG_BIT(0x0c, 3),/*VNC*/ - RST_GPIOC = _REG_BIT(0x0c, 4),/*VNC*/ - RST_GPIOD = _REG_BIT(0x0c, 5),/*VNC*/ - RST_GPIOE = _REG_BIT(0x0c, 6),/*VNC*/ - RST_GPIOF = _REG_BIT(0x0c, 7),/*VN-*/ - RST_GPIOG = _REG_BIT(0x0c, 8),/*VN-*/ - RST_ADC1 = _REG_BIT(0x0c, 9),/*VNC*/ - RST_ADC2 = _REG_BIT(0x0c, 10),/*-NC*/ - RST_TIM1 = _REG_BIT(0x0c, 11),/*VNC*/ - RST_SPI1 = _REG_BIT(0x0c, 12),/*VNC*/ - RST_TIM8 = _REG_BIT(0x0c, 13),/*-N-*/ - RST_USART1 = _REG_BIT(0x0c, 14),/*VNC*/ - RST_ADC3 = _REG_BIT(0x0c, 15),/*-N-*/ - RST_TIM15 = _REG_BIT(0x0c, 16),/*V--*/ - RST_TIM16 = _REG_BIT(0x0c, 17),/*V--*/ - RST_TIM17 = _REG_BIT(0x0c, 18),/*V--*/ - RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/ - RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/ - RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/ - - /* APB1 peripherals */ - RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/ - RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/ - RST_TIM4 = _REG_BIT(0x10, 2),/*VNC*/ - RST_TIM5 = _REG_BIT(0x10, 3),/*VNC*/ - RST_TIM6 = _REG_BIT(0x10, 4),/*VNC*/ - RST_TIM7 = _REG_BIT(0x10, 5),/*VNC*/ - RST_TIM12 = _REG_BIT(0x10, 6),/*VN-*/ - RST_TIM13 = _REG_BIT(0x10, 7),/*VN-*/ - RST_TIM14 = _REG_BIT(0x10, 8),/*VN-*/ - RST_WWDG = _REG_BIT(0x10, 11),/*VNC*/ - RST_SPI2 = _REG_BIT(0x10, 14),/*VNC*/ - RST_SPI3 = _REG_BIT(0x10, 15),/*VNC*/ - RST_USART2 = _REG_BIT(0x10, 17),/*VNC*/ - RST_USART3 = _REG_BIT(0x10, 18),/*VNC*/ - RST_UART4 = _REG_BIT(0x10, 19),/*VNC*/ - RST_UART5 = _REG_BIT(0x10, 20),/*VNC*/ - RST_I2C1 = _REG_BIT(0x10, 21),/*VNC*/ - RST_I2C2 = _REG_BIT(0x10, 22),/*VNC*/ - RST_USB = _REG_BIT(0x10, 23),/*-N-*/ - RST_CAN = _REG_BIT(0x10, 25),/*-N-*/ - RST_CAN1 = _REG_BIT(0x10, 25),/*--C*/ - RST_CAN2 = _REG_BIT(0x10, 26),/*--C*/ - RST_BKP = _REG_BIT(0x10, 27),/*VNC*/ - RST_PWR = _REG_BIT(0x10, 28),/*VNC*/ - RST_DAC = _REG_BIT(0x10, 29),/*VNC*/ - RST_CEC = _REG_BIT(0x10, 30),/*V--*/ -}; - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_multiplication_factor(uint32_t mul); -void rcc_set_pll2_multiplication_factor(uint32_t mul); -void rcc_set_pll3_multiplication_factor(uint32_t mul); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_pllxtpre(uint32_t pllxtpre); -uint32_t rcc_rtc_clock_enabled_flag(void); -void rcc_enable_rtc_clock(void); -void rcc_set_rtc_clock_source(enum rcc_osc clock_source); -void rcc_set_adcpre(uint32_t adcpre); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_usbpre(uint32_t usbpre); -void rcc_set_prediv1(uint32_t prediv); -void rcc_set_prediv2(uint32_t prediv); -void rcc_set_prediv1_source(uint32_t rccsrc); -uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_in_hsi_out_64mhz(void); -void rcc_clock_setup_in_hsi_out_48mhz(void); -void rcc_clock_setup_in_hsi_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_25mhz_out_72mhz(void); -void rcc_backupdomain_reset(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f1/rtc.h b/libopencm3/include/libopencm3/stm32/f1/rtc.h deleted file mode 100644 index 242efef..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/rtc.h +++ /dev/null @@ -1,176 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the STM32F1xx Real Time Clock - * - * @ingroup STM32F1xx_defines - * - * @author @htmlonly © @endhtmlonly 2010 Uwe Hermann - * - * @version 1.0.0 - * - * @date 4 March 2013 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * The F1 RTC is a straight time stamp, a completely different peripheral to - * that found in the F2, F3, F4, L1 and F0. - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H -/**@{*/ - -#include -#include - -/* --- RTC registers ------------------------------------------------------- */ - -/* RTC control register high (RTC_CRH) */ -#define RTC_CRH MMIO32(RTC_BASE + 0x00) - -/* RTC control register low (RTC_CRL) */ -#define RTC_CRL MMIO32(RTC_BASE + 0x04) - -/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ -#define RTC_PRLH MMIO32(RTC_BASE + 0x08) -#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) - -/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ -#define RTC_DIVH MMIO32(RTC_BASE + 0x10) -#define RTC_DIVL MMIO32(RTC_BASE + 0x14) - -/* RTC counter register (RTC_CNTH / RTC_CNTL) */ -#define RTC_CNTH MMIO32(RTC_BASE + 0x18) -#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) - -/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ -#define RTC_ALRH MMIO32(RTC_BASE + 0x20) -#define RTC_ALRL MMIO32(RTC_BASE + 0x24) - -/* --- RTC_CRH values -------------------------------------------------------*/ - -/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ - -/* OWIE: Overflow interrupt enable */ -#define RTC_CRH_OWIE (1 << 2) - -/* ALRIE: Alarm interrupt enable */ -#define RTC_CRH_ALRIE (1 << 1) - -/* SECIE: Second interrupt enable */ -#define RTC_CRH_SECIE (1 << 0) - -/* --- RTC_CRL values -------------------------------------------------------*/ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* RTOFF: RTC operation OFF */ -#define RTC_CRL_RTOFF (1 << 5) - -/* CNF: Configuration flag */ -#define RTC_CRL_CNF (1 << 4) - -/* RSF: Registers synchronized flag */ -#define RTC_CRL_RSF (1 << 3) - -/* OWF: Overflow flag */ -#define RTC_CRL_OWF (1 << 2) - -/* ALRF: Alarm flag */ -#define RTC_CRL_ALRF (1 << 1) - -/* SECF: Second flag */ -#define RTC_CRL_SECF (1 << 0) - -/* --- RTC_PRLH values ------------------------------------------------------*/ - -/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ - -/* TODO */ - -/* --- RTC_PRLL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_DIVH values ------------------------------------------------------*/ - -/* Bits [15:4] are reserved. */ - -/* TODO */ - -/* --- RTC_DIVL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRL values ------------------------------------------------------*/ - -/* TODO */ - -/** RTC Interrupt Flags */ -typedef enum { - /** Counter Second Flag */ - RTC_SEC, - /** Alarm Event Flag */ - RTC_ALR, - /** Counter Overflow Flag */ - RTC_OW, -} rtcflag_t; - -/* --- Function prototypes --------------------------------------------------*/ - -BEGIN_DECLS - -void rtc_awake_from_off(enum rcc_osc clock_source); -void rtc_enter_config_mode(void); -void rtc_exit_config_mode(void); -void rtc_set_alarm_time(uint32_t alarm_time); -void rtc_enable_alarm(void); -void rtc_disable_alarm(void); -void rtc_set_prescale_val(uint32_t prescale_val); -uint32_t rtc_get_counter_val(void); -uint32_t rtc_get_prescale_div_val(void); -uint32_t rtc_get_alarm_val(void); -void rtc_set_counter_val(uint32_t counter_val); -void rtc_interrupt_enable(rtcflag_t flag_val); -void rtc_interrupt_disable(rtcflag_t flag_val); -void rtc_clear_flag(rtcflag_t flag_val); -uint32_t rtc_check_flag(rtcflag_t flag_val); -void rtc_awake_from_standby(void); -void rtc_auto_awake(enum rcc_osc clock_source, uint32_t prescale_val); - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/spi.h b/libopencm3/include/libopencm3/stm32/f1/spi.h deleted file mode 100644 index 6192242..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32F1xx SPI - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f1/st_usbfs.h b/libopencm3/include/libopencm3/stm32/f1/st_usbfs.h deleted file mode 100644 index 7da73f2..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/timer.h b/libopencm3/include/libopencm3/stm32/f1/timer.h deleted file mode 100644 index 6046d79..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/timer.h +++ /dev/null @@ -1,56 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 8 March 2013 - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -/** Input Capture input polarity */ -enum tim_ic_pol { - TIM_IC_RISING, - TIM_IC_FALLING, -}; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void timer_ic_set_polarity(uint32_t timer, - enum tim_ic_id ic, - enum tim_ic_pol pol); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/usart.h b/libopencm3/include/libopencm3/stm32/f1/usart.h deleted file mode 100644 index 324d78e..0000000 --- a/libopencm3/include/libopencm3/stm32/f1/usart.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup usart_defines USART Defines - -@brief Defined Constants and Types for the STM32F1xx USART - -@ingroup STM32F1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/crc.h b/libopencm3/include/libopencm3/stm32/f2/crc.h deleted file mode 100644 index 45c16ba..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup crc_defines CRC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F2xx CRC -Generator - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/crypto.h b/libopencm3/include/libopencm3/stm32/f2/crypto.h deleted file mode 100644 index 02ea8b5..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/crypto.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup crypto_defines CRYPTO Defines - * - * @brief Defined Constants and Types for the STM32F2xx CRYP Controller - * - * @ingroup STM32F2xx_defines - * - * @version 1.0.0 - * - * @date 17 Jun 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRYPTO_H -#define LIBOPENCM3_CRYPTO_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/dac.h b/libopencm3/include/libopencm3/stm32/f2/dac.h deleted file mode 100644 index 5d148a6..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/dac.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32F2xx DAC - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/dma.h b/libopencm3/include/libopencm3/stm32/f2/dma.h deleted file mode 100644 index 8fe846d..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/dma.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dma_defines DMA Defines - -@ingroup STM32F2xx_defines - -@brief Defined Constants and Types for the STM32F2xx DMA Controller - -@version 1.0.0 - -@date 18 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h b/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h deleted file mode 100644 index 0b928b8..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @page libopencm3 STM32F2 - -@version 1.0.0 - -@date 14 September 2012 - -API documentation for ST Microelectronics STM32F2 Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F2xx STM32F2xx -Libraries for ST Microelectronics STM32F2xx series. - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32F2xx_defines STM32F2xx Defines - -@brief Defined Constants and Types for the STM32F2xx series - -@version 1.0.0 - -@date 14 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/f2/exti.h b/libopencm3/include/libopencm3/stm32/f2/exti.h deleted file mode 100644 index 5015cde..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/exti.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F2xx External Interrupts - * - * - * @ingroup STM32F2xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Piotr Esden-Tempski - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/flash.h b/libopencm3/include/libopencm3/stm32/f2/flash.h deleted file mode 100644 index ed0e91e..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/flash.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32F2xx_defines - * - * @brief Defined Constants and Types for the STM32F2xx FLASH Memory - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include -#include - -#define FLASH_SR_PGSERR (1 << 7) -#define FLASH_OPTCR_WDG_SW (1 << 5) - - -BEGIN_DECLS - -void flash_clear_pgserr_flag(void); - -END_DECLS - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/gpio.h b/libopencm3/include/libopencm3/stm32/f2/gpio.h deleted file mode 100644 index fed9353..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/gpio.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32F2xx General Purpose I/O - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/hash.h b/libopencm3/include/libopencm3/stm32/f2/hash.h deleted file mode 100644 index 9f9cea9..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/hash.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup hash_defines HASH Defines - -@ingroup STM32F2xx_defines - -@brief Defined Constants and Types for the STM32F2xx HASH Controller - -@version 1.0.0 - -@date 31 May 2013 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_HASH_H -#define LIBOPENCM3_HASH_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/i2c.h b/libopencm3/include/libopencm3/stm32/f2/i2c.h deleted file mode 100644 index a658c11..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/i2c.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32F2xx I2C - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -/**@{*/ - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/irq.json b/libopencm3/include/libopencm3/stm32/f2/irq.json deleted file mode 100644 index ec59674..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/irq.json +++ /dev/null @@ -1,88 +0,0 @@ -{ - "irqs": [ - "nvic_wwdg", - "pvd", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_stream0", - "dma1_stream1", - "dma1_stream2", - "dma1_stream3", - "dma1_stream4", - "dma1_stream5", - "dma1_stream6", - "adc", - "can1_tx", - "can1_rx0", - "can1_rx1", - "can1_sce", - "exti9_5", - "tim1_brk_tim9", - "tim1_up_tim10", - "tim1_trg_com_tim11", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_fs_wkup", - "tim8_brk_tim12", - "tim8_up_tim13", - "tim8_trg_com_tim14", - "tim8_cc", - "dma1_stream7", - "fsmc", - "sdio", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dac", - "tim7", - "dma2_stream0", - "dma2_stream1", - "dma2_stream2", - "dma2_stream3", - "dma2_stream4", - "eth", - "eth_wkup", - "can2_tx", - "can2_rx0", - "can2_rx1", - "can2_sce", - "otg_fs", - "dma2_stream5", - "dma2_stream6", - "dma2_stream7", - "usart6", - "i2c3_ev", - "i2c3_er", - "otg_hs_ep1_out", - "otg_hs_ep1_in", - "otg_hs_wkup", - "otg_hs", - "dcmi", - "cryp", - "hash_rng" - ], - "partname_humanreadable": "STM32 F2 series", - "partname_doxygen": "STM32F2", - "includeguard": "LIBOPENCM3_STM32_F2_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f2/iwdg.h b/libopencm3/include/libopencm3/stm32/f2/iwdg.h deleted file mode 100644 index 23ccb10..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/iwdg.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - -@brief Defined Constants and Types for the STM32F2xx Independent Watchdog -Timer - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/memorymap.h b/libopencm3/include/libopencm3/stm32/f2/memorymap.h deleted file mode 100644 index 4f47a32..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/memorymap.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32F20x specific peripheral definitions --------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 (0x50000000U) -#define PERIPH_BASE_AHB3 (0x60000000U) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) -/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) -/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ -#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) -#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) -/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) -/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ -#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) -/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) -/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ - -/* AHB1 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) -#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) -/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) -#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) -/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) -/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) -/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ -#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) -/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ - -/* AHB2 */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) -/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ -#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) -/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ -#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) -#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) -/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ - -/* AHB3 */ -#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) -#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/pwr.h b/libopencm3/include/libopencm3/stm32/f2/pwr.h deleted file mode 100644 index 5100eee..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/pwr.h +++ /dev/null @@ -1,59 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32F2xx PWR Control - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -/* - * This file extends the common STM32 version with definitions only - * applicable to the STM32F2 series of devices. - */ - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* Bits [31:10]: Reserved, always read as 0. */ - -/* FPDS: Flash power down in stop mode */ -#define PWR_CR_FPDS (1 << 9) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* Bits [31:10]: Reserved, always read as 0. */ - -/* BRE: Backup regulator enable */ -#define PWR_CSR_BRE (1 << 9) - -/* Bits [7:4]: Reserved, always read as 0. */ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/rcc.h b/libopencm3/include/libopencm3/stm32/f2/rcc.h deleted file mode 100644 index 923ac81..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/rcc.h +++ /dev/null @@ -1,827 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F2xx Reset and Clock - * Control - * - * @ingroup STM32F2xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_CIR MMIO32(RCC_BASE + 0x0c) -#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) -#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) -/* RCC_BASE + 0x1c Reserved */ -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) -/* RCC_BASE + 0x28 Reserved */ -/* RCC_BASE + 0x2c Reserved */ -#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) -#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) -#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) -/* RCC_BASE + 0x3c Reserved */ -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) -/* RCC_BASE + 0x48 Reserved */ -/* RCC_BASE + 0x4c Reserved */ -#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) -#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) -#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) -/* RCC_BASE + 0x5c Reserved */ -#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) -#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) -/* RCC_BASE + 0x68 Reserved */ -/* RCC_BASE + 0x6c Reserved */ -#define RCC_BDCR MMIO32(RCC_BASE + 0x70) -#define RCC_CSR MMIO32(RCC_BASE + 0x74) -/* RCC_BASE + 0x78 Reserved */ -/* RCC_BASE + 0x7c Reserved */ -#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) -#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLI2SRDY (1 << 27) -#define RCC_CR_PLLI2SON (1 << 26) -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_PLLCFGR values -------------------------------------------------- */ - -/* PLLQ: [27:24] */ -#define RCC_PLLCFGR_PLLQ_SHIFT 24 -#define RCC_PLLCFGR_PLLSRC (1 << 22) -/* PLLP: [17:16] */ -#define RCC_PLLCFGR_PLLP_SHIFT 16 -/* PLLN: [14:6] */ -#define RCC_PLLCFGR_PLLN_SHIFT 6 -/* PLLM: [5:0] */ -#define RCC_PLLCFGR_PLLM_SHIFT 0 - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCO2: Microcontroller clock output 2 */ -#define RCC_CFGR_MCO2_SHIFT 30 -#define RCC_CFGR_MCO2_SYSCLK 0x0 -#define RCC_CFGR_MCO2_PLLI2S 0x1 -#define RCC_CFGR_MCO2_HSE 0x2 -#define RCC_CFGR_MCO2_PLL 0x3 - -/* MCO1/2PRE: MCO Prescalers */ -#define RCC_CFGR_MCO2PRE_SHIFT 27 -#define RCC_CFGR_MCO1PRE_SHIFT 24 -#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 -#define RCC_CFGR_MCOPRE_DIV_2 0x4 -#define RCC_CFGR_MCOPRE_DIV_3 0x5 -#define RCC_CFGR_MCOPRE_DIV_4 0x6 -#define RCC_CFGR_MCOPRE_DIV_5 0x7 - -/* I2SSRC: I2S clock selection */ -#define RCC_CFGR_I2SSRC (1 << 23) - -/* MCO1: Microcontroller clock output 1 */ -#define RCC_CFGR_MCO1_SHIFT 21 -#define RCC_CFGR_MCO1_MASK 0x3 -#define RCC_CFGR_MCO1_HSI 0x0 -#define RCC_CFGR_MCO1_LSE 0x1 -#define RCC_CFGR_MCO1_HSE 0x2 -#define RCC_CFGR_MCO1_PLL 0x3 -#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT -#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK - -/* RTCPRE: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_SHIFT 16 -#define RCC_CFGR_RTCPRE_MASK 0x1f - -/* PPRE1/2: APB high-speed prescalers */ -#define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 - -/* HPRE: AHB high-speed prescaler */ -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLL 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLLI2SRDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLLI2SRDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLLI2SRDYF (1 << 5) -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values -@{*/ -#define RCC_AHB1RSTR_OTGHSRST (1 << 29) -#define RCC_AHB1RSTR_ETHMACRST (1 << 25) -#define RCC_AHB1RSTR_DMA2RST (1 << 22) -#define RCC_AHB1RSTR_DMA1RST (1 << 21) -#define RCC_AHB1RSTR_CRCRST (1 << 12) -#define RCC_AHB1RSTR_GPIOIRST (1 << 8) -#define RCC_AHB1RSTR_GPIOHRST (1 << 7) -#define RCC_AHB1RSTR_GPIOGRST (1 << 6) -#define RCC_AHB1RSTR_GPIOFRST (1 << 5) -#define RCC_AHB1RSTR_GPIOERST (1 << 4) -#define RCC_AHB1RSTR_GPIODRST (1 << 3) -#define RCC_AHB1RSTR_GPIOCRST (1 << 2) -#define RCC_AHB1RSTR_GPIOBRST (1 << 1) -#define RCC_AHB1RSTR_GPIOARST (1 << 0) -/**@}*/ - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxRST with zzz_GPIOxRST - * @{ - */ -#define RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST -#define RCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRST -#define RCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRST -#define RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRST -#define RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERST -#define RCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRST -#define RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRST -#define RCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRST -#define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST -/**@}*/ - -/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values -@{*/ -#define RCC_AHB2RSTR_OTGFSRST (1 << 7) -#define RCC_AHB2RSTR_RNGRST (1 << 6) -#define RCC_AHB2RSTR_HASHRST (1 << 5) -#define RCC_AHB2RSTR_CRYPRST (1 << 4) -#define RCC_AHB2RSTR_DCMIRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values -@{*/ -#define RCC_AHB3RSTR_FSMCRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_CAN2RST (1 << 26) -#define RCC_APB1RSTR_CAN1RST (1 << 25) -#define RCC_APB1RSTR_I2C3RST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM14RST (1 << 8) -#define RCC_APB1RSTR_TIM13RST (1 << 7) -#define RCC_APB1RSTR_TIM12RST (1 << 6) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_TIM11RST (1 << 18) -#define RCC_APB2RSTR_TIM10RST (1 << 17) -#define RCC_APB2RSTR_TIM9RST (1 << 16) -#define RCC_APB2RSTR_SYSCFGRST (1 << 14) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_SDIORST (1 << 11) -#define RCC_APB2RSTR_ADCRST (1 << 8) -#define RCC_APB2RSTR_USART6RST (1 << 5) -#define RCC_APB2RSTR_USART1RST (1 << 4) -#define RCC_APB2RSTR_TIM8RST (1 << 1) -#define RCC_APB2RSTR_TIM1RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) -@{*/ -/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values -@{*/ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) -#define RCC_AHB1ENR_OTGHSEN (1 << 29) -#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) -#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) -#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) -#define RCC_AHB1ENR_ETHMACEN (1 << 25) -#define RCC_AHB1ENR_DMA2EN (1 << 22) -#define RCC_AHB1ENR_DMA1EN (1 << 21) -#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) -#define RCC_AHB1ENR_CRCEN (1 << 12) -#define RCC_AHB1ENR_GPIOIEN (1 << 8) -#define RCC_AHB1ENR_GPIOHEN (1 << 7) -#define RCC_AHB1ENR_GPIOGEN (1 << 6) -#define RCC_AHB1ENR_GPIOFEN (1 << 5) -#define RCC_AHB1ENR_GPIOEEN (1 << 4) -#define RCC_AHB1ENR_GPIODEN (1 << 3) -#define RCC_AHB1ENR_GPIOCEN (1 << 2) -#define RCC_AHB1ENR_GPIOBEN (1 << 1) -#define RCC_AHB1ENR_GPIOAEN (1 << 0) -/**@}*/ - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxEN with zzz_GPIOxEN - * @{ - */ -#define RCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIEN -#define RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHEN -#define RCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGEN -#define RCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFEN -#define RCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEEN -#define RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODEN -#define RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCEN -#define RCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBEN -#define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN -/**@}*/ - -/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values -@{*/ -#define RCC_AHB2ENR_OTGFSEN (1 << 7) -#define RCC_AHB2ENR_RNGEN (1 << 6) -#define RCC_AHB2ENR_HASHEN (1 << 5) -#define RCC_AHB2ENR_CRYPEN (1 << 4) -#define RCC_AHB2ENR_DCMIEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values -@{*/ -#define RCC_AHB3ENR_FSMCEN (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_CAN2EN (1 << 26) -#define RCC_APB1ENR_CAN1EN (1 << 25) -#define RCC_APB1ENR_I2C3EN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM14EN (1 << 8) -#define RCC_APB1ENR_TIM13EN (1 << 7) -#define RCC_APB1ENR_TIM12EN (1 << 6) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@{*/ -#define RCC_APB2ENR_TIM11EN (1 << 18) -#define RCC_APB2ENR_TIM10EN (1 << 17) -#define RCC_APB2ENR_TIM9EN (1 << 16) -#define RCC_APB2ENR_SYSCFGEN (1 << 14) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_SDIOEN (1 << 11) -#define RCC_APB2ENR_ADC3EN (1 << 10) -#define RCC_APB2ENR_ADC2EN (1 << 9) -#define RCC_APB2ENR_ADC1EN (1 << 8) -#define RCC_APB2ENR_USART6EN (1 << 5) -#define RCC_APB2ENR_USART1EN (1 << 4) -#define RCC_APB2ENR_TIM8EN (1 << 1) -#define RCC_APB2ENR_TIM1EN (1 << 0) -/**@}*/ - -/* --- RCC_AHB1LPENR values ------------------------------------------------- */ - -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) -#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) -#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) -#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) -#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) -#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) -#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) -#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) -#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) -#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) -#define RCC_AHB1LPENR_CRCLPEN (1 << 12) -#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) -#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) -#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) -#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) -#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) -#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) -#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) -#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) -#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxLPEN with zzz_GPIOxLPEN - * @{ - */ -#define RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPEN -#define RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPEN -#define RCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN -#define RCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN -#define RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPEN -#define RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPEN -#define RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPEN -#define RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPEN -#define RCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPEN -/**@}*/ - -/* --- RCC_AHB2LPENR values ------------------------------------------------- */ - -#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) -#define RCC_AHB2LPENR_RNGLPEN (1 << 6) -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) -#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) -#define RCC_AHB2LPENR_DCMILPEN (1 << 0) - -/* --- RCC_AHB3LPENR values ------------------------------------------------- */ - -#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) - -/* --- RCC_APB1LPENR values ------------------------------------------------- */ - -#define RCC_APB1LPENR_DACLPEN (1 << 29) -#define RCC_APB1LPENR_PWRLPEN (1 << 28) -#define RCC_APB1LPENR_CAN2LPEN (1 << 26) -#define RCC_APB1LPENR_CAN1LPEN (1 << 25) -#define RCC_APB1LPENR_I2C3LPEN (1 << 23) -#define RCC_APB1LPENR_I2C2LPEN (1 << 22) -#define RCC_APB1LPENR_I2C1LPEN (1 << 21) -#define RCC_APB1LPENR_UART5LPEN (1 << 20) -#define RCC_APB1LPENR_UART4LPEN (1 << 19) -#define RCC_APB1LPENR_USART3LPEN (1 << 18) -#define RCC_APB1LPENR_USART2LPEN (1 << 17) -#define RCC_APB1LPENR_SPI3LPEN (1 << 15) -#define RCC_APB1LPENR_SPI2LPEN (1 << 14) -#define RCC_APB1LPENR_WWDGLPEN (1 << 11) -#define RCC_APB1LPENR_TIM14LPEN (1 << 8) -#define RCC_APB1LPENR_TIM13LPEN (1 << 7) -#define RCC_APB1LPENR_TIM12LPEN (1 << 6) -#define RCC_APB1LPENR_TIM7LPEN (1 << 5) -#define RCC_APB1LPENR_TIM6LPEN (1 << 4) -#define RCC_APB1LPENR_TIM5LPEN (1 << 3) -#define RCC_APB1LPENR_TIM4LPEN (1 << 2) -#define RCC_APB1LPENR_TIM3LPEN (1 << 1) -#define RCC_APB1LPENR_TIM2LPEN (1 << 0) - -/* --- RCC_APB2LPENR values ------------------------------------------------- */ - -#define RCC_APB2LPENR_TIM11LPEN (1 << 18) -#define RCC_APB2LPENR_TIM10LPEN (1 << 17) -#define RCC_APB2LPENR_TIM9LPEN (1 << 16) -#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) -#define RCC_APB2LPENR_SDIOLPEN (1 << 11) -#define RCC_APB2LPENR_ADC3LPEN (1 << 10) -#define RCC_APB2LPENR_ADC2LPEN (1 << 9) -#define RCC_APB2LPENR_ADC1LPEN (1 << 8) -#define RCC_APB2LPENR_USART6LPEN (1 << 5) -#define RCC_APB2LPENR_USART1LPEN (1 << 4) -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_BORRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_BORRSTF) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- RCC_SSCGR values ---------------------------------------------------- */ - -/* PLL spread spectrum clock generation documented in Datasheet. */ - -#define RCC_SSCGR_SSCGEN (1 << 31) -#define RCC_SSCGR_SPREADSEL (1 << 30) -/* RCC_SSCGR[27:16]: INCSTEP */ -#define RCC_SSCGR_INCSTEP_SHIFT 16 -/* RCC_SSCGR[15:0]: MODPER */ -#define RCC_SSCGR_MODPER_SHIFT 15 - -/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ - -/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ -#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 -/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ -#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_clock_3v3 { - RCC_CLOCK_3V3_120MHZ, - RCC_CLOCK_3V3_END -}; - -struct rcc_clock_scale { - uint8_t pllm; - uint16_t plln; - uint8_t pllp; - uint8_t pllq; - uint32_t flash_config; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - uint32_t apb1_frequency; - uint32_t apb2_frequency; -}; - -extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; - -enum rcc_osc { - RCC_PLL, - RCC_HSE, - RCC_HSI, - RCC_LSE, - RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB1 peripherals */ - RCC_GPIOA = _REG_BIT(0x30, 0), - RCC_GPIOB = _REG_BIT(0x30, 1), - RCC_GPIOC = _REG_BIT(0x30, 2), - RCC_GPIOD = _REG_BIT(0x30, 3), - RCC_GPIOE = _REG_BIT(0x30, 4), - RCC_GPIOF = _REG_BIT(0x30, 5), - RCC_GPIOG = _REG_BIT(0x30, 6), - RCC_GPIOH = _REG_BIT(0x30, 7), - RCC_GPIOI = _REG_BIT(0x30, 8), - RCC_CRC = _REG_BIT(0x30, 12), - RCC_BKPSRAM = _REG_BIT(0x30, 18), - RCC_DMA1 = _REG_BIT(0x30, 21), - RCC_DMA2 = _REG_BIT(0x30, 22), - RCC_ETHMAC = _REG_BIT(0x30, 25), - RCC_ETHMACTX = _REG_BIT(0x30, 26), - RCC_ETHMACRX = _REG_BIT(0x30, 27), - RCC_ETHMACPTP = _REG_BIT(0x30, 28), - RCC_OTGHS = _REG_BIT(0x30, 29), - RCC_OTGHSULPI = _REG_BIT(0x30, 30), - - /* AHB2 peripherals */ - RCC_DCMI = _REG_BIT(0x34, 0), - RCC_CRYP = _REG_BIT(0x34, 4), - RCC_HASH = _REG_BIT(0x34, 5), - RCC_RNG = _REG_BIT(0x34, 6), - RCC_OTGFS = _REG_BIT(0x34, 7), - - /* AHB3 peripherals */ - RCC_FSMC = _REG_BIT(0x38, 0), - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x40, 0), - RCC_TIM3 = _REG_BIT(0x40, 1), - RCC_TIM4 = _REG_BIT(0x40, 2), - RCC_TIM5 = _REG_BIT(0x40, 3), - RCC_TIM6 = _REG_BIT(0x40, 4), - RCC_TIM7 = _REG_BIT(0x40, 5), - RCC_TIM12 = _REG_BIT(0x40, 6), - RCC_TIM13 = _REG_BIT(0x40, 7), - RCC_TIM14 = _REG_BIT(0x40, 8), - RCC_WWDG = _REG_BIT(0x40, 11), - RCC_SPI2 = _REG_BIT(0x40, 14), - RCC_SPI3 = _REG_BIT(0x40, 15), - RCC_USART2 = _REG_BIT(0x40, 17), - RCC_USART3 = _REG_BIT(0x40, 18), - RCC_UART4 = _REG_BIT(0x40, 19), - RCC_UART5 = _REG_BIT(0x40, 20), - RCC_I2C1 = _REG_BIT(0x40, 21), - RCC_I2C2 = _REG_BIT(0x40, 22), - RCC_I2C3 = _REG_BIT(0x40, 23), - RCC_CAN1 = _REG_BIT(0x40, 25), - RCC_CAN2 = _REG_BIT(0x40, 26), - RCC_PWR = _REG_BIT(0x40, 28), - RCC_DAC = _REG_BIT(0x40, 29), - - /* APB2 peripherals */ - RCC_TIM1 = _REG_BIT(0x44, 0), - RCC_TIM8 = _REG_BIT(0x44, 1), - RCC_USART1 = _REG_BIT(0x44, 4), - RCC_USART6 = _REG_BIT(0x44, 5), - RCC_ADC1 = _REG_BIT(0x44, 8), - RCC_ADC2 = _REG_BIT(0x44, 9), - RCC_ADC3 = _REG_BIT(0x44, 10), - RCC_SDIO = _REG_BIT(0x44, 11), - RCC_SPI1 = _REG_BIT(0x44, 12), - RCC_SYSCFG = _REG_BIT(0x44, 14), - RCC_TIM9 = _REG_BIT(0x44, 16), - RCC_TIM10 = _REG_BIT(0x44, 17), - RCC_TIM11 = _REG_BIT(0x44, 18), - - /* Extended peripherals */ - RCC_RTC = _REG_BIT(0x70, 15),/* BDCR[15] */ - - /* AHB1 peripherals */ - SCC_GPIOA = _REG_BIT(0x50, 0), - SCC_GPIOB = _REG_BIT(0x50, 1), - SCC_GPIOC = _REG_BIT(0x50, 2), - SCC_GPIOD = _REG_BIT(0x50, 3), - SCC_GPIOE = _REG_BIT(0x50, 4), - SCC_GPIOF = _REG_BIT(0x50, 5), - SCC_GPIOG = _REG_BIT(0x50, 6), - SCC_GPIOH = _REG_BIT(0x50, 7), - SCC_GPIOI = _REG_BIT(0x50, 8), - SCC_CRC = _REG_BIT(0x50, 12), - SCC_FLTIF = _REG_BIT(0x50, 15), - SCC_SRAM1 = _REG_BIT(0x50, 16), - SCC_SRAM2 = _REG_BIT(0x50, 17), - SCC_BKPSRAM = _REG_BIT(0x50, 18), - SCC_DMA1 = _REG_BIT(0x50, 21), - SCC_DMA2 = _REG_BIT(0x50, 22), - SCC_ETHMAC = _REG_BIT(0x50, 25), - SCC_ETHMACTX = _REG_BIT(0x50, 26), - SCC_ETHMACRX = _REG_BIT(0x50, 27), - SCC_ETHMACPTP = _REG_BIT(0x50, 28), - SCC_OTGHS = _REG_BIT(0x50, 29), - SCC_OTGHSULPI = _REG_BIT(0x50, 30), - - /* AHB2 peripherals */ - SCC_DCMI = _REG_BIT(0x54, 0), - SCC_CRYP = _REG_BIT(0x54, 4), - SCC_HASH = _REG_BIT(0x54, 5), - SCC_RNG = _REG_BIT(0x54, 6), - SCC_OTGFS = _REG_BIT(0x54, 7), - - /* AHB3 peripherals */ - SCC_FSMC = _REG_BIT(0x58, 0), - - /* APB1 peripherals */ - SCC_TIM2 = _REG_BIT(0x60, 0), - SCC_TIM3 = _REG_BIT(0x60, 1), - SCC_TIM4 = _REG_BIT(0x60, 2), - SCC_TIM5 = _REG_BIT(0x60, 3), - SCC_TIM6 = _REG_BIT(0x60, 4), - SCC_TIM7 = _REG_BIT(0x60, 5), - SCC_TIM12 = _REG_BIT(0x60, 6), - SCC_TIM13 = _REG_BIT(0x60, 7), - SCC_TIM14 = _REG_BIT(0x60, 8), - SCC_WWDG = _REG_BIT(0x60, 11), - SCC_SPI2 = _REG_BIT(0x60, 14), - SCC_SPI3 = _REG_BIT(0x60, 15), - SCC_USART2 = _REG_BIT(0x60, 17), - SCC_USART3 = _REG_BIT(0x60, 18), - SCC_UART4 = _REG_BIT(0x60, 19), - SCC_UART5 = _REG_BIT(0x60, 20), - SCC_I2C1 = _REG_BIT(0x60, 21), - SCC_I2C2 = _REG_BIT(0x60, 22), - SCC_I2C3 = _REG_BIT(0x60, 23), - SCC_CAN1 = _REG_BIT(0x60, 25), - SCC_CAN2 = _REG_BIT(0x60, 26), - SCC_PWR = _REG_BIT(0x60, 28), - SCC_DAC = _REG_BIT(0x60, 29), - - /* APB2 peripherals */ - SCC_TIM1 = _REG_BIT(0x64, 0), - SCC_TIM8 = _REG_BIT(0x64, 1), - SCC_USART1 = _REG_BIT(0x64, 4), - SCC_USART6 = _REG_BIT(0x64, 5), - SCC_ADC1 = _REG_BIT(0x64, 8), - SCC_ADC2 = _REG_BIT(0x64, 9), - SCC_ADC3 = _REG_BIT(0x64, 10), - SCC_SDIO = _REG_BIT(0x64, 11), - SCC_SPI1 = _REG_BIT(0x64, 12), - SCC_SYSCFG = _REG_BIT(0x64, 14), - SCC_TIM9 = _REG_BIT(0x64, 16), - SCC_TIM10 = _REG_BIT(0x64, 17), - SCC_TIM11 = _REG_BIT(0x64, 18), -}; - -enum rcc_periph_rst { - /* AHB1 peripherals */ - RST_GPIOA = _REG_BIT(0x10, 0), - RST_GPIOB = _REG_BIT(0x10, 1), - RST_GPIOC = _REG_BIT(0x10, 2), - RST_GPIOD = _REG_BIT(0x10, 3), - RST_GPIOE = _REG_BIT(0x10, 4), - RST_GPIOF = _REG_BIT(0x10, 5), - RST_GPIOG = _REG_BIT(0x10, 6), - RST_GPIOH = _REG_BIT(0x10, 7), - RST_GPIOI = _REG_BIT(0x10, 8), - RST_CRC = _REG_BIT(0x10, 12), - RST_DMA1 = _REG_BIT(0x10, 21), - RST_DMA2 = _REG_BIT(0x10, 22), - RST_ETHMAC = _REG_BIT(0x10, 25), - RST_OTGHS = _REG_BIT(0x10, 29), - - /* AHB2 peripherals */ - RST_DCMI = _REG_BIT(0x14, 0), - RST_CRYP = _REG_BIT(0x14, 4), - RST_HASH = _REG_BIT(0x14, 5), - RST_RNG = _REG_BIT(0x14, 6), - RST_OTGFS = _REG_BIT(0x14, 7), - - /* AHB3 peripherals */ - RST_FSMC = _REG_BIT(0x18, 0), - - /* APB1 peripherals */ - RST_TIM2 = _REG_BIT(0x20, 0), - RST_TIM3 = _REG_BIT(0x20, 1), - RST_TIM4 = _REG_BIT(0x20, 2), - RST_TIM5 = _REG_BIT(0x20, 3), - RST_TIM6 = _REG_BIT(0x20, 4), - RST_TIM7 = _REG_BIT(0x20, 5), - RST_TIM12 = _REG_BIT(0x20, 6), - RST_TIM13 = _REG_BIT(0x20, 7), - RST_TIM14 = _REG_BIT(0x20, 8), - RST_WWDG = _REG_BIT(0x20, 11), - RST_SPI2 = _REG_BIT(0x20, 14), - RST_SPI3 = _REG_BIT(0x20, 15), - RST_USART2 = _REG_BIT(0x20, 17), - RST_USART3 = _REG_BIT(0x20, 18), - RST_UART4 = _REG_BIT(0x20, 19), - RST_UART5 = _REG_BIT(0x20, 20), - RST_I2C1 = _REG_BIT(0x20, 21), - RST_I2C2 = _REG_BIT(0x20, 22), - RST_I2C3 = _REG_BIT(0x20, 23), - RST_CAN1 = _REG_BIT(0x20, 25), - RST_CAN2 = _REG_BIT(0x20, 26), - RST_PWR = _REG_BIT(0x20, 28), - RST_DAC = _REG_BIT(0x20, 29), - - /* APB2 peripherals */ - RST_TIM1 = _REG_BIT(0x24, 0), - RST_TIM8 = _REG_BIT(0x24, 1), - RST_USART1 = _REG_BIT(0x24, 4), - RST_USART6 = _REG_BIT(0x24, 5), - RST_ADC = _REG_BIT(0x24, 8), - RST_SDIO = _REG_BIT(0x24, 11), - RST_SPI1 = _REG_BIT(0x24, 12), - RST_SYSCFG = _REG_BIT(0x24, 14), - RST_TIM9 = _REG_BIT(0x24, 16), - RST_TIM10 = _REG_BIT(0x24, 17), - RST_TIM11 = _REG_BIT(0x24, 18), -}; - -#undef _REG_BIT - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_rtcpre(uint32_t rtcpre); -void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq); -void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq); -uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); -void rcc_backupdomain_reset(void); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f2/rng.h b/libopencm3/include/libopencm3/stm32/f2/rng.h deleted file mode 100644 index 09d014d..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/rng.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/rtc.h b/libopencm3/include/libopencm3/stm32/f2/rtc.h deleted file mode 100644 index bae06ac..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - -@brief Defined Constants and Types for the STM32F2xx RTC - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/spi.h b/libopencm3/include/libopencm3/stm32/f2/spi.h deleted file mode 100644 index cc5792d..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32F2xx SPI - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f2/syscfg.h b/libopencm3/include/libopencm3/stm32/f2/syscfg.h deleted file mode 100644 index 579e6d6..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/syscfg.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32F2xx_defines - * - * @brief Defined Constants and Types for the STM32F2xx Sysconfig - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/f2/timer.h b/libopencm3/include/libopencm3/stm32/f2/timer.h deleted file mode 100644 index 7dc6d32..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/timer.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32F2xx Timers - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 8 March 2013 - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/usart.h b/libopencm3/include/libopencm3/stm32/f2/usart.h deleted file mode 100644 index 8d4485b..0000000 --- a/libopencm3/include/libopencm3/stm32/f2/usart.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup usart_defines USART Defines - -@brief Defined Constants and Types for the STM32F2xx USART - -@ingroup STM32F2xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/adc.h b/libopencm3/include/libopencm3/stm32/f3/adc.h deleted file mode 100644 index 5465cf7..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/adc.h +++ /dev/null @@ -1,595 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the STM32F37x Analog to Digital - * converter - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 ARCOS-Lab UCR - * Copyright (C) 2013 Fernando Cortes - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/**@{*/ - -/** @defgroup adc_reg_base ADC register base addresses -@ingroup STM32xx_adc_defines -@{*/ -#define ADC1 ADC1_BASE -#define ADC2 ADC2_BASE -#define ADC3 ADC3_BASE -#define ADC4 ADC4_BASE -/**@}*/ - -/* Master and slave ADCs common registers (ADC12 or ADC34) */ - - -/*----------- ADC registers -------------------------------------- */ - -#define ADC1_ISR ADC_ISR(ADC1_BASE) -#define ADC2_ISR ADC_ISR(ADC2_BASE) -#define ADC3_ISR ADC_ISR(ADC3_BASE) -#define ADC4_ISR ADC_ISR(ADC4_BASE) - -#define ADC1_IER ADC_IER(ADC1_BASE) -#define ADC2_IER ADC_IER(ADC2_BASE) -#define ADC3_IER ADC_IER(ADC3_BASE) -#define ADC4_IER ADC_IER(ADC4_BASE) - -#define ADC1_CR ADC_CR(ADC1_BASE) -#define ADC2_CR ADC_CR(ADC2_BASE) -#define ADC3_CR ADC_CR(ADC3_BASE) -#define ADC4_CR ADC_CR(ADC4_BASE) - -#define ADC1_CFGR1 ADC_CFGR1(ADC1_BASE) -#define ADC2_CFGR1 ADC_CFGR1(ADC2_BASE) -#define ADC3_CFGR1 ADC_CFGR1(ADC3_BASE) -#define ADC4_CFGR1 ADC_CFGR1(ADC4_BASE) -/* Compatibility with original ref man names */ -#define ADC_CFGR(adc) ADC_CFGR1(adc) -#define ADC1_CFGR ADC_CFGR1(ADC1_BASE) -#define ADC2_CFGR ADC_CFGR1(ADC2_BASE) -#define ADC3_CFGR ADC_CFGR1(ADC3_BASE) -#define ADC4_CFGR ADC_CFGR1(ADC4_BASE) - -#define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) -#define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) -#define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) -#define ADC4_SMPR1 ADC_SMPR1(ADC4_BASE) - -#define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) -#define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) -#define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) -#define ADC4_SMPR2 ADC_SMPR2(ADC4_BASE) - -#define ADC1_TR1 ADC_TR1(ADC1_BASE) -#define ADC2_TR1 ADC_TR1(ADC2_BASE) -#define ADC3_TR1 ADC_TR1(ADC3_BASE) -#define ADC4_TR1 ADC_TR1(ADC4_BASE) - -#define ADC1_TR2 ADC_TR2(ADC1_BASE) -#define ADC2_TR2 ADC_TR2(ADC2_BASE) -#define ADC3_TR2 ADC_TR2(ADC3_BASE) -#define ADC4_TR2 ADC_TR2(ADC4_BASE) - -#define ADC1_TR3 ADC_TR3(ADC1_BASE) -#define ADC2_TR3 ADC_TR3(ADC2_BASE) -#define ADC3_TR3 ADC_TR3(ADC3_BASE) -#define ADC4_TR3 ADC_TR3(ADC4_BASE) - -#define ADC1_SQR1 ADC_SQR1(ADC1_BASE) -#define ADC2_SQR1 ADC_SQR1(ADC2_BASE) -#define ADC3_SQR1 ADC_SQR1(ADC3_BASE) -#define ADC4_SQR1 ADC_SQR1(ADC4_BASE) - -#define ADC1_SQR2 ADC_SQR2(ADC1_BASE) -#define ADC2_SQR2 ADC_SQR2(ADC2_BASE) -#define ADC3_SQR2 ADC_SQR2(ADC3_BASE) -#define ADC4_SQR2 ADC_SQR2(ADC4_BASE) - -#define ADC1_SQR3 ADC_SQR3(ADC1_BASE) -#define ADC2_SQR3 ADC_SQR3(ADC2_BASE) -#define ADC3_SQR3 ADC_SQR3(ADC3_BASE) -#define ADC4_SQR3 ADC_SQR3(ADC4_BASE) - -#define ADC1_SQR4 ADC_SQR4(ADC1_BASE) -#define ADC2_SQR4 ADC_SQR4(ADC2_BASE) -#define ADC3_SQR4 ADC_SQR4(ADC3_BASE) -#define ADC4_SQR4 ADC_SQR4(ADC4_BASE) - -#define ADC1_DR ADC_DR(ADC1_BASE) -#define ADC2_DR ADC_DR(ADC2_BASE) -#define ADC3_DR ADC_DR(ADC3_BASE) -#define ADC4_DR ADC_DR(ADC4_BASE) - -#define ADC1_JSQR ADC_JSQR(ADC1_BASE) -#define ADC2_JSQR ADC_JSQR(ADC2_BASE) -#define ADC3_JSQR ADC_JSQR(ADC3_BASE) -#define ADC4_JSQR ADC_JSQR(ADC4_BASE) - -#define ADC1_OFR1 ADC_OFR1(ADC1_BASE) -#define ADC2_OFR1 ADC_OFR1(ADC2_BASE) -#define ADC3_OFR1 ADC_OFR1(ADC3_BASE) -#define ADC4_OFR1 ADC_OFR1(ADC4_BASE) - -#define ADC1_OFR2 ADC_OFR2(ADC1_BASE) -#define ADC2_OFR2 ADC_OFR2(ADC2_BASE) -#define ADC3_OFR2 ADC_OFR2(ADC3_BASE) -#define ADC4_OFR2 ADC_OFR2(ADC4_BASE) - -#define ADC1_OFR3 ADC_OFR3(ADC1_BASE) -#define ADC2_OFR3 ADC_OFR3(ADC2_BASE) -#define ADC3_OFR3 ADC_OFR3(ADC3_BASE) -#define ADC4_OFR3 ADC_OFR3(ADC4_BASE) - -#define ADC1_OFR4 ADC_OFR4(ADC1_BASE) -#define ADC2_OFR4 ADC_OFR4(ADC2_BASE) -#define ADC3_OFR4 ADC_OFR4(ADC3_BASE) -#define ADC4_OFR4 ADC_OFR4(ADC4_BASE) - -#define ADC1_JDR1 ADC_JDR1(ADC1_BASE) -#define ADC2_JDR1 ADC_JDR1(ADC2_BASE) -#define ADC3_JDR1 ADC_JDR1(ADC3_BASE) -#define ADC4_JDR1 ADC_JDR1(ADC4_BASE) - -#define ADC1_JDR2 ADC_JDR2(ADC1_BASE) -#define ADC2_JDR2 ADC_JDR2(ADC2_BASE) -#define ADC3_JDR2 ADC_JDR2(ADC3_BASE) -#define ADC4_JDR2 ADC_JDR2(ADC4_BASE) - -#define ADC1_JDR3 ADC_JDR3(ADC1_BASE) -#define ADC2_JDR3 ADC_JDR3(ADC2_BASE) -#define ADC3_JDR3 ADC_JDR3(ADC3_BASE) -#define ADC4_JDR3 ADC_JDR3(ADC4_BASE) - -#define ADC1_JDR4 ADC_JDR4(ADC1_BASE) -#define ADC2_JDR4 ADC_JDR4(ADC2_BASE) -#define ADC3_JDR4 ADC_JDR4(ADC3_BASE) -#define ADC4_JDR4 ADC_JDR4(ADC4_BASE) - -#define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) -#define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) -#define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) -#define ADC4_AWD2CR ADC_AWD2CR(ADC4_BASE) - -#define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) -#define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) -#define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) -#define ADC4_AWD3CR ADC_AWD3CR(ADC4_BASE) - -#define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) -#define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) -#define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) -#define ADC4_DIFSEL ADC_DIFSEL(ADC4_BASE) - -#define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) -#define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) -#define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) -#define ADC4_CALFACT ADC_CALFACT(ADC4_BASE) - -#define ADC12_CSR ADC_CSR(ADC1) -#define ADC12_CCR ADC_CCR(ADC1) -#define ADC12_CDR ADC_CDR(ADC1) -#define ADC34_CSR ADC_CSR(ADC3) -#define ADC34_CCR ADC_CCR(ADC3) -#define ADC34_CDR ADC_CDR(ADC3) - - -/*------- ADC_CR values ---------*/ - -/** ADVREGEN: ADC voltage regulator enable */ -#define ADC_CR_ADVREGEN_ENABLE (0x1 << 28) -#define ADC_CR_ADVREGEN_DISABLE (0x2 << 28) -#define ADC_CR_ADVREGEN_MASK (0x3 << 28) - -/****************************************************************************/ -/* ADC_SMPRx ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample ADC Sample Time Selection values -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_1DOT5CYC 0x0 -#define ADC_SMPR_SMP_2DOT5CYC 0x1 -#define ADC_SMPR_SMP_4DOT5CYC 0x2 -#define ADC_SMPR_SMP_7DOT5CYC 0x3 -#define ADC_SMPR_SMP_19DOT5CYC 0x4 -#define ADC_SMPR_SMP_61DOT5CYC 0x5 -#define ADC_SMPR_SMP_181DOT5CYC 0x6 -#define ADC_SMPR_SMP_601DOT5CYC 0x7 -/**@}*/ - -/* SMPx[2:0]: Channel x sampling time selection */ - -/*------- ADC_T2 values ---------*/ - -/* Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold */ - -/* Bit 7:0 LT2[7:0]: Analog watchdog 2 lower threshold */ - - -/*------- ADC_T3 values ---------*/ - -/* Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold */ - -/* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */ - - -/*------- ADC_DR values ---------*/ - -/* Bits 15:0 RDATA[15:0]: Regular Data converted */ - - -/*------- ADC_JSQR values ---------*/ - -#define ADC_JSQR_JL_LSB 0 -#define ADC_JSQR_JL_SHIFT 0 -#define ADC_JSQR_JSQ4_LSB 26 -#define ADC_JSQR_JSQ3_LSB 20 -#define ADC_JSQR_JSQ2_LSB 14 -#define ADC_JSQR_JSQ1_LSB 8 - -#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8)) -#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) - -/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */ - -/* Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence */ - -/* Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence */ - -/* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ - -/* - * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected - * channels - */ -#define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) -#define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) -#define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) -#define ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 6) - -#define ADC_JSQR_JEXTEN_MASK (0x3 << 6) - -/* JEXTSEL[3:0]: External Trigger Selection for injected group */ -#define ADC_JSQR_JEXTSEL_EVENT_0 (0x0 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_1 (0x1 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_2 (0x2 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_3 (0x3 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_4 (0x4 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_5 (0x5 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_6 (0x6 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_7 (0x7 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_8 (0x8 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_9 (0x9 << 2) -#define ADC_JSQR_JEXTSEL_EVENT_10 (0xA << 2) -#define ADC_JSQR_JEXTSEL_EVENT_11 (0xB << 2) -#define ADC_JSQR_JEXTSEL_EVENT_12 (0xC << 2) -#define ADC_JSQR_JEXTSEL_EVENT_13 (0xD << 2) -#define ADC_JSQR_JEXTSEL_EVENT_14 (0xE << 2) -#define ADC_JSQR_JEXTSEL_EVENT_15 (0xF << 2) - -#define ADC_JSQR_JEXTSEL_MASK (0xF << 2) - -/* JL[1:0]: Injected channel sequence length */ -#define ADC_JSQR_JL_1_CONVERSION (0x0 << 0) -#define ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0) -#define ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0) -#define ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0) - - -/*------- ADC_OFR1 values ---------*/ - -/* OFFSET1_EN: Offset 1 Enable */ -#define ADC_OFR1_OFFSET1_EN (1 << 31) - -/* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ - -/* - * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits - * OFFSET1_CH[4:0] - */ - - -/*------- ADC_OFR2 values ---------*/ - -/* OFFSET2_EN: Offset 2 Enable */ -#define ADC_OFR2_OFFSET2_EN (1 << 31) - -/* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ - -/* - * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits - * OFFSET2_CH[4:0] - */ - - -/*------- ADC_OFR3 values ---------*/ - -/* OFFSET3_EN: Offset 3 Enable */ -#define ADC_OFR3_OFFSET3_EN (1 << 31) - -/* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ - -/* - * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits - * OFFSET3_CH[4:0] - */ - - -/*------- ADC_OFR4 values ---------*/ - -/* OFFSET4_EN: Offset 4 Enable */ -#define ADC_OFR4_OFFSET4_EN (1 << 31) - -/* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ - -/* - * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits - * OFFSET4_CH[4:0] - */ - - -/*------- ADC_JDRy, y= 1..4 values -------*/ - -/* Bits 15:0 JDATA[15:0]: Injected data */ - - -/*------- ADC_AWD2CR values ---------*/ - -/* Bits 18:1 AWD2CH[18:1]: Analog watchdog 2 channel selection */ - - -/*------- ADC_AWD3CR values ---------*/ - -/* Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection */ - - -/*------- ADC_DIFSEL values ---------*/ - -/* DIFSEL[18:16]: Differential mode for channels 18 to 16. */ - -/* Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 */ - - -/*------- ADC_CALFACT values ---------*/ - -/* Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode */ - -/* Bits 6:0 CALFACT_S[6:0]: Calibration Factors In Single-Ended mode */ - - -/*--------------- ADC_CSR values ------------------------*/ - -/* Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV (1 << 26) - -/* Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV (1 << 25) - -/* Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV (1 << 24) - -/* Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV (1 << 23) - -/* Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC */ -#define ADC_CSR_JEOS_SLV (1 << 22) - -/* Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV (1 << 21) - -/* Bit 20 OVR_SLV: Overrun flag of the slave ADC */ -#define ADC_CSR_OVR_SLV (1 << 20) - -/* Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC */ -#define ADC_CSR_EOS_SLV (1 << 19) - -/* Bit 18 EOC_SLV: End of regular conversion of the slave ADC */ -#define ADC_CSR_EOC_SLV (1 << 18) - -/* Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC */ -#define ADC_CSR_EOSMP_SLV (1 << 17) - -/* Bit 16 ADRDY_SLV: Slave ADC ready */ -#define ADC_CSR_ADRDY_SLV (1 << 16) - -/* Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC */ -#define ADC_CSR_JQOVF_MST (1 << 10) - -/* Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_AWD3_MST (1 << 9) - -/* Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD2_MST (1 << 8) - -/* Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD1_MST (1 << 7) - -/* Bit 6 JEOS_MST: End of injected sequence flag of the master ADC */ -#define ADC_CSR_JEOS_MST (1 << 6) - -/* Bit 5 JEOC_MST: End of injected conversion flag of the master ADC */ -#define ADC_CSR_JEOC_MST (1 << 5) - -/* Bit 4 OVR_MST: Overrun flag of the master ADC */ -#define ADC_CSR_OVR_MST (1 << 4) - -/* Bit 3 EOS_MST: End of regular sequence flag of the master ADC */ -#define ADC_CSR_EOS_MST (1 << 3) - -/* Bit 2 EOC_MST: End of regular conversion of the master ADC */ -#define ADC_CSR_EOC_MST (1 << 2) - -/* Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC */ -#define ADC_CSR_EOSMP_MST (1 << 1) - -/* Bit 0 ADRDY_MST: Master ADC ready */ -#define ADC_CSR_ADRDY_MST (1 << 0) - - -/*-------- ADC_CCR values ------------*/ - -/* VBATEN: VBAT enable */ -#define ADC_CCR_VBATEN (1 << 24) - -/* TSEN: Temperature sensor enable */ -#define ADC_CCR_TSEN (1 << 23) - -/* VREFEN: VREFINT enable */ -#define ADC_CCR_VREFEN (1 << 22) - -/* CKMODE[1:0]: ADC clock mode */ -#define ADC_CCR_CKMODE_CKX (0x0 << 16) -#define ADC_CCR_CKMODE_DIV1 (0x1 << 16) -#define ADC_CCR_CKMODE_DIV2 (0x2 << 16) -#define ADC_CCR_CKMODE_DIV4 (0x3 << 16) - -#define ADC_CCR_CKMODE_MASK (0x3 << 16) - -/* MDMA[1:0]: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_DISABLE (0x0 << 14) -/*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/ -#define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) -#define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) - -/* DMACFG: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_DMACFG (1 << 13) - -/* DELAY: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_SHIFT 8 - -/* DUAL[4:0]: Dual ADC mode selection */ -/****************************************************************************/ -/** @defgroup adc_multi_mode ADC Multi mode selection -@ingroup adc_defines - -@{*/ - -/** All ADCs independent */ -#define ADC_CCR_DUAL_INDEPENDENT 0x0 - -/* Dual modes: (ADC1 master + ADC2 slave or ADC3 master + ADC4 slave) */ -/** - * Dual modes combined regular simultaneous + - * injected simultaneous mode. - */ -#define ADC_CCR_DUAL_REG_SIMUL_AND_INJECTED_SIMUL 0x1 -/** - * Dual mode Combined regular simultaneous + - * alternate trigger mode. - */ -#define ADC_CCR_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG 0x2 -/** - * Dual mode Combined interleaved mode + - * injected simultaneous mode. - */ -#define ADC_CCR_DUAL_REG_INTERLEAVED_AND_INJECTED_SIMUL 0x3 - -/** Dual mode Injected simultaneous mode only. */ -#define ADC_CCR_DUAL_INJECTED_SIMUL 0x5 -/** Dual mode Regular simultaneous mode only. */ -#define ADC_CCR_DUAL_REGULAR_SIMUL 0x6 -/** Dual mode Interleaved mode only. */ -#define ADC_CCR_DUAL_INTERLEAVED 0x7 -/** Dual mode Alternate trigger mode only. */ -#define ADC_CCR_DUAL_ALTERNATE_TRIG 0x9 -/**@}*/ - -#define ADC_CCR_DUAL_MASK (0x1f) -#define ADC_CCR_DUAL_SHIFT 0 - - -/*---------------- ADC_CDR values -----------------*/ - -/* Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC */ - -/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */ - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_TEMP 16 -#define ADC_CHANNEL_VBAT 17 -#define ADC_CHANNEL_VREF 18 -/**@}*/ - - -BEGIN_DECLS - -void adc_enable_analog_watchdog_regular(uint32_t adc); -void adc_disable_analog_watchdog_regular(uint32_t adc); -void adc_enable_analog_watchdog_injected(uint32_t adc); -void adc_disable_analog_watchdog_injected(uint32_t adc); -void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); -void adc_disable_discontinuous_mode_regular(uint32_t adc); -void adc_enable_discontinuous_mode_injected(uint32_t adc); -void adc_disable_discontinuous_mode_injected(uint32_t adc); -void adc_enable_automatic_injected_group_conversion(uint32_t adc); -void adc_disable_automatic_injected_group_conversion(uint32_t adc); -void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); -void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, - uint8_t channel); -/*void adc_enable_scan_mode(uint32_t adc);*/ -/*void adc_disable_scan_mode(uint32_t adc);*/ -void adc_enable_eoc_interrupt_injected(uint32_t adc); -void adc_disable_eoc_interrupt_injected(uint32_t adc); -void adc_enable_eos_interrupt_injected(uint32_t adc); -void adc_disable_eos_interrupt_injected(uint32_t adc); -void adc_enable_all_awd_interrupt(uint32_t adc); -void adc_disable_all_awd_interrupt(uint32_t adc); -void adc_enable_eos_interrupt(uint32_t adc); -void adc_disable_eos_interrupt(uint32_t adc); -void adc_start_conversion_injected(uint32_t adc); -void adc_disable_external_trigger_regular(uint32_t adc); -void adc_disable_external_trigger_injected(uint32_t adc); -void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); -void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); -void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); -bool adc_eoc_injected(uint32_t adc); -bool adc_eos_injected(uint32_t adc); -uint32_t adc_read_injected(uint32_t adc, uint8_t reg); -void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); - -void adc_set_clk_prescale(uint32_t adc, uint32_t prescaler); -void adc_set_multi_mode(uint32_t adc, uint32_t mode); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity); -bool adc_awd(uint32_t adc); -/*void adc_set_dma_continue(uint32_t adc);*/ -/*void adc_set_dma_terminate(uint32_t adc);*/ - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/comparator.h b/libopencm3/include/libopencm3/stm32/f3/comparator.h deleted file mode 100644 index 87ce2d4..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/comparator.h +++ /dev/null @@ -1,106 +0,0 @@ -/** @defgroup comp_defines COMP Defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F3xx - * Comparator module - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 20 Jul 2018 - * - *LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_COMP_H -#define LIBOPENCM3_COMP_H -/**@{*/ - -#define COMP1 (COMP_BASE + 0x1C) -#define COMP2 (COMP_BASE + 0x20) -#define COMP3 (COMP_BASE + 0x24) -#define COMP4 (COMP_BASE + 0x28) -#define COMP5 (COMP_BASE + 0x2C) -#define COMP6 (COMP_BASE + 0x30) -#define COMP7 (COMP_BASE + 0x34) - -/* Comparator registers */ - -/* Control and status register (COMPx_CSR) */ -#define COMP_CSR(comp_base) MMIO32((comp_base) + 0x00) -#define COMP1_CSR COMP_CSR(COMP1) -#define COMP2_CSR COMP_CSR(COMP2) -#define COMP3_CSR COMP_CSR(COMP3) -#define COMP4_CSR COMP_CSR(COMP4) -#define COMP5_CSR COMP_CSR(COMP5) -#define COMP6_CSR COMP_CSR(COMP6) -#define COMP7_CSR COMP_CSR(COMP7) - -/* COMPx_CSR values */ - -#define COMP_CSR_LOCK (0x1 << 31) -#define COMP_CSR_OUT (0x1 << 30) - -/* individual blanking sources depends on COMP used */ -#define COMP_CSR_BLANKING_MASK (0x7) -#define COMP_CSR_BLANKING_SHIFT (18) -#define COMP_CSR_BLANKING_NONE (0x0) -#define COMP_CSR_BLANKING(blanking) (((blanking) & COMP_CSR_BLANKING_MASK) << COMP_CSR_BLANKING_SHIFT) - -/* only on COMP1/3/5/7 */ -#define COMP_CSR_HYST_NONE (0x0) -#define COMP_CSR_HYST_LOW (0x1) -#define COMP_CSR_HYST_MEDIUM (0x2) -#define COMP_CSR_HYST_HIGH (0x3) -#define COMP_CSR_HYST_MASK (0x3) -#define COMP_CSR_HYST_SHIFT (16) - -#define COMP_CSR_POL (0x1 << 15) - -/* individual value depends on COMP used */ -#define COMP_CSR_OUTSEL(outsel) (((outsel) & COMP_CSR_OUTSEL_MASK) << COMP_CSR_OUTSEL_SHIFT) -#define COMP_CSR_OUTSEL_MASK (0xf) -#define COMP_CSR_OUTSEL_SHIFT (10) - -/* only on COMP2/4/6 */ -#define COMP_CSR_WINMODE (0x1 << 9) - -/* not available on COMP1 */ -#define COMP_CSR_INPSEL (0x1 << 7) - -/* individual value depends on COMP used, - also respects bit 3 (INMSEL[3]) where available */ -#define COMP_CSR_INMSEL(inmsel) ((((inmsel) & 0x7) << 4) | \ - ((((inmsel) & 0x8) >> 3) << 22)) -#define COMP_CSR_INMSEL_MASK (0x7 << 4) - -#define COMP_CSR_MODE_HIGHSPEED (0x0) -#define COMP_CSR_MODE_MEDIUMSPEED (0x1) -#define COMP_CSR_MODE_LOWSPEED (0x2) -#define COMP_CSR_MODE_ULTRALOWPOWER (0x3) -#define COMP_CSR_MODE_MASK (0x3) -#define COMP_CSR_MODE_SHIFT (2) - -/* only on COMP1 and COMP2 */ -#define COMP_CSR_INPDAC (0x1 << 1) - -#define COMP_CSR_EN (0x1 << 0) - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/crc.h b/libopencm3/include/libopencm3/stm32/f3/crc.h deleted file mode 100644 index 469ffb7..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/crc.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief Defined Constants and Types for the STM32F3xx CRC Generator - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/dac.h b/libopencm3/include/libopencm3/stm32/f3/dac.h deleted file mode 100644 index aceea8c..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/dac.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dac_defines DAC Defines - * - * @brief Defined Constants and Types for the STM32F3xx DAC - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/dma.h b/libopencm3/include/libopencm3/stm32/f3/dma.h deleted file mode 100644 index ae738cc..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/dma.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32F3xx_defines - * - * @brief Defined Constants and Types for the STM32F3xx DMA Controller - * - * @version 1.0.0 - * - * @date 30 November 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h b/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h deleted file mode 100644 index 8732388..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32F3 - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * API documentation for ST Microelectronics STM32F3 Cortex M3 series. - * - * LGPL License Terms @ref lgpl_license - */ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F3xx STM32F3xx - * Libraries for ST Microelectronics STM32F3xx series. - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/** @defgroup STM32F3xx_defines STM32F3xx Defines - * - * @brief Defined Constants and Types for the STM32F3xx series - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - diff --git a/libopencm3/include/libopencm3/stm32/f3/exti.h b/libopencm3/include/libopencm3/stm32/f3/exti.h deleted file mode 100644 index c5ef4e9..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/exti.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F3xx External Interrupts - * - * - * @ingroup STM32F3xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Piotr Esden-Tempski - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H -/**@{*/ - -#include -#include - -/* --- EXTI registers ------------------------------------------------------ */ -#define EXTI_IMR2 MMIO32(EXTI_BASE + 0x18) -#define EXTI_EMR2 MMIO32(EXTI_BASE + 0x1C) -#define EXTI_RTSR2 MMIO32(EXTI_BASE + 0x20) -#define EXTI_FTSR2 MMIO32(EXTI_BASE + 0x24) -#define EXTI_SWIER2 MMIO32(EXTI_BASE + 0x28) -#define EXTI_PR2 MMIO32(EXTI_BASE + 0x2C) -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/flash.h b/libopencm3/include/libopencm3/stm32/f3/flash.h deleted file mode 100644 index ed0e2b9..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/flash.h +++ /dev/null @@ -1,113 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @brief Defined Constants and Types for the STM32F3xx Flash - * controller - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H -/**@{*/ - -#include -#include - -/** @defgroup flash_registers Flash Registers - * @ingroup flash_defines -@{*/ -/** Flash Access Control register */ -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -/** Flash Key register */ -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -/** Flash Option bytes key register */ -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -/** Flash Status register*/ -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -/** Flash Control register */ -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -/** Flash Address register */ -#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -/** Flash Option Byte register */ -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) -/** Flash Write Protection register */ -#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -/*@}*/ - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_ACR_PRFTBS (1 << 5) -#define FLASH_ACR_PRFTBE (1 << 4) -/** Compatibility alias */ -#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTBE -#define FLASH_ACR_HLFCYA (1 << 3) -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 0x0f -/** @defgroup flash_latency FLASH Wait States @{*/ -#define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK) -/**@}*/ - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_BSY (1 << 0) -#define FLASH_SR_ERLYBSY (1 << 1) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_WRPRTERR (1 << 4) -#define FLASH_SR_EOP (1 << 5) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_OBL_LAUNCH (1 << 13) -#define FLASH_CR_EOPIE (1 << 12) -#define FLASH_CR_ERRIE (1 << 10) -#define FLASH_CR_OPTWRE (1 << 9) -#define FLASH_CR_LOCK (1 << 7) -#define FLASH_CR_STRT (1 << 6) -#define FLASH_CR_OPTER (1 << 5) -#define FLASH_CR_OPTPG (1 << 4) -#define FLASH_CR_MER (1 << 2) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_PG (1 << 0) - -/* F3 uses the same keys for option bytes */ -#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 - -BEGIN_DECLS - -void flash_clear_pgerr_flag(void); -void flash_clear_wrprterr_flag(void); -void flash_program_half_word(uint32_t address, uint16_t data); -void flash_erase_page(uint32_t page_address); -void flash_erase_all_pages(void); - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/gpio.h b/libopencm3/include/libopencm3/stm32/f3/gpio.h deleted file mode 100644 index 82aad6b..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/gpio.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the STM32F3xx General Purpose - * I/O - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 1 July 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/hrtim.h b/libopencm3/include/libopencm3/stm32/f3/hrtim.h deleted file mode 100644 index 9fb8afc..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/hrtim.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup hrtim_defines HRTIM Defines - * - * @brief Defined Constants and Types for the STM32F3xx High Resolution Timer - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 25 February 2017 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_HRTIM_H -#define LIBOPENCM3_HRTIM_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/i2c.h b/libopencm3/include/libopencm3/stm32/f3/i2c.h deleted file mode 100644 index ee16a86..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/i2c.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the STM32F3xx I2C - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 12 October 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f3/irq.json b/libopencm3/include/libopencm3/stm32/f3/irq.json deleted file mode 100644 index 9aaf533..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/irq.json +++ /dev/null @@ -1,88 +0,0 @@ -{ - "irqs": [ - "nvic_wwdg", - "pvd", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2_tsc", - "exti3", - "exti4", - "dma1_channel1", - "dma1_channel2", - "dma1_channel3", - "dma1_channel4", - "dma1_channel5", - "dma1_channel6", - "dma1_channel7", - "adc1_2", - "usb_hp_can1_tx", - "usb_lp_can1_rx0", - "can1_rx1", - "can1_sce", - "exti9_5", - "tim1_brk_tim15", - "tim1_up_tim16", - "tim1_trg_com_tim17", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev_exti23", - "i2c1_er", - "i2c2_ev_exti24", - "i2c2_er", - "spi1", - "spi2", - "usart1_exti25", - "usart2_exti26", - "usart3_exti28", - "exti15_10", - "rtc_alarm", - "usb_wkup_a", - "tim8_brk", - "tim8_up", - "tim8_trg_com", - "tim8_cc", - "adc3", - "reserved_1", - "reserved_2", - "reserved_3", - "spi3", - "uart4_exti34", - "uart5_exti35", - "tim6_dac", - "tim7", - "dma2_channel1", - "dma2_channel2", - "dma2_channel3", - "dma2_channel4", - "dma2_channel5", - "eth", - "reserved_4", - "reserved_5", - "comp123", - "comp456", - "comp7", - "hrtim_master", - "hrtim_tima", - "hrtim_timb", - "hrtim_timc", - "hrtim_timd", - "hrtim_time", - "hrtim_flt", - "usb_hp", - "usb_lp", - "usb_wkup", - "reserved_13", - "reserved_14", - "reserved_15", - "reserved_16" - ], - "partname_humanreadable": "STM32 F3 series", - "partname_doxygen": "STM32F3", - "includeguard": "LIBOPENCM3_STM32_F3_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/f3/iwdg.h b/libopencm3/include/libopencm3/stm32/f3/iwdg.h deleted file mode 100644 index cf5b197..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/iwdg.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @brief Defined Constants and Types for the STM32F3xx Independent Watchdog - * Timer - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/memorymap.h b/libopencm3/include/libopencm3/stm32/f3/memorymap.h deleted file mode 100644 index 369192e..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/memorymap.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * Modified by 2013 Fernando Cortes (stm32f3) - * Modified by 2013 Guillermo Rivera (stm32f3) - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32F3 specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 (0x48000000U) -#define PERIPH_BASE_AHB3 (0x50000000U) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -/* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */ -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */ -/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */ - - -/* APB2 */ -#define HRTIM_BASE (PERIPH_BASE_APB2 + 0x7400) -#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) -#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) -/* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */ -#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3C00) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) -/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */ -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) -#define COMP_BASE (PERIPH_BASE_APB2 + 0x0000) -#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0000) - - -/* AHB2 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1C00) - - -/* AHB1 */ -#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) -/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) -/* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) -/* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) - - -/* AHB3 */ -#define ADC3_BASE (PERIPH_BASE_AHB3 + 0x0400) -#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x0500) -#define ADC1_BASE (PERIPH_BASE_AHB3 + 0x0000) -#define ADC2_BASE (PERIPH_BASE_AHB3 + 0x0100) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU) -#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - -/* ST provided factory calibration values @ 3.3V */ -#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA) -#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8) -#define ST_TSENSE_CAL2_110C MMIO16(0x1FFFF7C2) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/pwr.h b/libopencm3/include/libopencm3/stm32/f3/pwr.h deleted file mode 100644 index be392ab..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/pwr.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - * - * @brief Defined Constants and Types for the STM32F3xx Power control - * - * @ingroup STM32F3xx_defines - * - * @author @htmlonly © @endhtmlonly 2011 - * Stephen Caudle - * @author @htmlonly © @endhtmlonly 2013 - * Fernando Cortes - * @author @htmlonly © @endhtmlonly 2013 - * Guillermo Rivera - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Stephen Caudle - * Modified by 2013 Fernando Cortes (stm32f3) - * Modified by 2013 Guillermo Rivera (stm32f3) - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/** Enable WKUP pin 3 */ -#define PWR_CSR_EWUP3 (1 << 10) -/** Enable WKUP pin 2 */ -#define PWR_CSR_EWUP2 (1 << 9) -/** Enable WKUP pin 1 */ -#define PWR_CSR_EWUP1 PWR_CSR_EWUP - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rcc.h b/libopencm3/include/libopencm3/stm32/f3/rcc.h deleted file mode 100644 index c83b2ac..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/rcc.h +++ /dev/null @@ -1,638 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F3xx Reset and Clock - * Control - * - * @ingroup STM32F3xx_defines - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2011 - * Stephen Caudle - * @author @htmlonly © @endhtmlonly 2013 - * Fernando Cortes - * @author @htmlonly © @endhtmlonly 2013 - * Guillermo Rivera - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2011 Stephen Caudle - * Modified by 2013 Fernando Cortes (stm32f3) - * Modified by 2013 Guillermo Rivera (stm32f3) - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C) -#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ -#define RCC_CFGR_MCOF (1 << 28) -#define RCC_CFGR_I2SSRC (1 << 23) -#define RCC_CFGR_USBPRES (1 << 22) -#define RCC_CFGR_PLLXTPRE (1 << 17) -#define RCC_CFGR_PLLSRC (1 << 16) - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0x7 -#define RCC_CFGR_MCO_NOCLK 0x0 -/*Reserve RCC_CFGR_MCO 0x1*/ -#define RCC_CFGR_MCO_LSI 0x2 -#define RCC_CFGR_MCO_LSE 0x3 -#define RCC_CFGR_MCO_SYSCLK 0x4 -#define RCC_CFGR_MCO_HSI 0x5 -#define RCC_CFGR_MCO_HSE 0x6 -#define RCC_CFGR_MCO_PLL 0x7 - -/* PLLSRC: PLL source values */ -#define RCC_CFGR_PLLSRC_HSI_DIV2 0 -#define RCC_CFGR_PLLSRC_HSE_PREDIV 1 - -/* PLLMUL: PLL multiplication factor */ -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLMUL_MASK 0xF -#define RCC_CFGR_PLLMUL_MUL2 0x0 -#define RCC_CFGR_PLLMUL_MUL3 0x1 -#define RCC_CFGR_PLLMUL_MUL4 0x2 -#define RCC_CFGR_PLLMUL_MUL5 0x3 -#define RCC_CFGR_PLLMUL_MUL6 0x4 -#define RCC_CFGR_PLLMUL_MUL7 0x5 -#define RCC_CFGR_PLLMUL_MUL8 0x6 -#define RCC_CFGR_PLLMUL_MUL9 0x7 -#define RCC_CFGR_PLLMUL_MUL10 0x8 -#define RCC_CFGR_PLLMUL_MUL11 0x9 -#define RCC_CFGR_PLLMUL_MUL12 0xA -#define RCC_CFGR_PLLMUL_MUL13 0xB -#define RCC_CFGR_PLLMUL_MUL14 0xC -#define RCC_CFGR_PLLMUL_MUL15 0xD -#define RCC_CFGR_PLLMUL_MUL16 0xE - -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_SHIFT 11 -#define RCC_CFGR_PPRE2_MASK 0x7 -/* 0XX: HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV_NONE 0x0 - -#define RCC_CFGR_PPRE2_DIV_2 0x4 -#define RCC_CFGR_PPRE2_DIV_4 0x5 -#define RCC_CFGR_PPRE2_DIV_8 0x6 -#define RCC_CFGR_PPRE2_DIV_16 0x7 - -/* PPRE1:APB Low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_SHIFT 8 -#define RCC_CFGR_PPRE1_MASK 0x7 -/* 0XX: HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV_NONE 0x0 -#define RCC_CFGR_PPRE1_DIV_2 0x4 -#define RCC_CFGR_PPRE1_DIV_4 0x5 -#define RCC_CFGR_PPRE1_DIV_8 0x6 -#define RCC_CFGR_PPRE1_DIV_16 0x7 - -/* HPRE: HLCK prescaler */ -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE_MASK 0xf -/* 0XXX: SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 0x8 -#define RCC_CFGR_HPRE_DIV_4 0x9 -#define RCC_CFGR_HPRE_DIV_8 0xA -#define RCC_CFGR_HPRE_DIV_16 0xB -#define RCC_CFGR_HPRE_DIV_64 0xC -#define RCC_CFGR_HPRE_DIV_128 0xD -#define RCC_CFGR_HPRE_DIV_256 0xE -#define RCC_CFGR_HPRE_DIV_512 0xF - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLL 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_TIM20RST (1 << 20) -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_SPI4RST (1 << 15) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_I2C3RST (1 << 30) -#define RCC_APB1RSTR_DAC1RST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_DAC2RST (1 << 26) -#define RCC_APB1RSTR_CAN1RST (1 << 25) -#define RCC_APB1RSTR_USBRST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values - *@{*/ -#define RCC_AHBENR_ADC34EN (1 << 29) -#define RCC_AHBENR_ADC12EN (1 << 28) -#define RCC_AHBENR_TSCEN (1 << 24) -#define RCC_AHBENR_IOPGEN (1 << 23) -#define RCC_AHBENR_IOPFEN (1 << 22) -#define RCC_AHBENR_IOPEEN (1 << 21) -#define RCC_AHBENR_IOPDEN (1 << 20) -#define RCC_AHBENR_IOPCEN (1 << 19) -#define RCC_AHBENR_IOPBEN (1 << 18) -#define RCC_AHBENR_IOPAEN (1 << 17) -#define RCC_AHBENR_IOPHEN (1 << 16) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FMCEN (1 << 5) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) -/*@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@{*/ -#define RCC_APB2ENR_TIM20EN (1 << 20) -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_SPI4EN (1 << 15) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_SYSCFGEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_I2C3EN (1 << 30) -#define RCC_APB1ENR_DAC1EN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_DAC2EN (1 << 26) -#define RCC_APB1ENR_CANEN (1 << 25) -#define RCC_APB1ENR_USBEN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART5EN (1 << 20) -#define RCC_APB1ENR_USART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -/* RCC_BDCR[4:3]: LSEDRV */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -#define RCC_AHBRSTR_ADC34RST (1 << 29) -#define RCC_AHBRSTR_ADC12RST (1 << 28) -#define RCC_AHBRSTR_TSCRST (1 << 24) -#define RCC_AHBRSTR_IOPGRST (1 << 23) -#define RCC_AHBRSTR_IOPFRST (1 << 22) -#define RCC_AHBRSTR_IOPERST (1 << 21) -#define RCC_AHBRSTR_IOPDRST (1 << 20) -#define RCC_AHBRSTR_IOPCRST (1 << 19) -#define RCC_AHBRSTR_IOPBRST (1 << 18) -#define RCC_AHBRSTR_IOPARST (1 << 17) -#define RCC_AHBRSTR_IOPHRST (1 << 16) -#define RCC_AHBRSTR_FMCRST (1 << 5) -/**@}*/ - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ -/* ADCxxPRES: ADCxx prescaler */ -#define RCC_CFGR2_ADC34PRES_SHIFT 9 -#define RCC_CFGR2_ADC12PRES_SHIFT 4 -#define RCC_CFGR2_ADCxPRES_MASK 0x1f -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_1 0x10 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_2 0x11 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_4 0x12 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_6 0x13 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_8 0x14 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_10 0x15 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_12 0x16 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_16 0x17 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_32 0x18 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_64 0x19 -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_128 0x1A -#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_256 0x1B - -#define RCC_CFGR2_PREDIV 0xf -/** @defgroup rcc_cfgr2_prediv PLL source predividers -@ingroup rcc_defines -@{*/ -#define RCC_CFGR2_PREDIV_NODIV 0x0 -#define RCC_CFGR2_PREDIV_DIV2 0x1 -#define RCC_CFGR2_PREDIV_DIV3 0x2 -#define RCC_CFGR2_PREDIV_DIV4 0x3 -#define RCC_CFGR2_PREDIV_DIV5 0x4 -#define RCC_CFGR2_PREDIV_DIV6 0x5 -#define RCC_CFGR2_PREDIV_DIV7 0x6 -#define RCC_CFGR2_PREDIV_DIV8 0x7 -#define RCC_CFGR2_PREDIV_DIV9 0x8 -#define RCC_CFGR2_PREDIV_DIV10 0x9 -#define RCC_CFGR2_PREDIV_DIV11 0xa -#define RCC_CFGR2_PREDIV_DIV12 0xb -#define RCC_CFGR2_PREDIV_DIV13 0xc -#define RCC_CFGR2_PREDIV_DIV14 0xd -#define RCC_CFGR2_PREDIV_DIV15 0xe -#define RCC_CFGR2_PREDIV_DIV16 0xf -/**@}*/ - -/* --- RCC_CFGR3 values ---------------------------------------------------- */ -#define RCC_CFGR3_TIM8SW (1 << 9) -#define RCC_CFGR3_TIM1SW (1 << 8) -#define RCC_CFGR3_I2C2SW (1 << 5) -#define RCC_CFGR3_I2C1SW (1 << 4) -/* UART5SW: UART5 clock source selection */ -#define RCC_CFGR3_UART5SW_SHIFT 22 -#define RCC_CFGR3_UART5SW_PCLK 0x0 -#define RCC_CFGR3_UART5SW_SYSCLK 0x1 -#define RCC_CFGR3_UART5SW_LSE 0x2 -#define RCC_CFGR3_UART5SW_HSI 0x3 -/* UART4SW: UART4 clock source selection */ -#define RCC_CFGR3_UART4SW_SHIFT 20 -#define RCC_CFGR3_UART4SW_PCLK 0x0 -#define RCC_CFGR3_UART4SW_SYSCLK 0x1 -#define RCC_CFGR3_UART4SW_LSE 0x2 -#define RCC_CFGR3_UART4SW_HSI 0x3 -/* UART3SW: UART3 clock source selection */ -#define RCC_CFGR3_UART3SW_SHIFT 18 -#define RCC_CFGR3_UART3SW_PCLK 0x0 -#define RCC_CFGR3_UART3SW_SYSCLK 0x1 -#define RCC_CFGR3_UART3SW_LSE 0x2 -#define RCC_CFGR3_UART3SW_HSI 0x3 -/* UART2SW: UART2 clock source selection */ -#define RCC_CFGR3_UART2SW_SHIFT 16 -#define RCC_CFGR3_UART2SW_PCLK 0x0 -#define RCC_CFGR3_UART2SW_SYSCLK 0x1 -#define RCC_CFGR3_UART2SW_LSE 0x2 -#define RCC_CFGR3_UART2SW_HSI 0x3 -/* UART1SW: UART1 clock source selection */ -#define RCC_CFGR3_UART1SW_SHIFT 0 -#define RCC_CFGR3_UART1SW_PCLK 0x0 -#define RCC_CFGR3_UART1SW_SYSCLK 0x1 -#define RCC_CFGR3_UART1SW_LSE 0x2 -#define RCC_CFGR3_UART1SW_HSI 0x3 - - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_clock_hsi { - RCC_CLOCK_HSI_48MHZ, - RCC_CLOCK_HSI_64MHZ, /* Max from HSI */ - RCC_CLOCK_HSI_END -}; -enum rcc_clock_hse8 { - RCC_CLOCK_HSE8_72MHZ, - RCC_CLOCK_HSE8_END -}; - - -struct rcc_clock_scale { - uint8_t pllsrc; - uint8_t pllmul; - uint8_t plldiv; - bool usbdiv1; - uint32_t flash_waitstates; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - uint8_t power_save; - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; -}; - -extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END]; -extern const struct rcc_clock_scale rcc_hse8mhz_configs[RCC_CLOCK_HSE8_END]; - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -/* Availability in comment: - * 0: F30x - * 1: F31x - * 7: F37x - * 8: F38x - */ -enum rcc_periph_clken { - /* AHB peripherals*/ - RCC_DMA1 = _REG_BIT(0x14, 0),/*0178*/ - RCC_DMA2 = _REG_BIT(0x14, 1),/*0178*/ - RCC_SRAM = _REG_BIT(0x14, 2),/*0178*/ - RCC_FLTIF = _REG_BIT(0x14, 4),/*0178*/ - RCC_FMC = _REG_BIT(0x14, 5),/*0178*/ - RCC_CRC = _REG_BIT(0x14, 6),/*0178*/ - RCC_GPIOH = _REG_BIT(0x14, 16),/*0178*/ - RCC_GPIOA = _REG_BIT(0x14, 17),/*0178*/ - RCC_GPIOB = _REG_BIT(0x14, 18),/*0178*/ - RCC_GPIOC = _REG_BIT(0x14, 19),/*0178*/ - RCC_GPIOD = _REG_BIT(0x14, 20),/*0178*/ - RCC_GPIOE = _REG_BIT(0x14, 21),/*0178*/ - RCC_GPIOF = _REG_BIT(0x14, 22),/*0178*/ - RCC_GPIOG = _REG_BIT(0x14, 23),/*0178*/ - RCC_TSC = _REG_BIT(0x14, 24),/*0178*/ - RCC_ADC12 = _REG_BIT(0x14, 28),/*01--*/ - RCC_ADC34 = _REG_BIT(0x14, 29),/*01--*/ - - /* APB2 peripherals */ - RCC_SYSCFG = _REG_BIT(0x18, 0),/*0178*/ - RCC_ADC = _REG_BIT(0x18, 9),/*--78*/ - RCC_TIM1 = _REG_BIT(0x18, 11),/*01--*/ - RCC_SPI1 = _REG_BIT(0x18, 12),/*0178*/ - RCC_TIM8 = _REG_BIT(0x18, 13),/*01--*/ - RCC_USART1 = _REG_BIT(0x18, 14),/*0178*/ - RCC_SPI4 = _REG_BIT(0x18, 15), - RCC_TIM15 = _REG_BIT(0x18, 16),/*0178*/ - RCC_TIM16 = _REG_BIT(0x18, 17),/*0178*/ - RCC_TIM17 = _REG_BIT(0x18, 18),/*0178*/ - RCC_TIM19 = _REG_BIT(0x18, 19),/*--78*/ - RCC_TIM20 = _REG_BIT(0x18, 20), - RCC_DBGMCU = _REG_BIT(0x18, 22),/*--78*/ - RCC_SDADC1 = _REG_BIT(0x18, 24),/*--78*/ - RCC_SDADC2 = _REG_BIT(0x18, 25),/*--78*/ - RCC_SDADC3 = _REG_BIT(0x18, 26),/*--78*/ - RCC_HRTIM = _REG_BIT(0x18, 29), - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x1C, 0),/*0178*/ - RCC_TIM3 = _REG_BIT(0x1C, 1),/*0178*/ - RCC_TIM4 = _REG_BIT(0x1C, 2),/*0178*/ - RCC_TIM5 = _REG_BIT(0x1C, 3),/*--78*/ - RCC_TIM6 = _REG_BIT(0x1C, 4),/*0178*/ - RCC_TIM7 = _REG_BIT(0x1C, 5),/*0178*/ - RCC_TIM12 = _REG_BIT(0x1C, 6),/*--78*/ - RCC_TIM13 = _REG_BIT(0x1C, 7),/*--78*/ - RCC_TIM14 = _REG_BIT(0x1C, 8),/*--78*/ - RCC_TIM18 = _REG_BIT(0x1C, 9),/*--78*/ - RCC_WWDG = _REG_BIT(0x1C, 11),/*0178*/ - RCC_SPI2 = _REG_BIT(0x1C, 14),/*0178*/ - RCC_SPI3 = _REG_BIT(0x1C, 15),/*0178*/ - RCC_USART2 = _REG_BIT(0x1C, 17),/*0178*/ - RCC_USART3 = _REG_BIT(0x1C, 18),/*0178*/ - RCC_UART4 = _REG_BIT(0x1C, 19),/*01--*/ - RCC_UART5 = _REG_BIT(0x1C, 20),/*01--*/ - RCC_I2C1 = _REG_BIT(0x1C, 21),/*0178*/ - RCC_I2C2 = _REG_BIT(0x1C, 22),/*0178*/ - RCC_USB = _REG_BIT(0x1C, 23),/*0178*/ - RCC_CAN = _REG_BIT(0x1C, 25),/*0178*/ - RCC_CAN1 = _REG_BIT(0x1C, 25),/*0178*/ - RCC_DAC2 = _REG_BIT(0x1C, 26), - RCC_PWR = _REG_BIT(0x1C, 28),/*0178*/ - RCC_DAC1 = _REG_BIT(0x1C, 29), - RCC_CEC = _REG_BIT(0x1C, 30),/*--78*/ - RCC_I2C3 = _REG_BIT(0x1C, 30), -}; - -enum rcc_periph_rst { - /* APB2 peripherals*/ - RST_SYSCFG = _REG_BIT(0x0C, 0),/*0178*/ - RST_ADC = _REG_BIT(0x0C, 9),/*--78*/ - RST_TIM1 = _REG_BIT(0x0C, 11),/*01--*/ - RST_SPI1 = _REG_BIT(0x0C, 12),/*0178*/ - RST_TIM8 = _REG_BIT(0x0C, 13),/*01--*/ - RST_USART1 = _REG_BIT(0x0C, 14),/*0178*/ - RST_SPI4 = _REG_BIT(0x0C, 15), - RST_TIM15 = _REG_BIT(0x0C, 16),/*0178*/ - RST_TIM16 = _REG_BIT(0x0C, 17),/*0178*/ - RST_TIM17 = _REG_BIT(0x0C, 18),/*0178*/ - RST_TIM19 = _REG_BIT(0x0C, 19),/*--78*/ - RST_TIM20 = _REG_BIT(0x0C, 20), - RST_SDADC1 = _REG_BIT(0x0C, 24),/*--78*/ - RST_SDADC2 = _REG_BIT(0x0C, 25),/*--78*/ - RST_SDADC3 = _REG_BIT(0x0C, 26),/*--78*/ - RST_HRTIM = _REG_BIT(0x0C, 29), - - /* APB1 peripherals */ - RST_TIM2 = _REG_BIT(0x10, 0),/*0178*/ - RST_TIM3 = _REG_BIT(0x10, 1),/*0178*/ - RST_TIM4 = _REG_BIT(0x10, 2),/*0178*/ - RST_TIM5 = _REG_BIT(0x10, 3),/*--78*/ - RST_TIM6 = _REG_BIT(0x10, 4),/*0178*/ - RST_TIM7 = _REG_BIT(0x10, 5),/*0178*/ - RST_TIM12 = _REG_BIT(0x10, 6),/*--78*/ - RST_TIM13 = _REG_BIT(0x10, 7),/*--78*/ - RST_TIM14 = _REG_BIT(0x10, 8),/*--78*/ - RST_TIM18 = _REG_BIT(0x10, 9),/*--78*/ - RST_WWDG = _REG_BIT(0x10, 11),/*0178*/ - RST_SPI2 = _REG_BIT(0x10, 14),/*0178*/ - RST_SPI3 = _REG_BIT(0x10, 15),/*0178*/ - RST_USART2 = _REG_BIT(0x10, 17),/*0178*/ - RST_USART3 = _REG_BIT(0x10, 18),/*0178*/ - RST_UART4 = _REG_BIT(0x10, 19),/*01--*/ - RST_UART5 = _REG_BIT(0x10, 20),/*01--*/ - RST_I2C1 = _REG_BIT(0x10, 21),/*0178*/ - RST_I2C2 = _REG_BIT(0x10, 22),/*0178*/ - RST_USB = _REG_BIT(0x10, 23),/*0178*/ - RST_CAN = _REG_BIT(0x10, 25),/*0178*/ - RST_CAN1 = _REG_BIT(0x10, 25),/*0178*/ - RST_DAC2 = _REG_BIT(0x10, 26), - RST_PWR = _REG_BIT(0x10, 28),/*0178*/ - RST_DAC1 = _REG_BIT(0x10, 29), - RST_CEC = _REG_BIT(0x10, 30),/*--78*/ - RST_I2C3 = _REG_BIT(0x10, 30), - - /* AHB peripherals */ - RST_FMC = _REG_BIT(0x28, 5), - RST_GPIOH = _REG_BIT(0x28, 16), - RST_GPIOA = _REG_BIT(0x28, 17),/*0178*/ - RST_GPIOB = _REG_BIT(0x28, 18),/*0178*/ - RST_GPIOC = _REG_BIT(0x28, 19),/*0178*/ - RST_GPIOD = _REG_BIT(0x28, 20),/*0178*/ - RST_GPIOE = _REG_BIT(0x28, 21),/*0178*/ - RST_GPIOF = _REG_BIT(0x28, 22),/*0178*/ - RST_GPIOG = _REG_BIT(0x28, 23), - RST_TSC = _REG_BIT(0x28, 24),/*0178*/ - RST_ADC12 = _REG_BIT(0x28, 28),/*01--*/ - RST_ADC34 = _REG_BIT(0x28, 29),/*01--*/ - - /* BDCR[16] */ - RST_BD = _REG_BIT(0x20, 16), -}; - -#undef _REG_BIT - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_osc_not_ready(enum rcc_osc osc); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_prediv(uint32_t prediv); -void rcc_set_pll_multiplier(uint32_t pll); -uint32_t rcc_get_system_clock_source(void); -void rcc_backupdomain_reset(void); -void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); -void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock); -void rcc_set_i2c_clock_hsi(uint32_t i2c); -void rcc_set_i2c_clock_sysclk(uint32_t i2c); -uint32_t rcc_get_i2c_clocks(void); -void rcc_usb_prescale_1_5(void); -void rcc_usb_prescale_1(void); -void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rtc.h b/libopencm3/include/libopencm3/stm32/f3/rtc.h deleted file mode 100644 index b7cbbb4..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/rtc.h +++ /dev/null @@ -1,40 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the STM32F3xx Real Time Clock - * - * @ingroup STM32F3xx_defines - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies - * - * @version 1.0.0 - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_F3_H -#define LIBOPENCM3_RTC_F3_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/spi.h b/libopencm3/include/libopencm3/stm32/f3/spi.h deleted file mode 100644 index 05b6c9d..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/spi.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup spi_defines SPI Defines - * - * @brief Defined Constants and Types for the STM32F3xx SPI - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/st_usbfs.h b/libopencm3/include/libopencm3/stm32/f3/st_usbfs.h deleted file mode 100644 index 7da73f2..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/syscfg.h b/libopencm3/include/libopencm3/stm32/f3/syscfg.h deleted file mode 100644 index 39733da..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/syscfg.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32F3xx_defines - * - * @brief Defined Constants and Types for the STM32F3xx Sysconfig - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/timer.h b/libopencm3/include/libopencm3/stm32/f3/timer.h deleted file mode 100644 index f9284c7..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/timer.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup timer_defines Timer Defines - * - * @brief Defined Constants and Types for the STM32F3xx Timers - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 8 March 2013 - * - * @author @htmlonly © @endhtmlonly 2011 Fergus Noble - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/usart.h b/libopencm3/include/libopencm3/stm32/f3/usart.h deleted file mode 100644 index 860eba0..0000000 --- a/libopencm3/include/libopencm3/stm32/f3/usart.h +++ /dev/null @@ -1,57 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32F3xx USART - * - * @ingroup STM32F3xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/**@{*/ - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/adc.h b/libopencm3/include/libopencm3/stm32/f4/adc.h deleted file mode 100644 index 6c50248..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/adc.h +++ /dev/null @@ -1,200 +0,0 @@ -/** @defgroup adc_defines ADC Defines - -@brief Defined Constants and Types for the STM32F4xx Analog to Digital -Converters - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2019 -Matthew Lai -@author @htmlonly © @endhtmlonly 2009 -Edward Cheeseman - -@date 31 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Matthew Lai - * Copyright (C) 2009 Edward Cheeseman - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32((block) + 0x14) -#define ADC_JOFR2(block) MMIO32((block) + 0x18) -#define ADC_JOFR3(block) MMIO32((block) + 0x1c) -#define ADC_JOFR4(block) MMIO32((block) + 0x20) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32((block) + 0x24) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32((block) + 0x28) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32((block) + 0x2c) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32((block) + 0x30) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32((block) + 0x34) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32((block) + 0x38) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32((block) + 0x3c) -#define ADC_JDR2(block) MMIO32((block) + 0x40) -#define ADC_JDR3(block) MMIO32((block) + 0x44) -#define ADC_JDR4(block) MMIO32((block) + 0x48) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32((block) + 0x4c) - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! - *@{*/ -#define ADC_CHANNEL_TEMP_F40 16 -#define ADC_CHANNEL_TEMP_F42 18 -#define ADC_CHANNEL_VREF 17 -#define ADC_CHANNEL_VBAT 18 -/**@}*/ - - -/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ -#define ADC_CR1_AWDCH_MAX 18 - - -/* --- Convenience macros -------------------------------------------------- */ -/* EXTSEL[3:0]: External event selection for regular group. */ -/****************************************************************************/ -/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group -@ingroup adc_defines - -@{*/ -/** Timer 1 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) -/** Timer 1 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) -/** Timer 1 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) -/** Timer 2 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) -/** Timer 2 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) -/** Timer 2 Compare Output 4 */ -#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) -/** Timer 2 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24) -/** Timer 3 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) -/** Timer 3 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) -/** Timer 4 Compare Output 4 */ -#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) -/** Timer 5 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) -/** Timer 5 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) -/** Timer 5 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) -/** Timer 8 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) -/** Timer 8 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) -/** EXTI Line 11 Event */ -#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) -/**@}*/ - -/* JEXTSEL[3:0]: External event selection for injected group. */ -/****************************************************************************/ -/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group -@ingroup adc_defines - -@{*/ -#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) -#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) -#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) -#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) -#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) -#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) -#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) -#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) -#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) -#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) -/**@}*/ - -/* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_3CYC 0x0 -#define ADC_SMPR_SMP_15CYC 0x1 -#define ADC_SMPR_SMP_28CYC 0x2 -#define ADC_SMPR_SMP_56CYC 0x3 -#define ADC_SMPR_SMP_84CYC 0x4 -#define ADC_SMPR_SMP_112CYC 0x5 -#define ADC_SMPR_SMP_144CYC 0x6 -#define ADC_SMPR_SMP_480CYC 0x7 -/**@}*/ - -/* --- ADC_SQR1 values ----------------------------------------------------- */ -#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) - -#define ADC_SQR_MAX_CHANNELS_REGULAR 16 - -/* ADCPRE: ADC prescaler. */ -/****************************************************************************/ -/** @defgroup adc_ccr_adcpre ADC Prescale -@ingroup adc_defines - -@{*/ -#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) -#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) -#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) -#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) -/**@}*/ -#define ADC_CCR_ADCPRE_MASK (0x3 << 16) -#define ADC_CCR_ADCPRE_SHIFT 16 - - -BEGIN_DECLS - -void adc_set_multi_mode(uint32_t mode); -void adc_enable_vbat_sensor(void); -void adc_disable_vbat_sensor(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crc.h b/libopencm3/include/libopencm3/stm32/f4/crc.h deleted file mode 100644 index ccda3a4..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup crc_defines CRC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F4xx CRC -Generator - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crypto.h b/libopencm3/include/libopencm3/stm32/f4/crypto.h deleted file mode 100644 index 5e6d4e4..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/crypto.h +++ /dev/null @@ -1,97 +0,0 @@ -/** @defgroup crypto_defines CRYPTO Defines - * - * @brief Defined constants and Types for the STM32F4xx Crypto Coprocessor - * - * @ingroup STM32F4xx_defines - * - * @version 1.0.0 - * - * @date 22 Jun 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRYPTO_H -#define LIBOPENCM3_CRYPTO_H - -#include - -/**@{*/ - -/* --- CRYP registers ------------------------------------------------------ */ -/** @defgroup crypto_defines_registers Registers (for F42xx or F43xx only) - * - * @brief Register access to the CRYP controller. Registers for F42xx and 43xx - * - * @ingroup crypto_defines - */ -/**@{*/ - -/* CRYP_CSGCMCCMxR: Crypto context registers CCM mode, i=0-7*/ -#define CRYP_CSGCMCCMR(i) MMIO32(CRYP_BASE + 0x50 + (i) * 4) - -/* CRYP_CSGCMxR: Crypto context registers all modes, i=0-7*/ -#define CRYP_CSGCMR(i) MMIO32(CRYP_BASE + 0x70 + (i) * 4) - -/* --- CRYP_CR values ------------------------------------------------------ */ - -/* Only for part STM32F42xx and STM32F43xx: */ - -/* GCM_CMPH: GCM or CCM phase state */ -#define CRYP_CR_GCM_CMPH_SHIFT 16 -#define CRYP_CR_GCM_CMPH (3 << CRYP_CR_GCM_CMPH_SHIFT) -#define CRYP_CR_GCM_CMPH_INIT (0 << CRYP_CR_GCM_CMPH_SHIFT) -#define CRYP_CR_GCM_CMPH_HEADER (1 << CRYP_CR_GCM_CMPH_SHIFT) -#define CRYP_CR_GCM_CMPH_PAYLOAD (2 << CRYP_CR_GCM_CMPH_SHIFT) -#define CRYP_CR_GCM_CMPH_FINAL (3 << CRYP_CR_GCM_CMPH_SHIFT) - -/* ALGOMODE3: Algorithm mode, fourth bit */ -#define CRYP_CR_ALGOMODE3 (1 << 19) - -/**@}*/ - -/** @defgroup crypto_api API (for F42xx or F43xx only) - * - * @brief API for the CRYP controller. - * - * @warning Only for F42xx and 43xx - * - * @ingroup crypto_defines - */ -/**@{*/ - -enum crypto_mode_mac { - ENCRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3, - ENCRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3, - DECRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3 | - CRYP_CR_ALGODIR, - DECRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3 | - CRYP_CR_ALGODIR, -}; - -BEGIN_DECLS - -void crypto_context_swap(uint32_t *buf); -void crypto_set_mac_algorithm(enum crypto_mode_mac mode); - -END_DECLS -/**@}*/ -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/dac.h b/libopencm3/include/libopencm3/stm32/f4/dac.h deleted file mode 100644 index 3a38403..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/dac.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32F4xx DAC - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/dcmi.h b/libopencm3/include/libopencm3/stm32/f4/dcmi.h deleted file mode 100644 index ae9639e..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/dcmi.h +++ /dev/null @@ -1,229 +0,0 @@ -/** @defgroup dcmi_defines DCMI Defines - * - * @ingroup STM32F4xx_defines - * - * @brief Defined Constants and Macros for the STM32F4xx DCMI Peripheral - * - * @version 1.0.0 - * - * @date 2017-10-16 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * STM32F4 DCMI Defines - * - * Copyright (C) 2017, Marek Koza - * - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -#include -#include - -#pragma once - -/**@{*/ - -/** - * DCMI control register 1 - */ -#define DCMI_CR MMIO32(DCMI_BASE + 0x0U) -/** - * @defgroup dcmi_cr_values DCMI_CR Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_CR_EN (1 << 14) -#define DCMI_CR_EDM1 (1 << 11) -#define DCMI_CR_EDM0 (1 << 10) -#define DCMI_CR_FCRC1 (1 << 9) -#define DCMI_CR_FCRC0 (1 << 8) -#define DCMI_CR_VSPOL (1 << 7) -#define DCMI_CR_HSPOL (1 << 6) -#define DCMI_CR_PCKPOL (1 << 5) -#define DCMI_CR_ESS (1 << 4) -#define DCMI_CR_JPEG (1 << 3) -#define DCMI_CR_CROP (1 << 2) -#define DCMI_CR_CM (1 << 1) -#define DCMI_CR_CAPTURE (1 << 0) -/**@}*/ - -/** - * DCMI status register - */ -#define DCMI_SR MMIO32(DCMI_BASE + 0x04U) - -/** - * DCMI raw interrupt status register - * - * DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this - * register returns the status of the corresponding interrupt before masking with the DCMI_IER - * register value. - */ -#define DCMI_RIS MMIO32(DCMI_BASE + 0x08U) -/** - * @defgroup dcmi_ris_values DCMI_RIS Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_RIS_LINE (1 << 4) -#define DCMI_RIS_VSYNC (1 << 3) -#define DCMI_RIS_ERR (1 << 2) -#define DCMI_RIS_OVR (1 << 1) -#define DCMI_RIS_FRAME (1 << 0) -/**@}*/ - -/** - * DCMI interrupt enable register - * - * The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, - * the corresponding interrupt is enabled. This register is accessible in both read and write. - */ -#define DCMI_IER MMIO32(DCMI_BASE + 0x0CU) -/** - * @defgroup dcmi_ier_values DCMI_IER Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_IER_LINE (1 << 4) -#define DCMI_IER_VSYNC (1 << 3) -#define DCMI_IER_ERR (1 << 2) -#define DCMI_IER_OVR (1 << 1) -#define DCMI_IER_FRAME (1 << 0) -/**@}*/ - -/** - * DCMI masked interrupt status register - * - * This DCMI_MIS register is a read-only register. When read, it returns the current masked - * status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in - * this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding - * bit in DCMI_RIS is set. - */ -#define DCMI_MIS MMIO32(DCMI_BASE + 0x10U) -/** - * @defgroup dcmi_mis_values DCMI_MIS Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_MIS_LINE (1 << 4) -#define DCMI_MIS_VSYNC (1 << 3) -#define DCMI_MIS_ERR (1 << 2) -#define DCMI_MIS_OVR (1 << 1) -#define DCMI_MIS_FRAME (1 << 0) -/**@}*/ - -/** - * DCMI interrupt clear register - * - * The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the - * corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect. - */ -#define DCMI_ICR MMIO32(DCMI_BASE + 0x14U) -/** - * @defgroup dcmi_icr_values DCMI_ICR Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_ICR_LINE (1 << 4) -#define DCMI_ICR_VSYNC (1 << 3) -#define DCMI_ICR_ERR (1 << 2) -#define DCMI_ICR_OVR (1 << 1) -#define DCMI_ICR_FRAME (1 << 0) -/**@}*/ - -/** - * DCMI embedded synchronization code register - */ -#define DCMI_ESCR MMIO32(DCMI_BASE + 0x18U) -/** - * @defgroup dcmi_escr_values DCMI_ESCR Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_ESCR_FEC_SHIFT 24 -#define DCMI_ESCR_FEC_MASK 0xff -#define DCMI_ESCR_LEC_SHIFT 16 -#define DCMI_ESCR_LEC_MASK 0xff -#define DCMI_ESCR_LSC_SHIFT 8 -#define DCMI_ESCR_LSC_MASK 0xff -#define DCMI_ESCR_FSC_SHIFT 0 -#define DCMI_ESCR_FSC_MASK 0xff -/**@}*/ - - -/** - * DCMI embedded synchronization unmask register - */ -#define DCMI_ESUR MMIO32(DCMI_BASE + 0x1CU) -/** - * @defgroup dcmi_esur_values DCMI_ESUR Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_ESUR_FEU_SHIFT 24 -#define DCMI_ESUR_FEU_MASK 0xff -#define DCMI_ESUR_LEU_SHIFT 16 -#define DCMI_ESUR_LEU_MASK 0xff -#define DCMI_ESUR_LSU_SHIFT 8 -#define DCMI_ESUR_LSU_MASK 0xff -#define DCMI_ESUR_FSU_SHIFT 0 -#define DCMI_ESUR_FSU_MASK 0xff -/**@}*/ - -/** - * DCMI crop window start - */ -#define DCMI_CWSTRT MMIO32(DCMI_BASE + 0x20U) -/** - * @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_CWSTRT_VST_SHIFT 16 -#define DCMI_CWSTRT_VST_MASK 0x1fff -#define DCMI_CWSTRT_HOFFCNT_SHIFT 0 -#define DCMI_CWSTRT_HOFFCNT_MASK 0x3fff -/**@}*/ - -/** - * DCMI crop window size - */ -#define DCMI_CWSIZE MMIO32(DCMI_BASE + 0x24U) -/** - * @defgroup dcmi_cwsize_values DCMI_CWSIZE Values - * @ingroup dcmi_defines - * @{ - */ -#define DCMI_CWSIZE_VLINE_SHIFT 16 -#define DCMI_CWSIZE_VLINE_MASK 0x3fff -#define DCMI_CWSIZE_CAPCNT_SHIFT 0 -#define DCMI_CWSIZE_CAPCNT_MASK 0x3fff -/**@}*/ - -/** - * DCMI data register - * - * The digital camera Interface packages all the received data in 32-bit format before - * requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA - * transfers and avoid DMA overrun conditions. - */ -#define DCMI_DR MMIO32(DCMI_BASE + 0x28U) - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f4/dma.h b/libopencm3/include/libopencm3/stm32/f4/dma.h deleted file mode 100644 index 229c64c..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/dma.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dma_defines DMA Defines - -@ingroup STM32F4xx_defines - -@brief Defined Constants and Types for the STM32F4xx DMA Controller - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/dma2d.h b/libopencm3/include/libopencm3/stm32/f4/dma2d.h deleted file mode 100644 index 80c2359..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/dma2d.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dma2d_defines DMA2D Defines - * @brief Defined Constants and Types for the STM32F4xx DMA2D Peripheral - * @ingroup STM32F4xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F4_DMA2D_H_ -#define LIBOPENCM3_STM32_F4_DMA2D_H_ - -#include - -#endif /* LIBOPENCM3_STM32_F4_DMA2D_H_ */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h b/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h deleted file mode 100644 index 1c17a1f..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32F4 - -@version 1.0.0 - -@date 7 September 2012 - -API documentation for ST Microelectronics STM32F4 Cortex M4F series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F4xx STM32F4xx -Libraries for ST Microelectronics STM32F4xx series. - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32F4xx_defines STM32F4xx Defines - -@brief Defined Constants and Types for the STM32F4xx series - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/f4/dsi.h b/libopencm3/include/libopencm3/stm32/f4/dsi.h deleted file mode 100644 index dc8a639..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/dsi.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dsi_defines DSI Defines - * @brief Defines Constants and Macros for the STM32F4xx Display Serial - * Interface Host and Wrapper - * @ingroup STM32F4xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F4_DSI_H_ -#define LIBOPENCM3_STM32_F4_DSI_H_ - -#include - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f4/exti.h b/libopencm3/include/libopencm3/stm32/f4/exti.h deleted file mode 100644 index 8557dd7..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/exti.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F4xx External Interrupts - * - * - * @ingroup STM32F4xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Piotr Esden-Tempski - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/flash.h b/libopencm3/include/libopencm3/stm32/f4/flash.h deleted file mode 100644 index dafe839..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/flash.h +++ /dev/null @@ -1,47 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32F4xx_defines - * - * @brief Defined Constants and Types for the STM32F4xx FLASH Memory - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include -#include - -#define FLASH_SR_PGSERR (1 << 7) -#define FLASH_OPTCR_WDG_SW (1 << 5) - -BEGIN_DECLS - -void flash_clear_pgserr_flag(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/fmc.h b/libopencm3/include/libopencm3/stm32/f4/fmc.h deleted file mode 100644 index 920daa1..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/fmc.h +++ /dev/null @@ -1,35 +0,0 @@ -/** @defgroup fmc_defines FMC Defines - * @brief Defined Constants and Types for the STM32F4xx Flexible Memory - * Controller - * @ingroup STM32F4xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_F4_FMC_H -#define LIBOPENCM3_F4_FMC_H - -#ifndef LIBOPENCM3_FSMC_H -#error "This file should not be included directly, it is included with fsmc.h" -#endif - -#include - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f4/gpio.h b/libopencm3/include/libopencm3/stm32/f4/gpio.h deleted file mode 100644 index 696b88b..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/gpio.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32F4xx General Purpose I/O - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/hash.h b/libopencm3/include/libopencm3/stm32/f4/hash.h deleted file mode 100644 index a44b374..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/hash.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup hash_defines HASH Defines - -@ingroup STM32F4xx_defines - -@brief Defined Constants and Types for the STM32F4xx HASH Controller - -@version 1.0.0 - -@date 31 May 2013 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_HASH_H -#define LIBOPENCM3_HASH_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/i2c.h b/libopencm3/include/libopencm3/stm32/f4/i2c.h deleted file mode 100644 index a6b8de2..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/i2c.h +++ /dev/null @@ -1,65 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32F4xx I2C - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include -#include - -/** -@addtogroup i2c_defines -@{*/ - -/** FLTR register (I2Cx_FLTR) (noise filter) */ -#define I2C_FLTR(i2c_base) MMIO32((i2c_base) + 0x24) -#define I2C1_FLTR I2C_FLTR(I2C1) -#define I2C2_FLTR I2C_FLTR(I2C2) -#define I2C3_FLTR I2C_FLTR(I2C3) - -/** - * Bits [3:0] DNF - Digital noise filter - * These bits configure a digital noise filter on SDA and SCL pins. - * Value sets minimum pulse width needed to trigger i2c operations. - * 0 disables, 1 - 15 set minimum width to 'n' * TPCLK1 - */ -#define I2C_FLTR_DNF_MASK 0xF -#define I2C_FLTR_DNF_SHIFT 0 - -/** - * Bit 4 - Analog Noise filter disable - * Turns off the built in analog noise filter. - */ -#define I2C_FLTR_ANOFF (1<<4) - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/irq.json b/libopencm3/include/libopencm3/stm32/f4/irq.json deleted file mode 100644 index 9acf1dd..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/irq.json +++ /dev/null @@ -1,98 +0,0 @@ -{ - "irqs": [ - "nvic_wwdg", - "pvd", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_stream0", - "dma1_stream1", - "dma1_stream2", - "dma1_stream3", - "dma1_stream4", - "dma1_stream5", - "dma1_stream6", - "adc", - "can1_tx", - "can1_rx0", - "can1_rx1", - "can1_sce", - "exti9_5", - "tim1_brk_tim9", - "tim1_up_tim10", - "tim1_trg_com_tim11", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_fs_wkup", - "tim8_brk_tim12", - "tim8_up_tim13", - "tim8_trg_com_tim14", - "tim8_cc", - "dma1_stream7", - "fsmc", - "sdio", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dac", - "tim7", - "dma2_stream0", - "dma2_stream1", - "dma2_stream2", - "dma2_stream3", - "dma2_stream4", - "eth", - "eth_wkup", - "can2_tx", - "can2_rx0", - "can2_rx1", - "can2_sce", - "otg_fs", - "dma2_stream5", - "dma2_stream6", - "dma2_stream7", - "usart6", - "i2c3_ev", - "i2c3_er", - "otg_hs_ep1_out", - "otg_hs_ep1_in", - "otg_hs_wkup", - "otg_hs", - "dcmi", - "cryp", - "hash_rng", - "fpu", - "uart7", - "uart8", - "spi4", - "spi5", - "spi6", - "sai1", - "lcd_tft", - "lcd_tft_err", - "dma2d" - ], - "partname_humanreadable": "STM32 F4 series", - "partname_doxygen": "STM32F4", - "includeguard": "LIBOPENCM3_STM32_F4_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/f4/iwdg.h b/libopencm3/include/libopencm3/stm32/f4/iwdg.h deleted file mode 100644 index 12f3612..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/iwdg.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - -@brief Defined Constants and Types for the STM32F4xx Independent Watchdog -Timer - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/lptimer.h b/libopencm3/include/libopencm3/stm32/f4/lptimer.h deleted file mode 100644 index 97203ad..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/lptimer.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @defgroup lptimer_defines LPTIM Defines - * - * @ingroup STM32F4xx_defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F4xx Low Power Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPTIMER_H -#define LIBOPENCM3_LPTIMER_H -/**@{*/ - -#include - -/** @defgroup lptim_reg_base Low Power Timer register base addresses -@{*/ -#define LPTIM1 LPTIM1_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/ltdc.h b/libopencm3/include/libopencm3/stm32/f4/ltdc.h deleted file mode 100644 index 810772b..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/ltdc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup ltdc_defines LTDC Defines - * @brief Defined Constants and Types for the STM32F4xx LCD TFT Display - * Controller - * @ingroup STM32F4xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F4_LTDC_H_ -#define LIBOPENCM3_STM32_F4_LTDC_H_ - -#include - -#endif /* LIBOPENCM3_STM32_F4_LTDC_H_ */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f4/memorymap.h b/libopencm3/include/libopencm3/stm32/f4/memorymap.h deleted file mode 100644 index 6b96ac0..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/memorymap.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32F4 specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 0x50000000U -#define PERIPH_BASE_AHB3 0x60000000U - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) -#define FMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800) -#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) -/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ -#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) -#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) -/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) -#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) -/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ -#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) -/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400) -/* PERIPH_BASE_APB2 + 0x3500 (0x4001 3500 - 0x4001 37FF): Reserved */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) -/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */ -#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000) -#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400) -#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) -#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) -#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00) -/* PERIPH_BASE_APB2 + 0x7400 (0x4001 7400 - 0x4001 FFFF): Reserved */ - -/* AHB1 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) -#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) -#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400) -#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800) -/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */ -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) -#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) -/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) -/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) -#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U) -/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ -#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) -/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ - -/* AHB2 */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000) -/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ -#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) -/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ -#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) -/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */ -#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) -/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ - -/* AHB3 */ -/* Address: 0x60000000 */ -#define FMC_BANK1 (PERIPH_BASE_AHB3) -/* Address: 0x70000000 */ -#define FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U) -/* Address: 0x80000000 */ -#define FMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U) -/* Address: 0x90000000 */ -#define QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U) -#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) -#define FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) -#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U) -/* Address: 0xC0000000 */ -#define FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U) -/* Address: 0xD0000000 */ -#define FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) -#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - -/* ST provided factory calibration values @ 3.3V */ -#define ST_VREFINT_CAL MMIO16(0x1FFF7A2A) -#define ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C) -#define ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/pwr.h b/libopencm3/include/libopencm3/stm32/f4/pwr.h deleted file mode 100644 index 63f1015..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/pwr.h +++ /dev/null @@ -1,88 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32F4xx Power Control - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2011 Stephen Caudle - -@date 4 March 2013 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -/* - * This file extends the common STM32 version with definitions only - * applicable to the STM32F4 series of devices. - */ - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* Bits [31:16]: Reserved */ - -/* VOS: Regulator voltage scaling output selection */ -#define PWR_CR_VOS_SHIFT 14 -#define PWR_CR_VOS_MASK 0x3 - -/* Bits [13:10]: Reserved */ - -/* FPDS: Flash power down in stop mode */ -#define PWR_CR_FPDS (1 << 9) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* Bits [31:15]: Reserved */ - -/* VOSRDY: Regulator voltage scaling output selection ready bit */ -#define PWR_CSR_VOSRDY (1 << 14) - -/* Bits [13:10]: Reserved */ - -/* BRE: Backup regulator enable */ -#define PWR_CSR_BRE (1 << 9) - -/* Bits [7:4]: Reserved */ - -/* BRR: Backup regulator ready */ -#define PWR_CSR_BRR (1 << 3) - -/* --- Function prototypes ------------------------------------------------- */ - -enum pwr_vos_scale { - PWR_SCALE1 = 0x3, - PWR_SCALE2 = 0x2, - PWR_SCALE3 = 0x1, -}; - -BEGIN_DECLS - -void pwr_set_vos_scale(enum pwr_vos_scale scale); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/quadspi.h b/libopencm3/include/libopencm3/stm32/f4/quadspi.h deleted file mode 100644 index 2808f02..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/quadspi.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * STM32F4 Quad SPI defines - * - * Copyright (C) 2016, Chuck McManis - * - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -#include - -/* QUADSPI Control register */ -#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U) - -#define QUADSPI_CR_PRESCALE_MASK 0xff -#define QUADSPI_CR_PRESCALE_SHIFT 24 -#define QUADSPI_CR_PMM (1 << 23) -#define QUADSPI_CR_APMS (1 << 22) -/* bit 21 is reserved */ -#define QUADSPI_CR_TOIE (1 << 20) -#define QUADSPI_CR_SMIE (1 << 19) -#define QUADSPI_CR_FTIE (1 << 18) -#define QUADSPI_CR_TCIE (1 << 17) -#define QUADSPI_CR_TEIE (1 << 16) - -/* bits 15:13 reserved */ -#define QUADSPI_CR_FTHRES_MASK 0x1f -#define QUADSPI_CR_FTHRES_SHIFT 8 -#define QUADSPI_CR_FSEL (1 << 7) -#define QUADSPI_CR_DFM (1 << 6) -/* bit 5 reserved */ -#define QUADSPI_CR_SSHIFT (1 << 4) -#define QUADSPI_CR_TCEN (1 << 3) -#define QUADSPI_CR_DMAEN (1 << 2) -#define QUADSPI_CR_ABORT (1 << 1) -#define QUADSPI_CR_EN (1 << 0) - -/* QUADSPI Device Configuration */ -#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U) - -/* bits 31:21 reserved */ -#define QUADSPI_DCR_FSIZE_MASK 0x1f -#define QUADSPI_DCR_FSIZE_SHIFT 16 -/* bits 15:11 reserved */ -#define QUADSPI_DCR_CSHT_MASK 0x7 -#define QUADSPI_DCR_CSHT_SHIFT 8 -/* bits 7:1 reserved */ -#define QUADSPI_DCR_CKMODE (1 << 0) - -/* QUADSPI Status Register */ -#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U) - -/* bits 31:14 reserved */ -#define QUADSPI_SR_FLEVEL_MASK 0x3f -#define QUADSPI_SR_FLEVEL_SHIFT 8 - -/* bits 7:6 reserved */ -#define QUADSPI_SR_BUSY (1 << 5) -#define QUADSPI_SR_TOF (1 << 4) -#define QUADSPI_SR_SMF (1 << 3) -#define QUADSPI_SR_FTF (1 << 2) -#define QUADSPI_SR_TCF (1 << 1) -#define QUADSPI_SR_TEF (1 << 0) - -/* QUADSPI Flag Clear Register */ -#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU) - -/* bits 31:5 reserved */ -#define QUADSPI_FCR_CTOF (1 << 4) -#define QUADSPI_FCR_CSMF (1 << 3) -/* bit 2 reserved */ -#define QUADSPI_FCR_CTCF (1 << 1) -#define QUADSPI_FCR_CTEF (1 << 0) - -/* QUADSPI Data Length Register */ -#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U) - -/* QUADSPI Communication Configuration Register */ -#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U) - -#define QUADSPI_CCR_DDRM (1 << 31) -#define QUADSPI_CCR_DHHC (1 << 30) -/* bit 29 reserved */ -#define QUADSPI_CCR_SIOO (1 << 28) -#define QUADSPI_CCR_FMODE_MASK 0x3 -#define QUADSPI_CCR_FMODE_SHIFT 26 -#define QUADSPI_CCR_DMODE_MASK 0x3 -#define QUADSPI_CCR_DMODE_SHIFT 24 -/* bit 23 reserved */ -#define QUADSPI_CCR_DCYC_MASK 0x1f -#define QUADSPI_CCR_DCYC_SHIFT 18 - -#define QUADSPI_CCR_ABSIZE_MASK 0x3 -#define QUADSPI_CCR_ABSIZE_SHIFT 16 - -#define QUADSPI_CCR_ABMODE_MASK 0x3 -#define QUADSPI_CCR_ABMODE_SHIFT 14 - -#define QUADSPI_CCR_ADSIZE_MASK 0x3 -#define QUADSPI_CCR_ADSIZE_SHIFT 12 - -#define QUADSPI_CCR_ADMODE_MASK 0x3 -#define QUADSPI_CCR_ADMODE_SHIFT 10 - -#define QUADSPI_CCR_IMODE_MASK 0x3 -#define QUADSPI_CCR_IMODE_SHIFT 8 - -#define QUADSPI_CCR_INST_MASK 0xff -#define QUADSPI_CCR_INST_SHIFT 0 - -/* MODE values */ -#define QUADSPI_CCR_MODE_NONE 0 -#define QUADSPI_CCR_MODE_1LINE 1 -#define QUADSPI_CCR_MODE_2LINE 2 -#define QUADSPI_CCR_MODE_4LINE 3 - -/* FMODE values */ -#define QUADSPI_CCR_FMODE_IWRITE 0 -#define QUADSPI_CCR_FMODE_IREAD 1 -#define QUADSPI_CCR_FMODE_APOLL 2 -#define QUADSPI_CCR_FMODE_MEMMAP 3 - - -/* QUADSPI address register */ -#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U) - -/* QUADSPI alternate bytes register */ -#define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU) - -/* QUADSPI data register */ -#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U) -/* BYTE addressable version for fetching bytes from the interface */ -#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U) - -/* QUADSPI polling status */ -#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U) - -/* QUADSPI polling status match */ -#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U) - -/* QUADSPI polling interval register */ -#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU) - -/* QUADSPI low power timeout */ -#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U) - diff --git a/libopencm3/include/libopencm3/stm32/f4/rcc.h b/libopencm3/include/libopencm3/stm32/f4/rcc.h deleted file mode 100644 index 8e39f06..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/rcc.h +++ /dev/null @@ -1,1106 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F4xx Reset and Clock - * Control - * - * @ingroup STM32F4xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2011 - * Stephen Caudle - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include - -/** @defgroup rcc_registers RCC Registers - * @brief Reset / Clock Control Registers -@{*/ -/** Clock control register */ -#define RCC_CR MMIO32(RCC_BASE + 0x00) -/** PLL Configuration register */ -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) -/** Clock Configuration register */ -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -/** Clock interrupt register */ -#define RCC_CIR MMIO32(RCC_BASE + 0x0c) -/** AHB1 peripheral reset register */ -#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) -/** AHB2 peripheral reset register */ -#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) -/** AHB3 peripheral reset register */ -#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) -/* RCC_BASE + 0x1c Reserved */ -/** APB1 peripheral reset register */ -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) -/** APB2 peripheral reset register */ -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) -/* RCC_BASE + 0x28 Reserved */ -/* RCC_BASE + 0x2c Reserved */ -/** AHB1 peripheral enable register */ -#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) -/** AHB2 peripheral enable register */ -#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) -/** AHB3 peripheral enable register */ -#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) -/* RCC_BASE + 0x3c Reserved */ -/** APB1 peripheral enable register */ -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) -/** APB2 peripheral enable register */ -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) -/* RCC_BASE + 0x48 Reserved */ -/* RCC_BASE + 0x4c Reserved */ -/** AHB1 peripheral enable in low power register */ -#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) -/** AHB2 peripheral enable in low power register */ -#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) -/** AHB3 peripheral enable in low power register */ -#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) -/* RCC_BASE + 0x5c Reserved */ -/** APB1 peripheral enable in low power register */ -#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) -/** APB2 peripheral enable in low power register */ -#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) -/* RCC_BASE + 0x68 Reserved */ -/* RCC_BASE + 0x6c Reserved */ -/** Backup Domain control register */ -#define RCC_BDCR MMIO32(RCC_BASE + 0x70) -/** Clock control and status register */ -#define RCC_CSR MMIO32(RCC_BASE + 0x74) -/* RCC_BASE + 0x78 Reserved */ -/* RCC_BASE + 0x7c Reserved */ -/** Spread spectrum clock generation register */ -#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) -/** PLLI2S configuration register */ -#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) -/** PLLSAI configuration register */ -#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) -/** Dedicated clocks configuration register */ -#define RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C) -/** RCC clocks gated enable register */ -#define RCC_CKGATENR MMIO32(RCC_BASE + 0x90) -/** RCC Dedicated Clocks Configuration Register 2 */ -#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94) -/**@}*/ - -/** @defgroup rcc_cr_values RCC_CR values - * @ingroup rcc_registers - * @brief Clock Control register values -@{*/ -#define RCC_CR_PLLSAIRDY (1 << 29) -#define RCC_CR_PLLSAION (1 << 28) -#define RCC_CR_PLLI2SRDY (1 << 27) -#define RCC_CR_PLLI2SON (1 << 26) -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSITRIM_SHIFT 3 -#define RCC_CR_HSITRIM_MASK 0x1f -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) -/**@}*/ - -/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR values - * @ingroup rcc_registers - * @brief PLL Configuration register values -@{*/ -/* PLLR: [30:28] */ -#define RCC_PLLCFGR_PLLR_SHIFT 28 -#define RCC_PLLCFGR_PLLR_MASK 0x7 -/* PLLQ: [27:24] */ -#define RCC_PLLCFGR_PLLQ_SHIFT 24 -#define RCC_PLLCFGR_PLLQ_MASK 0xf -#define RCC_PLLCFGR_PLLSRC (1 << 22) -/* PLLP: [17:16] */ -#define RCC_PLLCFGR_PLLP_SHIFT 16 -#define RCC_PLLCFGR_PLLP_MASK 0x3 -/* PLLN: [14:6] */ -#define RCC_PLLCFGR_PLLN_SHIFT 6 -#define RCC_PLLCFGR_PLLN_MASK 0x1ff -/* PLLM: [5:0] */ -#define RCC_PLLCFGR_PLLM_SHIFT 0 -#define RCC_PLLCFGR_PLLM_MASK 0x3f -/**@}*/ - -/** @defgroup rcc_cfgr_values RCC_CFGR values - * @ingroup rcc_registers - * @brief Clock Configuration register values -@{*/ -/* MCO2: Microcontroller clock output 2 */ -#define RCC_CFGR_MCO2_SHIFT 30 -#define RCC_CFGR_MCO2_MASK 0x3 -#define RCC_CFGR_MCO2_SYSCLK 0x0 -#define RCC_CFGR_MCO2_PLLI2S 0x1 -#define RCC_CFGR_MCO2_HSE 0x2 -#define RCC_CFGR_MCO2_PLL 0x3 - -/* MCO1/2PRE: MCO Prescalers */ -#define RCC_CFGR_MCO2PRE_SHIFT 27 -#define RCC_CFGR_MCO2PRE_MASK 0x7 -#define RCC_CFGR_MCO1PRE_SHIFT 24 -#define RCC_CFGR_MCO1PRE_MASK 0x7 -#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 -#define RCC_CFGR_MCOPRE_DIV_2 0x4 -#define RCC_CFGR_MCOPRE_DIV_3 0x5 -#define RCC_CFGR_MCOPRE_DIV_4 0x6 -#define RCC_CFGR_MCOPRE_DIV_5 0x7 - -/* PLLSRC: PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI_CLK 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 - -/* I2SSRC: I2S clock selection */ -#define RCC_CFGR_I2SSRC (1 << 23) - -/* MCO1: Microcontroller clock output 1 */ -#define RCC_CFGR_MCO1_SHIFT 21 -#define RCC_CFGR_MCO1_MASK 0x3 -#define RCC_CFGR_MCO1_HSI 0x0 -#define RCC_CFGR_MCO1_LSE 0x1 -#define RCC_CFGR_MCO1_HSE 0x2 -#define RCC_CFGR_MCO1_PLL 0x3 -#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT -#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK - -/* RTCPRE: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_SHIFT 16 -#define RCC_CFGR_RTCPRE_MASK 0x1f - -/* PPRE1/2: APB high-speed prescalers */ -#define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 - -/* HPRE: AHB high-speed prescaler */ -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLL 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 -/**@}*/ - -/** @defgroup rcc_cir_values RCC_CIR values - * @ingroup rcc_registers - * @brief Clock Interrupt register values -@{*/ -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLLSAIRDYC (1 << 22) -#define RCC_CIR_PLLI2SRDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLLSAIRDYIE (1 << 14) -#define RCC_CIR_PLLI2SRDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLLSAIRDYF (1 << 6) -#define RCC_CIR_PLLI2SRDYF (1 << 5) -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values -@{*/ -#define RCC_AHB1RSTR_OTGHSRST (1 << 29) -#define RCC_AHB1RSTR_ETHMACRST (1 << 25) -#define RCC_AHB1RSTR_DMA2DRST (1 << 23) -#define RCC_AHB1RSTR_DMA2RST (1 << 22) -#define RCC_AHB1RSTR_DMA1RST (1 << 21) -#define RCC_AHB1RSTR_CRCRST (1 << 12) -#define RCC_AHB1RSTR_GPIOKRST (1 << 10) -#define RCC_AHB1RSTR_GPIOJRST (1 << 9) -#define RCC_AHB1RSTR_GPIOIRST (1 << 8) -#define RCC_AHB1RSTR_GPIOHRST (1 << 7) -#define RCC_AHB1RSTR_GPIOGRST (1 << 6) -#define RCC_AHB1RSTR_GPIOFRST (1 << 5) -#define RCC_AHB1RSTR_GPIOERST (1 << 4) -#define RCC_AHB1RSTR_GPIODRST (1 << 3) -#define RCC_AHB1RSTR_GPIOCRST (1 << 2) -#define RCC_AHB1RSTR_GPIOBRST (1 << 1) -#define RCC_AHB1RSTR_GPIOARST (1 << 0) -/**@}*/ - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxRST with zzz_GPIOxRST - * @{ - */ -#define RCC_AHB1RSTR_IOPKRST RCC_AHB1RSTR_GPIOKRST -#define RCC_AHB1RSTR_IOPJRST RCC_AHB1RSTR_GPIOJRST -#define RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST -#define RCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRST -#define RCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRST -#define RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRST -#define RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERST -#define RCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRST -#define RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRST -#define RCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRST -#define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST -/**@}*/ - -/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values -@{*/ -#define RCC_AHB2RSTR_OTGFSRST (1 << 7) -#define RCC_AHB2RSTR_RNGRST (1 << 6) -#define RCC_AHB2RSTR_HASHRST (1 << 5) -#define RCC_AHB2RSTR_CRYPRST (1 << 4) -#define RCC_AHB2RSTR_DCMIRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values -@{*/ -#define RCC_AHB3RSTR_QSPIRST (1 << 1) -#define RCC_AHB3RSTR_FSMCRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_UART8RST (1 << 31) -#define RCC_APB1RSTR_UART7RST (1 << 30) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_CAN2RST (1 << 26) -#define RCC_APB1RSTR_CAN1RST (1 << 25) -#define RCC_APB1RSTR_I2C3RST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM14RST (1 << 8) -#define RCC_APB1RSTR_TIM13RST (1 << 7) -#define RCC_APB1RSTR_TIM12RST (1 << 6) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_DSIRST (1 << 27) -#define RCC_APB2RSTR_LTDCRST (1 << 26) -#define RCC_APB2RSTR_SAI1RST (1 << 22) -#define RCC_APB2RSTR_SPI6RST (1 << 21) -#define RCC_APB2RSTR_SPI5RST (1 << 20) -#define RCC_APB2RSTR_TIM11RST (1 << 18) -#define RCC_APB2RSTR_TIM10RST (1 << 17) -#define RCC_APB2RSTR_TIM9RST (1 << 16) -#define RCC_APB2RSTR_SYSCFGRST (1 << 14) -#define RCC_APB2RSTR_SPI4RST (1 << 13) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_SDIORST (1 << 11) -#define RCC_APB2RSTR_ADCRST (1 << 8) -#define RCC_APB2RSTR_USART6RST (1 << 5) -#define RCC_APB2RSTR_USART1RST (1 << 4) -#define RCC_APB2RSTR_TIM8RST (1 << 1) -#define RCC_APB2RSTR_TIM1RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) -@{*/ -/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values -@{*/ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) -#define RCC_AHB1ENR_OTGHSEN (1 << 29) -#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) -#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) -#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) -#define RCC_AHB1ENR_ETHMACEN (1 << 25) -#define RCC_AHB1ENR_DMA2DEN (1 << 23) -#define RCC_AHB1ENR_DMA2EN (1 << 22) -#define RCC_AHB1ENR_DMA1EN (1 << 21) -#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) -#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) -#define RCC_AHB1ENR_CRCEN (1 << 12) -#define RCC_AHB1ENR_GPIOKEN (1 << 10) -#define RCC_AHB1ENR_GPIOJEN (1 << 9) -#define RCC_AHB1ENR_GPIOIEN (1 << 8) -#define RCC_AHB1ENR_GPIOHEN (1 << 7) -#define RCC_AHB1ENR_GPIOGEN (1 << 6) -#define RCC_AHB1ENR_GPIOFEN (1 << 5) -#define RCC_AHB1ENR_GPIOEEN (1 << 4) -#define RCC_AHB1ENR_GPIODEN (1 << 3) -#define RCC_AHB1ENR_GPIOCEN (1 << 2) -#define RCC_AHB1ENR_GPIOBEN (1 << 1) -#define RCC_AHB1ENR_GPIOAEN (1 << 0) -/**@}*/ - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxEN with zzz_GPIOxEN - * @{ - */ -#define RCC_AHB1ENR_IOPKEN RCC_AHB1ENR_GPIOKEN -#define RCC_AHB1ENR_IOPJEN RCC_AHB1ENR_GPIOJEN -#define RCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIEN -#define RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHEN -#define RCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGEN -#define RCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFEN -#define RCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEEN -#define RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODEN -#define RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCEN -#define RCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBEN -#define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN -/**@}*/ - -/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values -@{*/ -#define RCC_AHB2ENR_OTGFSEN (1 << 7) -#define RCC_AHB2ENR_RNGEN (1 << 6) -#define RCC_AHB2ENR_HASHEN (1 << 5) -#define RCC_AHB2ENR_CRYPEN (1 << 4) -#define RCC_AHB2ENR_DCMIEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values -@{*/ -#define RCC_AHB3ENR_QSPIEN (1 << 1) -#define RCC_AHB3ENR_FSMCEN (1 << 0) -/* Alternate now that F429 has DRAM controller as well */ -#define RCC_AHB3ENR_FMCEN (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_UART8EN (1 << 31) -#define RCC_APB1ENR_UART7EN (1 << 30) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_CAN2EN (1 << 26) -#define RCC_APB1ENR_CAN1EN (1 << 25) -#define RCC_APB1ENR_I2C3EN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM14EN (1 << 8) -#define RCC_APB1ENR_TIM13EN (1 << 7) -#define RCC_APB1ENR_TIM12EN (1 << 6) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@{*/ -#define RCC_APB2ENR_DSIEN (1 << 27) -#define RCC_APB2ENR_LTDCEN (1 << 26) -#define RCC_APB2ENR_SAI1EN (1 << 22) -#define RCC_APB2ENR_SPI6EN (1 << 21) -#define RCC_APB2ENR_SPI5EN (1 << 20) -#define RCC_APB2ENR_TIM11EN (1 << 18) -#define RCC_APB2ENR_TIM10EN (1 << 17) -#define RCC_APB2ENR_TIM9EN (1 << 16) -#define RCC_APB2ENR_SYSCFGEN (1 << 14) -#define RCC_APB2ENR_SPI4EN (1 << 13) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_SDIOEN (1 << 11) -#define RCC_APB2ENR_ADC3EN (1 << 10) -#define RCC_APB2ENR_ADC2EN (1 << 9) -#define RCC_APB2ENR_ADC1EN (1 << 8) -#define RCC_APB2ENR_USART6EN (1 << 5) -#define RCC_APB2ENR_USART1EN (1 << 4) -#define RCC_APB2ENR_TIM8EN (1 << 1) -#define RCC_APB2ENR_TIM1EN (1 << 0) -/**@}*/ - -/* --- RCC_AHB1LPENR values ------------------------------------------------- */ - -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) -#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) -#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) -#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) -#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) -#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) -#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) -#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) -#define RCC_AHB1LPENR_SRAM3LPEN (1 << 19) -#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) -#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) -#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) -#define RCC_AHB1LPENR_CRCLPEN (1 << 12) -#define RCC_AHB1LPENR_GPIOKLPEN (1 << 10) -#define RCC_AHB1LPENR_GPIOJLPEN (1 << 9) -#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) -#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) -#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) -#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) -#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) -#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) -#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) -#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) -#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) - -/** @addtogroup deprecated_201802_rcc Deprecated 2018 - * @deprecated replace zzz_IOPxLPEN with zzz_GPIOxLPEN - * @{ - */ -#define RCC_AHB1LPENR_IOPKLPEN RCC_AHB1LPENR_GPIOKLPEN -#define RCC_AHB1LPENR_IOPJLPEN RCC_AHB1LPENR_GPIOJLPEN -#define RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPEN -#define RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPEN -#define RCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN -#define RCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN -#define RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPEN -#define RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPEN -#define RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPEN -#define RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPEN -#define RCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPEN -/**@}*/ - -/* --- RCC_AHB2LPENR values ------------------------------------------------- */ - -#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) -#define RCC_AHB2LPENR_RNGLPEN (1 << 6) -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) -#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) -#define RCC_AHB2LPENR_DCMILPEN (1 << 0) - -/* --- RCC_AHB3LPENR values ------------------------------------------------- */ - -#define RCC_AHB3LPENR_QSPIEN (1 << 1) -#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) -#define RCC_AHB3LPENR_FMCLPEN (1 << 0) - -/* --- RCC_APB1LPENR values ------------------------------------------------- */ - -/** @defgroup rcc_apblpenr_en RCC_APBxLPENR enable values (full set) -@{*/ -#define RCC_APB1LPENR_UART8EN (1 << 31) -#define RCC_APB1LPENR_UART7EN (1 << 30) -#define RCC_APB1LPENR_DACLPEN (1 << 29) -#define RCC_APB1LPENR_PWRLPEN (1 << 28) -#define RCC_APB1LPENR_CAN2LPEN (1 << 26) -#define RCC_APB1LPENR_CAN1LPEN (1 << 25) -#define RCC_APB1LPENR_I2C3LPEN (1 << 23) -#define RCC_APB1LPENR_I2C2LPEN (1 << 22) -#define RCC_APB1LPENR_I2C1LPEN (1 << 21) -#define RCC_APB1LPENR_UART5LPEN (1 << 20) -#define RCC_APB1LPENR_UART4LPEN (1 << 19) -#define RCC_APB1LPENR_USART3LPEN (1 << 18) -#define RCC_APB1LPENR_USART2LPEN (1 << 17) -#define RCC_APB1LPENR_SPI3LPEN (1 << 15) -#define RCC_APB1LPENR_SPI2LPEN (1 << 14) -#define RCC_APB1LPENR_WWDGLPEN (1 << 11) -#define RCC_APB1LPENR_TIM14LPEN (1 << 8) -#define RCC_APB1LPENR_TIM13LPEN (1 << 7) -#define RCC_APB1LPENR_TIM12LPEN (1 << 6) -#define RCC_APB1LPENR_TIM7LPEN (1 << 5) -#define RCC_APB1LPENR_TIM6LPEN (1 << 4) -#define RCC_APB1LPENR_TIM5LPEN (1 << 3) -#define RCC_APB1LPENR_TIM4LPEN (1 << 2) -#define RCC_APB1LPENR_TIM3LPEN (1 << 1) -#define RCC_APB1LPENR_TIM2LPEN (1 << 0) - -/* --- RCC_APB2LPENR values ------------------------------------------------- */ - -#define RCC_APB2LPENR_DSILPEN (1 << 27) -#define RCC_APB2LPENR_LTDCLPEN (1 << 26) -#define RCC_APB2LPENR_SAI1LPEN (1 << 22) -#define RCC_APB2LPENR_SPI6LPEN (1 << 21) -#define RCC_APB2LPENR_SPI5LPEN (1 << 20) -#define RCC_APB2LPENR_TIM11LPEN (1 << 18) -#define RCC_APB2LPENR_TIM10LPEN (1 << 17) -#define RCC_APB2LPENR_TIM9LPEN (1 << 16) -#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) -#define RCC_APB2LPENR_SDIOLPEN (1 << 11) -#define RCC_APB2LPENR_ADC3LPEN (1 << 10) -#define RCC_APB2LPENR_ADC2LPEN (1 << 9) -#define RCC_APB2LPENR_ADC1LPEN (1 << 8) -#define RCC_APB2LPENR_USART6LPEN (1 << 5) -#define RCC_APB2LPENR_USART1LPEN (1 << 4) -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_bdcr_values RCC_BDCR values - * @ingroup rcc_registers - * @brief Backup Domain control register values -@{*/ -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_MASK 0x3 -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSE 3 -#define RCC_BDCR_LSEMOD (1 << 3) -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) -/**@}*/ - -/** @defgroup rcc_csr_values RCC_CSR values - * @ingroup rcc_registers - * @brief Clock control and status register values -@{*/ -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_BORRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_BORRSTF) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) -/**@}*/ - -/** @defgroup rcc_sscgr_values RCC_SSCGR values - * @ingroup rcc_registers - * @brief Spread spectrum clock generation register values -@{*/ -/* PLL spread spectrum clock generation documented in Datasheet. */ - -#define RCC_SSCGR_SSCGEN (1 << 31) -#define RCC_SSCGR_SPREADSEL (1 << 30) -/* RCC_SSCGR[27:13]: INCSTEP */ -#define RCC_SSCGR_INCSTEP_SHIFT 13 -#define RCC_SSCGR_INCSTEP_MASK 0x7fff -/* RCC_SSCGR[15:0]: MODPER */ -#define RCC_SSCGR_MODPER_SHIFT 0 -#define RCC_SSCGR_MODPER_MASK 0x1fff -/**@}*/ - -/** @defgroup rcc_pllded_values RCC_PLLxxx/DCKy values - * @ingroup rcc_registers - * @brief PLL and other dedicated clock register values -@{*/ -/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ - -/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ -#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 -#define RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7 -/* RCC_PLLI2SCFGR[27:24] PLLI2SQ */ -#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24 -#define RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf -/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ -#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 -#define RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff - -/* --- RCC_PLLSAICFGR values ----------------------------------------------- */ - -/* RCC_PLLSAICFGR[30:28]: PLLSAIR */ -#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 -#define RCC_PLLSAICFGR_PLLSAIR_MASK 0x7 - -/* RCC_PLLSAICFGR[27:24]: PLLSAIQ */ -#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24 -#define RCC_PLLSAICFGR_PLLSAIQ_MASK 0xF - -/* RCC_PLLSAICFGR[18:16]: PLLSAIP */ -#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 -#define RCC_PLLSAICFGR_PLLSAIP_MASK 0x3 -/** @defgroup rcc_pllsaicfgr_pllsaip PLLSAICFGR PLLSAIP values -@ingroup rcc_defines -@{*/ -#define RCC_PLLSAICFGR_PLLSAIP_DIV2 0x0 -#define RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1 -#define RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2 -#define RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3 -/**@}*/ - -/* RCC_PLLSAICFGR[14:6]: PLLSAIN */ -#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 -#define RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF - - -/* --- RCC_DCKCFGR values -------------------------------------------------- */ -#define RCC_DCKCFGR_DSISEL (1 << 29) -#define RCC_DCKCFGR_SDMMCSEL (1 << 28) -#define RCC_DCKCFGR_48MSEL (1 << 27) -#define RCC_DCKCFGR_TIMPRE (1 << 24) - -#define RCC_DCKCFGR_SAI1BSRC_SHIFT 22 -#define RCC_DCKCFGR_SAI1BSRC_MASK 0x3 - -#define RCC_DCKCFGR_SAI1ASRC_SHIFT 20 -#define RCC_DCKCFGR_SAI1ASRC_MASK 0x3 - -/* Values for the BSRC and ASRC fields */ -#define RCC_DCKCFGR_SAI1SRC_SAIQ 0x0 -#define RCC_DCKCFGR_SAI1SRC_I2SQ 0x1 -#define RCC_DCKCFGR_SAI1SRC_ALT 0x2 -#define RCC_DCKCFGR_SAI1SRC_ERROR 0x3 - -#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16 -#define RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3 -#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0 -#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1 -#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2 -#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3 - -#define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8 -#define RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f - -#define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0 -#define RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f -/**@}*/ - -/** @defgroup rcc_ckgatenr_values RCC_CKGATENR bits - * @ingroup rcc_registers - * @brief Allows to enable or disable the clock gating for the specified IPs. -@{*/ -#define RCC_CKGATENR_EVTCL_CKEN (1<<7) -#define RCC_CKGATENR_RCC_CKEN (1<<6) -#define RCC_CKGATENR_FLITF_CKEN (1<<5) -#define RCC_CKGATENR_SRAM_CKEN (1<<4) -#define RCC_CKGATENR_SPARE_CKEN (1<<3) -#define RCC_CKGATENR_CM4DBG_CKEN (1<<2) -#define RCC_CKGATENR_AHB2APB2_CKEN (1<<1) -#define RCC_CKGATENR_AHB2APB1_CKEN (1<<0) -/**@}*/ - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_clock_3v3 { - RCC_CLOCK_3V3_84MHZ, - RCC_CLOCK_3V3_168MHZ, - RCC_CLOCK_3V3_180MHZ, - RCC_CLOCK_3V3_END -}; - -struct rcc_clock_scale { - uint8_t pllm; - uint16_t plln; - uint8_t pllp; - uint8_t pllq; - uint8_t pllr; - uint8_t pll_source; - uint32_t flash_config; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - enum pwr_vos_scale voltage_scale; - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; -}; - -extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]; -extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; -extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]; -extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]; -extern const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END]; - -enum rcc_osc { - RCC_PLL, - RCC_PLLSAI, - RCC_PLLI2S, - RCC_HSE, - RCC_HSI, - RCC_LSE, - RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB1 peripherals*/ - RCC_GPIOA = _REG_BIT(0x30, 0), - RCC_GPIOB = _REG_BIT(0x30, 1), - RCC_GPIOC = _REG_BIT(0x30, 2), - RCC_GPIOD = _REG_BIT(0x30, 3), - RCC_GPIOE = _REG_BIT(0x30, 4), - RCC_GPIOF = _REG_BIT(0x30, 5), - RCC_GPIOG = _REG_BIT(0x30, 6), - RCC_GPIOH = _REG_BIT(0x30, 7), - RCC_GPIOI = _REG_BIT(0x30, 8), - RCC_GPIOJ = _REG_BIT(0x30, 9), - RCC_GPIOK = _REG_BIT(0x30, 10), - RCC_CRC = _REG_BIT(0x30, 12), - RCC_BKPSRAM = _REG_BIT(0x30, 18), - RCC_CCMDATARAM = _REG_BIT(0x30, 20), - RCC_DMA1 = _REG_BIT(0x30, 21), - RCC_DMA2 = _REG_BIT(0x30, 22), - RCC_DMA2D = _REG_BIT(0x30, 23), - RCC_ETHMAC = _REG_BIT(0x30, 25), - RCC_ETHMACTX = _REG_BIT(0x30, 26), - RCC_ETHMACRX = _REG_BIT(0x30, 27), - RCC_ETHMACPTP = _REG_BIT(0x30, 28), - RCC_OTGHS = _REG_BIT(0x30, 29), - RCC_OTGHSULPI = _REG_BIT(0x30, 30), - - /* AHB2 peripherals */ - RCC_DCMI = _REG_BIT(0x34, 0), - RCC_CRYP = _REG_BIT(0x34, 4), - RCC_HASH = _REG_BIT(0x34, 5), - RCC_RNG = _REG_BIT(0x34, 6), - RCC_OTGFS = _REG_BIT(0x34, 7), - - /* AHB3 peripherals */ - RCC_FSMC = _REG_BIT(0x38, 0), - RCC_FMC = _REG_BIT(0x38, 0), - RCC_QUADSPI = _REG_BIT(0x38, 1), - - /* APB1 peripherals*/ - RCC_TIM2 = _REG_BIT(0x40, 0), - RCC_TIM3 = _REG_BIT(0x40, 1), - RCC_TIM4 = _REG_BIT(0x40, 2), - RCC_TIM5 = _REG_BIT(0x40, 3), - RCC_TIM6 = _REG_BIT(0x40, 4), - RCC_TIM7 = _REG_BIT(0x40, 5), - RCC_TIM12 = _REG_BIT(0x40, 6), - RCC_TIM13 = _REG_BIT(0x40, 7), - RCC_TIM14 = _REG_BIT(0x40, 8), - RCC_WWDG = _REG_BIT(0x40, 11), - RCC_SPI2 = _REG_BIT(0x40, 14), - RCC_SPI3 = _REG_BIT(0x40, 15), - RCC_USART2 = _REG_BIT(0x40, 17), - RCC_USART3 = _REG_BIT(0x40, 18), - RCC_UART4 = _REG_BIT(0x40, 19), - RCC_UART5 = _REG_BIT(0x40, 20), - RCC_I2C1 = _REG_BIT(0x40, 21), - RCC_I2C2 = _REG_BIT(0x40, 22), - RCC_I2C3 = _REG_BIT(0x40, 23), - RCC_CAN1 = _REG_BIT(0x40, 25), - RCC_CAN2 = _REG_BIT(0x40, 26), - RCC_PWR = _REG_BIT(0x40, 28), - RCC_DAC = _REG_BIT(0x40, 29), - RCC_UART7 = _REG_BIT(0x40, 30),/* F2xx, F3xx */ - RCC_UART8 = _REG_BIT(0x40, 31),/* F2xx, F3xx */ - - /* APB2 peripherals */ - RCC_TIM1 = _REG_BIT(0x44, 0), - RCC_TIM8 = _REG_BIT(0x44, 1), - RCC_USART1 = _REG_BIT(0x44, 4), - RCC_USART6 = _REG_BIT(0x44, 5), - RCC_ADC1 = _REG_BIT(0x44, 8), - RCC_ADC2 = _REG_BIT(0x44, 9), - RCC_ADC3 = _REG_BIT(0x44, 10), - RCC_SDIO = _REG_BIT(0x44, 11), - RCC_SPI1 = _REG_BIT(0x44, 12), - RCC_SPI4 = _REG_BIT(0x44, 13),/* F2xx, F3xx */ - RCC_SYSCFG = _REG_BIT(0x44, 14), - RCC_TIM9 = _REG_BIT(0x44, 16), - RCC_TIM10 = _REG_BIT(0x44, 17), - RCC_TIM11 = _REG_BIT(0x44, 18), - RCC_SPI5 = _REG_BIT(0x44, 20),/* F2xx, F3xx */ - RCC_SPI6 = _REG_BIT(0x44, 21),/* F2xx, F3xx */ - RCC_SAI1EN = _REG_BIT(0x44, 22),/* F42x, F43x */ - RCC_LTDC = _REG_BIT(0x44, 26),/* F42x, F43x */ - RCC_DSI = _REG_BIT(0x44, 27),/* F4x9, F4x9 */ - - - /* BDCR */ - RCC_RTC = _REG_BIT(0x70, 15), - - /* AHB1 peripherals*/ - SCC_GPIOA = _REG_BIT(0x50, 0), - SCC_GPIOB = _REG_BIT(0x50, 1), - SCC_GPIOC = _REG_BIT(0x50, 2), - SCC_GPIOD = _REG_BIT(0x50, 3), - SCC_GPIOE = _REG_BIT(0x50, 4), - SCC_GPIOF = _REG_BIT(0x50, 5), - SCC_GPIOG = _REG_BIT(0x50, 6), - SCC_GPIOH = _REG_BIT(0x50, 7), - SCC_GPIOI = _REG_BIT(0x50, 8), - SCC_GPIOJ = _REG_BIT(0x50, 9), - SCC_GPIOK = _REG_BIT(0x50, 10), - SCC_CRC = _REG_BIT(0x50, 12), - SCC_FLTIF = _REG_BIT(0x50, 15), - SCC_SRAM1 = _REG_BIT(0x50, 16), - SCC_SRAM2 = _REG_BIT(0x50, 17), - SCC_BKPSRAM = _REG_BIT(0x50, 18), - SCC_SRAM3 = _REG_BIT(0x50, 19),/* F2xx, F3xx */ - SCC_DMA1 = _REG_BIT(0x50, 21), - SCC_DMA2 = _REG_BIT(0x50, 22), - SCC_DMA2D = _REG_BIT(0x50, 23), /* F4x9 */ - SCC_ETHMAC = _REG_BIT(0x50, 25), - SCC_ETHMACTX = _REG_BIT(0x50, 26), - SCC_ETHMACRX = _REG_BIT(0x50, 27), - SCC_ETHMACPTP = _REG_BIT(0x50, 28), - SCC_OTGHS = _REG_BIT(0x50, 29), - SCC_OTGHSULPI = _REG_BIT(0x50, 30), - - /* AHB2 peripherals */ - SCC_DCMI = _REG_BIT(0x54, 0), - SCC_CRYP = _REG_BIT(0x54, 4), - SCC_HASH = _REG_BIT(0x54, 5), - SCC_RNG = _REG_BIT(0x54, 6), - SCC_OTGFS = _REG_BIT(0x54, 7), - - /* AHB3 peripherals */ - SCC_QSPIC = _REG_BIT(0x58, 1), - SCC_FMC = _REG_BIT(0x58, 0), - SCC_FSMC = _REG_BIT(0x58, 0), - - /* APB1 peripherals*/ - SCC_TIM2 = _REG_BIT(0x60, 0), - SCC_TIM3 = _REG_BIT(0x60, 1), - SCC_TIM4 = _REG_BIT(0x60, 2), - SCC_TIM5 = _REG_BIT(0x60, 3), - SCC_TIM6 = _REG_BIT(0x60, 4), - SCC_TIM7 = _REG_BIT(0x60, 5), - SCC_TIM12 = _REG_BIT(0x60, 6), - SCC_TIM13 = _REG_BIT(0x60, 7), - SCC_TIM14 = _REG_BIT(0x60, 8), - SCC_WWDG = _REG_BIT(0x60, 11), - SCC_SPI2 = _REG_BIT(0x60, 14), - SCC_SPI3 = _REG_BIT(0x60, 15), - SCC_USART2 = _REG_BIT(0x60, 17), - SCC_USART3 = _REG_BIT(0x60, 18), - SCC_UART4 = _REG_BIT(0x60, 19), - SCC_UART5 = _REG_BIT(0x60, 20), - SCC_I2C1 = _REG_BIT(0x60, 21), - SCC_I2C2 = _REG_BIT(0x60, 22), - SCC_I2C3 = _REG_BIT(0x60, 23), - SCC_CAN1 = _REG_BIT(0x60, 25), - SCC_CAN2 = _REG_BIT(0x60, 26), - SCC_PWR = _REG_BIT(0x60, 28), - SCC_DAC = _REG_BIT(0x60, 29), - SCC_UART7 = _REG_BIT(0x60, 30),/* F2xx, F3xx */ - SCC_UART8 = _REG_BIT(0x60, 31),/* F2xx, F3xx */ - - /* APB2 peripherals */ - SCC_TIM1 = _REG_BIT(0x64, 0), - SCC_TIM8 = _REG_BIT(0x64, 1), - SCC_USART1 = _REG_BIT(0x64, 4), - SCC_USART6 = _REG_BIT(0x64, 5), - SCC_ADC1 = _REG_BIT(0x64, 8), - SCC_ADC2 = _REG_BIT(0x64, 9), - SCC_ADC3 = _REG_BIT(0x64, 10), - SCC_SDIO = _REG_BIT(0x64, 11), - SCC_SPI1 = _REG_BIT(0x64, 12), - SCC_SPI4 = _REG_BIT(0x64, 13),/* F2xx, F3xx */ - SCC_SYSCFG = _REG_BIT(0x64, 14), - SCC_TIM9 = _REG_BIT(0x64, 16), - SCC_TIM10 = _REG_BIT(0x64, 17), - SCC_TIM11 = _REG_BIT(0x64, 18), - SCC_SPI5 = _REG_BIT(0x64, 20),/* F2xx, F3xx */ - SCC_SPI6 = _REG_BIT(0x64, 21),/* F2xx, F3xx */ - SCC_SAI1 = _REG_BIT(0x64, 22),/* F4x9 */ - SCC_LTDC = _REG_BIT(0x64, 26),/* F4x9 */ - SCC_DSI = _REG_BIT(0x64, 27),/* F4x9 */ -}; - -enum rcc_periph_rst { - /* AHB1 peripherals*/ - RST_GPIOA = _REG_BIT(0x10, 0), - RST_GPIOB = _REG_BIT(0x10, 1), - RST_GPIOC = _REG_BIT(0x10, 2), - RST_GPIOD = _REG_BIT(0x10, 3), - RST_GPIOE = _REG_BIT(0x10, 4), - RST_GPIOF = _REG_BIT(0x10, 5), - RST_GPIOG = _REG_BIT(0x10, 6), - RST_GPIOH = _REG_BIT(0x10, 7), - RST_GPIOI = _REG_BIT(0x10, 8), - RST_GPIOJ = _REG_BIT(0x10, 9), - RST_GPIOK = _REG_BIT(0x10, 10), - RST_CRC = _REG_BIT(0x10, 12), - RST_DMA1 = _REG_BIT(0x10, 21), - RST_DMA2 = _REG_BIT(0x10, 22), - RST_DMA2D = _REG_BIT(0x10, 23), - RST_ETHMAC = _REG_BIT(0x10, 25), - RST_OTGHS = _REG_BIT(0x10, 29), - - /* AHB2 peripherals */ - RST_DCMI = _REG_BIT(0x14, 0), - RST_CRYP = _REG_BIT(0x14, 4), - RST_HASH = _REG_BIT(0x14, 5), - RST_RNG = _REG_BIT(0x14, 6), - RST_OTGFS = _REG_BIT(0x14, 7), - - /* AHB3 peripherals */ - RST_QSPI = _REG_BIT(0x18, 1), /* F4x9 */ - RST_FSMC = _REG_BIT(0x18, 0), - RST_FMC = _REG_BIT(0x18, 0), /* F4x9 */ - - /* APB1 peripherals*/ - RST_TIM2 = _REG_BIT(0x20, 0), - RST_TIM3 = _REG_BIT(0x20, 1), - RST_TIM4 = _REG_BIT(0x20, 2), - RST_TIM5 = _REG_BIT(0x20, 3), - RST_TIM6 = _REG_BIT(0x20, 4), - RST_TIM7 = _REG_BIT(0x20, 5), - RST_TIM12 = _REG_BIT(0x20, 6), - RST_TIM13 = _REG_BIT(0x20, 7), - RST_TIM14 = _REG_BIT(0x20, 8), - RST_WWDG = _REG_BIT(0x20, 11), - RST_SPI2 = _REG_BIT(0x20, 14), - RST_SPI3 = _REG_BIT(0x20, 15), - RST_USART2 = _REG_BIT(0x20, 17), - RST_USART3 = _REG_BIT(0x20, 18), - RST_UART4 = _REG_BIT(0x20, 19), - RST_UART5 = _REG_BIT(0x20, 20), - RST_I2C1 = _REG_BIT(0x20, 21), - RST_I2C2 = _REG_BIT(0x20, 22), - RST_I2C3 = _REG_BIT(0x20, 23), - RST_CAN1 = _REG_BIT(0x20, 25), - RST_CAN2 = _REG_BIT(0x20, 26), - RST_PWR = _REG_BIT(0x20, 28), - RST_DAC = _REG_BIT(0x20, 29), - RST_UART7 = _REG_BIT(0x20, 30),/* F2xx, F3xx */ - RST_UART8 = _REG_BIT(0x20, 31),/* F2xx, F3xx */ - - /* APB2 peripherals */ - RST_TIM1 = _REG_BIT(0x24, 0), - RST_TIM8 = _REG_BIT(0x24, 1), - RST_USART1 = _REG_BIT(0x24, 4), - RST_USART6 = _REG_BIT(0x24, 5), - RST_ADC = _REG_BIT(0x24, 8), - RST_SDIO = _REG_BIT(0x24, 11), - RST_SPI1 = _REG_BIT(0x24, 12), - RST_SPI4 = _REG_BIT(0x24, 13),/* F2xx, F3xx */ - RST_SYSCFG = _REG_BIT(0x24, 14), - RST_TIM9 = _REG_BIT(0x24, 16), - RST_TIM10 = _REG_BIT(0x24, 17), - RST_TIM11 = _REG_BIT(0x24, 18), - RST_SPI5 = _REG_BIT(0x24, 20),/* F2xx, F3xx */ - RST_SPI6 = _REG_BIT(0x24, 21),/* F2xx, F3xx */ - RST_SAI1RST = _REG_BIT(0x24, 22),/* F42x, F43x */ - RST_LTDC = _REG_BIT(0x24, 26),/* F42x, F43x */ - RST_DSI = _REG_BIT(0x24, 27),/* F42x, F43x */ -}; - -#undef _REG_BIT - -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_plli2s_config(uint16_t n, uint8_t r); -void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r); -void rcc_pllsai_postscalers(uint8_t q, uint8_t r); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_rtcpre(uint32_t rtcpre); -void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq, uint32_t pllr); -void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq, uint32_t pllr); -uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); -void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); - -END_DECLS - -#endif -/**@}*/ \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f4/rng.h b/libopencm3/include/libopencm3/stm32/f4/rng.h deleted file mode 100644 index 09d014d..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/rng.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rtc.h b/libopencm3/include/libopencm3/stm32/f4/rtc.h deleted file mode 100644 index 555efcb..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/rtc.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - -@brief Defined Constants and Types for the STM32F4xx RTC - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -BEGIN_DECLS - -void rtc_enable_wakeup_timer(void); -void rtc_disable_wakeup_timer(void); -void rtc_enable_wakeup_timer_interrupt(void); -void rtc_disable_wakeup_timer_interrupt(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/spi.h b/libopencm3/include/libopencm3/stm32/f4/spi.h deleted file mode 100644 index eecb597..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32F4xx SPI - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f4/syscfg.h b/libopencm3/include/libopencm3/stm32/f4/syscfg.h deleted file mode 100644 index 5f4fba4..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/syscfg.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32F4xx_defines - * - * @brief Defined Constants and Types for the STM32F4xx Sysconfig - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/timer.h b/libopencm3/include/libopencm3/stm32/f4/timer.h deleted file mode 100644 index 604a83f..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/timer.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32F4xx Timers - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 8 March 2013 - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/usart.h b/libopencm3/include/libopencm3/stm32/f4/usart.h deleted file mode 100644 index 1332641..0000000 --- a/libopencm3/include/libopencm3/stm32/f4/usart.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup usart_defines USART Defines - -@brief Defined Constants and Types for the STM32F4xx USART - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f7/adc.h b/libopencm3/include/libopencm3/stm32/f7/adc.h deleted file mode 100644 index d97a188..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/adc.h +++ /dev/null @@ -1,194 +0,0 @@ -/** @defgroup adc_defines ADC Defines - -@brief Defined Constants and Types for the STM32F7xx Analog to Digital -Converters - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2019 -Matthew Lai -@author @htmlonly © @endhtmlonly 2009 -Edward Cheeseman - -@date 31 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Matthew Lai - * Copyright (C) 2009 Edward Cheeseman - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32((block) + 0x14) -#define ADC_JOFR2(block) MMIO32((block) + 0x18) -#define ADC_JOFR3(block) MMIO32((block) + 0x1c) -#define ADC_JOFR4(block) MMIO32((block) + 0x20) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32((block) + 0x24) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32((block) + 0x28) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32((block) + 0x2c) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32((block) + 0x30) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32((block) + 0x34) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32((block) + 0x38) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32((block) + 0x3c) -#define ADC_JDR2(block) MMIO32((block) + 0x40) -#define ADC_JDR3(block) MMIO32((block) + 0x44) -#define ADC_JDR4(block) MMIO32((block) + 0x48) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32((block) + 0x4c) - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - *@{*/ -#define ADC_CHANNEL_TEMP 18 -#define ADC_CHANNEL_VREF 17 -#define ADC_CHANNEL_VBAT 18 -/**@}*/ - - -/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ -#define ADC_CR1_AWDCH_MAX 18 - -/* --- Convenience macros -------------------------------------------------- */ -/* EXTSEL[3:0]: External event selection for regular group. */ -/****************************************************************************/ -/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group -@ingroup adc_defines - -@{*/ -/** Timer 1 Compare Output 1 */ -#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) -/** Timer 1 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) -/** Timer 1 Compare Output 3 */ -#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) -/** Timer 2 Compare Output 2 */ -#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) -/** Timer 5 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM5_TRGO (0x4 << 24) -/** Timer 4 Compare Output 4 */ -#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 24) -/** Timer 3 Compare Output 4 */ -#define ADC_CR2_EXTSEL_TIM3_CC4 (0x6 << 24) -/** Timer 8 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM8_TRGO (0x7 << 24) -/** Timer 8 TRGO2 Event */ -#define ADC_CR2_EXTSEL_TIM8_TRGO2 (0x8 << 24) -/** Timer 1 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM1_TRGO (0x9 << 24) -/** Timer 1 TRGO2 Event */ -#define ADC_CR2_EXTSEL_TIM1_TRGO2 (0xA << 24) -/** Timer 2 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM2_TRGO (0xB << 24) -/** Timer 4 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM4_TRGO (0xC << 24) -/** Timer 6 TRGO Event */ -#define ADC_CR2_EXTSEL_TIM6_TRGO (0xD << 24) -/** EXTI Line 11 Event */ -#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) -/**@}*/ - -/* JEXTSEL[3:0]: External event selection for injected group. */ -/****************************************************************************/ -/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group -@ingroup adc_defines - -@{*/ -#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 16) -#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 16) -#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 16) -#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 16) -#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 16) -/* 0x6 undefined */ -#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x7 << 16) -#define ADC_CR2_JEXTSEL_TIM1_TRGO2 (0x8 << 16) -#define ADC_CR2_JEXTSEL_TIM8_TRGO (0x9 << 16) -#define ADC_CR2_JEXTSEL_TIM8_TRGO2 (0xA << 16) -#define ADC_CR2_JEXTSEL_TIM3_cc3 (0xB << 16) -#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xC << 16) -#define ADC_CR2_JEXTSEL_TIM3_CC1 (0xD << 16) -#define ADC_CR2_JEXTSEL_TIM6_TRGO (0xE << 16) -/* 0xf undefined */ -/**@}*/ - -/* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_3CYC 0x0 -#define ADC_SMPR_SMP_15CYC 0x1 -#define ADC_SMPR_SMP_28CYC 0x2 -#define ADC_SMPR_SMP_56CYC 0x3 -#define ADC_SMPR_SMP_84CYC 0x4 -#define ADC_SMPR_SMP_112CYC 0x5 -#define ADC_SMPR_SMP_144CYC 0x6 -#define ADC_SMPR_SMP_480CYC 0x7 -/**@}*/ - -/* --- ADC_SQR1 values ----------------------------------------------------- */ -#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) - -#define ADC_SQR_MAX_CHANNELS_REGULAR 16 - -/* ADCPRE: ADC prescaler. */ -/****************************************************************************/ -/** @defgroup adc_ccr_adcpre ADC Prescale -@ingroup adc_defines - -@{*/ -#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) -#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) -#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) -#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) -/**@}*/ -#define ADC_CCR_ADCPRE_MASK (0x3 << 16) -#define ADC_CCR_ADCPRE_SHIFT 16 - -BEGIN_DECLS - -void adc_set_multi_mode(uint32_t mode); -void adc_enable_vbat_sensor(void); -void adc_disable_vbat_sensor(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/crc.h b/libopencm3/include/libopencm3/stm32/f7/crc.h deleted file mode 100644 index ae6d467..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/crc.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F7xx CRC - * Generator - * - * @ingroup STM32F7xx_defines - * - * @version 1.0.0 - * - * @date 11 Apr 2019 - * - *LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/dac.h b/libopencm3/include/libopencm3/stm32/f7/dac.h deleted file mode 100644 index 1e5607e..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/dac.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32F7xx DAC - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@date 6 May 2019 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/dma.h b/libopencm3/include/libopencm3/stm32/f7/dma.h deleted file mode 100644 index 01a7e18..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/dma.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup dma_defines DMA Defines - -@ingroup STM32F7xx_defines - -@brief Defined Constants and Types for the STM32F7xx DMA Controller - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f7/dma2d.h b/libopencm3/include/libopencm3/stm32/f7/dma2d.h deleted file mode 100644 index 47b2647..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/dma2d.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup dma2d_defines DMA2D Defines - * @brief Defined Constants and Types for the STM32F7xx DMA2D Peripheral - * @ingroup STM32F7xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F7_DMA2D_H_ -#define LIBOPENCM3_STM32_F7_DMA2D_H_ - -#include - -#endif /* LIBOPENCM3_STM32_F7_DMA2D_H_ */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f7/doc-stm32f7.h b/libopencm3/include/libopencm3/stm32/f7/doc-stm32f7.h deleted file mode 100644 index cd02498..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/doc-stm32f7.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32F7 - -@version 1.0.0 - -@date 15 September 2014 - -API documentation for ST Microelectronics STM32F7 Cortex M7 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32F7xx STM32F7xx -Libraries for ST Microelectronics STM32F7xx series. - -@version 1.0.0 - -@date 15 September 2014 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32F7xx_defines STM32F7xx Defines - -@brief Defined Constants and Types for the STM32F7xx series - -@version 1.0.0 - -@date 15 September 2014 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/f7/dsi.h b/libopencm3/include/libopencm3/stm32/f7/dsi.h deleted file mode 100644 index 45f727e..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/dsi.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dsi_defines DSI Defines - * @brief Defines Constants and Macros for the STM32F7xx Display Serial - * Interface Host and Wrapper - * @ingroup STM32F7xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F7_DSI_H_ -#define LIBOPENCM3_STM32_F7_DSI_H_ - -#include - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f7/exti.h b/libopencm3/include/libopencm3/stm32/f7/exti.h deleted file mode 100644 index edb2648..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/exti.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32F7xx External Interrupts - * - * - * @ingroup STM32F7xx_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/flash.h b/libopencm3/include/libopencm3/stm32/f7/flash.h deleted file mode 100644 index 0047da8..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/flash.h +++ /dev/null @@ -1,101 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32F7xx_defines - * - * @author @htmlonly © @endhtmlonly 2017 - * Matthew Lai - * @author @htmlonly © @endhtmlonly 2010 - * Thomas Otto - * @author @htmlonly © @endhtmlonly 2010 - * Mark Butler - * - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Matthew Lai - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include -#include - -/* - * Differences between F7 and F4: - * 1. icache and dcache are now combined into a unified ART cache. The CPU has - * its own d/i-caches, but those are unrelated to this. They are on the - * AXIM bus. - * 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR ( - * erase sequence error). - * 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG ( - * window watchdog). - */ - -/**@{*/ - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -/** @addtogroup flash_acr_values FLASH_ACR values - * @ingroup flash_registers -@{*/ -#define FLASH_ACR_ARTRST (1 << 11) -#define FLASH_ACR_ARTEN (1 << 9) -#define FLASH_ACR_PRFTEN (1 << 8) -/*@}*/ - -#define FLASH_SR_ERSERR (1 << 7) - -/* --- FLASH_OPTCR values -------------------------------------------------- */ - -#define FLASH_OPTCR_IWDG_STOP (1 << 31) -#define FLASH_OPTCR_IWDG_STDBY (1 << 30) - -#define FLASH_OPTCR_NWRP_SHIFT 16 -#define FLASH_OPTCR_NWRP_MASK 0xff - -#define FLASH_OPTCR_RDP_SHIFT 8 -#define FLASH_OPTCR_RDP_MASK 0xff - -#define FLASH_OPTCR_IWDG_SW (1 << 5) -#define FLASH_OPTCR_WWDG_SW (1 << 4) - -#define FLASH_OPTCR_OPTSTRT (1 << 1) -#define FLASH_OPTCR_OPTLOCK (1 << 0) - -/* --- FLASH_OPTCR1 values ------------------------------------------------- */ -#define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffff -#define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16 -#define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffff -#define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0 - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_clear_erserr_flag(void); -void flash_art_enable(void); -void flash_art_reset(void); - -END_DECLS -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f7/fmc.h b/libopencm3/include/libopencm3/stm32/f7/fmc.h deleted file mode 100644 index 8eef83a..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/fmc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup fmc_defines FMC Defines - * @brief Defined Constants and Types for the STM32F7xx Flexible Memory - * Controller - * @ingroup STM32F7xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_F7_FMC_H -#define LIBOPENCM3_F7_FMC_H - -#ifndef LIBOPENCM3_FSMC_H -#error "This file should not be included directly, it is included with fsmc.h" -#endif - -#include - -/* --- Convenience macros -------------------------------------------------- */ -#define FSMC_BASE FMCC_BASE - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f7/gpio.h b/libopencm3/include/libopencm3/stm32/f7/gpio.h deleted file mode 100644 index 6e88e22..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/gpio.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32F7xx General Purpose I/O - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f7/i2c.h b/libopencm3/include/libopencm3/stm32/f7/i2c.h deleted file mode 100644 index 23b7d6b..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/i2c.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @brief Defined Constants and Types for the STM32F7xx I2C - * - * @ingroup STM32F7xx_defines - * - * @version 1.0.0 - * - * @date 04 April 2019 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f7/irq.json b/libopencm3/include/libopencm3/stm32/f7/irq.json deleted file mode 100644 index 31bbe61..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/irq.json +++ /dev/null @@ -1,111 +0,0 @@ -{ - "irqs": [ - "nvic_wwdg", - "pvd", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_stream0", - "dma1_stream1", - "dma1_stream2", - "dma1_stream3", - "dma1_stream4", - "dma1_stream5", - "dma1_stream6", - "adc", - "can1_tx", - "can1_rx0", - "can1_rx1", - "can1_sce", - "exti9_5", - "tim1_brk_tim9", - "tim1_up_tim10", - "tim1_trg_com_tim11", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_fs_wkup", - "tim8_brk_tim12", - "tim8_up_tim13", - "tim8_trg_com_tim14", - "tim8_cc", - "dma1_stream7", - "fsmc", - "sdmmc1", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dac", - "tim7", - "dma2_stream0", - "dma2_stream1", - "dma2_stream2", - "dma2_stream3", - "dma2_stream4", - "eth", - "eth_wkup", - "can2_tx", - "can2_rx0", - "can2_rx1", - "can2_sce", - "otg_fs", - "dma2_stream5", - "dma2_stream6", - "dma2_stream7", - "usart6", - "i2c3_ev", - "i2c3_er", - "otg_hs_ep1_out", - "otg_hs_ep1_in", - "otg_hs_wkup", - "otg_hs", - "dcmi", - "cryp", - "hash_rng", - "fpu", - "uart7", - "uart8", - "spi4", - "spi5", - "spi6", - "sai1", - "lcd_tft", - "lcd_tft_err", - "dma2d", - "sai2", - "quadspi", - "lp_timer1", - "hdmi_cec", - "i2c4_ev", - "i2c4_er", - "spdifrx", - "dsihost", - "dfsdm1_flt0", - "dfsdm1_flt1", - "dfsdm1_flt2", - "dfsdm1_flt3", - "sdmmc2" - ], - "partname_humanreadable": "STM32 F7 series", - "partname_doxygen": "STM32F7", - "includeguard": "LIBOPENCM3_STM32_F7_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/f7/iwdg.h b/libopencm3/include/libopencm3/stm32/f7/iwdg.h deleted file mode 100644 index c70f20d..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/iwdg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @brief Defined Constants and Types for the STM32F7xx Independent Watchdog - * Timer - * - * @ingroup STM32F7xx_defines - * - * @version 1.0.0 - * - * @date 11 April 2018 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/lptimer.h b/libopencm3/include/libopencm3/stm32/f7/lptimer.h deleted file mode 100644 index 4c721af..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/lptimer.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @defgroup lptimer_defines LPTIM Defines - * - * @ingroup STM32F7xx_defines - * - * @brief libopencm3 Defined Constants and Types for the STM32F7xx Low Power Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPTIMER_H -#define LIBOPENCM3_LPTIMER_H -/**@{*/ - -#include - -/** @defgroup lptim_reg_base Low Power Timer register base addresses -@{*/ -#define LPTIM1 LPTIM1_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/ltdc.h b/libopencm3/include/libopencm3/stm32/f7/ltdc.h deleted file mode 100644 index 37bde22..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/ltdc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup ltdc_defines LTDC Defines - * @brief Defined Constants and Types for the STM32F7xx LCD TFT Display - * Controller - * @ingroup STM32F7xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_STM32_F7_LTDC_H_ -#define LIBOPENCM3_STM32_F7_LTDC_H_ - -#include - -#endif /* LIBOPENCM3_STM32_F7_LTDC_H_ */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/f7/memorymap.h b/libopencm3/include/libopencm3/stm32/f7/memorymap.h deleted file mode 100644 index 5cb4212..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/memorymap.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32F7 specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 0x50000000U -#define PERIPH_BASE_AHB3 0x60000000U - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -#define SPDIF_BASE (PERIPH_BASE_APB1 + 0x4000) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) -#define I2C4_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -#define CEC_BASE (PERIPH_BASE_APB1 + 0x6C00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800) -#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) -/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ -#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) -#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) -/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */ -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */ -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */ -#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */ -/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ -#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */ -/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400) -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) -/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */ -#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000) -#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400) -#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) -#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5C00) -#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800) -#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) /* compat. with f4 */ -#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00) -#define DFSDM1_BASE (PERIPH_BASE_APB2 + 0x7400) -#define MDIOS_BASE (PERIPH_BASE_APB2 + 0x7800) -/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 7C00 - 0x4001 FFFF): Reserved */ - -/* AHB1 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) -#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) -#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400) -#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800) -/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */ -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) -#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) -/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) -/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) - -#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000) - -#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) - - -/* AHB2 */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000) -/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ -#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) -/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ -#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) -/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */ -#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) -/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ - -/* AHB3 */ -#define FMC1_BASE (PERIPH_BASE_AHB3 + 0x00000000U) -#define FMC2_BASE (PERIPH_BASE_AHB3 + 0x10000000U) -#define FMC3_BASE (PERIPH_BASE_AHB3 + 0x20000000U) -#define QSPI_BASE (PERIPH_BASE_AHB3 + 0x30000000U) -#define FMCC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) -#define QSPIC_BASE (PERIPH_BASE_AHB3 + 0x40001000U) -#define FMC5_BASE (PERIPH_BASE_AHB3 + 0x60000000U) -#define FMC6_BASE (PERIPH_BASE_AHB3 + 0x70000000U) - -/* Private peripherals */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* Device Electronic Signature */ -/* On F7 the base address are different depending on the device ID in DBBGMCU. */ -#define DESIG_FLASH_SIZE_BASE_449 (0x1FF0F422U) -#define DESIG_FLASH_SIZE_BASE_451 (0x1FF0F422U) -#define DESIG_FLASH_SIZE_BASE_452 (0x1FF07A22U) - -#define DESIG_UNIQUE_ID_BASE_449 (0x1FF0F420U) -#define DESIG_UNIQUE_ID_BASE_451 (0x1FF0F420U) -#define DESIG_UNIQUE_ID_BASE_452 (0x1FF07A10U) - -/* ST provided factory calibration values @ 3.3V */ -#define ST_VREFINT_CAL MMIO16(0x1FF07A4A) -#define ST_TSENSE_CAL1_30C MMIO16(0x1FF07A4C) -#define ST_TSENSE_CAL2_110C MMIO16(0x1FF07A4E) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/pwr.h b/libopencm3/include/libopencm3/stm32/f7/pwr.h deleted file mode 100644 index 4605571..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/pwr.h +++ /dev/null @@ -1,297 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32F7xx Power Control - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2017 Matthew Lai - -@date 12 March 2017 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Matthew Lai - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -/**@{*/ - -/** @defgroup pwr_registers PWR Registers - * @ingroup STM32F_pwr_defines -@{*/ -/** Power control register (PWR_CR1) */ -#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) - -/** Power control/status register (PWR_CSR1) */ -#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04) - -/** Power control register 2 (PWR_CR2) */ -#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08) - -/** Power control/status register 2 (PWR_CSR2) */ -#define PWR_CSR2 MMIO32(POWER_CONTROL_BASE + 0x0c) -/*@}*/ - -/** @defgroup pwr_cr1_defines PWR_CR1 values - * @ingroup STM32F_pwr_defines -@{*/ - -/* Bits [31:20]: Reserved, must be kept at reset value. */ - -/** UDEN[19:18]: Under-drive enable in stop mode */ -#define PWR_CR1_UDEN_LSB 18 -/** @defgroup pwr_uden Under-drive enable in stop mode -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CR1_UDEN_DISABLED (0x0 << PWR_CR1_UDEN_LSB) -#define PWR_CR1_UDEN_ENABLED (0x3 << PWR_CR1_UDEN_LSB) -/**@}*/ -#define PWR_CR1_UDEN_MASK (0x3 << PWR_CR1_UDEN_LSB) - -/** ODSWEN: Over-drive switching enabled */ -#define PWR_CR1_ODSWEN (1 << 17) - -/** ODEN: Over-drive enable */ -#define PWR_CR1_ODEN (1 << 16) - -/* VOS[15:14]: Regulator voltage scaling output selection */ -#define PWR_CR1_VOS_LSB 14 -/** @defgroup pwr_vos Regulator voltage scaling output selection -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CR1_VOS_SCALE_3 (0x1 << PWR_CR1_VOS_LSB) -#define PWR_CR1_VOS_SCALE_2 (0x2 << PWR_CR1_VOS_LSB) -#define PWR_CR1_VOS_SCALE_1 (0x3 << PWR_CR1_VOS_LSB) -/**@}*/ -#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_LSB) - -/** ADCDC1: Masks extra flash accesses by prefetch (see AN4073) */ -#define PWR_CR1_ADCDC1 (1 << 13) - -/* Bit 12: Reserved, must be kept at reset value. */ - -/** MRUDS: Main regulator in deepsleep under-drive mode */ -#define PWR_CR1_MRUDS (1 << 11) - -/** LPUDS: Low-power regulator in deepsleep under-drive mode */ -#define PWR_CR1_LPUDS (1 << 10) - -/** FPDS: Flash power-down in Stop mode */ -#define PWR_CR1_FPDS (1 << 9) - -/** DBP: Disable backup domain write protection */ -#define PWR_CR1_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR1_PLS_LSB 5 -/** @defgroup pwr_pls PVD level selection -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CR1_PLS_2V0 (0x0 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V1 (0x1 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V3 (0x2 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) -#define PWR_CR1_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) -/**@}*/ -#define PWR_CR1_PLS_MASK (0x7 << PWR_CR_PLS_LSB) - -/** PVDE: Power voltage detector enable */ -#define PWR_CR1_PVDE (1 << 4) - -/** CSBF: Clear standby flag */ -#define PWR_CR1_CSBF (1 << 3) - -/* Bit 2: Reserved, must be kept at reset value. */ - -/** PDDS: Power down deepsleep */ -#define PWR_CR1_PDDS (1 << 1) - -/** LPDS: Low-power deepsleep */ -#define PWR_CR1_LPDS (1 << 0) -/*@}*/ - -/** @defgroup pwr_csr1_defines PWR_CSR1 values - * @ingroup STM32F_pwr_defines -@{*/ - -/* Bits [31:20]: Reserved, must be kept at reset value. */ - -/* UDRDY[19:18]: Under-drive ready flag */ -#define PWR_CSR1_UDRDY_LSB 18 -/** @defgroup pwr_udrdy Under-drive ready flag -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CSR1_UDRDY_DISABLED (0x0 << PWR_CSR1_UDRDY_LSB) -#define PWR_CSR1_UDRDY_ACTIVATED (0x3 << PWR_CSR1_UDRDY_LSB) -/**@}*/ -#define PWR_CSR1_UDRDY_MASK (0x3 << PWR_CSR1_UDRDY_LSB) - -/** ODSWRDY: Over-drive mode switching ready */ -#define PWR_CSR1_ODSWRDY (1 << 17) - -/** ODRDY: Over-drive mode ready */ -#define PWR_CSR1_ODRDY (1 << 16) - -/* Bit 15: Reserved, must be kept at reset value. */ - -/** VOSRDY: Regulator voltage scaling output selection ready bit */ -#define PWR_CSR1_VOSRDY (1 << 14) - -/* Bits [13:10]: Reserved, must be kept at reset value. */ - -/** BRE: Backup regulator enable */ -#define PWR_CSR1_BRE (1 << 9) - -/** EIWUP: Enable internal wakeup */ -#define PWR_CSR1_EIWUP (1 << 8) - -/* Bits [7:4]: Reserved, must be kept at reset value. */ - -/** BRR: Backup regulator ready */ -#define PWR_CSR1_BRR (1 << 3) - -/** PVDO: PVD output */ -#define PWR_CSR1_PVDO (1 << 2) - -/** SBF: Standby flag */ -#define PWR_CSR1_SBF (1 << 1) - -/** WUIF: Wakeup internal flag */ -#define PWR_CSR1_WUIF (1 << 0) -/*@}*/ - -/** @defgroup pwr_cr2_defines PWR_CR2 values - * @ingroup STM32F_pwr_defines -@{*/ - -/* Bits [31:14]: Reserved, must be kept at reset value. */ - -/** WUPP6: Wakeup pin polarity bit for PI11 */ -#define PWR_CR2_WUPP6 (1 << 13) - -/** WUPP5: Wakeup pin polarity bit for PI8 */ -#define PWR_CR2_WUPP5 (1 << 12) - -/** WUPP4: Wakeup pin polarity bit for PC13 */ -#define PWR_CR2_WUPP4 (1 << 11) - -/** WUPP3: Wakeup pin polarity bit for PC1 */ -#define PWR_CR2_WUPP3 (1 << 10) - -/** WUPP2: Wakeup pin polarity bit for PA2 */ -#define PWR_CR2_WUPP2 (1 << 9) - -/** WUPP1: Wakeup pin polarity bit for PA0 */ -#define PWR_CR2_WUPP1 (1 << 8) - -/* Bits [7:6]: Reserved, must be kept at reset value. */ - -/** CWUPF6: Clear Wakeup Pin flag for PI11 */ -#define PWR_CR2_CWUPF6 (1 << 5) - -/** CWUPF5: Clear Wakeup Pin flag for PI8 */ -#define PWR_CR2_CWUPF5 (1 << 4) - -/** CWUPF4: Clear Wakeup Pin flag for PC13 */ -#define PWR_CR2_CWUPF4 (1 << 3) - -/** CWUPF3: Clear Wakeup Pin flag for PC1 */ -#define PWR_CR2_CWUPF3 (1 << 2) - -/** CWUPF2: Clear Wakeup Pin flag for PA2 */ -#define PWR_CR2_CWUPF2 (1 << 1) - -/** CWUPF1: Clear Wakeup Pin flag for PA0 */ -#define PWR_CR2_CWUPF1 (1 << 0) -/*@}*/ - -/** @defgroup pwr_csr2_defines PWR_CSR2 values - * @ingroup STM32F_pwr_defines -@{*/ - -/* Bits [31:14]: Reserved, must be kept at reset value. */ - -/** EWUP6: Enable Wakeup pin for PI11 */ -#define PWR_CSR2_EWUP6 (1 << 13) - -/** EWUP5: Enable Wakeup pin for PI8 */ -#define PWR_CSR2_EWUP5 (1 << 12) - -/** EWUP4: Enable Wakeup pin for PC13 */ -#define PWR_CSR2_EWUP4 (1 << 11) - -/** EWUP3: Enable Wakeup pin for PC1 */ -#define PWR_CSR2_EWUP3 (1 << 10) - -/** EWUP2: Enable Wakeup pin for PA2 */ -#define PWR_CSR2_EWUP2 (1 << 19) - -/** EWUP1: Enable Wakeup pin for PA0 */ -#define PWR_CSR2_EWUP1 (1 << 18) - -/* Bits [7:6]: Reserved, must be kept at reset value. */ - -/** WUPF6: Wakeup Pin flag for PI11 */ -#define PWR_CSR2_WUPF6 (1 << 5) - -/** WUPF5: Wakeup Pin flag for PI8 */ -#define PWR_CSR2_WUPF5 (1 << 4) - -/** WUPF4: Wakeup Pin flag for PC13 */ -#define PWR_CSR2_WUPF4 (1 << 3) - -/** WUPF3: Wakeup Pin flag for PC1 */ -#define PWR_CSR2_WUPF3 (1 << 2) - -/** WUPF2: Wakeup Pin flag for PA2 */ -#define PWR_CSR2_WUPF2 (1 << 1) - -/** WUPF1: Wakeup Pin flag for PA0 */ -#define PWR_CSR2_WUPF1 (1 << 0) -/*@}*/ -/* --- Function prototypes ------------------------------------------------- */ - -enum pwr_vos_scale { - PWR_SCALE1, /** <= 180MHz w/o overdrive, <= 216MHz w/ overdrive */ - PWR_SCALE2, /** <= 168MHz w/o overdrive, <= 180MHz w/ overdrive */ - PWR_SCALE3, /** <= 144MHz */ -}; - -BEGIN_DECLS - -void pwr_set_vos_scale(enum pwr_vos_scale scale); -void pwr_enable_overdrive(void); -void pwr_disable_overdrive(void); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/rcc.h b/libopencm3/include/libopencm3/stm32/f7/rcc.h deleted file mode 100644 index 20ed3a5..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/rcc.h +++ /dev/null @@ -1,965 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @brief Defined Constants and Types for the STM32F7xx Reset and Clock - * Control - * - * @ingroup STM32F7xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2015 - * Karl Palsson - * - * @date October, 2015 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include - -/**@{*/ - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_CIR MMIO32(RCC_BASE + 0x0c) -#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) -#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) -#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) -#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) -#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) -#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) -#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) -#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) -#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) -#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) -#define RCC_BDCR MMIO32(RCC_BASE + 0x70) -#define RCC_CSR MMIO32(RCC_BASE + 0x74) -#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) -#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) -#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) -#define RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C) -#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLSAIRDY (1 << 29) -#define RCC_CR_PLLSAION (1 << 28) -#define RCC_CR_PLLI2SRDY (1 << 27) -#define RCC_CR_PLLI2SON (1 << 26) -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSICAL_MASK 0xff -#define RCC_CR_HSICAL_SHIFT 8 -#define RCC_CR_HSITRIM_MASK 0x1f -#define RCC_CR_HSITRIM_SHIFT 3 -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_PLLCFGR values -------------------------------------------------- */ - -#define RCC_PLLCFGR_PLLQ_MASK 0xf -#define RCC_PLLCFGR_PLLQ_SHIFT 24 -#define RCC_PLLCFGR_PLLSRC (1 << 22) -#define RCC_PLLCFGR_PLLP_MASK 0x3 -#define RCC_PLLCFGR_PLLP_SHIFT 16 -#define RCC_PLLCFGR_PLLN_MASK 0x1ff -#define RCC_PLLCFGR_PLLN_SHIFT 6 -#define RCC_PLLCFGR_PLLM_MASK 0x3f -#define RCC_PLLCFGR_PLLM_SHIFT 0 - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCO2: Microcontroller clock output 2 */ -#define RCC_CFGR_MCO2_MASK 0x3 -#define RCC_CFGR_MCO2_SHIFT 30 -#define RCC_CFGR_MCO2_SYSCLK 0x0 -#define RCC_CFGR_MCO2_PLLI2S 0x1 -#define RCC_CFGR_MCO2_HSE 0x2 -#define RCC_CFGR_MCO2_PLL 0x3 - -/* MCO1/2PRE: MCO Prescalers */ -#define RCC_CFGR_MCOPRE_MASK 0x7 -#define RCC_CFGR_MCO2PRE_SHIFT 27 -#define RCC_CFGR_MCO1PRE_SHIFT 24 -#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 -#define RCC_CFGR_MCOPRE_DIV_2 0x4 -#define RCC_CFGR_MCOPRE_DIV_3 0x5 -#define RCC_CFGR_MCOPRE_DIV_4 0x6 -#define RCC_CFGR_MCOPRE_DIV_5 0x7 - -/* I2SSRC: I2S clock selection */ -#define RCC_CFGR_I2SSRC (1 << 23) - -/* MCO1: Microcontroller clock output 1 */ -#define RCC_CFGR_MCO1_MASK 0x3 -#define RCC_CFGR_MCO1_SHIFT 21 -#define RCC_CFGR_MCO1_HSI 0x0 -#define RCC_CFGR_MCO1_LSE 0x1 -#define RCC_CFGR_MCO1_HSE 0x2 -#define RCC_CFGR_MCO1_PLL 0x3 -#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT -#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK - -/* RTCPRE: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_SHIFT 16 -#define RCC_CFGR_RTCPRE_MASK 0x1f - -/* PPRE1/2: APB high-speed prescalers */ -#define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE_DIV_NONE 0x0 -#define RCC_CFGR_PPRE_DIV_2 0x4 -#define RCC_CFGR_PPRE_DIV_4 0x5 -#define RCC_CFGR_PPRE_DIV_8 0x6 -#define RCC_CFGR_PPRE_DIV_16 0x7 - -/* HPRE: AHB high-speed prescaler */ -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) -#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) -#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) -#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) -#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) -#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) -#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) -#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLL 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLLSAIRDYC (1 << 22) -#define RCC_CIR_PLLI2SRDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLLSAIRDYIE (1 << 14) -#define RCC_CIR_PLLI2SRDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLLSAIRDYF (1 << 6) -#define RCC_CIR_PLLI2SRDYF (1 << 5) -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values -@{*/ -#define RCC_AHB1RSTR_OTGHSRST (1 << 29) -#define RCC_AHB1RSTR_ETHMACRST (1 << 25) -#define RCC_AHB1RSTR_DMA2DRST (1 << 23) -#define RCC_AHB1RSTR_DMA2RST (1 << 22) -#define RCC_AHB1RSTR_DMA1RST (1 << 21) -#define RCC_AHB1RSTR_CRCRST (1 << 12) -#define RCC_AHB1RSTR_GPIOKRST (1 << 10) -#define RCC_AHB1RSTR_GPIOJRST (1 << 9) -#define RCC_AHB1RSTR_GPIOIRST (1 << 8) -#define RCC_AHB1RSTR_GPIOHRST (1 << 7) -#define RCC_AHB1RSTR_GPIOGRST (1 << 6) -#define RCC_AHB1RSTR_GPIOFRST (1 << 5) -#define RCC_AHB1RSTR_GPIOERST (1 << 4) -#define RCC_AHB1RSTR_GPIODRST (1 << 3) -#define RCC_AHB1RSTR_GPIOCRST (1 << 2) -#define RCC_AHB1RSTR_GPIOBRST (1 << 1) -#define RCC_AHB1RSTR_GPIOARST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values -@{*/ -#define RCC_AHB2RSTR_OTGFSRST (1 << 7) -#define RCC_AHB2RSTR_RNGRST (1 << 6) -#define RCC_AHB2RSTR_HASHRST (1 << 5) -#define RCC_AHB2RSTR_CRYPRST (1 << 4) -#define RCC_AHB2RSTR_DCMIRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values -@{*/ -#define RCC_AHB3RSTR_QSPIRST (1 << 1) -#define RCC_AHB3RSTR_FSMCRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_UART8RST (1 << 31) -#define RCC_APB1RSTR_UART7RST (1 << 30) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_CECRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) -#define RCC_APB1RSTR_CAN1RST (1 << 25) -#define RCC_APB1RSTR_I2C4RST (1 << 24) -#define RCC_APB1RSTR_I2C3RST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) -#define RCC_APB1RSTR_UART3RST (1 << 18) -#define RCC_APB1RSTR_UART2RST (1 << 17) -#define RCC_APB1RSTR_SPDIFRXRST (1 << 16) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_LPTIM1RST (1 << 9) -#define RCC_APB1RSTR_TIM14RST (1 << 8) -#define RCC_APB1RSTR_TIM13RST (1 << 7) -#define RCC_APB1RSTR_TIM12RST (1 << 6) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_LTDCRST (1 << 26) -#define RCC_APB2RSTR_SAI2RST (1 << 23) -#define RCC_APB2RSTR_SAI1RST (1 << 22) -#define RCC_APB2RSTR_SPI6RST (1 << 21) -#define RCC_APB2RSTR_SPI5RST (1 << 20) -#define RCC_APB2RSTR_TIM11RST (1 << 18) -#define RCC_APB2RSTR_TIM10RST (1 << 17) -#define RCC_APB2RSTR_TIM9RST (1 << 16) -#define RCC_APB2RSTR_SYSCFGRST (1 << 14) -#define RCC_APB2RSTR_SPI4RST (1 << 13) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_SDMMC1RST (1 << 11) -#define RCC_APB2RSTR_ADCRST (1 << 8) -#define RCC_APB2RSTR_USART6RST (1 << 5) -#define RCC_APB2RSTR_USART1RST (1 << 4) -#define RCC_APB2RSTR_TIM8RST (1 << 1) -#define RCC_APB2RSTR_TIM1RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) -@{*/ -/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values -@{*/ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) -#define RCC_AHB1ENR_OTGHSEN (1 << 29) -#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) -#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) -#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) -#define RCC_AHB1ENR_ETHMACEN (1 << 25) -#define RCC_AHB1ENR_DMA2DEN (1 << 23) -#define RCC_AHB1ENR_DMA2EN (1 << 22) -#define RCC_AHB1ENR_DMA1EN (1 << 21) -#define RCC_AHB1ENR_DTCMRAMEN (1 << 20) -#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) -#define RCC_AHB1ENR_CRCEN (1 << 12) -#define RCC_AHB1ENR_GPIOKEN (1 << 10) -#define RCC_AHB1ENR_GPIOJEN (1 << 9) -#define RCC_AHB1ENR_GPIOIEN (1 << 8) -#define RCC_AHB1ENR_GPIOHEN (1 << 7) -#define RCC_AHB1ENR_GPIOGEN (1 << 6) -#define RCC_AHB1ENR_GPIOFEN (1 << 5) -#define RCC_AHB1ENR_GPIOEEN (1 << 4) -#define RCC_AHB1ENR_GPIODEN (1 << 3) -#define RCC_AHB1ENR_GPIOCEN (1 << 2) -#define RCC_AHB1ENR_GPIOBEN (1 << 1) -#define RCC_AHB1ENR_GPIOAEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values -@{*/ -#define RCC_AHB2ENR_OTGFSEN (1 << 7) -#define RCC_AHB2ENR_RNGEN (1 << 6) -#define RCC_AHB2ENR_HASHEN (1 << 5) -#define RCC_AHB2ENR_CRYPEN (1 << 4) -#define RCC_AHB2ENR_DCMIEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values -@{*/ -#define RCC_AHB3ENR_QSPIEN (1 << 1) -#define RCC_AHB3ENR_FMCEN (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_UART8EN (1 << 31) -#define RCC_APB1ENR_UART7EN (1 << 30) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_CECEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) -#define RCC_APB1ENR_CAN1EN (1 << 25) -#define RCC_APB1ENR_I2C4EN (1 << 24) -#define RCC_APB1ENR_I2C3EN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPIDIFRXEN (1 << 16) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_LPTIM1EN (1 << 9) -#define RCC_APB1ENR_TIM14EN (1 << 8) -#define RCC_APB1ENR_TIM13EN (1 << 7) -#define RCC_APB1ENR_TIM12EN (1 << 6) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@{*/ -#define RCC_APB2ENR_LTDCEN (1 << 26) -#define RCC_APB2ENR_SAI2EN (1 << 23) -#define RCC_APB2ENR_SAI1EN (1 << 22) -#define RCC_APB2ENR_SPI6EN (1 << 21) -#define RCC_APB2ENR_SPI5EN (1 << 20) -#define RCC_APB2ENR_TIM11EN (1 << 18) -#define RCC_APB2ENR_TIM10EN (1 << 17) -#define RCC_APB2ENR_TIM9EN (1 << 16) -#define RCC_APB2ENR_SYSCFGEN (1 << 14) -#define RCC_APB2ENR_SPI4EN (1 << 13) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_SDMMC1EN (1 << 11) -#define RCC_APB2ENR_ADC3EN (1 << 10) -#define RCC_APB2ENR_ADC2EN (1 << 9) -#define RCC_APB2ENR_ADC1EN (1 << 8) -#define RCC_APB2ENR_USART6EN (1 << 5) -#define RCC_APB2ENR_USART1EN (1 << 4) -#define RCC_APB2ENR_TIM8EN (1 << 1) -#define RCC_APB2ENR_TIM1EN (1 << 0) -/**@}*/ - -/* --- RCC_AHB1LPENR values ------------------------------------------------- */ - -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) -#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) -#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) -#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) -#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) -#define RCC_AHB1LPENR_DMA2DLPEN (1 << 23) -#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) -#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) -#define RCC_AHB1LPENR_DTCMLPEN (1 << 20) -#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) -#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) -#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) -#define RCC_AHB1LPENR_AXILPEN (1 << 13) -#define RCC_AHB1LPENR_CRCLPEN (1 << 12) -#define RCC_AHB1LPENR_GPIOKLPEN (1 << 10) -#define RCC_AHB1LPENR_GPIOJLPEN (1 << 9) -#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) -#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) -#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) -#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) -#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) -#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) -#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) -#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) -#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) - -/* --- RCC_AHB2LPENR values ------------------------------------------------- */ - -#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) -#define RCC_AHB2LPENR_RNGLPEN (1 << 6) -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) -#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) -#define RCC_AHB2LPENR_DCMILPEN (1 << 0) - -/* --- RCC_AHB3LPENR values ------------------------------------------------- */ - -#define RCC_AHB3LPENR_QSPILPEN (1 << 1) -#define RCC_AHB3LPENR_FMCLPEN (1 << 0) - -/* --- RCC_APB1LPENR values ------------------------------------------------- */ - -#define RCC_APB1LPENR_UART8LPEN (1 << 31) -#define RCC_APB1LPENR_UART7LPEN (1 << 30) -#define RCC_APB1LPENR_DACLPEN (1 << 29) -#define RCC_APB1LPENR_PWRLPEN (1 << 28) -#define RCC_APB1LPENR_CECLPEN (1 << 27) -#define RCC_APB1LPENR_CAN2LPEN (1 << 26) -#define RCC_APB1LPENR_CAN1LPEN (1 << 25) -#define RCC_APB1LPENR_I2C4LPEN (1 << 24) -#define RCC_APB1LPENR_I2C3LPEN (1 << 23) -#define RCC_APB1LPENR_I2C2LPEN (1 << 22) -#define RCC_APB1LPENR_I2C1LPEN (1 << 21) -#define RCC_APB1LPENR_UART5LPEN (1 << 20) -#define RCC_APB1LPENR_UART4LPEN (1 << 19) -#define RCC_APB1LPENR_USART3LPEN (1 << 18) -#define RCC_APB1LPENR_USART2LPEN (1 << 17) -#define RCC_APB1LPENR_SPIDIFRXLPEN (1 << 16) -#define RCC_APB1LPENR_SPI3LPEN (1 << 15) -#define RCC_APB1LPENR_SPI2LPEN (1 << 14) -#define RCC_APB1LPENR_WWDGLPEN (1 << 11) -#define RCC_APB1LPENR_LPTIM1LPEN (1 << 9) -#define RCC_APB1LPENR_TIM14LPEN (1 << 8) -#define RCC_APB1LPENR_TIM13LPEN (1 << 7) -#define RCC_APB1LPENR_TIM12LPEN (1 << 6) -#define RCC_APB1LPENR_TIM7LPEN (1 << 5) -#define RCC_APB1LPENR_TIM6LPEN (1 << 4) -#define RCC_APB1LPENR_TIM5LPEN (1 << 3) -#define RCC_APB1LPENR_TIM4LPEN (1 << 2) -#define RCC_APB1LPENR_TIM3LPEN (1 << 1) -#define RCC_APB1LPENR_TIM2LPEN (1 << 0) - -/* --- RCC_APB2LPENR values ------------------------------------------------- */ - -#define RCC_APB2LPENR_LTDCLPEN (1 << 26) -#define RCC_APB2LPENR_SAI2LPEN (1 << 23) -#define RCC_APB2LPENR_SAI1LPEN (1 << 22) -#define RCC_APB2LPENR_SPI6LPEN (1 << 21) -#define RCC_APB2LPENR_SPI5LPEN (1 << 20) -#define RCC_APB2LPENR_TIM11LPEN (1 << 18) -#define RCC_APB2LPENR_TIM10LPEN (1 << 17) -#define RCC_APB2LPENR_TIM9LPEN (1 << 16) -#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) -#define RCC_APB2LPENR_SPI4LPEN (1 << 13) -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) -#define RCC_APB2LPENR_SDMMC1LPEN (1 << 11) -#define RCC_APB2LPENR_ADC3LPEN (1 << 10) -#define RCC_APB2LPENR_ADC2LPEN (1 << 9) -#define RCC_APB2LPENR_ADC1LPEN (1 << 8) -#define RCC_APB2LPENR_USART6LPEN (1 << 5) -#define RCC_APB2LPENR_USART1LPEN (1 << 4) -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -#define RCC_BDCR_RTCSEL_MASK 0x3 -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSE 3 -#define RCC_BDCR_LSEDRV_MASK 0x3 -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV_LOW 0 -#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */ -#define RCC_BDCR_LSEDRV_MEDL 2 -#define RCC_BDCR_LSEDRV_HIGH 3 -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_BORRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_BORRSTF) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- RCC_SSCGR values ---------------------------------------------------- */ - -#define RCC_SSCGR_SSCGEN (1 << 31) -#define RCC_SSCGR_SPREADSEL (1 << 30) -#define RCC_SSCGR_INCSTEP_MASK 0x7fff -#define RCC_SSCGR_INCSTEP_SHIFT 13 -#define RCC_SSCGR_MODPER_MASK 0x1fff -#define RCC_SSCGR_MODPER_SHIFT 0 - -/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ - -/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ -#define RCC_PLLI2SCFGR_PLLI2S_MASK 0x7 -#define RCC_PLLI2SCFGR_PLLI2S_SHIFT 28 -#define RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf -#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24 -#define RCC_PLLI2SCFGR_PLLI2SP_MASK 0x3 -#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT 16 -#define RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff -#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 - -/* --- RCC_PLLSAICFGR values ----------------------------------------------- */ - -#define RCC_PLLSAICFGR_PLLSAIR_MASK 0x7 -#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 -#define RCC_PLLSAICFGR_PLLSAIQ_MASK 0xf -#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24 -#define RCC_PLLSAICFGR_PLLSAIP_MASK 0x3 -#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 -#define RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF -#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 - -/* --- RCC_DCKCFGR1 values -------------------------------------------------- */ - -#define RCC_DCKCFGR1_TIMPRE (1<<24) -#define RCC_DCKCFGR1_SAI2SEL_MASK 0x3 -#define RCC_DCKCFGR1_SAI2SEL_SHIFT 22 -#define RCC_DCKCFGR1_SAI1SEL_MASK 0x3 -#define RCC_DCKCFGR1_SAI1SEL_SHIFT 20 -#define RCC_DCKCFGR1_PLLSAIDIVR_MASK 0x3 -#define RCC_DCKCFGR1_PLLSAIDIVR_SHIFT 16 -#define RCC_DCKCFGR1_PLLSAIDIVR_DIVR_2 0 -#define RCC_DCKCFGR1_PLLSAIDIVR_DIVR_4 1 -#define RCC_DCKCFGR1_PLLSAIDIVR_DIVR_8 2 -#define RCC_DCKCFGR1_PLLSAIDIVR_DIVR_16 3 -#define RCC_DCKCFGR1_PLLSAIDIVQ_MASK 0x1f -#define RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT 8 -#define RCC_DCKCFGR1_PLLI2SDIVQ_MASK 0x1f -#define RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT 0 - -/* --- RCC_DCKCFGR2 values -------------------------------------------------- */ - -#define RCC_DCKCFGR2_SDMMCSEL (1<<28) -#define RCC_DCKCFGR2_CK48MSEL (1<<27) -#define RCC_DCKCFGR2_CECSEL (1<<26) -#define RCC_DCKCFGR2_LPTIM1SEL_MASK 0x3 -#define RCC_DCKCFGR2_LPTIM1SEL_SHIFT 24 -#define RCC_DCKCFGR2_I2C4SEL_MASK 0x3 -#define RCC_DCKCFGR2_I2C4SEL_SHIFT 22 -#define RCC_DCKCFGR2_I2C3SEL_MASK 0x3 -#define RCC_DCKCFGR2_I2C3SEL_SHIFT 20 -#define RCC_DCKCFGR2_I2C2SEL_MASK 0x3 -#define RCC_DCKCFGR2_I2C2SEL_SHIFT 18 -#define RCC_DCKCFGR2_I2C1SEL_MASK 0x3 -#define RCC_DCKCFGR2_I2C1SEL_SHIFT 16 -#define RCC_DCKCFGR2_UART8SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART8SEL_SHIFT 14 -#define RCC_DCKCFGR2_UART7SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART7SEL_SHIFT 12 -#define RCC_DCKCFGR2_USART6SEL_MASK 0x3 -#define RCC_DCKCFGR2_USART6SEL_SHIFT 10 -#define RCC_DCKCFGR2_UART5SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART5SEL_SHIFT 8 -#define RCC_DCKCFGR2_UART4SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART4SEL_SHIFT 6 -#define RCC_DCKCFGR2_UART3SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART3SEL_SHIFT 4 -#define RCC_DCKCFGR2_UART2SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART2SEL_SHIFT 2 -#define RCC_DCKCFGR2_UART1SEL_MASK 0x3 -#define RCC_DCKCFGR2_UART1SEL_SHIFT 0 - -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -enum rcc_clock_3v3 { - RCC_CLOCK_3V3_216MHZ, - RCC_CLOCK_3V3_168MHZ, - RCC_CLOCK_3V3_120MHZ, - RCC_CLOCK_3V3_72MHZ, - RCC_CLOCK_3V3_48MHZ, - RCC_CLOCK_3V3_24MHZ, - RCC_CLOCK_3V3_END -}; - -struct rcc_clock_scale { - // PLLM not specified here because it depends on input clock freq. - uint16_t plln; - uint8_t pllp; - uint8_t pllq; - uint32_t flash_waitstates; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - enum pwr_vos_scale vos_scale; - uint8_t overdrive; - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; -}; - -extern const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END]; - -enum rcc_osc { - RCC_PLL, - RCC_HSE, - RCC_HSI, - RCC_LSE, - RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB1 peripherals*/ - RCC_GPIOA = _REG_BIT(0x30, 0), - RCC_GPIOB = _REG_BIT(0x30, 1), - RCC_GPIOC = _REG_BIT(0x30, 2), - RCC_GPIOD = _REG_BIT(0x30, 3), - RCC_GPIOE = _REG_BIT(0x30, 4), - RCC_GPIOF = _REG_BIT(0x30, 5), - RCC_GPIOG = _REG_BIT(0x30, 6), - RCC_GPIOH = _REG_BIT(0x30, 7), - RCC_GPIOI = _REG_BIT(0x30, 8), - RCC_GPIOJ = _REG_BIT(0x30, 9), - RCC_GPIOK = _REG_BIT(0x30, 10), - RCC_CRC = _REG_BIT(0x30, 12), - RCC_BKPSRAM = _REG_BIT(0x30, 18), - RCC_DTCMRAM = _REG_BIT(0x30, 20), - RCC_DMA1 = _REG_BIT(0x30, 21), - RCC_DMA2 = _REG_BIT(0x30, 22), - RCC_DMA2D = _REG_BIT(0x30, 23), - RCC_ETHMAC = _REG_BIT(0x30, 25), - RCC_ETHMACTX = _REG_BIT(0x30, 26), - RCC_ETHMACRX = _REG_BIT(0x30, 27), - RCC_ETHMACPTP = _REG_BIT(0x30, 28), - RCC_OTGHS = _REG_BIT(0x30, 29), - RCC_OTGHSULPI = _REG_BIT(0x30, 30), - - /* AHB2 peripherals */ - RCC_DCMI = _REG_BIT(0x34, 0), - RCC_CRYP = _REG_BIT(0x34, 4), - RCC_HASH = _REG_BIT(0x34, 5), - RCC_RNG = _REG_BIT(0x34, 6), - RCC_OTGFS = _REG_BIT(0x34, 7), - - /* AHB3 peripherals */ - RCC_QSPI = _REG_BIT(0x38, 1), - RCC_FMC = _REG_BIT(0x38, 0), - - /* APB1 peripherals*/ - RCC_TIM2 = _REG_BIT(0x40, 0), - RCC_TIM3 = _REG_BIT(0x40, 1), - RCC_TIM4 = _REG_BIT(0x40, 2), - RCC_TIM5 = _REG_BIT(0x40, 3), - RCC_TIM6 = _REG_BIT(0x40, 4), - RCC_TIM7 = _REG_BIT(0x40, 5), - RCC_TIM12 = _REG_BIT(0x40, 6), - RCC_TIM13 = _REG_BIT(0x40, 7), - RCC_TIM14 = _REG_BIT(0x40, 8), - RCC_LPTIM1 = _REG_BIT(0x40, 9), - RCC_WWDG = _REG_BIT(0x40, 11), - RCC_SPI2 = _REG_BIT(0x40, 14), - RCC_SPI3 = _REG_BIT(0x40, 15), - RCC_SPDIFRX = _REG_BIT(0x40, 16), - RCC_USART2 = _REG_BIT(0x40, 17), - RCC_USART3 = _REG_BIT(0x40, 18), - RCC_UART4 = _REG_BIT(0x40, 19), - RCC_UART5 = _REG_BIT(0x40, 20), - RCC_I2C1 = _REG_BIT(0x40, 21), - RCC_I2C2 = _REG_BIT(0x40, 22), - RCC_I2C3 = _REG_BIT(0x40, 23), - RCC_I2C4 = _REG_BIT(0x40, 24), - RCC_CAN1 = _REG_BIT(0x40, 25), - RCC_CAN2 = _REG_BIT(0x40, 26), - RCC_CEC = _REG_BIT(0x40, 27), - RCC_PWR = _REG_BIT(0x40, 28), - RCC_DAC = _REG_BIT(0x40, 29), - RCC_UART7 = _REG_BIT(0x40, 30), - RCC_UART8 = _REG_BIT(0x40, 31), - - /* APB2 peripherals */ - RCC_TIM1 = _REG_BIT(0x44, 0), - RCC_TIM8 = _REG_BIT(0x44, 1), - RCC_USART1 = _REG_BIT(0x44, 4), - RCC_USART6 = _REG_BIT(0x44, 5), - RCC_ADC1 = _REG_BIT(0x44, 8), - RCC_ADC2 = _REG_BIT(0x44, 9), - RCC_ADC3 = _REG_BIT(0x44, 10), - RCC_SDMMC1 = _REG_BIT(0x44, 11), - RCC_SPI1 = _REG_BIT(0x44, 12), - RCC_SPI4 = _REG_BIT(0x44, 13), - RCC_SYSCFG = _REG_BIT(0x44, 14), - RCC_TIM9 = _REG_BIT(0x44, 16), - RCC_TIM10 = _REG_BIT(0x44, 17), - RCC_TIM11 = _REG_BIT(0x44, 18), - RCC_SPI5 = _REG_BIT(0x44, 20), - RCC_SPI6 = _REG_BIT(0x44, 21), - RCC_SAI1EN = _REG_BIT(0x44, 22), - RCC_SAI2EN = _REG_BIT(0x44, 23), - RCC_LTDC = _REG_BIT(0x44, 26), - - - /* BDCR */ - RCC_RTC = _REG_BIT(0x70, 15), - - /* AHB1 peripherals*/ - SCC_GPIOA = _REG_BIT(0x50, 0), - SCC_GPIOB = _REG_BIT(0x50, 1), - SCC_GPIOC = _REG_BIT(0x50, 2), - SCC_GPIOD = _REG_BIT(0x50, 3), - SCC_GPIOE = _REG_BIT(0x50, 4), - SCC_GPIOF = _REG_BIT(0x50, 5), - SCC_GPIOG = _REG_BIT(0x50, 6), - SCC_GPIOH = _REG_BIT(0x50, 7), - SCC_GPIOI = _REG_BIT(0x50, 8), - SCC_GPIOJ = _REG_BIT(0x50, 9), - SCC_GPIOK = _REG_BIT(0x50, 10), - SCC_CRC = _REG_BIT(0x50, 12), - SCC_AXI = _REG_BIT(0x50, 13), - SCC_FLTIF = _REG_BIT(0x50, 15), - SCC_SRAM1 = _REG_BIT(0x50, 16), - SCC_SRAM2 = _REG_BIT(0x50, 17), - SCC_BKPSRAM = _REG_BIT(0x50, 18), - SCC_DTCM = _REG_BIT(0x50, 20), - SCC_DMA1 = _REG_BIT(0x50, 21), - SCC_DMA2 = _REG_BIT(0x50, 22), - SCC_DMA2D = _REG_BIT(0x50, 23), - SCC_ETHMAC = _REG_BIT(0x50, 25), - SCC_ETHMACTX = _REG_BIT(0x50, 26), - SCC_ETHMACRX = _REG_BIT(0x50, 27), - SCC_ETHMACPTP = _REG_BIT(0x50, 28), - SCC_OTGHS = _REG_BIT(0x50, 29), - SCC_OTGHSULPI = _REG_BIT(0x50, 30), - - /* AHB2 peripherals */ - SCC_DCMI = _REG_BIT(0x54, 0), - SCC_CRYP = _REG_BIT(0x54, 4), - SCC_HASH = _REG_BIT(0x54, 5), - SCC_RNG = _REG_BIT(0x54, 6), - SCC_OTGFS = _REG_BIT(0x54, 7), - - /* AHB3 peripherals */ - SCC_QSPI = _REG_BIT(0x58, 1), - SCC_FMC = _REG_BIT(0x58, 0), - - /* APB1 peripherals*/ - SCC_TIM2 = _REG_BIT(0x60, 0), - SCC_TIM3 = _REG_BIT(0x60, 1), - SCC_TIM4 = _REG_BIT(0x60, 2), - SCC_TIM5 = _REG_BIT(0x60, 3), - SCC_TIM6 = _REG_BIT(0x60, 4), - SCC_TIM7 = _REG_BIT(0x60, 5), - SCC_TIM12 = _REG_BIT(0x60, 6), - SCC_TIM13 = _REG_BIT(0x60, 7), - SCC_TIM14 = _REG_BIT(0x60, 8), - SCC_LPTIM1 = _REG_BIT(0x60, 9), - SCC_WWDG = _REG_BIT(0x60, 11), - SCC_SPI2 = _REG_BIT(0x60, 14), - SCC_SPI3 = _REG_BIT(0x60, 15), - SCC_SPDIFRX = _REG_BIT(0x60, 16), - SCC_USART2 = _REG_BIT(0x60, 17), - SCC_USART3 = _REG_BIT(0x60, 18), - SCC_UART4 = _REG_BIT(0x60, 19), - SCC_UART5 = _REG_BIT(0x60, 20), - SCC_I2C1 = _REG_BIT(0x60, 21), - SCC_I2C2 = _REG_BIT(0x60, 22), - SCC_I2C3 = _REG_BIT(0x60, 23), - SCC_I2C4 = _REG_BIT(0x60, 24), - SCC_CAN1 = _REG_BIT(0x60, 25), - SCC_CAN2 = _REG_BIT(0x60, 26), - SCC_CEC = _REG_BIT(0x60, 27), - SCC_PWR = _REG_BIT(0x60, 28), - SCC_DAC = _REG_BIT(0x60, 29), - SCC_UART7 = _REG_BIT(0x60, 30), - SCC_UART8 = _REG_BIT(0x60, 31), - - /* APB2 peripherals */ - SCC_TIM1 = _REG_BIT(0x64, 0), - SCC_TIM8 = _REG_BIT(0x64, 1), - SCC_USART1 = _REG_BIT(0x64, 4), - SCC_USART6 = _REG_BIT(0x64, 5), - SCC_ADC1 = _REG_BIT(0x64, 8), - SCC_ADC2 = _REG_BIT(0x64, 9), - SCC_ADC3 = _REG_BIT(0x64, 10), - SCC_SDMMC1 = _REG_BIT(0x64, 11), - SCC_SPI1 = _REG_BIT(0x64, 12), - SCC_SPI4 = _REG_BIT(0x64, 13), - SCC_SYSCFG = _REG_BIT(0x64, 14), - SCC_TIM9 = _REG_BIT(0x64, 16), - SCC_TIM10 = _REG_BIT(0x64, 17), - SCC_TIM11 = _REG_BIT(0x64, 18), - SCC_SPI5 = _REG_BIT(0x64, 20), - SCC_SPI6 = _REG_BIT(0x64, 21), - SCC_SAI1 = _REG_BIT(0x64, 22), - SCC_SAI2 = _REG_BIT(0x64, 23), - SCC_LTDC = _REG_BIT(0x64, 26), -}; - -enum rcc_periph_rst { - /* AHB1 peripherals*/ - RST_GPIOA = _REG_BIT(0x10, 0), - RST_GPIOB = _REG_BIT(0x10, 1), - RST_GPIOC = _REG_BIT(0x10, 2), - RST_GPIOD = _REG_BIT(0x10, 3), - RST_GPIOE = _REG_BIT(0x10, 4), - RST_GPIOF = _REG_BIT(0x10, 5), - RST_GPIOG = _REG_BIT(0x10, 6), - RST_GPIOH = _REG_BIT(0x10, 7), - RST_GPIOI = _REG_BIT(0x10, 8), - RST_GPIOJ = _REG_BIT(0x10, 9), - RST_GPIOK = _REG_BIT(0x10, 10), - RST_CRC = _REG_BIT(0x10, 12), - RST_DMA1 = _REG_BIT(0x10, 21), - RST_DMA2 = _REG_BIT(0x10, 22), - RST_DMA2D = _REG_BIT(0x10, 23), - RST_ETHMAC = _REG_BIT(0x10, 25), - RST_OTGHS = _REG_BIT(0x10, 29), - - /* AHB2 peripherals */ - RST_DCMI = _REG_BIT(0x14, 0), - RST_CRYP = _REG_BIT(0x14, 4), - RST_HASH = _REG_BIT(0x14, 5), - RST_RNG = _REG_BIT(0x14, 6), - RST_OTGFS = _REG_BIT(0x14, 7), - - /* AHB3 peripherals */ - RST_QSPI = _REG_BIT(0x18, 1), - RST_FMC = _REG_BIT(0x18, 0), - - /* APB1 peripherals*/ - RST_TIM2 = _REG_BIT(0x20, 0), - RST_TIM3 = _REG_BIT(0x20, 1), - RST_TIM4 = _REG_BIT(0x20, 2), - RST_TIM5 = _REG_BIT(0x20, 3), - RST_TIM6 = _REG_BIT(0x20, 4), - RST_TIM7 = _REG_BIT(0x20, 5), - RST_TIM12 = _REG_BIT(0x20, 6), - RST_TIM13 = _REG_BIT(0x20, 7), - RST_TIM14 = _REG_BIT(0x20, 8), - RST_LPTIM1 = _REG_BIT(0x20, 9), - RST_WWDG = _REG_BIT(0x20, 11), - RST_SPI2 = _REG_BIT(0x20, 14), - RST_SPI3 = _REG_BIT(0x20, 15), - RST_SPDIFRX = _REG_BIT(0x20, 16), - RST_UART2 = _REG_BIT(0x20, 17), - RST_UART3 = _REG_BIT(0x20, 18), - RST_UART4 = _REG_BIT(0x20, 19), - RST_UART5 = _REG_BIT(0x20, 20), - RST_I2C1 = _REG_BIT(0x20, 21), - RST_I2C2 = _REG_BIT(0x20, 22), - RST_I2C3 = _REG_BIT(0x20, 23), - RST_I2C4 = _REG_BIT(0x20, 24), - RST_CAN1 = _REG_BIT(0x20, 25), - RST_CAN2 = _REG_BIT(0x20, 26), - RST_CEC = _REG_BIT(0x20, 27), - RST_PWR = _REG_BIT(0x20, 28), - RST_DAC = _REG_BIT(0x20, 29), - RST_UART7 = _REG_BIT(0x20, 30), - RST_UART8 = _REG_BIT(0x20, 31), - - /* APB2 peripherals */ - RST_TIM1 = _REG_BIT(0x24, 0), - RST_TIM8 = _REG_BIT(0x24, 1), - RST_USART1 = _REG_BIT(0x24, 4), - RST_USART6 = _REG_BIT(0x24, 5), - RST_ADC = _REG_BIT(0x24, 8), - RST_SDMMC1 = _REG_BIT(0x24, 11), - RST_SPI1 = _REG_BIT(0x24, 12), - RST_SPI4 = _REG_BIT(0x24, 13), - RST_SYSCFG = _REG_BIT(0x24, 14), - RST_TIM9 = _REG_BIT(0x24, 16), - RST_TIM10 = _REG_BIT(0x24, 17), - RST_TIM11 = _REG_BIT(0x24, 18), - RST_SPI5 = _REG_BIT(0x24, 20), - RST_SPI6 = _REG_BIT(0x24, 21), - RST_SAI1RST = _REG_BIT(0x24, 22), - RST_SAI2RST = _REG_BIT(0x24, 23), - RST_LTDC = _REG_BIT(0x24, 26), -}; - -#undef _REG_BIT - -#include - -BEGIN_DECLS -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_rtcpre(uint32_t rtcpre); -void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq); -void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, - uint32_t pllq); -uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz); -void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock); -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/rng.h b/libopencm3/include/libopencm3/stm32/f7/rng.h deleted file mode 100644 index 09d014d..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/rng.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/spi.h b/libopencm3/include/libopencm3/stm32/f7/spi.h deleted file mode 100644 index 5952876..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32F7xx SPI - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@date 28 August 2018 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/f7/syscfg.h b/libopencm3/include/libopencm3/stm32/f7/syscfg.h deleted file mode 100644 index 48735ac..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/syscfg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32F7xx_defines - * - * @brief Defined Constants and Types for the STM32F7xx Sysconfig - * - * @version 1.0.0 - * - * @date 11 April 2019 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/timer.h b/libopencm3/include/libopencm3/stm32/f7/timer.h deleted file mode 100644 index da89094..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/timer.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32F7xx Timers - -@ingroup STM32F7xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2018 Karl Palsson - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2018 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/f7/usart.h b/libopencm3/include/libopencm3/stm32/f7/usart.h deleted file mode 100644 index df496a0..0000000 --- a/libopencm3/include/libopencm3/stm32/f7/usart.h +++ /dev/null @@ -1,60 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32F7xx USART - * - * @ingroup STM32F7xx_defines - * - * @version 1.0.0 - * - * @date 5 December 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/**@{*/ - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -#define USART6 USART6_BASE -#define UART7 UART7_BASE -#define UART8 UART8_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/flash.h b/libopencm3/include/libopencm3/stm32/flash.h deleted file mode 100644 index 7da5a69..0000000 --- a/libopencm3/include/libopencm3/stm32/flash.h +++ /dev/null @@ -1,50 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#elif defined(GD32F1X0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/fsmc.h b/libopencm3/include/libopencm3/stm32/fsmc.h deleted file mode 100644 index c3a0aee..0000000 --- a/libopencm3/include/libopencm3/stm32/fsmc.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FSMC_H -#define LIBOPENCM3_FSMC_H - -#include -#include - -#if defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32H7) -# include -#endif - -/* --- Convenience macros -------------------------------------------------- */ -#define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */ -#define FSMC_BANK2_BASE 0x70000000U /* NAND flash (reserved in F7) */ -#define FSMC_BANK3_BASE 0x80000000U /* NAND flash */ -#define FSMC_BANK4_BASE 0x90000000U /* PC card (reserved in F7) */ - -/* --- FSMC registers ------------------------------------------------------ */ - -/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x)) -#define FSMC_BCR1 FSMC_BCR(0) -#define FSMC_BCR2 FSMC_BCR(1) -#define FSMC_BCR3 FSMC_BCR(2) -#define FSMC_BCR4 FSMC_BCR(3) - -/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x)) -#define FSMC_BTR1 FSMC_BTR(0) -#define FSMC_BTR2 FSMC_BTR(1) -#define FSMC_BTR3 FSMC_BTR(2) -#define FSMC_BTR4 FSMC_BTR(3) - -/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x)) -#define FSMC_BWTR1 FSMC_BWTR(0) -#define FSMC_BWTR2 FSMC_BWTR(1) -#define FSMC_BWTR3 FSMC_BWTR(2) -#define FSMC_BWTR4 FSMC_BWTR(3) - -/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x)) -#define FSMC_PCR2 FSMC_PCR(1) -#define FSMC_PCR3 FSMC_PCR(2) -#define FSMC_PCR4 FSMC_PCR(3) - -/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x)) -#define FSMC_SR2 FSMC_SR(1) -#define FSMC_SR3 FSMC_SR(2) -#define FSMC_SR4 FSMC_SR(3) - -/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x)) -#define FSMC_PMEM2 FSMC_PMEM(1) -#define FSMC_PMEM3 FSMC_PMEM(2) -#define FSMC_PMEM4 FSMC_PMEM(3) - -/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x)) -#define FSMC_PATT2 FSMC_PATT(1) -#define FSMC_PATT3 FSMC_PATT(2) -#define FSMC_PATT4 FSMC_PATT(3) - -/* I/O space timing register 4 (FSMC_PIO4) */ -#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) - -/* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x)) -#define FSMC_ECCR2 FSMC_ECCR(1) -#define FSMC_ECCR3 FSMC_ECCR(2) - -/* --- FSMC_BCRx values ---------------------------------------------------- */ - -/* Bits [31:20]: Reserved. */ - -/* CBURSTRW: Write burst enable */ -#define FSMC_BCR_CBURSTRW (1 << 19) - -/* Bits [18:16]: Reserved. */ - -/* ASYNCWAIT: Wait signal during asynchronous transfers */ -#define FSMC_BCR_ASYNCWAIT (1 << 15) - -/* EXTMOD: Extended mode enable */ -#define FSMC_BCR_EXTMOD (1 << 14) - -/* WAITEN: Wait enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) - -/* WREN: Write enable bit */ -#define FSMC_BCR_WREN (1 << 12) - -/* WAITCFG: Wait timing configuration */ -#define FSMC_BCR_WAITCFG (1 << 11) - -/* WRAPMOD: Wrapped burst mode support */ -#define FSMC_BCR_WRAPMOD (1 << 10) - -/* WAITPOL: Wait signal polarity bit */ -#define FSMC_BCR_WAITPOL (1 << 9) - -/* BURSTEN: Burst enable bit */ -#define FSMC_BCR_BURSTEN (1 << 8) - -/* Bit 7: Reserved. */ - -/* FACCEN: Flash access enable */ -#define FSMC_BCR_FACCEN (1 << 6) - -/* MWID[5:4]: Memory data bus width */ -#define FSMC_BCR_MWID (1 << 4) - -/* MTYP[3:2]: Memory type */ -#define FSMC_BCR_MTYP (1 << 2) - -/* MUXEN: Address/data multiplexing enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) - -/* MBKEN: Memory bank enable bit */ -#define FSMC_BCR_MBKEN (1 << 0) - -/* --- FSMC_BTRx values ---------------------------------------------------- */ - -/* Bits [31:30]: Reserved. */ - -/* Same for read and write */ -#define FSMC_BTx_ACCMOD_A (0) -#define FSMC_BTx_ACCMOD_B (1) -#define FSMC_BTx_ACCMOD_C (2) -#define FSMC_BTx_ACCMOD_D (3) - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BTR_ACCMOD (1 << 28) -#define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ -#define FSMC_BTR_DATLAT (1 << 24) -#define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BTR_CLKDIV (1 << 20) -#define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20) - -/* BUSTURN[19:16]: Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN (1 << 16) -#define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16) - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BTR_DATAST (1 << 8) -#define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BTR_ADDHLD (1 << 4) -#define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BTR_ADDSET (1 << 0) -#define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0) - -/* --- FSMC_BWTRx values --------------------------------------------------- */ - -/* Bits [31:30]: Reserved. */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BWTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ -#define FSMC_BWTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BWTR_CLKDIV (1 << 20) - -/* Bits [19..16]: Reserved. */ - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BWTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BWTR_ADDSET (1 << 0) - -/* --- FSMC_PCRx values ---------------------------------------------------- */ - -/* Bits [31:20]: Reserved. */ - -/* ECCPS[19:17]: ECC page size */ -#define FSMC_PCR_ECCPS (1 << 17) - -/* TAR[16:13]: ALE to RE delay */ -#define FSMC_PCR_TAR (1 << 13) - -/* TCLR[12:9]: CLE to RE delay */ -#define FSMC_PCR_TCLR (1 << 9) - -/* Bits [8..7]: Reserved. */ - -/* ECCEN: ECC computation logic enable bit */ -#define FSMC_PCR_ECCEN (1 << 6) - -/* PWID[5:4]: Databus width */ -#define FSMC_PCR_PWID (1 << 4) - -/* PTYP: Memory type */ -#define FSMC_PCR_PTYP (1 << 3) - -/* PBKEN: PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) - -/* PWAITEN: Wait feature enable bit */ -#define FSMC_PCR_PWAITEN (1 << 1) - -/* Bit 0: Reserved. */ - -/* --- FSMC_SRx values ----------------------------------------------------- */ - -/* Bits [31:7]: Reserved. */ - -/* FEMPT: FIFO empty */ -#define FSMC_SR_FEMPT (1 << 6) - -/* IFEN: Interrupt falling edge detection enable bit */ -#define FSMC_SR_IFEN (1 << 5) - -/* ILEN: Interrupt high-level detection enable bit */ -#define FSMC_SR_ILEN (1 << 4) - -/* IREN: Interrupt rising edge detection enable bit */ -#define FSMC_SR_IREN (1 << 3) - -/* IFS: Interrupt falling edge status */ -#define FSMC_SR_IFS (1 << 2) - -/* ILS: Interrupt high-level status */ -#define FSMC_SR_ILS (1 << 1) - -/* IRS: Interrupt rising edge status */ -#define FSMC_SR_IRS (1 << 0) - -/* --- FSMC_PMEMx values --------------------------------------------------- */ - -/* MEMHIZx[31:24]: Common memory x databus HiZ time */ -#define FSMC_PMEM_MEMHIZX (1 << 24) - -/* MEMHOLDx[23:16]: Common memory x hold time */ -#define FSMC_PMEM_MEMHOLDX (1 << 16) - -/* MEMWAITx[15:8]: Common memory x wait time */ -#define FSMC_PMEM_MEMWAITX (1 << 8) - -/* MEMSETx[7:0]: Common memory x setup time */ -#define FSMC_PMEM_MEMSETX (1 << 0) - -/* --- FSMC_PATTx values --------------------------------------------------- */ - -/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ -#define FSMC_PATT_ATTHIZX (1 << 24) - -/* ATTHOLDx[23:16]: Attribute memory x hold time */ -#define FSMC_PATT_ATTHOLDX (1 << 16) - -/* ATTWAITx[15:8]: Attribute memory x wait time */ -#define FSMC_PATT_ATTWAITX (1 << 8) - -/* ATTSETx[7:0]: Attribute memory x setup time */ -#define FSMC_PATT_ATTSETX (1 << 0) - -/* --- FSMC_PIO4 values ---------------------------------------------------- */ - -/* IOHIZx[31:24]: I/O x databus HiZ time */ -#define FSMC_PIO4_IOHIZX (1 << 24) - -/* IOHOLDx[23:16]: I/O x hold time */ -#define FSMC_PIO4_IOHOLDX (1 << 16) - -/* IOWAITx[15:8]: I/O x wait time */ -#define FSMC_PIO4_IOWAITX (1 << 8) - -/* IOSETx[7:0]: I/O x setup time */ -#define FSMC_PIO4_IOSETX (1 << 0) - -/* --- FSMC_ECCRx values --------------------------------------------------- */ - -/* ECCx[31:0]: ECC result */ -#define FSMC_ECCR_ECCX (1 << 0) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/adc.h b/libopencm3/include/libopencm3/stm32/g0/adc.h deleted file mode 100644 index b40e32b..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/adc.h +++ /dev/null @@ -1,328 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @ingroup STM32G0xx_defines -* - * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot - * - * @brief Defined Constants and Types for the STM32STM32G0xx Analog to Digital Converter - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/** @defgroup adc_reg_base ADC register base addresses - *@{*/ -#define ADC1 ADC1_BASE -/**@}*/ - -/** @defgroup adc_channel ADC Channel Numbers - *@{*/ -#define ADC_CHANNEL_TEMP 12 -#define ADC_CHANNEL_VREF 13 -#define ADC_CHANNEL_VBAT 14 -/**@}*/ - -/** @addtogroup adc_registers - *@{*/ -/* ----- ADC registers -----------------------------------------------------*/ -/** ADC_AWD1TR Watchdog 1 Threshold register */ -#define ADC_AWD1TR(adc) MMIO32((adc) + 0x20) -/** ADC_AWD2TR Watchdog 2 Threshold register */ -#define ADC_AWD2TR(adc) MMIO32((adc) + 0x22) -/** ADC_AWD3TR Watchdog 3 Threshold register */ -#define ADC_AWD3TR(adc) MMIO32((adc) + 0x2c) - -/** ADC_AWD2CR Watchdog 2 Configuration register */ -#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0) -/** ADC_AWD3CR Watchdog 3 Configuration register */ -#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4) - -/** ADC_CALFACT Calibration factor register */ -#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4) - -/** ADC_OR Option register */ -#define ADC_OR(adc) MMIO32((adc) + 0xD0) -/**@}*/ - -/* --- Register values -------------------------------------------------------*/ - -/** @addtogroup adc_isr -@{*/ - -/** CCRDY: Channel Configuration Ready flag */ -#define ADC_ISR_CCRDY (1 << 13) - -/**@}*/ - -/** @addtogroup adc_ier -@{*/ - -/** CCRDYIE: Channel Configuration Ready Interrupt enable bit */ -#define ADC_IER_CCRDYIE (1 << 13) - -/**@}*/ - -/** @addtogroup adc_ccr -@{*/ - -#define ADC_CCR_PRESC_MASK (0xf) -#define ADC_CCR_PRESC_SHIFT (18) -/** @defgroup adc_ccr_presc ADC clock prescaler - *@{*/ -#define ADC_CCR_PRESC_NODIV (0x0) -#define ADC_CCR_PRESC_DIV1 (0x1) -#define ADC_CCR_PRESC_DIV2 (0x2) -#define ADC_CCR_PRESC_DIV6 (0x3) -#define ADC_CCR_PRESC_DIV8 (0x4) -#define ADC_CCR_PRESC_DIV10 (0x5) -#define ADC_CCR_PRESC_DIV12 (0x6) -#define ADC_CCR_PRESC_DIV16 (0x7) -#define ADC_CCR_PRESC_DIV32 (0x8) -#define ADC_CCR_PRESC_DIV64 (0x9) -#define ADC_CCR_PRESC_DIV128 (0x10) -#define ADC_CCR_PRESC_DIV256 (0x11) -/**@}*/ - -/**@}*/ - -/** @addtogroup adc_cr -@{*/ - -/** ADVREGEN: Voltage regulator enable bit */ -#define ADC_CR_ADVREGEN (1 << 28) - -/**@}*/ - -/** @addtogroup adc_cfgr1 -@{*/ - -/** CHSELRMOD: Mode Selection of the ADC_CHSELR register */ -#define ADC_CFGR1_CHSELRMOD (1 << 21) - -/**@}*/ - -/** @addtogroup adc_cfgr2 -@{*/ - -#define ADC_CFGR2_CKMODE_SHIFT (30) -#define ADC_CFGR2_CKMODE_MASK (0x3) -/** @defgroup adc_cfgr2_ckmode ADC Clock mode - *@{*/ -#define ADC_CFGR2_CKMODE_ADCCLK (0x0) -#define ADC_CFGR2_CKMODE_PCLK_DIV2 (0x1) -#define ADC_CFGR2_CKMODE_PCLK_DIV4 (0x2) -#define ADC_CFGR2_CKMODE_PCLK (0x3) -/**@}*/ - -/** LFTRIG: Low Frequency Trigger Mode enable bit */ -#define ADC_CFGR2_LFTRIG (1 << 29) - -/** TOVS: Triggered Oversampling */ -#define ADC_CFGR2_TOVS (1 << 9) - -#define ADC_CFGR2_OVSS_SHIFT (5) -#define ADC_CFGR2_OVSS_MASK (0xf) -/** @defgroup adc_cfgr2_ovss ADC Oversampling shift - *@{*/ -#define ADC_CFGR2_OVSS_BITS(bits) (bits) -/**@}*/ - -#define ADC_CFGR2_OVSR_SHIFT (2) -#define ADC_CFGR2_OVSR_MASK (0x7) -/** @defgroup adc_cfgr2_ovsr ADC Oversampling ratio - *@{*/ -#define ADC_CFGR2_OVSR_2x (0x0) -#define ADC_CFGR2_OVSR_4x (0x1) -#define ADC_CFGR2_OVSR_8x (0x2) -#define ADC_CFGR2_OVSR_16x (0x3) -#define ADC_CFGR2_OVSR_32x (0x4) -#define ADC_CFGR2_OVSR_64x (0x5) -#define ADC_CFGR2_OVSR_128x (0x6) -#define ADC_CFGR2_OVSR_256x (0x7) -/**@}*/ - -/** OVSE: Oversampler mode enable bit */ -#define ADC_CFGR2_OVSE (1 << 0) - -/**@}*/ - -/** @addtogroup adc_smpr -@{*/ - -/* SMP1 ADC Channel Sample Time selection */ -#define ADC_SMPR_SMPSEL_SHIFT 0x8 -#define ADC_SMPR_SMPSEL_MASK 0x7ffff -#define ADC_SMPR_SMPSEL_CHANNEL_SHIFT(channel) ((channel) + ADC_SMPR_SMPSEL_SHIFT) -#define ADC_SMPR_SMPSEL_CHANNEL_MASK (1) -/** @defgroup adc_smpr_smpsel ADC Sample Time selection -@{*/ -#define ADC_SMPR_SMPSEL_SMP1 0x0 -#define ADC_SMPR_SMPSEL_SMP2 0x1 -/**@}*/ - -/** SMP1 ADC Sample Time #1 selection */ -#define ADC_SMPR_SMP1_SHIFT 0x0 -#define ADC_SMPR_SMP1_MASK 0x7 - -/** SMP1 ADC Sample Time #2 selection */ -#define ADC_SMPR_SMP2_SHIFT 0x4 -#define ADC_SMPR_SMP2_MASK 0x7 - -/** @defgroup adc_smpr_smp ADC Sample Time selection values -@{*/ -#define ADC_SMPR_SMPx_001DOT5CYC 0x0 -#define ADC_SMPR_SMPx_003DOT5CYC 0x1 -#define ADC_SMPR_SMPx_007DOT5CYC 0x2 -#define ADC_SMPR_SMPx_012DOT5CYC 0x3 -#define ADC_SMPR_SMPx_019DOT5CYC 0x4 -#define ADC_SMPR_SMPx_039DOT5CYC 0x5 -#define ADC_SMPR_SMPx_079DOT5CYC 0x6 -#define ADC_SMPR_SMPx_160DOT5CYC 0x7 -/**@}*/ - -/**@}*/ - -/** @defgroup adc_awdtr1 AWDTR1 ADC watchdog threshold register 1 -* Shadows adc adc_tr1 register on other chips. -@{*/ - -#define ADC_AWDTR1_LT_SHIFT 0 -#define ADC_AWDTR1_LT (0xFFF << ADC_TR1_LT_SHIFT) -#define ADC_AWDTR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT) - -#define ADC_AWDTR1_HT_SHIFT 16 -#define ADC_AWDTR1_HT (0xFFF << ADC_TR1_HT_SHIFT) -#define ADC_AWDTR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT) - -/**@}*/ - -/** @defgroup adc_awdtr2 AWDTR2 ADC watchdog threshold register 2 -@{*/ - -#define ADC_AWDTR2_LT_SHIFT 0 -#define ADC_AWDTR2_LT (0xFFF << ADC_TR2_LT_SHIFT) -#define ADC_AWDTR2_LT_VAL(x) ((x) << ADC_TR2_LT_SHIFT) - -#define ADC_AWDTR2_HT_SHIFT 16 -#define ADC_AWDTR2_HT (0xFFF << ADC_TR2_HT_SHIFT) -#define ADC_AWDTR2_HT_VAL(x) ((x) << ADC_TR2_HT_SHIFT) - -/**@}*/ - -/** @addtogroup adc_chselr -@{*/ - -/** ADC_CHSELR_MAX_CHANNELS Maximum number of channel in regular sequence */ -#define ADC_CHSELR_MAX_CHANNELS 18 - -/** ADC_CHSELR_MAX_SQ_CHANNELS Maximum number of sequences in fully configurable mode */ -#define ADC_CHSELR_MAX_SQS 8 -/** ADC_CHSELR_SQS_MAX_CHANNEL Maximum channel number in a fully configuralbe sequence */ -#define ADC_CHSELR_SQS_MAX_CHANNEL 14 - -#define ADC_CHSELR_SQx_MASK 0xf -#define ADC_CHSELR_SQx_SHIFT(seqnum) (4 * ((seqnum)-1)) - -/** ADC_CHSELR_SQx Xth conversion of ADC sequence channel number value */ -#define ADC_CHSELR_SQx(seqnum, value) ((value) << ADC_CHSELR_SQx_SHIFT(seqnum)) - -/** ADC_CHSELR_SQx_EOS End of Sequence */ -#define ADC_CHSELR_SQx_EOS 0xf - -/**@}*/ - -/** @defgroup adc_awdtr2 AWDTR2 ADC watchdog threshold register 2 -@{*/ - -#define ADC_AWDTR3_LT_SHIFT 0 -#define ADC_AWDTR3_LT (0xFFF << ADC_TR3_LT_SHIFT) -#define ADC_AWDTR3_LT_VAL(x) ((x) << ADC_TR3_LT_SHIFT) - -#define ADC_AWDTR3_HT_SHIFT 16 -#define ADC_AWDTR3_HT (0xFFF << ADC_TR3_HT_SHIFT) -#define ADC_AWDTR3_HT_VAL(x) ((x) << ADC_TR3_HT_SHIFT) - -/**@}*/ - -/** @defgroup adc_awd2cr AWD2CR ADC Analog watchdog 2 configuration register -@{*/ - -/** AWD2CR Analog watchdog channel selection */ -#define ADC_AW2CR_AWD2CHx_EN(x) (1 << x) - -/**@}*/ - -/** @defgroup adc_awd3cr AWD3CR ADC Analog watchdog 3 configuration register -@{*/ - -/** AWD3CR Analog watchdog channel selection */ -#define ADC_AW3CR_AWD3CHx_EN(x) (1 << x) - -/**@}*/ - -/* --- API definition ----------------------------------------------------- */ - -/** @defgroup adc_api_clksource ADC clock source - *@{*/ -#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_ADCCLK -#define ADC_CLKSOURCE_PCLK ADC_CFGR2_CKMODE_PCLK -#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2 -#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4 -/**@}*/ - -/** @defgroup adc_api_smptime ADC Sampling Time - *@{*/ -#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMPx_001DOT5CYC -#define ADC_SMPTIME_003DOT5 ADC_SMPR_SMPx_003DOT5CYC -#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMPx_007DOT5CYC -#define ADC_SMPTIME_012DOT5 ADC_SMPR_SMPx_012DOT5CYC -#define ADC_SMPTIME_019DOT5 ADC_SMPR_SMPx_019DOT5CYC -#define ADC_SMPTIME_039DOT5 ADC_SMPR_SMPx_039DOT5CYC -#define ADC_SMPTIME_079DOT5 ADC_SMPR_SMPx_079DOT5CYC -#define ADC_SMPTIME_160DOT5 ADC_SMPR_SMPx_160DOT5CYC -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void adc_set_clk_source(uint32_t adc, uint32_t source); -void adc_set_clk_prescale(uint32_t adc, uint32_t prescale); - -void adc_set_channel_sample_time_selection(uint32_t adc, uint8_t channel, uint8_t selection); -void adc_set_selection_sample_time(uint32_t adc, uint8_t selection, uint8_t time); - -void adc_enable_regulator(uint32_t adc); -void adc_disable_regulator(uint32_t adc); - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/g0/crc.h b/libopencm3/include/libopencm3/stm32/g0/crc.h deleted file mode 100644 index 43d689d..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/crc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief Defined Constants and Types for the STM32G0xx CRC Generator - * - * @ingroup STM32G0xx_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/dma.h b/libopencm3/include/libopencm3/stm32/g0/dma.h deleted file mode 100644 index 9d03346..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/dma.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx DMA Controller - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/dmamux.h b/libopencm3/include/libopencm3/stm32/g0/dmamux.h deleted file mode 100644 index 2777534..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/dmamux.h +++ /dev/null @@ -1,172 +0,0 @@ -/** @defgroup dmamux_defines DMAMUX Defines - * - * @ingroup STM32G0xx_defines - * - * @author @htmlonly © @endhtmlonly 2019 - * Guillaume Revaillot - * - * @brief Defined Constants and Types for the STM32G0xx DMAMUX DMA request router - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMAMUX_H -#define LIBOPENCM3_DMAMUX_H -/**@{*/ - -#include - - /** @defgroup dmamux_reg_base DMAMUX register base addresses - * @{ - */ -#define DMAMUX1 DMAMUX_BASE -/**@}*/ - -/* --- DMAMUX_CxCR values ------------------------------------ */ - -/** @defgroup dmamux_cxcr_sync_id SYNCID Synchronization input selected -@{*/ -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE0 0 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE1 1 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE2 2 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE3 3 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE4 4 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE5 5 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE6 6 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE7 7 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE8 8 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE9 9 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE10 10 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE11 11 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE12 12 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE13 13 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE14 14 -#define DMAMUX_CxCR_SYNC_ID_EXTI_LINE15 15 -#define DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT0 16 -#define DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT1 17 -#define DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT2 18 -#define DMAMUX_CxCR_SYNC_ID_DMAMUX_EVT3 19 -#define DMAMUX_CxCR_SYNC_ID_LPTIM1_OUT 20 -#define DMAMUX_CxCR_SYNC_ID_LPTIM2_OUT 21 -#define DMAMUX_CxCR_SYNC_ID_TIM14_OC 22 -#define DMAMUX_CxCR_SYNC_ID_RESERVED23 23 -/**@}*/ - -/** @defgroup dmamux_cxcr_dmareq_id DMAREQID DMA request line selected -@{*/ -#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN0 1 -#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN1 2 -#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN2 3 -#define DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN3 4 -#define DMAMUX_CxCR_DMAREQ_ID_ADC 5 -#define DMAMUX_CxCR_DMAREQ_ID_AES_IN 6 -#define DMAMUX_CxCR_DMAREQ_ID_AES_OUT 7 -#define DMAMUX_CxCR_DMAREQ_ID_DAC_Channel1 8 -#define DMAMUX_CxCR_DMAREQ_ID_DAC_Channel2 9 -#define DMAMUX_CxCR_DMAREQ_ID_I2C1_RX 10 -#define DMAMUX_CxCR_DMAREQ_ID_I2C1_TX 11 -#define DMAMUX_CxCR_DMAREQ_ID_I2C2_RX 12 -#define DMAMUX_CxCR_DMAREQ_ID_I2C2_TX 13 -#define DMAMUX_CxCR_DMAREQ_ID_LPUART_RX 14 -#define DMAMUX_CxCR_DMAREQ_ID_LPUART_TX 15 -#define DMAMUX_CxCR_DMAREQ_ID_SPI1_RX 16 -#define DMAMUX_CxCR_DMAREQ_ID_SPI1_TX 17 -#define DMAMUX_CxCR_DMAREQ_ID_SPI2_RX 18 -#define DMAMUX_CxCR_DMAREQ_ID_SPI2_TX 19 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH1 20 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH2 21 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH3 22 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_CH4 23 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_TRIG_COM 24 -#define DMAMUX_CxCR_DMAREQ_ID_TIM1_UP 25 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH1 26 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH2 27 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH3 28 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_CH4 29 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_TRIG 30 -#define DMAMUX_CxCR_DMAREQ_ID_TIM2_UP 31 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH1 32 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH2 33 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH3 34 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_CH4 35 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_TRIG 36 -#define DMAMUX_CxCR_DMAREQ_ID_TIM3_UP 37 -#define DMAMUX_CxCR_DMAREQ_ID_TIM6_UP 38 -#define DMAMUX_CxCR_DMAREQ_ID_TIM7_UP 39 -#define DMAMUX_CxCR_DMAREQ_ID_TIM15_CH1 40 -#define DMAMUX_CxCR_DMAREQ_ID_TIM15_CH2 41 -#define DMAMUX_CxCR_DMAREQ_ID_TIM15_TRIG_COM 42 -#define DMAMUX_CxCR_DMAREQ_ID_TIM15_UP 43 -#define DMAMUX_CxCR_DMAREQ_ID_TIM16_CH1 44 -#define DMAMUX_CxCR_DMAREQ_ID_TIM16_TRIG_COM 45 -#define DMAMUX_CxCR_DMAREQ_ID_TIM16_UP 46 -#define DMAMUX_CxCR_DMAREQ_ID_TIM17_CH1 47 -#define DMAMUX_CxCR_DMAREQ_ID_TIM17_TRIG_COM 48 -#define DMAMUX_CxCR_DMAREQ_ID_TIM17_UP 49 -#define DMAMUX_CxCR_DMAREQ_ID_USART1_RX 50 -#define DMAMUX_CxCR_DMAREQ_ID_USART1_TX 51 -#define DMAMUX_CxCR_DMAREQ_ID_USART2_RX 52 -#define DMAMUX_CxCR_DMAREQ_ID_USART2_TX 53 -#define DMAMUX_CxCR_DMAREQ_ID_USART3_RX 54 -#define DMAMUX_CxCR_DMAREQ_ID_USART3_TX 55 -#define DMAMUX_CxCR_DMAREQ_ID_USART4_RX 56 -#define DMAMUX_CxCR_DMAREQ_ID_USART4_TX 57 -#define DMAMUX_CxCR_DMAREQ_ID_UCPD1_RX 58 -#define DMAMUX_CxCR_DMAREQ_ID_UCPD1_TX 59 -#define DMAMUX_CxCR_DMAREQ_ID_UCPD2_RX 60 -#define DMAMUX_CxCR_DMAREQ_ID_UCPD2_TX 61 -#define DMAMUX_CxCR_DMAREQ_ID_RESERVED62 62 -#define DMAMUX_CxCR_DMAREQ_ID_RESERVED63 63 -/**@}*/ - -/* --- DMAMUX_RGxCR values ----------------------------------- */ - -/** @defgroup dmamux_rgxcr_sig_id SIGID DMA request trigger input selected -@{*/ -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE0 0 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE1 1 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE2 2 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE3 3 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE4 4 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE5 5 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE6 6 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE7 7 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE8 8 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE9 9 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE10 10 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE11 11 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE12 12 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE13 13 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE14 14 -#define DMAMUX_RGxCR_SIG_ID_EXTI_LINE15 15 -#define DMAMUX_RGxCR_SIG_ID_DMAMUX_EVT0 16 -#define DMAMUX_RGxCR_SIG_ID_DMAMUX_EVT1 17 -#define DMAMUX_RGxCR_SIG_ID_DMAMUX_EVT2 18 -#define DMAMUX_RGxCR_SIG_ID_DMAMUX_EVT3 19 -#define DMAMUX_RGxCR_SIG_ID_LPTIM1_OUT 20 -#define DMAMUX_RGxCR_SIG_ID_LPTIM2_OUT 21 -#define DMAMUX_RGxCR_SIG_ID_TIM14_OC 22 -#define DMAMUX_RGxCR_SIG_ID_RESERVED 23 -/**@}*/ - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/doc-stm32g0.h b/libopencm3/include/libopencm3/stm32/g0/doc-stm32g0.h deleted file mode 100644 index 66243ca..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/doc-stm32g0.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32G0 - -@version 1.0.0 - -@date 30 January 2019 - -API documentation for ST Microelectronics STM32G0 Cortex M0+ series - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32G0xx STM32G0xx -Libraries for ST Microelectronics STM32G0xx series. - -@version 1.0.0 - -@date 30 January 2019 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32G0xx_defines STM32G0xx Defines - -@brief Defined Constants and Types for the STM32G0xx series - -@version 1.0.0 - -@date 30 January 2019 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/g0/exti.h b/libopencm3/include/libopencm3/stm32/g0/exti.h deleted file mode 100644 index e4e8f1f..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/exti.h +++ /dev/null @@ -1,57 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx EXTI Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -/** EXTI External Interrupt Selection Registers */ -#define EXTI_EXTICR(i) MMIO32(EXTI_BASE + 0x60 + (i)*4) -#define EXTI_EXTICR1 MMIO32(EXTI_BASE + 0x60) -#define EXTI_EXTICR2 MMIO32(EXTI_BASE + 0x64) -#define EXTI_EXTICR3 MMIO32(EXTI_BASE + 0x68) -#define EXTI_EXTICR4 MMIO32(EXTI_BASE + 0x6c) - -/** EXTI Rising Edge Pending Register */ -#define EXTI_RPR1 MMIO32(EXTI_BASE + 0x0c) -/** EXTI Falling Edge Pending Register */ -#define EXTI_FPR1 MMIO32(EXTI_BASE + 0x10) - -BEGIN_DECLS - -END_DECLS - -#else -/** @cond */ -#warning "exti_common_v1.h should not be included directly, only via exti.h" -#endif -/** @endcond */ - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/g0/flash.h b/libopencm3/include/libopencm3/stm32/g0/flash.h deleted file mode 100644 index 2de4bc5..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/flash.h +++ /dev/null @@ -1,297 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx Flash Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include - -/** @defgroup flash_registers FLASH Registers -@{*/ -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) -#define FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -#define FLASH_PCROP1ASR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24) -#define FLASH_PCROP1AER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28) -#define FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c) -#define FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30) -#define FLASH_PCROP1BSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34) -#define FLASH_PCROP1BER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38) -#define FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) -/**@}*/ - - -/** @defgroup flash_acr ACR Access control register -@{*/ - -/** FLASH_ACR_DBG_SWEN Debug access software enable **/ -#define FLASH_ACR_DBG_SWEN (1 << 18) -/** FLASH_ACR_EMPTY Flash User area empty **/ -#define FLASH_ACR_EMPTY (1 << 16) -/** FLASH_ACR_ICRST Instruction cache reset **/ -#define FLASH_ACR_ICRST (1 << 11) -/** FLASH_ACR_ICEN Instruction cache enable **/ -#define FLASH_ACR_ICEN (1 << 9) -/** FLASH_ACR_PRFTEN Prefetch enable **/ -#define FLASH_ACR_PRFTEN (1 << 8) - -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 0x7 -/** @defgroup flash_latency FLASH Wait States - * @brief Flash memory access latency. flash HCLK max freq for 0ws is 24mhz (range 1 voltage) / 8mhz (range 0), 48mhz/16mhz for 1ws and 64mhz for 2ws. -@{*/ -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -#define FLASH_ACR_LATENCY_2WS 0x02 -/**@}*/ - -/**@}*/ - -/** @defgroup flash_keyr KEYR Flash key register -@{*/ - -/** FLASH_KEYR_KEY1 Flash key 1 **/ -#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) -/** FLASH_KEYR_KEY2 Flash key 2 **/ -#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) - -/**@}*/ - -/** @defgroup flash_optkeyr OPTKEYR Option byte key register -@{*/ - -/** FLASH_OPTKEYR_KEY1 Option key 1 **/ -#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) -/** FLASH_OPTKEYR_KEY2 Option key 2 **/ -#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) - -/**@}*/ - -/** @defgroup flash_sr SR Status register -@{*/ - -/** FLASH_SR_CFGBSY Programming or erase configuration busy. **/ -#define FLASH_SR_CFGBSY (1 << 18) -/** FLASH_SR_BSY Busy **/ -#define FLASH_SR_BSY (1 << 16) -/** FLASH_SR_OPTVERR Option and Engineering bits loading validity error **/ -#define FLASH_SR_OPTVERR (1 << 15) -/** FLASH_SR_RDERR PCROP read error **/ -#define FLASH_SR_RDERR (1 << 14) -/** FLASH_SR_FASTERR Fast programming error **/ -#define FLASH_SR_FASTERR (1 << 9) -/** FLASH_SR_MISERR Fast programming data miss error **/ -#define FLASH_SR_MISERR (1 << 8) -/** FLASH_SR_PGSERR Programming sequence error **/ -#define FLASH_SR_PGSERR (1 << 7) -/** FLASH_SR_SIZERR Size error **/ -#define FLASH_SR_SIZERR (1 << 6) -/** FLASH_SR_PGAERR Programming alignment error **/ -#define FLASH_SR_PGAERR (1 << 5) -/** FLASH_SR_WRPERR Write protected error **/ -#define FLASH_SR_WRPERR (1 << 4) -/** FLASH_SR_PROGERR Programming error **/ -#define FLASH_SR_PROGERR (1 << 3) -/** FLASH_SR_OPERR Operation error **/ -#define FLASH_SR_OPERR (1 << 1) -/** FLASH_SR_EOP End of operation **/ -#define FLASH_SR_EOP (1 << 0) - -/**@}*/ - -/** @defgroup flash_cr CR Flash control register -@{*/ - -/** FLASH_CR_LOCK FLASH_CR Lock **/ -#define FLASH_CR_LOCK (1 << 31) -/** FLASH_CR_OPTLOCK Options Lock **/ -#define FLASH_CR_OPTLOCK (1 << 30) -/** FLASH_CR_SEC_PROT Securable memory area protection enable **/ -#define FLASH_CR_SEC_PROT (1 << 28) -/** FLASH_CR_OBL_LAUNCH Force the option byte loading **/ -#define FLASH_CR_OBL_LAUNCH (1 << 27) -/** FLASH_CR_RDERRIE PCROP read error interrupt enable **/ -#define FLASH_CR_RDERRIE (1 << 26) -/** FLASH_CR_ERRIE Error interrupt enable **/ -#define FLASH_CR_ERRIE (1 << 25) -/** FLASH_CR_EOPIE End of operation interrupt enable **/ -#define FLASH_CR_EOPIE (1 << 24) -/** FLASH_CR_FSTPG Fast programming **/ -#define FLASH_CR_FSTPG (1 << 18) -/** FLASH_CR_OPTSTRT Options modification start **/ -#define FLASH_CR_OPTSTRT (1 << 17) -/** FLASH_CR_STRT Start **/ -#define FLASH_CR_STRT (1 << 16) - -#define FLASH_CR_PNB_SHIFT 3 -#define FLASH_CR_PNB_MASK 0x3f - -/** FLASH_CR_MER Mass erase **/ -#define FLASH_CR_MER (1 << 2) -/** FLASH_CR_PER Page erase **/ -#define FLASH_CR_PER (1 << 1) -/** FLASH_CR_PG Programming **/ -#define FLASH_CR_PG (1 << 0) - -/**@}*/ - -/** @defgroup flash_eccr ECCR Flash ECC register -@{*/ -/** FLASH_ECCR_ECCD ECC detection **/ -#define FLASH_ECCR_ECCD (1 << 31) -/** FLASH_ECCR_ECCC ECC correction **/ -#define FLASH_ECCR_ECCC (1 << 30) -/** FLASH_ECCR_ECCIE ECC correction interrupt enable **/ -#define FLASH_ECCR_ECCIE (1 << 24) -/** FLASH_ECCR_SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block **/ -#define FLASH_ECCR_SYSF_ECC (1 << 20) - -#define FLASH_ECCR_ADDR_ECC_SHIFT 0 -#define FLASH_ECCR_ADDR_ECC_MASK 0x3fff - -/**@}*/ - -/** @defgroup flash_optr OPTR Flash option register -@{*/ - -/** FLASH_OPTR_IRHEN Internal reset holder enable bit **/ -#define FLASH_OPTR_IRHEN (1 << 29) - -#define FLASH_OPTR_NRST_MODE_SHIFT 27 -#define FLASH_OPTR_NRST_MODE_MASK 0x03 -/** @defgroup flash_optr_nrst_mode NRST MODE -* @brief NRST_MODE -@{*/ -#define FLASH_OPTR_NRST_MODE_RESET 1 -#define FLASH_OPTR_NRST_MODE_GPIO 2 -#define FLASH_OPTR_NRST_MODE_BIDIR 3 -/**@}*/ - -/** FLASH_OPTR_nBOOT0 nBOOT0 option bit **/ -#define FLASH_OPTR_nBOOT0 (1 << 26) -/** FLASH_OPTR_nBOOT1 Boot configuration **/ -#define FLASH_OPTR_nBOOT1 (1 << 25) -/** FLASH_OPTR_nBOOT_SEL nBOOT_SEL **/ -#define FLASH_OPTR_nBOOT_SEL (1 << 24) -/** FLASH_OPTR_RAM_PARITY_CHECK SRAM parity check control **/ -#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) -/** FLASH_OPTR_WWDG_SW Window watchdog selection **/ -#define FLASH_OPTR_WWDG_SW (1 << 19) -/** FLASH_OPTR_IWDG_STDBY Independent watchdog counter freeze in Standby mode **/ -#define FLASH_OPTR_IWDG_STDBY (1 << 18) -/** FLASH_OPTR_IWDG_STOP Independent watchdog counter freeze in Stop mode **/ -#define FLASH_OPTR_IWDG_STOP (1 << 17) -/** FLASH_OPTR_IDWG_SW Independent watchdog selection **/ -#define FLASH_OPTR_IDWG_SW (1 << 16) -/** FLASH_OPTR_nRSTS_HDW nRSTS_HDW **/ -#define FLASH_OPTR_nRSTS_HDW (1 << 15) -/** FLASH_OPTR_nRST_STDBY nRST_STDBY **/ -#define FLASH_OPTR_nRST_STDBY (1 << 14) -/** FLASH_OPTR_nRST_STOP nRST_STOP **/ -#define FLASH_OPTR_nRST_STOP (1 << 13) - -#define FLASH_OPTR_BORR_LEV_SHIFT 11 -#define FLASH_OPTR_BORR_LEV_MASK 0x03 -/** @defgroup flash_optr_borr_lev BORR LEV -* @brief These bits contain the VDD supply level threshold that releases the reset. -@{*/ -#define FLASH_OPTR_BORR_LEV_2V1 0 -#define FLASH_OPTR_BORR_LEV_2V3 1 -#define FLASH_OPTR_BORR_LEV_2V6 2 -#define FLASH_OPTR_BORR_LEV_2V9 3 -/**@}*/ - -#define FLASH_OPTR_BORF_LEV_SHIFT 9 -#define FLASH_OPTR_BORF_LEV_MASK 0x03 -/** @defgroup flash_optr_borf_lev BOR FLEV -* @brief These bits contain the VDD supply level threshold that activates the reset -@{*/ -#define FLASH_OPTR_BORF_LEV_2V0 0 -#define FLASH_OPTR_BORF_LEV_2V2 1 -#define FLASH_OPTR_BORF_LEV_2V5 2 -#define FLASH_OPTR_BORF_LEV_2V8 3 -/**@}*/ - -/** FLASH_OPTR_BOREN BOR reset Level **/ -#define FLASH_OPTR_BOREN (1 << 8) - -#define FLASH_OPTR_RDP_SHIFT 0 -#define FLASH_OPTR_RDP_MASK 0xff -/** @defgroup flash_optr_rdp RDP -* @brief Read protection level -@{*/ -#define FLASH_OPTR_RDP_LEVEL_0 0xAA -#define FLASH_OPTR_RDP_LEVEL_1 0xBB /* or any other value. */ -#define FLASH_OPTR_RDP_LEVEL_2 0xCC -/**@}*/ - -/**@}*/ - -BEGIN_DECLS - -void flash_clear_progerr_flag(void); -void flash_clear_pgserr_flag(void); -void flash_clear_size_flag(void); -void flash_clear_pgaerr_flag(void); -void flash_clear_wrperr_flag(void); -void flash_clear_operr_flag(void); -void flash_clear_eop_flag(void); - -void flash_clear_status_flags(void); - -void flash_wait_for_last_operation(void); - -void flash_program_double_word(uint32_t address, uint64_t data); -void flash_program(uint32_t address, uint8_t *data, uint32_t len); - -void flash_erase_page(uint32_t page); -void flash_erase_all_pages(void); - -/** Enable instruction cache */ -void flash_icache_enable(void); -/** Disable instruction cache */ -void flash_icache_disable(void); -/** Reset instruction cache */ -void flash_icache_reset(void); - -/** Unlock program memory */ -void flash_unlock_progmem(void); -/** lock program memory */ -void flash_lock_progmem(void); - -/** Lock Option Byte Access */ -void flash_lock_option_bytes(void); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/g0/gpio.h b/libopencm3/include/libopencm3/stm32/g0/gpio.h deleted file mode 100644 index 1b8357d..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/gpio.h +++ /dev/null @@ -1,75 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx General Purpose I/O - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define GPIO_BRR(port) MMIO32((port) + 0x28) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @defgroup gpio_speed GPIO Output Pin Speed -@{*/ -#define GPIO_OSPEED_LOW 0x0 -#define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x2 -#define GPIO_OSPEED_VERYHIGH 0x3 -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/g0/i2c.h b/libopencm3/include/libopencm3/stm32/g0/i2c.h deleted file mode 100644 index d91cc77..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/i2c.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx I2C - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/g0/irq.json b/libopencm3/include/libopencm3/stm32/g0/irq.json deleted file mode 100644 index aa43cbc..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/irq.json +++ /dev/null @@ -1,39 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "rtc", - "flash", - "rcc", - "exti0_1", - "exti2_3", - "exti4_15", - "ucpd1_ucpd2", - "dma1_channel1", - "dma1_channel2_3", - "dma1_channel4_7_dmamux", - "adc_comp", - "tim1_brk_up_trg_com", - "tim1_cc", - "tim2", - "tim3", - "tim6_dac_lptim1", - "tim7_lptim2", - "tim14", - "tim15", - "tim16", - "tim17", - "i2c1", - "i2c2", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3_usart4_lpuart1", - "cec", - "aes_rng" - ], - "partname_humanreadable": "STM32 G0 series", - "partname_doxygen": "STM32G0", - "includeguard": "LIBOPENCM3_STM32_G0_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/g0/iwdg.h b/libopencm3/include/libopencm3/stm32/g0/iwdg.h deleted file mode 100644 index 76af04b..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/iwdg.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx Independent Watchdog Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/lptimer.h b/libopencm3/include/libopencm3/stm32/g0/lptimer.h deleted file mode 100644 index e3606d7..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/lptimer.h +++ /dev/null @@ -1,70 +0,0 @@ -/** @defgroup lptimer_defines LPTIM Defines - * - * @ingroup STM32G0xx_defines - * - * @brief libopencm3 Defined Constants and Types for the STM32G0xx Low Power Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPTIMER_H -#define LIBOPENCM3_LPTIMER_H -/**@{*/ - -#include - -/** @defgroup lptim_reg_base Low Power Timer register base addresses -@{*/ -#define LPTIM1 LPTIM1_BASE -#define LPTIM2 LPTIM2_BASE -/**@}*/ - -/** LPTIM_CFGR2 LPTIM configuration register 2 */ -#define LPTIM_CFGR2(tim_base) MMIO32((tim_base) + 0x24) - -/** @addtogroup lptim_cr -@{*/ -/** COUNTRST Counter reset **/ -#define LPTIM_CR_COUNTRST (1 << 3) -/** RSTARE Reset after read enable **/ -#define LPTIM_CR_RSTARE (1 << 4) -/**@}*/ - -/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2 -@{*/ - -#define LPTIM_CFGR2_IN2SEL_SHIFT 4 -#define LPTIM_CFGR2_IN2SEL_MASK 0x03 - -#define LPTIM_CFGR2_IN1SEL_SHIFT 0 -#define LPTIM_CFGR2_IN1SEL_MASK 0x03 - -/**@}*/ - - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/memorymap.h b/libopencm3/include/libopencm3/stm32/g0/memorymap.h deleted file mode 100644 index ebe342b..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/memorymap.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -#define PERIPH_BASE (0x40000000U) -#define IOPORT_BASE (0x50000000U) -#define INFO_BASE (0x1fff7500U) -#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) - -/* APB */ -#define TIM2_BASE (PERIPH_BASE_APB + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB + 0x0400) -#define TIM6_BASE (PERIPH_BASE_APB + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB + 0x1400) -#define TIM14_BASE (PERIPH_BASE_APB + 0x2000) -#define RTC_BASE (PERIPH_BASE_APB + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB + 0x3000) -#define SPI2_BASE (PERIPH_BASE_APB + 0x3800) -#define USART2_BASE (PERIPH_BASE_APB + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB + 0x4800) -#define USART4_BASE (PERIPH_BASE_APB + 0x4C00) -#define I2C1_BASE (PERIPH_BASE_APB + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB + 0x5800) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB + 0x7400) -#define CEC_BASE (PERIPH_BASE_APB + 0x7800) -#define LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00) -#define LPUART1_BASE (PERIPH_BASE_APB + 0x8000) -#define LPTIM2_BASE (PERIPH_BASE_APB + 0x9400) -#define UCPD1_BASE (PERIPH_BASE_APB + 0xA000) -#define UCPD2_BASE (PERIPH_BASE_APB + 0xA400) -#define TAMP_BASE (PERIPH_BASE_APB + 0xB000) -#define SYSCFG_BASE (PERIPH_BASE_APB + 0x10000) -#define VREFBUF_BASE (PERIPH_BASE_APB + 0x10030) -#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080) -#define COMP_BASE (PERIPH_BASE_APB + 0x10200) -#define ADC1_BASE (PERIPH_BASE_APB + 0x12400) -#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) -#define SPI1_BASE (PERIPH_BASE_APB + 0x13000) -#define USART1_BASE (PERIPH_BASE_APB + 0x13800) -#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) -#define TIM16_BASE (PERIPH_BASE_APB + 0x14400) -#define TIM17_BASE (PERIPH_BASE_APB + 0x14800) -#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) - -/* AHB */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) -#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800) -#define RCC_BASE (PERIPH_BASE_AHB + 0x01000) -#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) -#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) -#define RNG_BASE (PERIPH_BASE_AHB + 0x05000) -#define AES_BASE (PERIPH_BASE_AHB + 0x06000) - -#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) -#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) -#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) -#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) -#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000) -#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (0x1FFF75E0) -#define DESIG_UNIQUE_ID_BASE (0x1FFF7590) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) - -/* ST provided factory calibration values @ 3.0V */ -#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA)) -#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8)) -#define ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA)) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/pwr.h b/libopencm3/include/libopencm3/stm32/g0/pwr.h deleted file mode 100644 index c2264d9..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/pwr.h +++ /dev/null @@ -1,202 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - * - * @brief Defined Constants and Types for the STM32G0xx PWR Control - * - * @ingroup STM32G0xx_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H -/**@{*/ - -/** @defgroup pwr_registers PWR Registers -@{*/ -/** Power control register 1 (PWR_CR1) */ -#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) - -/** Power control register 2 (PWR_CR2) */ -#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04) - -/** Power control register 3 (PWR_CR3) */ -#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08) - -/** Power control register 4 (PWR_CR4) */ -#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c) - -/** Power status register 1 (PWR_SR1) */ -#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10) - -/** Power status registery 2 (PWR_SR2) */ -#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14) - -/** Power status clear register (PWR_SCR) */ -#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18) - -#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20) -#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28) -#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30) -#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38) -#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40) -#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48) - -#define PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00) -#define PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04) -/**@}*/ - -/* --- PWR_CR1 values ------------------------------------------------------- */ - -#define PWR_CR1_LPR (1 << 14) - -#define PWR_CR1_VOS_SHIFT 9 -#define PWR_CR1_VOS_MASK 0x3 -/** @defgroup pwr_cr1_vos VOS - * @brief Voltage scaling range selection. -@{*/ -#define PWR_CR1_VOS_RANGE_1 1 -#define PWR_CR1_VOS_RANGE_2 2 -/**@}*/ - -#define PWR_CR1_DBP (1 << 8) - -#define PWR_CR1_FPD_LPSLP (1 << 5) -#define PWR_CR1_FPD_LPRUN (1 << 4) -#define PWR_CR1_FPD_STOP (1 << 3) - -#define PWR_CR1_LPMS_SHIFT 0 -#define PWR_CR1_LPMS_MASK 0x07 -/** @defgroup pwr_cr1_lpms LPMS - * @ingroup STM32G0xx_pwr_defines - * @brief Low-power mode selection -@{*/ -#define PWR_CR1_LPMS_STOP_0 0 -#define PWR_CR1_LPMS_STOP_1 1 -#define PWR_CR1_LPMS_STANDBY 3 -#define PWR_CR1_LPMS_SHUTDOWN 4 -/**@}*/ - -/* --- PWR_CR2 values ------------------------------------------------------- */ - -#define PWR_CR2_PVDRT_SHIFT 4 -#define PWR_CR2_PVDRT_MASK 0x07 -/** @defgroup pwr_cr2_pvdrt PVDRT - * @brief Power voltage detector rising threshold selection -@{*/ -#define PWR_CR2_PVDRT_2V1 0x00 -#define PWR_CR2_PVDRT_2V2 0x01 -#define PWR_CR2_PVDRT_2V5 0x02 -#define PWR_CR2_PVDRT_2V6 0x03 -#define PWR_CR2_PVDRT_2V7 0x04 -#define PWR_CR2_PVDRT_2V9 0x05 -#define PWR_CR2_PVDRT_3V0 0x06 -#define PWR_CR2_PVDRT_PVD_IN 0x07 -/**@}*/ - -#define PWR_CR2_PVDFT_SHIFT 1 -#define PWR_CR2_PVDFT_MASK 0x07 -/** @defgroup pwr_cr2_pvdft PVDFT - * @brief Power voltage detector falling threshold selection -@{*/ -#define PWR_CR2_PVDFT_2V0 0x00 -#define PWR_CR2_PVDFT_2V2 0x01 -#define PWR_CR2_PVDFT_2V4 0x02 -#define PWR_CR2_PVDFT_2V5 0x03 -#define PWR_CR2_PVDFT_2V6 0x04 -#define PWR_CR2_PVDFT_2V8 0x05 -#define PWR_CR2_PVDFT_2V9 0x06 -/**@}*/ - -#define PWR_CR2_PVDE (1 << 0) - -/* --- PWR_CR3 values ------------------------------------------------------- */ - -#define PWR_CR3_EIWUL (1 << 15) -#define PWR_CR3_APC (1 << 10) -#define PWR_CR3_ULPEN (1 << 9) -#define PWR_CR3_RRS (1 << 8) -#define PWR_CR3_EWUP6 (1 << 5) -#define PWR_CR3_EWUP5 (1 << 4) -#define PWR_CR3_EWUP4 (1 << 3) -#define PWR_CR3_EWUP2 (1 << 1) -#define PWR_CR3_EWUP1 (1 << 0) - -/* --- PWR_CR4 values ------------------------------------------------------- */ - -#define PWR_CR4_VBRS (1 << 9) -#define PWR_CR4_VBE (1 << 8) -#define PWR_CR4_WP6 (1 << 5) -#define PWR_CR4_WP5 (1 << 4) -#define PWR_CR4_WP4 (1 << 3) -#define PWR_CR4_WP2 (1 << 1) -#define PWR_CR4_WP1 (1 << 0) - -/* --- PWR_SR1 values ------------------------------------------------------- */ - -#define PWR_SR1_WUFI (1 << 15) -#define PWR_SR1_SBF (1 << 8) -#define PWR_SR1_WUF6 (1 << 5) -#define PWR_SR1_WUF5 (1 << 4) -#define PWR_SR1_WUF4 (1 << 3) -#define PWR_SR1_WUF2 (1 << 1) -#define PWR_SR1_WUF1 (1 << 0) - -/* --- PWR_SR2 values ------------------------------------------------------- */ - -#define PWR_SR2_PVDO (1 << 11) -#define PWR_SR2_VOSF (1 << 10) -#define PWR_SR2_REGLPF (1 << 9) -#define PWR_SR2_REGLPS (1 << 8) -#define PWR_SR2_FLASHRDY (1 << 8) - -/* --- PWR_SCR values ------------------------------------------------------- */ - -#define PWR_SCR_CSBF (1 << 8) -#define PWR_SCR_CWUF6 (1 << 5) -#define PWR_SCR_CWUF5 (1 << 4) -#define PWR_SCR_CWUF4 (1 << 3) -#define PWR_SCR_CWUF2 (1 << 1) -#define PWR_SCR_CWUF1 (1 << 0) - -/* --- Function prototypes ------------------------------------------------- */ - -enum pwr_vos_scale { - PWR_SCALE1 = PWR_CR1_VOS_RANGE_1, - PWR_SCALE2 = PWR_CR1_VOS_RANGE_2, -}; - -BEGIN_DECLS - -void pwr_set_vos_scale(enum pwr_vos_scale scale); - -void pwr_disable_backup_domain_write_protect(void); -void pwr_enable_backup_domain_write_protect(void); - -void pwr_set_low_power_mode_selection(uint32_t lpms); - -void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level); -void pwr_disable_power_voltage_detect(void); - -END_DECLS - -/**@}*/ -#endif - diff --git a/libopencm3/include/libopencm3/stm32/g0/rcc.h b/libopencm3/include/libopencm3/stm32/g0/rcc.h deleted file mode 100644 index 77409f7..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/rcc.h +++ /dev/null @@ -1,849 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx Reset and Clock Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include - -/** @defgroup rcc_registers Reset and Clock Control Register -@{*/ -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) -#define RCC_CIER MMIO32(RCC_BASE + 0x18) -#define RCC_CIFR MMIO32(RCC_BASE + 0x1c) -#define RCC_CICR MMIO32(RCC_BASE + 0x20) -#define RCC_IOPRSTR_OFFSET 0x24 -#define RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET) -#define RCC_AHBRSTR_OFFSET 0x28 -#define RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET) -#define RCC_APBRSTR1_OFFSET 0x2c -#define RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET) -#define RCC_APBRSTR2_OFFSET 0x30 -#define RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET) -#define RCC_IOPENR_OFFSET 0x34 -#define RCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET) -#define RCC_AHBENR_OFFSET 0x38 -#define RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET) -#define RCC_APBENR1_OFFSET 0x3c -#define RCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET) -#define RCC_APBENR2_OFFSET 0x40 -#define RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET) -#define RCC_IOPSMENR_OFFSET 0x44 -#define RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET) -#define RCC_AHBSMENR_OFFSET 0x48 -#define RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET) -#define RCC_APBSMENR1_OFFSET 0x4c -#define RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET) -#define RCC_APBSMENR2_OFFSET 0x50 -#define RCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET) -#define RCC_CCIPR MMIO32(RCC_BASE + 0x54) -#define RCC_BDCR MMIO32(RCC_BASE + 0x5c) -#define RCC_CSR MMIO32(RCC_BASE + 0x60) -/**@}*/ - -/** @defgroup rcc_cr CR Clock control Register -@{*/ -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) - -#define RCC_CR_HSIDIV_SHIFT 11 -#define RCC_CR_HSIDIV_MASK 0x7 -/** @defgroup rcc_cr_hsidiv HSI Div - * @brief Division factor of the HSI16 oscillator to produce HSISYS clock -@sa rcc_cr_hsidiv -@{*/ -#define RCC_CR_HSIDIV_DIV1 0 -#define RCC_CR_HSIDIV_DIV2 1 -#define RCC_CR_HSIDIV_DIV4 2 -#define RCC_CR_HSIDIV_DIV8 3 -#define RCC_CR_HSIDIV_DIV16 4 -#define RCC_CR_HSIDIV_DIV32 5 -#define RCC_CR_HSIDIV_DIV64 6 -#define RCC_CR_HSIDIV_DIV128 7 -/**@}*/ - -#define RCC_CR_HSIRDY (1 << 10) -#define RCC_CR_HSIKERON (1 << 9) -#define RCC_CR_HSION (1 << 8) -/**@}*/ - - -/** @defgroup rcc_icscr ICSCR Internal Clock Source Calibration Register -@{*/ -#define RCC_ICSCR_HSITRIM_SHIFT 8 -#define RCC_ICSCR_HSITRIM_MASK 0x1f -#define RCC_ICSCR_HSICAL_SHIFT 0 -#define RCC_ICSCR_HSICAL_MASK 0xff -/**@}*/ - - -/** @defgroup rcc_cfgr CFGR Configuration Register -@{*/ -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE_MASK 0x7 -/** @defgroup rcc_cfgr_mcopre MCO Pre - * @brief Division factor of microcontroler clock output -@sa rcc_cfgr_mcopre -@{*/ -#define RCC_CFGR_MCOPRE_DIV1 0 -#define RCC_CFGR_MCOPRE_DIV2 1 -#define RCC_CFGR_MCOPRE_DIV4 2 -#define RCC_CFGR_MCOPRE_DIV8 3 -#define RCC_CFGR_MCOPRE_DIV16 4 -#define RCC_CFGR_MCOPRE_DIV32 5 -#define RCC_CFGR_MCOPRE_DIV64 6 -#define RCC_CFGR_MCOPRE_DIV128 7 -/**@}*/ - -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf - -/** @defgroup rcc_cfgr_mcosel MCO Sel - * @brief Microcontroler clock output selector -@sa rcc_cfgr_mcosel -@{*/ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x1 -#define RCC_CFGR_MCO_HSI16 0x3 -#define RCC_CFGR_MCO_HSE 0x4 -#define RCC_CFGR_MCO_PLLRCLK 0x5 -#define RCC_CFGR_MCO_LSI 0x6 -#define RCC_CFGR_MCO_LSE 0x7 -/**@}*/ - -#define RCC_CFGR_PPRE_MASK 0x7 -#define RCC_CFGR_PPRE_SHIFT 12 - -/** @defgroup rcc_cfgr_ppre PPRE - * @brief APB Prescaler -@sa rcc_cfgr_ppre -@{*/ -#define RCC_CFGR_PPRE_NODIV 0x0 -#define RCC_CFGR_PPRE_DIV2 0x4 -#define RCC_CFGR_PPRE_DIV4 0x5 -#define RCC_CFGR_PPRE_DIV8 0x6 -#define RCC_CFGR_PPRE_DIV16 0x7 -/**@}*/ - -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_SHIFT 8 -/** @defgroup rcc_cfgr_hpre HPRE - * @brief APB Prescaler -@sa rcc_cfgr_hpre -@{*/ -#define RCC_CFGR_HPRE_NODIV 0x0 -#define RCC_CFGR_HPRE_DIV2 0x8 -#define RCC_CFGR_HPRE_DIV4 0x9 -#define RCC_CFGR_HPRE_DIV8 0xa -#define RCC_CFGR_HPRE_DIV16 0xb -#define RCC_CFGR_HPRE_DIV64 0xc -#define RCC_CFGR_HPRE_DIV128 0xd -#define RCC_CFGR_HPRE_DIV256 0xe -#define RCC_CFGR_HPRE_DIV512 0xf -/**@}*/ - -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_SHIFT 3 -/** @defgroup rcc_cfgr_sws SWS - * @brief System clock switch status -@sa rcc_cfgr_sws -@{*/ -#define RCC_CFGR_SWS_HSISYS 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLLRCLK 0x2 -#define RCC_CFGR_SWS_LSI 0x3 -#define RCC_CFGR_SWS_LSE 0x4 -/**@}*/ - -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_SHIFT 0 -/** @defgroup rcc_cfgr_sw SW - * @brief System clock switch -@sa rcc_cfgr_sw -@{*/ -#define RCC_CFGR_SW_HSISYS 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLLRCLK 0x2 -#define RCC_CFGR_SW_LSI 0x3 -#define RCC_CFGR_SW_LSE 0x4 -/**@}*/ -/**@}*/ - - - -/** @defgroup rcc_pllcfgr PLLCFGR PLL Configuration Register -@{*/ -#define RCC_PLLCFGR_PLLR_SHIFT 29 -#define RCC_PLLCFGR_PLLR_MASK 0x7 -/** @defgroup rcc_pllcfgr_pllr PLLR - * @brief VCO Division factor R for PLLRCLK clock output [2..8]. Frequency must not exceed 64mhz in voltage range 1, or 16mhz in voltage range 2. -@sa rcc_pllcfgr_pllr -@{*/ -#define RCC_PLLCFGR_PLLR_DIV(x) ((x)-1) -/**@}*/ - -#define RCC_PLLCFGR_PLLREN (1<<28) - -#define RCC_PLLCFGR_PLLQ_SHIFT 25 -#define RCC_PLLCFGR_PLLQ_MASK 0x7 -/** @defgroup rcc_pllcfgr_pllq PLLQ - * @brief VCO Division factor Q for PLLQCLK clock output [2..8]. Frequency must not exceed 128mhz in voltage range 1, or 32mhz in range 2 -@sa rcc_pllcfgr_pllq -@{*/ -#define RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1) -/**@}*/ - -#define RCC_PLLCFGR_PLLQEN (1 << 24) - -#define RCC_PLLCFGR_PLLP_SHIFT 17 -#define RCC_PLLCFGR_PLLP_MASK 0x1f -/** @defgroup rcc_pllcfgr_pllp PLLP - * @brief VCO Division factor P for PLLPCLK clock output [2..32]. Frequency must not exceed 122mhz in voltage range 1, or 40mhz in range 2 -@sa rcc_pllcfgr_pllp -@{*/ -#define RCC_PLLCFGR_PLLP_DIV(x) ((x)-1) -/**@}*/ - -#define RCC_PLLCFGR_PLLPEN (1 << 16) - -#define RCC_PLLCFGR_PLLN_SHIFT 0x8 -#define RCC_PLLCFGR_PLLN_MASK 0x7f -/** @defgroup rcc_pllcfgr_plln PLLN - * @brief Multiplication factor N [8..86] for PLL VCO output frequency. Frequency must be between 64mhz and 344mhz. -@{*/ -#define RCC_PLLCFGR_PLLN_MUL(x) (x) -/**@}*/ - -#define RCC_PLLCFGR_PLLM_SHIFT 0x4 -#define RCC_PLLCFGR_PLLM_MASK 0x7 -/** @defgroup rcc_pllcfgr_pllm PLLM - * @brief Division factor M [1..8] for PLL input clock. Input frequency must be between 4mhz and 16mhz. -@{*/ -#define RCC_PLLCFGR_PLLM_DIV(x) ((x)-1) -/**@}*/ - -#define RCC_PLLCFGR_PLLSRC_SHIFT 0 -#define RCC_PLLCFGR_PLLSRC_MASK 0x3 -/** @defgroup rcc_pllcfgr_pllsrc PLLSRC - * @brief PLL input clock source -@sa rcc_pllcfgr_pllsrc -@{*/ -#define RCC_PLLCFGR_PLLSRC_NONE 0 -#define RCC_PLLCFGR_PLLSRC_HSI16 2 -#define RCC_PLLCFGR_PLLSRC_HSE 3 -/**@}*/ -/**@}*/ - -/** @defgroup rcc_cier CIER Clock Interrupt Enable Register -@{*/ -#define RCC_CIER_PLLRDYIE (1 << 5) -#define RCC_CIER_HSERDYIE (1 << 4) -#define RCC_CIER_HSIRDYIE (1 << 3) -#define RCC_CIER_LSERDYIE (1 << 1) -#define RCC_CIER_LSIRDYIE (1 << 0) -/**@}*/ - -/** @defgroup rcc_cifr CIFR Clock Interrupt Flag Register -@{*/ -#define RCC_CIFR_LSECSSF (1 << 9) -#define RCC_CIFR_CSSF (1 << 8) -#define RCC_CIFR_PLLRDYF (1 << 5) -#define RCC_CIFR_HSERDYF (1 << 4) -#define RCC_CIFR_HSIRDYF (1 << 3) -#define RCC_CIFR_LSERDYF (1 << 1) -#define RCC_CIFR_LSIRDYF (1 << 0) -/**@}*/ - -/** @defgroup rcc_cicr CICR Clock Interrupt Clear Register -@{*/ -#define RCC_CICR_LSECSSC (1 << 9) -#define RCC_CICR_CSSC (1 << 8) -#define RCC_CICR_PLLRDYC (1 << 5) -#define RCC_CICR_HSERDYC (1 << 4) -#define RCC_CICR_HSIRDYC (1 << 3) -#define RCC_CICR_LSERDYC (1 << 1) -#define RCC_CICR_LSIRDYC (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values -@{*/ -#define RCC_AHBRSTR_RNGRST (1 << 18) -#define RCC_AHBRSTR_AESRST (1 << 16) -#define RCC_AHBRSTR_CRCRST (1 << 12) -#define RCC_AHBRSTR_FLASHRST (1 << 8) -#define RCC_AHBRSTR_DMARST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APBRSTRx reset values (full set) -@{*/ -/** @defgroup rcc_apbrstr1_rst RCC_APBRSTR1 reset values -@{*/ -#define RCC_APBRSTR1_LPTIM1RST (1 << 31) -#define RCC_APBRSTR1_LPTIM2RST (1 << 30) -#define RCC_APBRSTR1_DAC1RST (1 << 29) -#define RCC_APBRSTR1_PWRRST (1 << 28) -#define RCC_APBRSTR1_DBGRST (1 << 27) -#define RCC_APBRSTR1_UCPD2RST (1 << 26) -#define RCC_APBRSTR1_UCPD1RST (1 << 25) -#define RCC_APBRSTR1_I2C2RST (1 << 22) -#define RCC_APBRSTR1_I2C1RST (1 << 21) -#define RCC_APBRSTR1_LPUART1RST (1 << 20) -#define RCC_APBRSTR1_USART4RST (1 << 19) -#define RCC_APBRSTR1_USART3RST (1 << 18) -#define RCC_APBRSTR1_USART2RST (1 << 17) -#define RCC_APBRSTR1_SPI2RST (1 << 14) -#define RCC_APBRSTR1_TIM7RST (1 << 5) -#define RCC_APBRSTR1_TIM6RST (1 << 4) -#define RCC_APBRSTR1_TIM3RST (1 << 1) -#define RCC_APBRSTR1_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apbrstr2_rst RCC_APBRSTR2 reset values -@{*/ -#define RCC_APBRSTR2_ADCRST (1 << 20) -#define RCC_APBRSTR2_TIM17RST (1 << 18) -#define RCC_APBRSTR2_TIM16RST (1 << 17) -#define RCC_APBRSTR2_TIM16RST (1 << 17) -#define RCC_APBRSTR2_TIM15RST (1 << 16) -#define RCC_APBRSTR2_TIM14RST (1 << 15) -#define RCC_APBRSTR2_USART1RST (1 << 14) -#define RCC_APBRSTR2_SPI1RST (1 << 12) -#define RCC_APBRSTR2_TIM1RST (1 << 11) -#define RCC_APBRSTR2_SYSCFGRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@{*/ -#define RCC_AHBENR_RNGEN (1 << 18) -#define RCC_AHBENR_AESEN (1 << 16) -#define RCC_AHBENR_CRCEN (1 << 12) -#define RCC_AHBENR_FLASHEN (1 << 8) -#define RCC_AHBENR_DMAEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APBENRx enable values (full set) -@{*/ -/** @defgroup rcc_apbenr1_en RCC_APBENR1 enable values -@{*/ -#define RCC_APBENR1_LPTIM1EN (1 << 31) -#define RCC_APBENR1_LPTIM2EN (1 << 30) -#define RCC_APBENR1_DAC1EN (1 << 29) -#define RCC_APBENR1_PWREN (1 << 28) -#define RCC_APBENR1_DBGEN (1 << 27) -#define RCC_APBENR1_UCPD2EN (1 << 26) -#define RCC_APBENR1_UCPD1EN (1 << 25) -#define RCC_APBENR1_CECEN (1 << 24) -#define RCC_APBENR1_I2C2EN (1 << 22) -#define RCC_APBENR1_I2C1EN (1 << 21) -#define RCC_APBENR1_LPUART1EN (1 << 20) -#define RCC_APBENR1_USART4EN (1 << 19) -#define RCC_APBENR1_USART3EN (1 << 18) -#define RCC_APBENR1_USART2EN (1 << 17) -#define RCC_APBENR1_SPI2EN (1 << 14) -#define RCC_APBENR1_WWDGEN (1 << 11) -#define RCC_APBENR1_RTCAPBEN (1 << 10) -#define RCC_APBENR1_TIM7EN (1 << 5) -#define RCC_APBENR1_TIM6EN (1 << 4) -#define RCC_APBENR1_TIM3EN (1 << 1) -#define RCC_APBENR1_TIM2EN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apbenr2_en RCC_APBENR2 enable values -@{*/ -#define RCC_APBENR2_ADCEN (1 << 20) -#define RCC_APBENR2_TIM17EN (1 << 18) -#define RCC_APBENR2_TIM16EN (1 << 17) -#define RCC_APBENR2_TIM16EN (1 << 17) -#define RCC_APBENR2_TIM15EN (1 << 16) -#define RCC_APBENR2_TIM14EN (1 << 15) -#define RCC_APBENR2_USART1EN (1 << 14) -#define RCC_APBENR2_SPI1EN (1 << 12) -#define RCC_APBENR2_TIM1EN (1 << 11) -#define RCC_APBENR2_SYSCFGEN (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_aphbsmenr_en RCC_AHBSMENR enable in sleep/stop mode values -@{*/ -#define RCC_AHBSMENR_RNGSMEN (1 << 18) -#define RCC_AHBSMENR_AESSMEN (1 << 16) -#define RCC_AHBSMENR_CRCSMEN (1 << 12) -#define RCC_AHBSMENR_SRAMSMEN (1 << 9) -#define RCC_AHBSMENR_FLASHSMEN (1 << 8) -#define RCC_AHBSMENR_DMASMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apbsmenr_en RCC_APBSMENR1 enable in sleep/stop mode values -@{*/ -#define RCC_APBSMENR1_LPTIM1SMEN (1 << 31) -#define RCC_APBSMENR1_LPTIM2SMEN (1 << 30) -#define RCC_APBSMENR1_DAC1SMEN (1 << 29) -#define RCC_APBSMENR1_PWRSMEN (1 << 28) -#define RCC_APBSMENR1_DBGSMEN (1 << 27) -#define RCC_APBSMENR1_UCPD2SMEN (1 << 26) -#define RCC_APBSMENR1_UCPD1SMEN (1 << 25) -#define RCC_APBSMENR1_CECSMEN (1 << 24) -#define RCC_APBSMENR1_I2C2SMEN (1 << 22) -#define RCC_APBSMENR1_I2C1SMEN (1 << 21) -#define RCC_APBSMENR1_LPUART1SMEN (1 << 20) -#define RCC_APBSMENR1_USART4SMEN (1 << 19) -#define RCC_APBSMENR1_USART3SMEN (1 << 18) -#define RCC_APBSMENR1_USART2SMEN (1 << 17) -#define RCC_APBSMENR1_SPI2SMEN (1 << 14) -#define RCC_APBSMENR1_WWDGSMEN (1 << 11) -#define RCC_APBSMENR1_RTCAPBSMEN (1 << 10) -#define RCC_APBSMENR1_TIM7SMEN (1 << 5) -#define RCC_APBSMENR1_TIM6SMEN (1 << 4) -#define RCC_APBSMENR1_TIM3SMEN (1 << 1) -#define RCC_APBSMENR1_TIM2SMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apbsmenr2_en RCC_APBSMENR2 enable in sleep/stop mode values -@{*/ -#define RCC_APBSMENR2_ADCSMEN (1 << 20) -#define RCC_APBSMENR2_TIM17SMEN (1 << 18) -#define RCC_APBSMENR2_TIM16SMEN (1 << 17) -#define RCC_APBSMENR2_TIM15SMEN (1 << 16) -#define RCC_APBSMENR2_TIM14SMEN (1 << 15) -#define RCC_APBSMENR2_USART1SMEN (1 << 14) -#define RCC_APBSMENR2_SPI1SMEN (1 << 12) -#define RCC_APBSMENR2_TIM1SMEN (1 << 11) -#define RCC_APBSMENR2_SYSCFGSMEN (1 << 0) -/**@}*/ - - -/** @defgroup rcc_ccipr CCIPR Peripherals Independent Clock Config Register -@{*/ -#define RCC_CCIPR_ADCSEL_MASK 0x3 -#define RCC_CCIPR_ADCSEL_SHIFT 30 -/** @defgroup rcc_ccipr_adcsel ADCSEL -@{*/ -#define RCC_CCIPR_ADCSEL_SYSCLK 0 -#define RCC_CCIPR_ADCSEL_PLLPCLK 1 -#define RCC_CCIPR_ADCSEL_HSI16 2 -/**@}*/ - -#define RCC_CCIPR_RNGDIV_MASK 0x3 -#define RCC_CCIPR_RNGDIV_SHIFT 28 -/** @defgroup rcc_ccipr_rngdiv RNGDIV -@{*/ -#define RCC_CCIPR_RNGDIV_1 0 -#define RCC_CCIPR_RNGDIV_2 1 -#define RCC_CCIPR_RNGDIV_4 2 -#define RCC_CCIPR_RNGDIV_8 3 -/**@}*/ - -#define RCC_CCIPR_RNGSEL_MASK 0x3 -#define RCC_CCIPR_RNGSEL_SHIFT 26 -/** @defgroup rcc_ccipr_rngsel RNGSEL -@{*/ -#define RCC_CCIPR_RNGSEL_NONE 0 -#define RCC_CCIPR_RNGSEL_HSI16 1 -#define RCC_CCIPR_RNGSEL_SYSCLK 2 -#define RCC_CCIPR_RNGSEL_PLLQCLK 3 -/**@}*/ - -#define RCC_CCIPR_TIM15SEL_MASK 0x1 -#define RCC_CCIPR_TIM15SEL_SHIFT 24 -/** @defgroup rcc_ccipr_tim15sel TIM15SEL -@{*/ -#define RCC_CCIPR_TIM15SEL_TIMPCLK 0 -#define RCC_CCIPR_TIM15SEL_PLLQCLK 1 -/**@}*/ - -#define RCC_CCIPR_TIM1SEL_MASK 0x1 -#define RCC_CCIPR_TIM1SEL_SHIFT 20 -/** @defgroup rcc_ccipr_tim1sel TIM1SEL -@{*/ -#define RCC_CCIPR_TIM1SEL_TIMPCLK 0 -#define RCC_CCIPR_TIM1SEL_PLLQCLK 1 -/**@}*/ - -#define RCC_CCIPR_LPTIM2SEL_MASK 0x3 -#define RCC_CCIPR_LPTIM2SEL_SHIFT 20 -/** @defgroup rcc_ccipr_lptim2sel LPTIM2SEL LPTIM2 Clock source selection -@{*/ -#define RCC_CCIPR_LPTIM2SEL_PCLK 0 -#define RCC_CCIPR_LPTIM2SEL_LSI 1 -#define RCC_CCIPR_LPTIM2SEL_HSI16 2 -#define RCC_CCIPR_LPTIM2SEL_LSE 3 -/**@}*/ - -#define RCC_CCIPR_LPTIM1SEL_MASK 0x3 -#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 -/** @defgroup rcc_ccipr_lptim1sel LPTIM1SEL LPTIM1 Clock source selection -@{*/ -#define RCC_CCIPR_LPTIM1SEL_PCLK 0 -#define RCC_CCIPR_LPTIM1SEL_LSI 1 -#define RCC_CCIPR_LPTIM1SEL_HSI16 2 -#define RCC_CCIPR_LPTIM1SEL_LSE 3 -/**@}*/ - -#define RCC_CCIPR_I2S1SEL_MASK 0x3 -#define RCC_CCIPR_I2S1SEL_SHIFT 14 -/** @defgroup rcc_ccipr_i2s1sel I2S1SEL I2S1 Clock source selection -@{*/ -#define RCC_CCIPR_I2S1SEL_SYSCLK 0 -#define RCC_CCIPR_I2S1SEL_PLLPLCK 1 -#define RCC_CCIPR_I2S1SEL_HSI16 2 -#define RCC_CCIPR_I2S1SEL_I2S_CKIN 2 -/**@}*/ - -#define RCC_CCIPR_I2C1SEL_MASK 0x3 -#define RCC_CCIPR_I2C1SEL_SHIFT 12 -/** @defgroup rcc_ccipr_i2c1sel I2C1SEL I2C1 Clock source selection -@{*/ -#define RCC_CCIPR_I2C1SEL_PCLK 0 -#define RCC_CCIPR_I2C1SEL_SYSCLK 1 -#define RCC_CCIPR_I2C1SEL_HSI16 2 -/**@}*/ - -#define RCC_CCIPR_LPUART1SEL_MASK 0x3 -#define RCC_CCIPR_LPUART1SEL_SHIFT 10 -/** @defgroup rcc_ccipr_lpuart1sel LPUART1SEL LPUART1 Clock source selection -@{*/ -#define RCC_CCIPR_LPUART1SEL_PCLK 0 -#define RCC_CCIPR_LPUART1SEL_SYSCLK 1 -#define RCC_CCIPR_LPUART1SEL_HSI16 2 -#define RCC_CCIPR_LPUART1SEL_LSE 3 -/**@}*/ - -#define RCC_CCIPR_CECSEL_MASK 0x1 -#define RCC_CCIPR_CECSEL_SHIFT 6 -/** @defgroup rcc_ccipr_cecsel CECSEL CEC Clock souce selection -@{*/ -#define RCC_CCIPR_CECSEL_HSI16 0 -#define RCC_CCIPR_CECSEL_LSE 1 -/**@}*/ - -#define RCC_CCIPR_USART2SEL_MASK 0x3 -#define RCC_CCIPR_USART2SEL_SHIFT 2 -/** @defgroup rcc_ccipr_usart2sel USART2SEL USART2 Clock source selection -@{*/ -#define RCC_CCIPR_USART2SEL_PCLK 0 -#define RCC_CCIPR_USART2SEL_SYSCLK 1 -#define RCC_CCIPR_USART2SEL_HSI16 2 -#define RCC_CCIPR_USART2SEL_LSE 3 -/**@}*/ - -#define RCC_CCIPR_USART1SEL_MASK 0x3 -#define RCC_CCIPR_USART1SEL_SHIFT 0 -/** @defgroup rcc_ccipr_usart1sel USART1SEL USART1 Clock source selection -@{*/ -#define RCC_CCIPR_USART1SEL_PCLK 0 -#define RCC_CCIPR_USART1SEL_SYSCLK 1 -#define RCC_CCIPR_USART1SEL_HSI16 2 -#define RCC_CCIPR_USART1SEL_LSE 3 -/**@}*/ -/**@}*/ - -/** @defgroup rcc_bdcr BDCR Backup Domain Control Register -@{*/ -#define RCC_BDCR_LSCOSEL (1 << 25) -#define RCC_BDCR_LSCOEN (1 << 24) -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) - -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_MASK 0x3 -/** @defgroup rcc_bdcr_rtcsel RTCSEL RTC Clock source selection -@{*/ -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSE_DIV32 3 -/**@}*/ - -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV_MASK 0x3 -/** @defgroup rcc_bdcr_lsedrv LSEDRV LSE Oscillator drive capacity -@{*/ -#define RCC_BDCR_LSEDRV_LOW 0 -#define RCC_BDCR_LSEDRV_MEDLOW 1 -#define RCC_BDCR_LSEDRV_MEDHIGH 2 -#define RCC_BDCR_LSEDRV_HIGH 3 -/**@}*/ - -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) -/**@}*/ - -/** @defgroup rcc_csr CSR Control and Status Register -@{*/ -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PWRRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 23) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) -/**@}*/ - -/* --- Variable definitions ------------------------------------------------ */ - -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -/* - * as done for F0, fake out apb2_frequency as the device does not really have - * apb2 clock. - */ -#define rcc_apb2_frequency rcc_apb1_frequency - -/* --- Function prototypes ------------------------------------------------- */ - -#define _REG_BIT(offset, bit) (((offset) << 5) + (bit)) - -enum rcc_osc { - RCC_HSI, - RCC_HSE, - RCC_PLL, - RCC_LSE, - RCC_LSI, -}; - -enum rcc_periph_clken { - RCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5), - RCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4), - RCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3), - RCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2), - RCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1), - RCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0), - - RCC_RNG = _REG_BIT(RCC_AHBENR_OFFSET, 18), - RCC_AES = _REG_BIT(RCC_AHBENR_OFFSET, 16), - RCC_CRC = _REG_BIT(RCC_AHBENR_OFFSET, 12), - RCC_FLASH = _REG_BIT(RCC_AHBENR_OFFSET, 8), - RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0), - RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0), /* Compatibility */ - - RCC_LPTIM1 = _REG_BIT(RCC_APBENR1_OFFSET, 31), - RCC_LPTIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 30), - RCC_DAC1 = _REG_BIT(RCC_APBENR1_OFFSET, 29), - RCC_PWR = _REG_BIT(RCC_APBENR1_OFFSET, 28), - RCC_DBG = _REG_BIT(RCC_APBENR1_OFFSET, 27), - RCC_UCPD2 = _REG_BIT(RCC_APBENR1_OFFSET, 26), - RCC_UCPD1 = _REG_BIT(RCC_APBENR1_OFFSET, 25), - RCC_CEC = _REG_BIT(RCC_APBENR1_OFFSET, 24), - RCC_I2C2 = _REG_BIT(RCC_APBENR1_OFFSET, 22), - RCC_I2C1 = _REG_BIT(RCC_APBENR1_OFFSET, 21), - RCC_LPUART1 = _REG_BIT(RCC_APBENR1_OFFSET, 20), - RCC_USART4 = _REG_BIT(RCC_APBENR1_OFFSET, 19), - RCC_USART3 = _REG_BIT(RCC_APBENR1_OFFSET, 18), - RCC_USART2 = _REG_BIT(RCC_APBENR1_OFFSET, 17), - RCC_SPI2 = _REG_BIT(RCC_APBENR1_OFFSET, 14), - RCC_TIM7 = _REG_BIT(RCC_APBENR1_OFFSET, 5), - RCC_TIM6 = _REG_BIT(RCC_APBENR1_OFFSET, 4), - RCC_TIM3 = _REG_BIT(RCC_APBENR1_OFFSET, 1), - RCC_TIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 0), - - RCC_ADC = _REG_BIT(RCC_APBENR2_OFFSET, 20), - RCC_TIM17 = _REG_BIT(RCC_APBENR2_OFFSET, 18), - RCC_TIM16 = _REG_BIT(RCC_APBENR2_OFFSET, 17), - RCC_TIM15 = _REG_BIT(RCC_APBENR2_OFFSET, 16), - RCC_TIM14 = _REG_BIT(RCC_APBENR2_OFFSET, 15), - RCC_USART1 = _REG_BIT(RCC_APBENR2_OFFSET, 14), - RCC_SPI1 = _REG_BIT(RCC_APBENR2_OFFSET, 12), - RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11), - RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0), - - SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5), - SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4), - SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3), - SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2), - SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1), - SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0), - - SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18), - SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16), - SCC_CRC = _REG_BIT(RCC_AHBSMENR_OFFSET, 12), - SCC_FLASH = _REG_BIT(RCC_AHBSMENR_OFFSET, 8), - SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), - SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), /* Compatibility */ - - SCC_LPTIM1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 31), - SCC_LPTIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 30), - SCC_DAC1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 29), - SCC_PWR = _REG_BIT(RCC_APBSMENR1_OFFSET, 28), - SCC_DBG = _REG_BIT(RCC_APBSMENR1_OFFSET, 27), - SCC_UCPD2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 26), - SCC_UCPD1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 25), - SCC_CEC = _REG_BIT(RCC_APBSMENR1_OFFSET, 24), - SCC_I2C2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 22), - SCC_I2C1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 21), - SCC_LPUART1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 20), - SCC_USART4 = _REG_BIT(RCC_APBSMENR1_OFFSET, 19), - SCC_USART3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 18), - SCC_USART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 17), - SCC_SPI2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 14), - SCC_TIM7 = _REG_BIT(RCC_APBSMENR1_OFFSET, 5), - SCC_TIM6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 4), - SCC_TIM3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 1), - SCC_TIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 0), - - SCC_ADC = _REG_BIT(RCC_APBSMENR2_OFFSET, 20), - SCC_TIM17 = _REG_BIT(RCC_APBSMENR2_OFFSET, 18), - SCC_TIM16 = _REG_BIT(RCC_APBSMENR2_OFFSET, 17), - SCC_TIM15 = _REG_BIT(RCC_APBSMENR2_OFFSET, 16), - SCC_TIM14 = _REG_BIT(RCC_APBSMENR2_OFFSET, 15), - SCC_USART1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 14), - SCC_SPI1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 12), - SCC_TIM1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 11), - SCC_SYSCFG = _REG_BIT(RCC_APBSMENR2_OFFSET, 0), -}; - -enum rcc_periph_rst { - RST_GPIOF = _REG_BIT(RCC_IOPRSTR_OFFSET, 5), - RST_GPIOE = _REG_BIT(RCC_IOPRSTR_OFFSET, 4), - RST_GPIOD = _REG_BIT(RCC_IOPRSTR_OFFSET, 3), - RST_GPIOC = _REG_BIT(RCC_IOPRSTR_OFFSET, 2), - RST_GPIOB = _REG_BIT(RCC_IOPRSTR_OFFSET, 1), - RST_GPIOA = _REG_BIT(RCC_IOPRSTR_OFFSET, 0), - - RST_RNG = _REG_BIT(RCC_AHBRSTR_OFFSET, 18), - RST_AES = _REG_BIT(RCC_AHBRSTR_OFFSET, 16), - RST_CRC = _REG_BIT(RCC_AHBRSTR_OFFSET, 12), - RST_FLASH = _REG_BIT(RCC_AHBRSTR_OFFSET, 8), - RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), - RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), /* Compatibility */ - - RST_LPTIM1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 31), - RST_LPTIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 30), - RST_DAC1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 29), - RST_PWR = _REG_BIT(RCC_APBRSTR1_OFFSET, 28), - RST_DBG = _REG_BIT(RCC_APBRSTR1_OFFSET, 27), - RST_UCPD2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 26), - RST_UCPD1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 25), - RST_CEC = _REG_BIT(RCC_APBRSTR1_OFFSET, 24), - RST_I2C2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 22), - RST_I2C1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 21), - RST_LPUART1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 20), - RST_USART4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 19), - RST_USART3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 18), - RST_USART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 17), - RST_SPI2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 14), - RST_TIM7 = _REG_BIT(RCC_APBRSTR1_OFFSET, 5), - RST_TIM6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 4), - RST_TIM3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 1), - RST_TIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 0), - - RST_ADC = _REG_BIT(RCC_APBRSTR2_OFFSET, 20), - RST_TIM17 = _REG_BIT(RCC_APBRSTR2_OFFSET, 18), - RST_TIM16 = _REG_BIT(RCC_APBRSTR2_OFFSET, 17), - RST_TIM15 = _REG_BIT(RCC_APBRSTR2_OFFSET, 16), - RST_TIM14 = _REG_BIT(RCC_APBRSTR2_OFFSET, 15), - RST_USART1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 14), - RST_SPI1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 12), - RST_TIM1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 11), - RST_SYSCFG = _REG_BIT(RCC_APBRSTR2_OFFSET, 0), -}; - -struct rcc_clock_scale { - enum rcc_osc sysclock_source; - - /* PLL as sysclock source cfg */ - uint8_t pll_source; - uint8_t pll_div; - uint8_t pll_mul; - uint8_t pllp_div; - uint8_t pllq_div; - uint8_t pllr_div; - - /* HSI as sysclock source cfg */ - uint8_t hsisys_div; - - uint8_t hpre; - uint8_t ppre; - uint8_t flash_waitstates; - enum pwr_vos_scale voltage_scale; - uint32_t ahb_frequency; - uint32_t apb_frequency; -}; - -enum rcc_clock { - RCC_CLOCK_CONFIG_LSI_32KHZ, - RCC_CLOCK_CONFIG_HSI_4MHZ, - RCC_CLOCK_CONFIG_HSI_16MHZ, - RCC_CLOCK_CONFIG_HSI_PLL_32MHZ, - RCC_CLOCK_CONFIG_HSI_PLL_64MHZ, - RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ, - RCC_CLOCK_CONFIG_END -}; - -extern const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END]; - -#include - -BEGIN_DECLS - -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); - -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); - -void rcc_set_sysclk_source(enum rcc_osc osc); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -enum rcc_osc rcc_system_clock_source(void); - -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr); -void rcc_enable_pllp(bool enable); -void rcc_enable_pllq(bool enable); -void rcc_enable_pllr(bool enable); - -void rcc_set_ppre(uint32_t ppre); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_hsisys_div(uint32_t hsidiv); -void rcc_set_mcopre(uint32_t mcopre); - -void rcc_clock_setup(const struct rcc_clock_scale *clock); - -void rcc_set_rng_clk_div(uint32_t rng_div); -void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/rng.h b/libopencm3/include/libopencm3/stm32/g0/rng.h deleted file mode 100644 index a7323e9..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/rng.h +++ /dev/null @@ -1,40 +0,0 @@ -/** @defgroup rng_defines RNG Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx RNG Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -/* --- RNG_CR values ------------------------------------------------------- */ - -/** Clock error detection : CED = 0 : Detection Enabled */ -#define RNG_CR_CED (1 << 5) - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/g0/spi.h b/libopencm3/include/libopencm3/stm32/g0/spi.h deleted file mode 100644 index 5eb17bc..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/spi.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup spi_defines SPI Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx SPI - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/syscfg.h b/libopencm3/include/libopencm3/stm32/g0/syscfg.h deleted file mode 100644 index 50dd930..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/syscfg.h +++ /dev/null @@ -1,350 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx System Configuration controller - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2019 - * Guillaume Revaillot - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -/**@{*/ - -/**@defgroup syscfg_registers SYSCFG Registers - @{*/ -#define SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x00) -#define SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x18) - -#define SYSCFG_ITLINE(line) MMIO32(SYSCFG_BASE + 0x80 + (line)*4) -/**@}*/ - -/** @defgroup syscfg_cfgr1 CFGR1 SYSCFG configuration register 1 -@{*/ - - -/** SYSCFG_CFGR1_I2C_PA10_FMP FM+ enable for PA10 */ -#define SYSCFG_CFGR1_I2C_PA10_FMP (1 << 23) - -/** SYSCFG_CFGR1_I2C_PA9_FMP FM+ enable for PA9 */ -#define SYSCFG_CFGR1_I2C_PA9_FMP (1 << 22) - -/** SYSCFG_CFGR1_I2C2_FMP FM+ driving capability activation for I2C2 */ -#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) - -/** SYSCFG_CFGR1_I2C1_FMP FM+ driving capability activation for I2C1 */ -#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) - -/** SYSCFG_CFGR1_I2C_PB9_FMP FM+ enable for PB9 */ -#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) - -/** SYSCFG_CFGR1_I2C_PB8_FMP FM+ enable for PB8 */ -#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) - -/** SYSCFG_CFGR1_I2C_PB7_FMP FM+ enable for PB7 */ -#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) - -/** SYSCFG_CFGR1_I2C_PB6_FMP FM+ enable for PB6 */ -#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) - -/** SYSCFG_CFGR1_UCPD2_STROBE Strobe signal bit for UCPD2 */ -#define SYSCFG_CFGR1_UCPD2_STROBE (1 << 10) - -/** SYSCFG_CFGR1_UCPD1_STROBE Strobe signal bit for UCPD1 */ -#define SYSCFG_CFGR1_UCPD1_STROBE (1 << 9) - -/** SYSCFG_CFGR1_BOOSTEN I/O analog switch voltage booster enable */ -#define SYSCFG_CFGR1_BOOSTEN (1 << 8) - -#define SYSCFG_CFGR1_IR_MOD_SHIFT 6 -#define SYSCFG_CFGR1_IR_MOD_MASK 0x03 -/** @defgroup syscfg_cfgr1_ir_mod IR MOD -* @brief IR Modulation Envelope signal selection. -@{*/ -#define SYSCFG_CFGR1_IR_MOD_TIM16 0 -#define SYSCFG_CFGR1_IR_MOD_USART1 1 -#define SYSCFG_CFGR1_IR_MOD_USART4 2 -/**@}*/ - -/** SYSCFG_CFGR1_IR_POL IR output polarity selection */ -#define SYSCFG_CFGR1_IR_POL (1 << 5) - -/** SYSCFG_CFGR1_PA12_RMP PA12 pin remapping */ -#define SYSCFG_CFGR1_PA12_RMP (1 << 4) - -/** SYSCFG_CFGR1_PA11_RMP PA11 pin remapping */ -#define SYSCFG_CFGR1_PA11_RMP (1 << 3) - -#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0 -#define SYSCFG_CFGR1_MEM_MODE_MASK 0x03 -/** @defgroup syscfg_cfgr1_mem_mode MEM MODE -* @brief Memory mapping selection bits -@{*/ -#define SYSCFG_CFGR1_MEM_MODE_FLASH 0 -#define SYSCFG_CFGR1_MEM_MODE_SYSTEM 1 -#define SYSCFG_CFGR1_MEM_MODE_SRAM 3 -/**@}*/ - -/**@}*/ - - -/** @defgroup syscfg_cfgr2 CFGR2 SYSCFG configuration register 2 -@{*/ - -/** SYSCFG_CFGR2_PB2_CDEN PB2 clamping diode enable */ -#define SYSCFG_CFGR2_PB2_CDEN (1 << 23) - -/** SYSCFG_CFGR2_PB1_CDEN PB1 clamping diode enable */ -#define SYSCFG_CFGR2_PB1_CDEN (1 << 22) - -/** SYSCFG_CFGR2_PB0_CDEN PB0 clamping diode enable */ -#define SYSCFG_CFGR2_PB0_CDEN (1 << 21) - -/** SYSCFG_CFGR2_PA13_CDEN PA13 clamping diode enable */ -#define SYSCFG_CFGR2_PA13_CDEN (1 << 20) - -/** SYSCFG_CFGR2_PA6_CDEN PA6 clamping diode enable */ -#define SYSCFG_CFGR2_PA6_CDEN (1 << 19) - -/** SYSCFG_CFGR2_PA5_CDEN PA5 clamping diode enable */ -#define SYSCFG_CFGR2_PA5_CDEN (1 << 18) - -/** SYSCFG_CFGR2_PA3_CDEN PA3 clamping diode enable */ -#define SYSCFG_CFGR2_PA3_CDEN (1 << 17) - -/** SYSCFG_CFGR2_PA1_CDEN PA1 clamping diode enable */ -#define SYSCFG_CFGR2_PA1_CDEN (1 << 16) - -/** SYSCFG_CFGR2_SRAM_PEF SRAM parity error flag */ -#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) - -/** SYSCFG_CFGR2_ECC_LOCK ECC error lock bit */ -#define SYSCFG_CFGR2_ECC_LOCK (1 << 3) - -/** SYSCFG_CFGR2_PVD_LOCK PVD lock enable bit */ -#define SYSCFG_CFGR2_PVD_LOCK (1 << 2) - -/** SYSCFG_CFGR2_SRAM_PARITY_LOCK SRAM parity lock bit */ -#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1) - -/** SYSCFG_CFGR2_LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit */ -#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0) - -/**@}*/ - -/** @defgroup syscfg_itline0 ITLINE0 interrupt line 0 status register -@{*/ -#define SYSCFG_ITLINE0_WWDG (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline1 ITLINE1 interrupt line 1 status register -@{*/ -#define SYSCFG_ITLINE1_PVDOUT (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline2 ITLINE2 interrupt line 2 status register -@{*/ -#define SYSCFG_ITLINE2_RTC (1 << 1) -#define SYSCFG_ITLINE2_TAMP (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline3 ITLINE3 interrupt line 3 status register -@{*/ -#define SYSCFG_ITLINE3_FLASH_ECC (1 << 1) -#define SYSCFG_ITLINE3_FLASH_ITF (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline4 ITLINE4 interrupt line 4 status register -@{*/ -#define SYSCFG_ITLINE4_RCC (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline5 ITLINE5 interrupt line 5 status register -@{*/ -#define SYSCFG_ITLINE5_EXTI1 (1 << 1) -#define SYSCFG_ITLINE5_EXTI0 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline6 ITLINE6 interrupt line 6 status register -@{*/ -#define SYSCFG_ITLINE6_EXTI3 (1 << 1) -#define SYSCFG_ITLINE6_EXTI2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline7 ITLINE7 interrupt line 7 status register -@{*/ -#define SYSCFG_ITLINE7_EXTI15 (1 << 11) -#define SYSCFG_ITLINE7_EXTI14 (1 << 10) -#define SYSCFG_ITLINE7_EXTI13 (1 << 9) -#define SYSCFG_ITLINE7_EXTI12 (1 << 8) -#define SYSCFG_ITLINE7_EXTI11 (1 << 7) -#define SYSCFG_ITLINE7_EXTI10 (1 << 6) -#define SYSCFG_ITLINE7_EXTI9 (1 << 5) -#define SYSCFG_ITLINE7_EXTI8 (1 << 4) -#define SYSCFG_ITLINE7_EXTI7 (1 << 3) -#define SYSCFG_ITLINE7_EXTI6 (1 << 2) -#define SYSCFG_ITLINE7_EXTI5 (1 << 1) -#define SYSCFG_ITLINE7_EXTI4 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline8 ITLINE8 interrupt line 8 status register -@{*/ -#define SYSCFG_ITLINE8_UCPD2 (1 << 1) -#define SYSCFG_ITLINE8_UCPD1 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline9 ITLINE9 interrupt line 9 status register -@{*/ -#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline10 ITLINE10 interrupt line 10 status register -@{*/ -#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) -#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline11 ITLINE11 interrupt line 11 status register -@{*/ -#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 4) -#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 3) -#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 2) -#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 1) -#define SYSCFG_ITLINE11_DMAMUX (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline12 ITLINE12 interrupt line 12 status register -@{*/ -#define SYSCFG_ITLINE12_COMP2 (1 << 2) -#define SYSCFG_ITLINE12_COMP1 (1 << 1) -#define SYSCFG_ITLINE12_ADC (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline13 ITLINE13 interrupt line 13 status register -@{*/ -#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) -#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) -#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) -#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline14 ITLINE14 interrupt line 14 status register -@{*/ -#define SYSCFG_ITLINE14_TIM1_CC (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline15 ITLINE15 interrupt line 15 status register -@{*/ -#define SYSCFG_ITLINE15_TIM2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline16 ITLINE16 interrupt line 16 status register -@{*/ -#define SYSCFG_ITLINE16_TIM3 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline17 ITLINE17 interrupt line 17 status register -@{*/ -#define SYSCFG_ITLINE17_LPTIM1 (1 << 2) -#define SYSCFG_ITLINE17_DAC (1 << 1) -#define SYSCFG_ITLINE17_TIM6 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline18 ITLINE18 interrupt line 18 status register -@{*/ -#define SYSCFG_ITLINE18_LPTIM2 (1 << 1) -#define SYSCFG_ITLINE18_TIM7 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline19 ITLINE19 interrupt line 19 status register -@{*/ -#define SYSCFG_ITLINE19_TIM14 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline20 ITLINE20 interrupt line 20 status register -@{*/ -#define SYSCFG_ITLINE20_TIM15 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline21 ITLINE21 interrupt line 21 status register -@{*/ -#define SYSCFG_ITLINE21_TIM16 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline22 ITLINE22 interrupt line 22 status register -@{*/ -#define SYSCFG_ITLINE22_TIM17 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline23 ITLINE23 interrupt line 23 status register -@{*/ -#define SYSCFG_ITLINE23_I2C1 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline24 ITLINE24 interrupt line 24 status register -@{*/ -#define SYSCFG_ITLINE24_I2C2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline25 ITLINE25 interrupt line 25 status register -@{*/ -#define SYSCFG_ITLINE25_SPI1 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline26 ITLINE26 interrupt line 26 status register -@{*/ -#define SYSCFG_ITLINE26_SPI2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline27 ITLINE27 interrupt line 27 status register -@{*/ -#define SYSCFG_ITLINE27_USART1 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline28 ITLINE28 interrupt line 28 status register -@{*/ -#define SYSCFG_ITLINE28_USART2 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline29 ITLINE29 interrupt line 29 status register -@{*/ -#define SYSCFG_ITLINE29_LPUART1 (1 << 2) -#define SYSCFG_ITLINE29_USART4 (1 << 1) -#define SYSCFG_ITLINE29_USART3 (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline30 ITLINE30 interrupt line 30 status register -@{*/ -#define SYSCFG_ITLINE30_CEC (1 << 0) -/**@}*/ - -/** @defgroup syscfg_itline31 ITLINE31 interrupt line 31 status register -@{*/ -#define SYSCFG_ITLINE31_AES (1 << 1) -#define SYSCFG_ITLINE31_RNG (1 << 0) -/**@}*/ - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/timer.h b/libopencm3/include/libopencm3/stm32/g0/timer.h deleted file mode 100644 index 1f102ba..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/timer.h +++ /dev/null @@ -1,74 +0,0 @@ -/** @defgroup timer_defines Timer Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx Timers - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -/**@{*/ - -/* Option Register (TIMx_OR1) */ -#define TIM_OR1(tim_base) MMIO32((tim_base) + 0x50) -#define TIM2_OR1 TIM_OR1(TIM2) -#define TIM3_OR1 TIM_OR1(TIM3) - -/* Alternate Function (TIMx_AF1) */ -#define TIM_AF1(tim_base) MMIO32((tim_base) + 0x60) -#define TIM2_AF1 TIM_AF1(TIM2) -#define TIM3_AF1 TIM_AF1(TIM3) -#define TIM16_AF1 TIM_AF1(TIM16) -#define TIM17_AF1 TIM_AF1(TIM17) - -/* Input Selection Register (TIMx_TISEL) */ -#define TIM_TISEL(tim_base) MMIO32((tim_base) + 0x68) -#define TIM2_TISEL TIM_TISEL(TIM2) -#define TIM3_TISEL TIM_TISEL(TIM3) -#define TIM14_TISEL TIM_TISEL(TIM14) -#define TIM16_TISEL TIM_TISEL(TIM16) -#define TIM17_TISEL TIM_TISEL(TIM17) - -/* --- TIMx_OR1 values ---------------------------------------------------- */ - -/* OCREF_CLR: ocref_clr Source Selection */ -#define TIM_OR1_OCREF_CLR (1 << 0) - -/** @defgroup tim_or1_ocref_clr TIM_OR1_OCREF_CLR Source Selection -@{*/ -#define TIM_OR1_OCREF_CLR_COMP1 (0) -#define TIM_OR1_OCREF_CLR_COMP2 (1) -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g0/usart.h b/libopencm3/include/libopencm3/stm32/g0/usart.h deleted file mode 100644 index 2078bf5..0000000 --- a/libopencm3/include/libopencm3/stm32/g0/usart.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @ingroup STM32G0xx_defines - * - * @brief Defined Constants and Types for the STM32G0xx USART - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/**@{*/ - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define USART4 USART4_BASE -#define LPUART1 LPUART1_BASE -/**@}*/ - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/g4/doc-stm32g4.h b/libopencm3/include/libopencm3/stm32/g4/doc-stm32g4.h deleted file mode 100644 index 2b57dc2..0000000 --- a/libopencm3/include/libopencm3/stm32/g4/doc-stm32g4.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 STM32G4 - -@version 1.0.0 - -@date April 2020 - -API documentation for ST Microelectronics STM32G4 Cortex M4 series - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32G4xx STM32G4xx -Libraries for ST Microelectronics STM32G4xx series. - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32G4xx_defines STM32G4xx Defines - -@brief Defined Constants and Types for the STM32G4xx series - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/g4/gpio.h b/libopencm3/include/libopencm3/stm32/g4/gpio.h deleted file mode 100644 index edbb229..0000000 --- a/libopencm3/include/libopencm3/stm32/g4/gpio.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the STM32G4xx General Purpose I/O - * - * @ingroup STM32G4xx_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/** GPIO Bit Reset Registers GPIOx_BRR - * @{ - */ -#define GPIO_BRR(port) MMIO32((port) + 0x28) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) -#define GPIOG_BRR GPIO_BRR(GPIOG) -#define GPIOH_BRR GPIO_BRR(GPIOH) -/**@}*/ - -/** @defgroup gpio_speed GPIO Output Pin Speed -@{*/ -#define GPIO_OSPEED_LOW 0x0 -#define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x2 -#define GPIO_OSPEED_VERYHIGH 0x3 -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/g4/irq.json b/libopencm3/include/libopencm3/stm32/g4/irq.json deleted file mode 100644 index fb4a91c..0000000 --- a/libopencm3/include/libopencm3/stm32/g4/irq.json +++ /dev/null @@ -1,109 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "rtc_tamp_css", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_channel1", - "dma1_channel2", - "dma1_channel3", - "dma1_channel4", - "dma1_channel5", - "dma1_channel6", - "dma1_channel7", - "adc12", - "usb_hp", - "usb_lp", - "fdcan1_intr1", - "fdcan1_intr0", - "exti9_5", - "tim1_brk_tim15", - "tim1_up_tim16", - "tim1_trg_tim17", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_wakeup", - "tim8_brk", - "tim8_up", - "tim8_trg", - "tim8_cc", - "adc3", - "fsmc", - "lptim1", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dac13under", - "tim7_dac24under", - "dma2_channel1", - "dma2_channel2", - "dma2_channel3", - "dma2_channel4", - "dma2_channel5", - "adc4", - "adc5", - "ucpd1", - "comp123", - "comp456", - "comp7", - "hrtim_master", - "hrtim_tima", - "hrtim_timb", - "hrtim_timc", - "hrtim_timd", - "hrtim_time", - "hrtim_fault", - "hrtim_timf", - "crs", - "sai", - "tim20_brk", - "tim20_up", - "tim20_trg", - "tim20_cc", - "fpu", - "i2c4_ev", - "i2c4_er", - "spi4", - "aes", - "fdcan2_intr0", - "fdcan2_intr1", - "fdcan3_intr0", - "fdcan3_intr1", - "rng", - "lpuart", - "i2c3_ev", - "i2c3_er", - "dmamux_ovr", - "quadspi", - "dma1_channel8", - "dma2_channel6", - "dma2_channel7", - "dma2_channel8", - "cordic", - "fmac" - ], - "partname_humanreadable": "STM32 G4 series", - "partname_doxygen": "STM32G4", - "includeguard": "LIBOPENCM3_STM32_G4_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/g4/memorymap.h b/libopencm3/include/libopencm3/stm32/g4/memorymap.h deleted file mode 100644 index 06a958c..0000000 --- a/libopencm3/include/libopencm3/stm32/g4/memorymap.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -#define INFO_BASE (0x1fff0000U) -#define PERIPH_BASE_APB1 (0x40000000U) -#define PERIPH_BASE_APB2 (0x40010000U) -#define PERIPH_BASE_AHB1 (0x40020000U) -#define PERIPH_BASE_IOPORT (0x48000000U) -#define PERIPH_BASE_AHB2 (0x50000000U) -#define FMC1_BANK_BASE (0x60000000U) -#define FMC3_BANK_BASE (0x80000000U) -#define QUADSPI_BANK_BASE (0x90000000U) - - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define CRS_BASE (PERIPH_BASE_APB1 + 0x2000) -#define TAMP_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4C00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -#define FDCAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define FDCAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -#define FDCAN3_BASE (PERIPH_BASE_APB1 + 0x6c00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800) -#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) -#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) -#define I2C4_BASE (PERIPH_BASE_APB1 + 0x8400) -#define UCPD1_BASE (PERIPH_BASE_APB1 + 0xA000) -#define FDCAN1_RAM_BASE (PERIPH_BASE_APB1 + 0xA400) -#define FDCAN2_RAM_BASE (PERIPH_BASE_APB1 + 0xA800) -#define FDCAN3_RAM_BASE (PERIPH_BASE_APB1 + 0xAc00) - -/* APB2 */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) -#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030) -#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200) -#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0300) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3c00) -#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) -#define TIM20_BASE (PERIPH_BASE_APB2 + 0x5000) -#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400) -#define HRTIM_BASE (PERIPH_BASE_APB2 + 0x6800) - -/* AHB1 */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define DMAMUX_BASE (PERIPH_BASE_AHB1 + 0x0800) -#define CORDIC_BASE (PERIPH_BASE_AHB1 + 0x0c00) -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define FMAC_BASE (PERIPH_BASE_AHB1 + 0x1400) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) - -/* IO */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_IOPORT + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_IOPORT + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_IOPORT + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_IOPORT + 0x0c00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_IOPORT + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_IOPORT + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_IOPORT + 0x1800) - -/* AHB2 */ -#define ADC1_BASE (PERIPH_BASE_AHB2 + 0x0000) -#define ADC2_BASE ADC1_BASE -#define ADC3_BASE (PERIPH_BASE_AHB2 + 0x0400) -#define ADC4_BASE ADC3_BASE -#define ADC5_BASE ADC3_BASE -#define DAC1_BASE (PERIPH_BASE_AHB2 + 0x0800) -#define DAC2_BASE (PERIPH_BASE_AHB2 + 0x0c00) -#define DAC3_BASE (PERIPH_BASE_AHB2 + 0x1000) -#define DAC4_BASE (PERIPH_BASE_AHB2 + 0x1400) -#define AES_BASE (PERIPH_BASE_AHB2 + 0x6000) -#define RNG_BASE (PERIPH_BASE_AHB2 + 0x6800) - -#define FMC_BASE (0xa0000000U) -#define QUADSPI_BASE (0xa0001000U) - -/* Private peripherals */ -#define DBGMCU_BASE (PPBI_BASE + 0x42000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0) -#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) -#define DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500)) - -/* ST provided factory calibration values @ 3.0V */ -#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa)) -#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8)) -#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca)) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/g4/rcc.h b/libopencm3/include/libopencm3/stm32/g4/rcc.h deleted file mode 100644 index bb1f809..0000000 --- a/libopencm3/include/libopencm3/stm32/g4/rcc.h +++ /dev/null @@ -1,935 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @ingroup STM32G4xx_defines - * - * @brief Defined Constants and Types for the STM32G4xx Reset and Clock - * Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2020 Karl Palsson - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2020 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/** @defgroup rcc_registers RCC Registers - * @{ - */ -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) -#define RCC_CIER MMIO32(RCC_BASE + 0x18) -#define RCC_CIFR MMIO32(RCC_BASE + 0x1c) -#define RCC_CICR MMIO32(RCC_BASE + 0x20) -#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x28) -#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x2c) -#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x30) -#define RCC_APB1RSTR1 MMIO32(RCC_BASE + 0x38) -#define RCC_APB1RSTR2 MMIO32(RCC_BASE + 0x3c) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x40) -#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x48) -#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x4c) -#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x50) -#define RCC_APB1ENR1 MMIO32(RCC_BASE + 0x58) -#define RCC_APB1ENR2 MMIO32(RCC_BASE + 0x5c) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x60) -#define RCC_AHB1SMENR MMIO32(RCC_BASE + 0x68) -#define RCC_AHB2SMENR MMIO32(RCC_BASE + 0x6c) -#define RCC_AHB3SMENR MMIO32(RCC_BASE + 0x70) -#define RCC_APB1SMENR1 MMIO32(RCC_BASE + 0x78) -#define RCC_APB1SMENR2 MMIO32(RCC_BASE + 0x7c) -#define RCC_APB2SMENR MMIO32(RCC_BASE + 0x80) -#define RCC_CCIPR MMIO32(RCC_BASE + 0x88) -#define RCC_BDCR MMIO32(RCC_BASE + 0x90) -#define RCC_CSR MMIO32(RCC_BASE + 0x94) -#define RCC_CRRCR MMIO32(RCC_BASE + 0x98) -#define RCC_CCIPR2 MMIO32(RCC_BASE + 0x9c) -/**@}*/ - - -/** @defgroup rcc_cr_values RCC_CR values - * @{ - */ -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSIRDY (1 << 10) -#define RCC_CR_HSIKERON (1 << 9) -#define RCC_CR_HSION (1 << 8) -/**@}*/ - -/** @defgroup rcc_icscr_values RCC_ICSCR values - * @{ - */ -#define RCC_ICSCR_HSITRIM_SHIFT 24 -#define RCC_ICSCR_HSITRIM_MASK 0x1f -#define RCC_ICSCR_HSICAL_SHIFT 16 -#define RCC_ICSCR_HSICAL_MASK 0xff -/**@}*/ - -/** @defgroup rcc_cfgr_values RCC_CFGR values - * @{ - */ -/** @defgroup rcc_cfgr_mcopre MCOPRE MCO prescaler - * @{ - */ -#define RCC_CFGR_MCOPRE_DIV1 0 -#define RCC_CFGR_MCOPRE_DIV2 1 -#define RCC_CFGR_MCOPRE_DIV4 2 -#define RCC_CFGR_MCOPRE_DIV8 3 -#define RCC_CFGR_MCOPRE_DIV16 4 -/**@}*/ -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE_MASK 0x7 - -/** @defgroup rcc_cfgr_mco MCO: Microcontroller clock output - * @{ - */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x1 -#define RCC_CFGR_MCO_HSI16 0x3 -#define RCC_CFGR_MCO_HSE 0x4 -#define RCC_CFGR_MCO_PLL 0x5 -#define RCC_CFGR_MCO_LSI 0x6 -#define RCC_CFGR_MCO_LSE 0x7 -#define RCC_CFGR_MCO_HSI48 0x8 -/**@}*/ -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf - -/** @defgroup rcc_cfgr_pprex PPREx: APBx prescaler - * @{ - */ -#define RCC_CFGR_PPREx_NODIV 0x0 -#define RCC_CFGR_PPREx_DIV2 0x4 -#define RCC_CFGR_PPREx_DIV4 0x5 -#define RCC_CFGR_PPREx_DIV8 0x6 -#define RCC_CFGR_PPREx_DIV16 0x7 -/**@}*/ -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE2_SHIFT 11 -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 8 - - -/** @defgroup rcc_cfgr_hpre HPRE: AHB prescaler - * @{ - */ -#define RCC_CFGR_HPRE_NODIV 0x0 -#define RCC_CFGR_HPRE_DIV2 0x8 -#define RCC_CFGR_HPRE_DIV4 0x9 -#define RCC_CFGR_HPRE_DIV8 0xa -#define RCC_CFGR_HPRE_DIV16 0xb -#define RCC_CFGR_HPRE_DIV64 0xc -#define RCC_CFGR_HPRE_DIV128 0xd -#define RCC_CFGR_HPRE_DIV256 0xe -#define RCC_CFGR_HPRE_DIV512 0xf -/*@}*/ -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_SHIFT 4 - -/** @defgroup rcc_cfgr_swx SW/SWS System clock switch (status) - * @{ - */ -#define RCC_CFGR_SWx_HSI16 0x1 -#define RCC_CFGR_SWx_HSE 0x2 -#define RCC_CFGR_SWx_PLL 0x3 -/**@}*/ -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_SHIFT 0 -/**@}*/ - -/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR - PLL Configuration Register - * @{ - */ -#define RCC_CFGR_PLLPDIV_MASK 0x1f -#define RCC_CFGR_PLLPDIV_SHIFT 27 - -#define RCC_PLLCFGR_PLLR_DIV2 0 -#define RCC_PLLCFGR_PLLR_DIV4 1 -#define RCC_PLLCFGR_PLLR_DIV6 2 -#define RCC_PLLCFGR_PLLR_DIV8 3 -#define RCC_PLLCFGR_PLLR_SHIFT 25 -#define RCC_PLLCFGR_PLLR_MASK 0x3 - -#define RCC_PLLCFGR_PLLREN BIT24 - -#define RCC_PLLCFGR_PLLQ_DIV2 0 -#define RCC_PLLCFGR_PLLQ_DIV4 1 -#define RCC_PLLCFGR_PLLQ_DIV6 2 -#define RCC_PLLCFGR_PLLQ_DIV8 3 -#define RCC_PLLCFGR_PLLQ_SHIFT 21 -#define RCC_PLLCFGR_PLLQ_MASK 0x3 - -#define RCC_PLLCFGR_PLLQEN BIT20 - -/* Division for PLLSAI3CLK, 0 == 7, 1 == 17 */ -#define RCC_PLLCFGR_PLLP BIT17 -#define RCC_PLLCFGR_PLLP_DIV7 0 -#define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP -#define RCC_PLLPEN (1 << 16) - -/** @defgroup rcc_pllcfgr_plln RCC_PLLCFGR PLLN values - * Allowed values 8 <= n <= 127, VCO output between 64 and 344 MHz - * @{*/ -#define RCC_PLLCFGR_PLLN_SHIFT 8 -#define RCC_PLLCFGR_PLLN_MASK 0x7f -/**@}*/ - -/** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values - * Allowed values 1 <= m <= 16, VCO input between 2.66 and 8 MHz - * @{*/ -#define RCC_PLLCFGR_PLLM_SHIFT 0x4 -#define RCC_PLLCFGR_PLLM_MASK 0xf -#define RCC_PLLCFGR_PLLM(x) ((x)-1) -/**@}*/ - -#define RCC_PLLCFGR_PLLSRC_NONE 0 -#define RCC_PLLCFGR_PLLSRC_HSI16 2 -#define RCC_PLLCFGR_PLLSRC_HSE 3 -#define RCC_PLLCFGR_PLLSRC_SHIFT 0 -#define RCC_PLLCFGR_PLLSRC_MASK 0x3 - -/**@}*/ - - -/** @defgroup rcc_cier_values RCC_CIER - Clock interrupt enable register - * @{ - */ -#define RCC_CIER_HSI48RDYIE (1 << 10) -#define RCC_CIER_LSE_CSSIE (1 << 9) -/* OSC ready interrupt enable bits */ -#define RCC_CIER_PLLRDYIE (1 << 5) -#define RCC_CIER_HSERDYIE (1 << 4) -#define RCC_CIER_HSIRDYIE (1 << 3) -#define RCC_CIER_LSERDYIE (1 << 1) -#define RCC_CIER_LSIRDYIE (1 << 0) -/**@}*/ - -/** @defgroup rcc_cifr_values RCC_CIFR - Clock interrupt flag register - * @{ - */ -#define RCC_CIFR_HSI48RDYF (1 << 10) -#define RCC_CIFR_LSECSSF (1 << 9) -#define RCC_CIFR_CSSF (1 << 8) -#define RCC_CIFR_PLLRDYF (1 << 5) -#define RCC_CIFR_HSERDYF (1 << 4) -#define RCC_CIFR_HSIRDYF (1 << 3) -#define RCC_CIFR_LSERDYF (1 << 1) -#define RCC_CIFR_LSIRDYF (1 << 0) -/**@}*/ - -/** @defgroup rcc_cicr_values RCC_CICR - Clock interrupt clear register - * @{ - */ -#define RCC_CICR_HSI48RDYC (1 << 10) -#define RCC_CICR_LSECSSC (1 << 9) -#define RCC_CICR_CSSC (1 << 8) -#define RCC_CICR_PLLRDYC (1 << 5) -#define RCC_CICR_HSERDYC (1 << 4) -#define RCC_CICR_HSIRDYC (1 << 3) -#define RCC_CICR_LSERDYC (1 << 1) -#define RCC_CICR_LSIRDYC (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values -@{*/ -#define RCC_AHB1RSTR_CRCRST (1 << 12) -#define RCC_AHB1RSTR_FLASHRST (1 << 8) -#define RCC_AHB1RSTR_FMACRST (1 << 4) -#define RCC_AHB1RSTR_CORDIC2RST (1 << 3) -#define RCC_AHB1RSTR_DMAMUX1RST (1 << 2) -#define RCC_AHB1RSTR_DMA2RST (1 << 1) -#define RCC_AHB1RSTR_DMA1RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values -@{*/ -#define RCC_AHB2RSTR_RNGRST (1 << 26) -#define RCC_AHB2RSTR_AESRST (1 << 24) -#define RCC_AHB2RSTR_DAC4RST (1 << 19) -#define RCC_AHB2RSTR_DAC3RST (1 << 18) -#define RCC_AHB2RSTR_DAC2RST (1 << 17) -#define RCC_AHB2RSTR_DAC1RST (1 << 16) -#define RCC_AHB2RSTR_ADC345RST (1 << 14) -#define RCC_AHB2RSTR_ADC12RST (1 << 13) -#define RCC_AHB2RSTR_GPIOGRST (1 << 6) -#define RCC_AHB2RSTR_GPIOFRST (1 << 5) -#define RCC_AHB2RSTR_GPIOERST (1 << 4) -#define RCC_AHB2RSTR_GPIODRST (1 << 3) -#define RCC_AHB2RSTR_GPIOCRST (1 << 2) -#define RCC_AHB2RSTR_GPIOBRST (1 << 1) -#define RCC_AHB2RSTR_GPIOARST (1 << 0) - -/**@}*/ - -/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values -@{*/ -#define RCC_AHB3RSTR_QSPIRST (1 << 8) -#define RCC_AHB3RSTR_FMCRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTRx reset values (full set) -@{*/ -/** @defgroup rcc_apb1rstr1_rst RCC_APB1RSTR1 reset values -@{*/ -#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) -#define RCC_APB1RSTR1_I2C3RST (1 << 30) -#define RCC_APB1RSTR1_PWRRST (1 << 28) -#define RCC_APB1RSTR1_FDCANRST (1 << 25) -#define RCC_APB1RSTR1_USBRST (1 << 23) -#define RCC_APB1RSTR1_I2C2RST (1 << 22) -#define RCC_APB1RSTR1_I2C1RST (1 << 21) -#define RCC_APB1RSTR1_UART5RST (1 << 20) -#define RCC_APB1RSTR1_UART4RST (1 << 19) -#define RCC_APB1RSTR1_USART3RST (1 << 18) -#define RCC_APB1RSTR1_USART2RST (1 << 17) -#define RCC_APB1RSTR1_SPI3RST (1 << 15) -#define RCC_APB1RSTR1_SPI2RST (1 << 14) -#define RCC_APB1RSTR1_CRSRST (1 << 8) -#define RCC_APB1RSTR1_TIM7RST (1 << 5) -#define RCC_APB1RSTR1_TIM6RST (1 << 4) -#define RCC_APB1RSTR1_TIM5RST (1 << 3) -#define RCC_APB1RSTR1_TIM4RST (1 << 2) -#define RCC_APB1RSTR1_TIM3RST (1 << 1) -#define RCC_APB1RSTR1_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr2_rst RCC_APB1RSTR2 reset values -@{*/ -#define RCC_APB1RSTR2_UCPD1RST (1 << 8) -#define RCC_APB1RSTR2_I2C4RST (1 << 1) -#define RCC_APB1RSTR2_LPUART1RST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_HRTIM1RST (1 << 26) -#define RCC_APB2RSTR_SAI1RST (1 << 21) -#define RCC_APB2RSTR_TIM20RST (1 << 20) -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_SPI4RST (1 << 15) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) - *@{*/ -/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values - *@{*/ -#define RCC_AHB1ENR_CRCEN (1 << 12) -#define RCC_AHB1ENR_FLASHEN (1 << 8) -#define RCC_AHB1ENR_FMACEN (1 << 4) -#define RCC_AHB1ENR_CORDICEN (1 << 3) -#define RCC_AHB1ENR_DMAMUX1EN (1 << 2) -#define RCC_AHB1ENR_DMA2EN (1 << 1) -#define RCC_AHB1ENR_DMA1EN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values - *@{*/ -#define RCC_AHB2ENR_RNGEN (1 << 26) -#define RCC_AHB2ENR_AESEN (1 << 24) -#define RCC_AHB2ENR_DAC4EN (1 << 19) -#define RCC_AHB2ENR_DAC3EN (1 << 18) -#define RCC_AHB2ENR_DAC2EN (1 << 17) -#define RCC_AHB2ENR_DAC1EN (1 << 16) -#define RCC_AHB2ENR_ADC345EN (1 << 14) -#define RCC_AHB2ENR_ADC12EN (1 << 13) -#define RCC_AHB2ENR_GPIOGEN (1 << 6) -#define RCC_AHB2ENR_GPIOFEN (1 << 5) -#define RCC_AHB2ENR_GPIOEEN (1 << 4) -#define RCC_AHB2ENR_GPIODEN (1 << 3) -#define RCC_AHB2ENR_GPIOCEN (1 << 2) -#define RCC_AHB2ENR_GPIOBEN (1 << 1) -#define RCC_AHB2ENR_GPIOAEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values - *@{*/ -#define RCC_AHB3ENR_QSPIEN (1 << 8) -#define RCC_AHB3ENR_FMCEN (1 << 0) -/**@}*/ - -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENRx enable values (full set) - *@{*/ -/** @defgroup rcc_apb1enr1_en RCC_APB1ENR1 enable values - *@{*/ -#define RCC_APB1ENR1_LPTIM1EN (1 << 31) -#define RCC_APB1ENR1_I2C3EN (1 << 30) -#define RCC_APB1ENR1_PWREN (1 << 28) -#define RCC_APB1ENR1_FDCANEN (1 << 25) -#define RCC_APB1ENR1_USBEN (1 << 23) -#define RCC_APB1ENR1_I2C2EN (1 << 22) -#define RCC_APB1ENR1_I2C1EN (1 << 21) -#define RCC_APB1ENR1_UART5EN (1 << 20) -#define RCC_APB1ENR1_UART4EN (1 << 19) -#define RCC_APB1ENR1_USART3EN (1 << 18) -#define RCC_APB1ENR1_USART2EN (1 << 17) -#define RCC_APB1ENR1_SPI3EN (1 << 15) -#define RCC_APB1ENR1_SPI2EN (1 << 14) -#define RCC_APB1ENR1_WWDGEN (1 << 11) -#define RCC_APB1ENR1_RTCAPBEN (1 << 10) -#define RCC_APB1ENR1_CRSEN (1 << 8) -#define RCC_APB1ENR1_TIM7EN (1 << 5) -#define RCC_APB1ENR1_TIM6EN (1 << 4) -#define RCC_APB1ENR1_TIM5EN (1 << 3) -#define RCC_APB1ENR1_TIM4EN (1 << 2) -#define RCC_APB1ENR1_TIM3EN (1 << 1) -#define RCC_APB1ENR1_TIM2EN (1 << 0) -/*@}*/ - -/** @defgroup rcc_apb1enr2_en RCC_APB1ENR2 enable values - *@{*/ -#define RCC_APB1ENR2_UCPD1EN (1 << 8) -#define RCC_APB1ENR2_I2C4EN (1 << 1) -#define RCC_APB1ENR2_LPUART1EN (1 << 0) -/*@}*/ -/*@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values - *@{*/ -#define RCC_APB2ENR_HRTIM1EN (1 << 26) -#define RCC_APB2ENR_SAI1EN (1 << 21) -#define RCC_APB2ENR_TIM20EN (1 << 20) -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_SPI4EN (1 << 15) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_SYSCFGEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb1smenr_values RCC_AHB1SMENR - AHB1 periph clock in sleep mode - * @{ - */ -#define RCC_AHB1SMENR_CRCSMEN (1 << 12) -#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) -#define RCC_AHB1SMENR_FLASHSMEN (1 << 8) -#define RCC_AHB1SMENR_FMACSMEN (1 << 4) -#define RCC_AHB1SMENR_CORFDICSMEN (1 << 3) -#define RCC_AHB1SMENR_DMAMUX1SMEN (1 << 2) -#define RCC_AHB1SMENR_DMA2SMEN (1 << 1) -#define RCC_AHB1SMENR_DMA1SMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2smenr RCC_AHB2SMENR - AHB2 periph clock in sleep mode - * @{ - */ -#define RCC_AHB2SMENR_RNGSMEN (1 << 26) -#define RCC_AHB2SMENR_AESSMEN (1 << 24) -#define RCC_AHB2SMENR_DAC4SMEN (1 << 19) -#define RCC_AHB2SMENR_DAC3SMEN (1 << 18) -#define RCC_AHB2SMENR_DAC2SMEN (1 << 17) -#define RCC_AHB2SMENR_DAC1SMEN (1 << 16) -#define RCC_AHB2SMENR_ADC345SMEN (1 << 14) -#define RCC_AHB2SMENR_ADC12SMEN (1 << 13) -#define RCC_AHB2SMENR_SRAM2SMEN (1 << 10) -#define RCC_AHB2SMENR_CCMSRAMSMEN (1 << 9) -#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6) -#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5) -#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) -#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) -#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) -#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) -#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb3smenr RCC_AHB3SMENR - AHB3 periph clock in sleep mode - * @{ - */ -#define RCC_AHB3SMENR_QSPISMEN (1 << 8) -#define RCC_AHB3SMENR_FMCSMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1smenr1 RCC_APB1SMENR1 - APB1 periph clock in sleep mode - * @{ - */ -#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) -#define RCC_APB1SMENR1_I2C3SMEN (1 << 30) -#define RCC_APB1SMENR1_PWRSMEN (1 << 28) -#define RCC_APB1SMENR1_FDCANSMEN (1 << 25) -#define RCC_APB1SMENR1_USBSMEN (1 << 23) -#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) -#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) -#define RCC_APB1SMENR1_UART5SMEN (1 << 20) -#define RCC_APB1SMENR1_UART4SMEN (1 << 19) -#define RCC_APB1SMENR1_USART3SMEN (1 << 18) -#define RCC_APB1SMENR1_USART2SMEN (1 << 17) -#define RCC_APB1SMENR1_SPI3SMEN (1 << 15) -#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) -#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) -#define RCC_APB1SMENR1_RTCAPBSMEN (1 << 10) -#define RCC_APB1SMENR1_TIM7SMEN (1 << 5) -#define RCC_APB1SMENR1_TIM6SMEN (1 << 4) -#define RCC_APB1SMENR1_TIM5SMEN (1 << 3) -#define RCC_APB1SMENR1_TIM4SMEN (1 << 2) -#define RCC_APB1SMENR1_TIM3SMEN (1 << 1) -#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1smenr2 RCC_APB1SMENR2 - APB1 periph clock in sleep mode - * @{ - */ -#define RCC_APB1SMENR2_UCPD1SMEN (1 << 8) -#define RCC_APB1SMENR2_I2C4SMEN (1 << 1) -#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2smenr RCC_APB2SMENR - APB2 periph clock in sleep mode - * @{ - */ -#define RCC_APB2SMENR_HRTIM1SMEN (1 << 26) -#define RCC_APB2SMENR_SAI1SMEN (1 << 21) -#define RCC_APB2SMENR_TIM20SMEN (1 << 20) -#define RCC_APB2SMENR_TIM17SMEN (1 << 18) -#define RCC_APB2SMENR_TIM16SMEN (1 << 17) -#define RCC_APB2SMENR_TIM15SMEN (1 << 16) -#define RCC_APB2SMENR_SPI4SMEN (1 << 15) -#define RCC_APB2SMENR_USART1SMEN (1 << 14) -#define RCC_APB2SMENR_TIM8SMEN (1 << 13) -#define RCC_APB2SMENR_SPI1SMEN (1 << 12) -#define RCC_APB2SMENR_TIM1SMEN (1 << 11) -#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_ccipr_values RCC_CCIPR - Peripherals independent clock config register - * @{ - */ -/* all fields are 2 bits */ -#define RCC_CCIPR_SEL_MASK 0x3 - -#define RCC_CCIPR_ADC345_NONE 0 -#define RCC_CCIPR_ADC345_PLLP 1 -#define RCC_CCIPR_ADC345_SYS 2 -#define RCC_CCIPR_ADC345_SHIFT 30 - -#define RCC_CCIPR_ADC12_NONE 0 -#define RCC_CCIPR_ADC12_PLLP 1 -#define RCC_CCIPR_ADC12_SYS 2 -#define RCC_CCIPR_ADC12_SHIFT 28 - -#define RCC_CCIPR_CLK48_HSI48 0 -#define RCC_CCIPR_CLK48_PLLQ 2 -#define RCC_CCIPR_CLK48_SHIFT 26 - -#define RCC_CCIPR_FDCAN_HSE 0 -#define RCC_CCIPR_FDCAN_PLLQ 1 -#define RCC_CCIPR_FDCAN_PCLK 2 -#define RCC_CCIPR_FDCAN_SHIFT 24 - -#define RCC_CCIPR_I2S23_SYS 0 -#define RCC_CCIPR_I2S23_PLLQ 1 -#define RCC_CCIPR_I2S23_EXT 2 -#define RCC_CCIPR_I2S23_SHI16 3 -#define RCC_CCIPR_I2S23_SHIFT 22 - -#define RCC_CCIPR_SAI1_SYS 0 -#define RCC_CCIPR_SAI1_PLLQ 1 -#define RCC_CCIPR_SAI1_EXT 2 -#define RCC_CCIPR_SAI1_HSI16 3 -#define RCC_CCIPR_SAI1_SHIFT 20 - -#define RCC_CCIPR_LPTIM1_PCLK 0 -#define RCC_CCIPR_LPTIM1_LSI 1 -#define RCC_CCIPR_LPTIM1_HSI16 2 -#define RCC_CCIPR_LPTIM1_LSE 3 -#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 - -#define RCC_CCIPR_I2Cx_PCLK 0 -#define RCC_CCIPR_I2Cx_SYS 1 -#define RCC_CCIPR_I2Cx_HSI16 2 -#define RCC_CCIPR_I2C3_SHIFT 16 -#define RCC_CCIPR_I2C2_SHIFT 14 -#define RCC_CCIPR_I2C1_SHIFT 12 - -#define RCC_CCIPR_LPUART1_PCLK 0 -#define RCC_CCIPR_LPUART1_SYS 1 -#define RCC_CCIPR_LPUART1_HSI16 2 -#define RCC_CCIPR_LPUART1_LSE 3 -#define RCC_CCIPR_LPUART1SEL_SHIFT 10 - -#define RCC_CCIPR_USARTx_PCLK 0 -#define RCC_CCIPR_USARTx_SYS 1 -#define RCC_CCIPR_USARTx_HSI16 2 -#define RCC_CCIPR_USARTx_LSE 3 -#define RCC_CCIPR_UARTx_PCLK RCC_CCIPR_USARTx_PCLK -#define RCC_CCIPR_UARTx_SYS RCC_CCIPR_USARTx_SYS -#define RCC_CCIPR_UARTx_HSI16 RCC_CCIPR_USARTx_HSI16 -#define RCC_CCIPR_UARTx_LSE RCC_CCIPR_USARTx_LSE -#define RCC_CCIPR_UART5_SHIFT 8 -#define RCC_CCIPR_UART4_SHIFT 6 -#define RCC_CCIPR_USART3_SHIFT 4 -#define RCC_CCIPR_USART2_SHIFT 2 -#define RCC_CCIPR_USART1_SHIFT 0 -/**@}*/ - -/** defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2 - * @{ - */ -#define RCC_CCIPR2_QSPI_SYS 0 -#define RCC_CCIPR2_QSPI_HSI16 1 -#define RCC_CCIPR2_QSPI_PLLQ 2 -#define RCC_CCIPR2_QSPI_SHIFT 20 - -#define RCC_CCIPR2_I2C4_PCLK 0 -#define RCC_CCIPR2_I2C4_SYS 1 -#define RCC_CCIPR2_I2C4_HSI16 2 -#define RCC_CCIPR2_I2C4_SHIFT 0 -/**@}*/ - -/** @defgroup rcc_bdcr_values RCC_BDCR - Backup domain control register - * @{ - */ - -#define RCC_BDCR_LSCOSEL (1 << 25) -#define RCC_BDCR_LSCOEN (1 << 24) -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) - -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSEDIV32 3 -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_MASK 0x3 - -#define RCC_BDCR_LSECSSD (1 << 6) -#define RCC_BDCR_LSECSSON (1 << 5) - -#define RCC_BDCR_LSEDRV_LOW 0 -#define RCC_BDCR_LSEDRV_MEDLOW 1 -#define RCC_BDCR_LSEDRV_MEDHIGH 2 -#define RCC_BDCR_LSEDRV_HIGH 3 -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV_MASK 0x3 - -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) -/**@}*/ - -/** @defgroup rcc_csr_values RCC_CSR - Control/Status register - * @{ - */ -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_BORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 23) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF) - -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) -/**@}*/ - -/** @defgroup rcc_crrcr RCC_CRRCR Clock Recovery RC register - * @{ - */ -#define RCC_CRRCR_HSI48VAL_MASK 0x1ff -#define RCC_CRRCR_HSI48VAL_SHIFT 7 - -#define RCC_CRRCR_HSI48RDY BIT1 -#define RCC_CRRCR_HSI48ON BIT0 -/**@}*/ - -/* --- Variable definitions ------------------------------------------------ */ - -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI16, RCC_LSE, RCC_LSI, RCC_HSI48 -}; - - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - - /* AHB1 peripherals */ - RCC_CRC = _REG_BIT(0x48, 12), - RCC_FLASH = _REG_BIT(0x48, 8), - RCC_FMAC = _REG_BIT(0x48, 4), - RCC_CORDIC = _REG_BIT(0x48, 3), - RCC_DMAMUX1 = _REG_BIT(0x48, 2), - RCC_DMA2 = _REG_BIT(0x48, 1), - RCC_DMA1 = _REG_BIT(0x48, 0), - - /* AHB2 peripherals */ - RCC_RNG = _REG_BIT(0x4c, 26), - RCC_AES = _REG_BIT(0x4c, 24), - RCC_DAC4 = _REG_BIT(0x4c, 19), - RCC_DAC3 = _REG_BIT(0x4c, 18), - RCC_DAC2 = _REG_BIT(0x4c, 17), - RCC_DAC1 = _REG_BIT(0x4c, 16), - RCC_ADC345 = _REG_BIT(0x4c, 14), - RCC_ADC12 = _REG_BIT(0x4c, 13), - RCC_ADC1 = _REG_BIT(0x4c, 13), /* Compatibility */ - RCC_GPIOG = _REG_BIT(0x4c, 6), - RCC_GPIOF = _REG_BIT(0x4c, 5), - RCC_GPIOE = _REG_BIT(0x4c, 4), - RCC_GPIOD = _REG_BIT(0x4c, 3), - RCC_GPIOC = _REG_BIT(0x4c, 2), - RCC_GPIOB = _REG_BIT(0x4c, 1), - RCC_GPIOA = _REG_BIT(0x4c, 0), - - /* AHB3 peripherals */ - RCC_QSPI = _REG_BIT(0x50, 8), - RCC_FMC = _REG_BIT(0x50, 0), - - /* APB1 peripherals */ - RCC_LPTIM1 = _REG_BIT(0x58, 31), - RCC_I2C3 = _REG_BIT(0x58, 30), - RCC_PWR = _REG_BIT(0x58, 28), - RCC_FDCAN = _REG_BIT(0x58, 25), - RCC_USB = _REG_BIT(0x58, 23), - RCC_I2C2 = _REG_BIT(0x58, 22), - RCC_I2C1 = _REG_BIT(0x58, 21), - RCC_UART5 = _REG_BIT(0x58, 20), - RCC_UART4 = _REG_BIT(0x58, 19), - RCC_USART3 = _REG_BIT(0x58, 18), - RCC_USART2 = _REG_BIT(0x58, 17), - RCC_SPI3 = _REG_BIT(0x58, 15), - RCC_SPI2 = _REG_BIT(0x58, 14), - RCC_WWDG = _REG_BIT(0x58, 11), - RCC_RTCAPB = _REG_BIT(0x58, 10), - RCC_CRS = _REG_BIT(0x58, 8), - RCC_TIM7 = _REG_BIT(0x58, 5), - RCC_TIM6 = _REG_BIT(0x58, 4), - RCC_TIM5 = _REG_BIT(0x58, 3), - RCC_TIM4 = _REG_BIT(0x58, 2), - RCC_TIM3 = _REG_BIT(0x58, 1), - RCC_TIM2 = _REG_BIT(0x58, 0), - /* apb1-2 */ - RCC_UCPD1 = _REG_BIT(0x5c, 8), - RCC_I2C4 = _REG_BIT(0x5c, 1), - RCC_LPUART1 = _REG_BIT(0x5c, 0), - - /* APB2 peripherals */ - RCC_HRTIM1 = _REG_BIT(0x60, 26), - RCC_SAI1 = _REG_BIT(0x60, 21), - RCC_TIM20 = _REG_BIT(0x60, 20), - RCC_TIM17 = _REG_BIT(0x60, 18), - RCC_TIM16 = _REG_BIT(0x60, 17), - RCC_TIM15 = _REG_BIT(0x60, 16), - RCC_SPI4 = _REG_BIT(0x60, 15), - RCC_USART1 = _REG_BIT(0x60, 14), - RCC_TIM8 = _REG_BIT(0x60, 13), - RCC_SPI1 = _REG_BIT(0x60, 12), - RCC_TIM1 = _REG_BIT(0x60, 11), - RCC_SYSCFG = _REG_BIT(0x60, 0), - - /* AHB1 peripherals in sleep mode */ - SCC_CRC = _REG_BIT(0x68, 12), - SCC_SRAM1 = _REG_BIT(0x68, 9), - SCC_FLASH = _REG_BIT(0x68, 8), - SCC_FMAC = _REG_BIT(0x68, 4), - SCC_CORDIC = _REG_BIT(0x68, 3), - SCC_DMAMUX1 = _REG_BIT(0x68, 2), - SCC_DMA2 = _REG_BIT(0x68, 1), - SCC_DMA1 = _REG_BIT(0x68, 0), - - /* AHB2 peripherals in sleep mode */ - SCC_RNG = _REG_BIT(0x6c, 26), - SCC_AES = _REG_BIT(0x6c, 24), - SCC_DAC4 = _REG_BIT(0x6c, 19), - SCC_DAC3 = _REG_BIT(0x6c, 18), - SCC_DAC2 = _REG_BIT(0x6c, 17), - SCC_DAC1 = _REG_BIT(0x6c, 16), - SCC_ADC345 = _REG_BIT(0x6c, 14), - SCC_ADC12 = _REG_BIT(0x6c, 13), - SCC_ADC1 = _REG_BIT(0x6c, 13), /* Compatibility */ - SCC_CCMSRAM = _REG_BIT(0x6c, 10), - SCC_SRAM2 = _REG_BIT(0x6c, 9), - SCC_GPIOG = _REG_BIT(0x6c, 6), - SCC_GPIOF = _REG_BIT(0x6c, 5), - SCC_GPIOE = _REG_BIT(0x6c, 4), - SCC_GPIOD = _REG_BIT(0x6c, 3), - SCC_GPIOC = _REG_BIT(0x6c, 2), - SCC_GPIOB = _REG_BIT(0x6c, 1), - SCC_GPIOA = _REG_BIT(0x6c, 0), - - /* AHB3 peripherals in sleep mode */ - SCC_QSPI = _REG_BIT(0x70, 8), - SCC_FMC = _REG_BIT(0x70, 0), - - /* APB1 peripherals in sleep mode */ - SCC_LPTIM1 = _REG_BIT(0x58, 31), - SCC_I2C3 = _REG_BIT(0x58, 30), - SCC_PWR = _REG_BIT(0x58, 28), - SCC_FDCAN = _REG_BIT(0x58, 25), - SCC_USB = _REG_BIT(0x58, 23), - SCC_I2C2 = _REG_BIT(0x58, 22), - SCC_I2C1 = _REG_BIT(0x58, 21), - SCC_UART5 = _REG_BIT(0x58, 20), - SCC_UART4 = _REG_BIT(0x58, 19), - SCC_USART3 = _REG_BIT(0x58, 18), - SCC_USART2 = _REG_BIT(0x58, 17), - SCC_SPI3 = _REG_BIT(0x58, 15), - SCC_SPI2 = _REG_BIT(0x58, 14), - SCC_WWDG = _REG_BIT(0x58, 11), - SCC_RTCAPB = _REG_BIT(0x58, 10), - SCC_CRS = _REG_BIT(0x58, 8), - SCC_TIM7 = _REG_BIT(0x58, 5), - SCC_TIM6 = _REG_BIT(0x58, 4), - SCC_TIM5 = _REG_BIT(0x58, 3), - SCC_TIM4 = _REG_BIT(0x58, 2), - SCC_TIM3 = _REG_BIT(0x58, 1), - SCC_TIM2 = _REG_BIT(0x58, 0), - /* apb1-2 */ - SCC_UCPD1 = _REG_BIT(0x5c, 8), - SCC_I2C4 = _REG_BIT(0x5c, 1), - SCC_LPUART1 = _REG_BIT(0x5c, 0), - - /* APB2 peripherals in sleep mode */ - SCC_HRTIM1 = _REG_BIT(0x60, 26), - SCC_SAI1 = _REG_BIT(0x60, 21), - SCC_TIM20 = _REG_BIT(0x60, 20), - SCC_TIM17 = _REG_BIT(0x60, 18), - SCC_TIM16 = _REG_BIT(0x60, 17), - SCC_TIM15 = _REG_BIT(0x60, 16), - SCC_SPI4 = _REG_BIT(0x60, 15), - SCC_USART1 = _REG_BIT(0x60, 14), - SCC_TIM8 = _REG_BIT(0x60, 13), - SCC_SPI1 = _REG_BIT(0x60, 12), - SCC_TIM1 = _REG_BIT(0x60, 11), - SCC_SYSCFG = _REG_BIT(0x60, 0), -}; - -enum rcc_periph_rst { - /* AHB1 peripherals */ - RST_CRC = _REG_BIT(0x28, 12), - RST_FLASH = _REG_BIT(0x28, 8), - RST_FMAC = _REG_BIT(0x28, 4), - RST_CORDIC = _REG_BIT(0x28, 3), - RST_DMAMUX1 = _REG_BIT(0x28, 2), - RST_DMA2 = _REG_BIT(0x28, 1), - RST_DMA1 = _REG_BIT(0x28, 0), - - /* AHB2 peripherals */ - RST_RNG = _REG_BIT(0x2c, 26), - RST_AES = _REG_BIT(0x2c, 24), - RST_DAC4 = _REG_BIT(0x2c, 19), - RST_DAC3 = _REG_BIT(0x2c, 18), - RST_DAC2 = _REG_BIT(0x2c, 17), - RST_DAC1 = _REG_BIT(0x2c, 16), - RST_ADC345 = _REG_BIT(0x2c, 14), - RST_ADC12 = _REG_BIT(0x2c, 13), - RST_ADC1 = _REG_BIT(0x2c, 13), /* Compatibility */ - RST_GPIOG = _REG_BIT(0x2c, 6), - RST_GPIOF = _REG_BIT(0x2c, 5), - RST_GPIOE = _REG_BIT(0x2c, 4), - RST_GPIOD = _REG_BIT(0x2c, 3), - RST_GPIOC = _REG_BIT(0x2c, 2), - RST_GPIOB = _REG_BIT(0x2c, 1), - RST_GPIOA = _REG_BIT(0x2c, 0), - - /* AHB3 peripherals */ - RST_QSPI = _REG_BIT(0x30, 8), - RST_FMC = _REG_BIT(0x30, 0), - - /* APB1 peripherals */ - RST_LPTIM1 = _REG_BIT(0x38, 31), - RST_I2C3 = _REG_BIT(0x38, 30), - RST_PWR = _REG_BIT(0x38, 28), - RST_FDCAN = _REG_BIT(0x38, 25), - RST_USB = _REG_BIT(0x38, 23), - RST_I2C2 = _REG_BIT(0x38, 22), - RST_I2C1 = _REG_BIT(0x38, 21), - RST_UART5 = _REG_BIT(0x38, 20), - RST_UART4 = _REG_BIT(0x38, 19), - RST_USART3 = _REG_BIT(0x38, 18), - RST_USART2 = _REG_BIT(0x38, 17), - RST_SPI3 = _REG_BIT(0x38, 15), - RST_SPI2 = _REG_BIT(0x38, 14), - RST_CRS = _REG_BIT(0x38, 8), - RST_TIM7 = _REG_BIT(0x38, 5), - RST_TIM6 = _REG_BIT(0x38, 4), - RST_TIM5 = _REG_BIT(0x38, 3), - RST_TIM4 = _REG_BIT(0x38, 2), - RST_TIM3 = _REG_BIT(0x38, 1), - RST_TIM2 = _REG_BIT(0x38, 0), - /* apb1-2 */ - RST_UCPD1 = _REG_BIT(0x3c, 8), - RST_I2C4 = _REG_BIT(0x3c, 1), - RST_LPUART1 = _REG_BIT(0x3c, 0), - - /* APB2 peripherals */ - RST_HRTIM1 = _REG_BIT(0x40, 26), - RST_SAI1 = _REG_BIT(0x40, 21), - RST_TIM20 = _REG_BIT(0x40, 20), - RST_TIM17 = _REG_BIT(0x40, 18), - RST_TIM16 = _REG_BIT(0x40, 17), - RST_TIM15 = _REG_BIT(0x40, 16), - RST_SPI4 = _REG_BIT(0x40, 15), - RST_USART1 = _REG_BIT(0x40, 14), - RST_TIM8 = _REG_BIT(0x40, 13), - RST_SPI1 = _REG_BIT(0x40, 12), - RST_TIM1 = _REG_BIT(0x40, 11), - RST_SYSCFG = _REG_BIT(0x40, 0), - -}; -#include - -BEGIN_DECLS - - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/gpio.h b/libopencm3/include/libopencm3/stm32/gpio.h deleted file mode 100644 index d237cda..0000000 --- a/libopencm3/include/libopencm3/stm32/gpio.h +++ /dev/null @@ -1,52 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32G4) -# include -#elif defined(STM32H7) -# include -#elif defined(GD32F1X0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/h7/dac.h b/libopencm3/include/libopencm3/stm32/h7/dac.h deleted file mode 100644 index 3106378..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/dac.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32H7xx DAC - -@ingroup STM32H7xx_defines - -@version 1.0.0 - -@date 6 November 2019 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/doc-stm32h7.h b/libopencm3/include/libopencm3/stm32/h7/doc-stm32h7.h deleted file mode 100644 index 97b6257..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/doc-stm32h7.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @page libopencm3 STM32H7 - -@version 1.0.0 - -API documentation for ST Microelectronics STM32H7 Cortex M7 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32H7xx STM32H7xx -Libraries for ST Microelectronics STM32H7xx series. - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32H7xx_defines STM32Hxx Defines - -@brief Defined Constants and Types for the STM32H7xx series - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/h7/exti.h b/libopencm3/include/libopencm3/stm32/h7/exti.h deleted file mode 100644 index 86b2d85..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/exti.h +++ /dev/null @@ -1,43 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @ingroup STM32H7xx_defines - * - * @brief Defined Constants and Types for the STM32H7xx EXTI Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -/** EXTI CPU Event Pending Register 1 */ -#define EXTI_CPUPR1 MMIO32(EXTI_BASE + 0x88) -#define EXTI_PR EXTI_CPUPR1 - -BEGIN_DECLS - -END_DECLS - -#endif /* LIBOPENCM3_EXTI_H */ -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/h7/flash.h b/libopencm3/include/libopencm3/stm32/h7/flash.h deleted file mode 100644 index 5fb258c..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/flash.h +++ /dev/null @@ -1,54 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * @brief Defined Constants and Types for the STM32H7xx Flash - * controller - * @ingroup STM32H7xx_defines - * - * @author @htmlonly © @endhtmlonly 2019 - * Brian Viele - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include -#include - -/**@{*/ - -/** @addtogroup flash_acr_values FLASH_ACR values - * @ingroup flash_registers -@{*/ -#define FLASH_ACR_WRHF_VOS1_70MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS1_185MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS1_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS2_55MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS2_165MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS2_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS3_45MHZ (0 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS3_135MHZ (1 << FLASH_ACR_WRHIGHFREQ_SHIFT) -#define FLASH_ACR_WRHF_VOS3_225MHZ (2 << FLASH_ACR_WRHIGHFREQ_SHIFT) -/*@}*/ -#define FLASH_ACR_WRHIGHFREQ_MASK (0x3) -#define FLASH_ACR_WRHIGHFREQ_SHIFT (0x4) - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/h7/fmc.h b/libopencm3/include/libopencm3/stm32/h7/fmc.h deleted file mode 100644 index 5bdd097..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/fmc.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @defgroup fmc_defines FMC Defines - * @brief Defined Constants and Types for the STM32H7xx Flexible Memory - * Controller - * @ingroup STM32H7xx_defines - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_H7_FMC_H -#define LIBOPENCM3_H7_FMC_H - -#ifndef LIBOPENCM3_FSMC_H -#error "This file should not be included directly, it is included with fsmc.h" -#endif - -#include - -/* --- Convenience macros -------------------------------------------------- */ -#define FSMC_BASE FMC_BASE - -/** FMCEN: Global FMC controller Enable. Note: Don't care in BCR2..4 */ -#define FSMC_BCR_FMCEN BIT31 -/** WFDIS: Global Write FIFO Disable. Note: Don't care in BCR2..4 */ -#define FSMC_BCR_WFDIS BIT21 -/** WFDIS: Global Continuous Clock Enable. Note: Don't care in BCR2..4 */ -#define FSMC_BCR_CCLKEN BIT20 - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/h7/gpio.h b/libopencm3/include/libopencm3/stm32/h7/gpio.h deleted file mode 100644 index 7f9067e..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/gpio.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32H7xx General Purpose I/O - -@ingroup STM32H7xx_defines - -@version 1.0.0 - -@date 6 November 2019 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/h7/irq.json b/libopencm3/include/libopencm3/stm32/h7/irq.json deleted file mode 100644 index 70d8c06..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/irq.json +++ /dev/null @@ -1,157 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_str0", - "dma1_str1", - "dma1_str2", - "dma1_str3", - "dma1_str4", - "dma1_str5", - "dma1_str6", - "adc1_2", - "fdcan1_it0", - "fdcan2_it0", - "fdcan1_it1", - "fdcan2_it2", - "exti9_5", - "tim1_brk_tim9", - "tim1_up_tim10", - "tim1_trg_com_tim11", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "reserved1", - "tim8_brk_tim12", - "tim8_up_tim13", - "tim8_trg_com_tim14", - "tim8_cc", - "dma1_str7", - "fsmc", - "sdmmc1", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dac", - "tim7", - "dma2_str0", - "dma2_str1", - "dma2_str2", - "dma2_str3", - "dma2_str4", - "eth", - "eth_wkup", - "fdcan_cal", - "cm7_sev", - "reserved2", - "reserved3", - "reserved4", - "dma2_str5", - "dma2_str6", - "dma2_str7", - "usart6", - "i2c3_ev", - "i2c3_er", - "otg_hs_ep1_out", - "otg_hs_ep1_in", - "otg_hs_wkup", - "otg_hs", - "dcmi", - "cryp", - "hash_rng", - "fpu", - "uart7", - "uart8", - "spi4", - "spi5", - "spi6", - "sai1", - "ltdc", - "ltdc_er", - "dma2d", - "sai2", - "quadspi", - "lp_tim1", - "cec", - "i2c4_ev", - "i2c4_er", - "spdifrx", - "otg_fs_ep1_out", - "otg_fs_ep1_in", - "otg_fs_wkup", - "otg_fs", - "dmamux1_ov", - "hrtim1_mst", - "hrtim1_tima", - "hrtim1_timb", - "hrtim1_timc", - "hrtim1_timd", - "hrtim1_time", - "hrtim1_flt", - "dfsdm1_it0", - "dfsdm1_it1", - "dfsdm1_it2", - "dfsdm1_it3", - "sai3", - "swpmi1", - "tim15", - "tim16", - "tim17", - "mdios_wkup", - "mdios", - "jpeg", - "mdma", - "reserved5", - "sdmmc2", - "hsem0", - "reserved6", - "adc3", - "dmamux2_ovr", - "bdma_ch0", - "bdma_ch1", - "bdma_ch2", - "bdma_ch3", - "bdma_ch4", - "bdma_ch5", - "bdma_ch6", - "bdma_ch7", - "comp", - "lptim2", - "lptim3", - "lptim4", - "lptim5", - "lpuart", - "wwdg1_rst", - "crs", - "ramecc1", - "sai4", - "reserved7", - "reserved8", - "wkup" - ], - "partname_humanreadable": "STM32 H7 series", - "partname_doxygen": "STM32H7", - "includeguard": "LIBOPENCM3_STM32_H7_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/h7/memorymap.h b/libopencm3/include/libopencm3/stm32/h7/memorymap.h deleted file mode 100644 index ec892d2..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/memorymap.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32H7 specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE 0x40000000U -#define PERIPH_BASE_APB1 0x40000000U -#define PERIPH_BASE_APB2 0x40010000U -#define PERIPH_BASE_APB3 0x50000000U -#define PERIPH_BASE_AHB1 0x40020000U -#define PERIPH_BASE_AHB2 0x48020000U -#define PERIPH_BASE_AHB3 0x51000000U -#define PERIPH_BASE_AHB4 0x58000000U - -/* Table 8: Register boundary addresses */ - -/* AHB4 Peripherals */ -#define GPIO_PORT_A_BASE 0x58020000U -#define GPIO_PORT_B_BASE 0x58020400U -#define GPIO_PORT_C_BASE 0x58020800U -#define GPIO_PORT_D_BASE 0x58020C00U -#define GPIO_PORT_E_BASE 0x58021000U -#define GPIO_PORT_F_BASE 0x58021400U -#define GPIO_PORT_G_BASE 0x58021800U -#define GPIO_PORT_H_BASE 0x58021C00U -#define GPIO_PORT_I_BASE 0x58022000U -#define GPIO_PORT_J_BASE 0x58022400U -#define GPIO_PORT_K_BASE 0x58022800U -#define RCC_BASE 0x58024400U -#define POWER_CONTROL_BASE 0x58024800U -#define CRC_BASE 0x58024C00U -#define BDMA_BASE 0x58025400U -#define DMAMUX2_BASE 0x58025800U -#define ADC3_BASE 0x58026000U -#define HSEM_BASE 0x58026400U - -/* APB4 Peripherals */ -#define SAI4_BASE 0x58005400U -#define IWDG1_BASE 0x58004800U -#define RTC_BASE 0x58004000U -#define VREF_BASE 0x58003C00U -#define COMP1_BASE 0x58003800U -#define LPTIM5_BASE 0x58003000U -#define LPTIM4_BASE 0x58002C00U -#define LPTIM3_BASE 0x58002800U -#define LPTIM2_BASE 0x58002400U -#define I2C4_BASE 0x58001C00U -#define SPI6_BASE 0x58001400U -#define LPUART1_BASE 0x58000C00U -#define SYSCFG_BASE 0x58000400U -#define EXTI_BASE 0x58000000U - -/* AHB3 Peripherals */ -#define DELAY_SDMMC1_BASE 0x52008000U -#define SDMMC1_BASE 0x52007000U -#define DELAY_QSPI_BASE 0x52006000U -#define QUADSPI_BASE 0x52005000U -#define FMC_BASE 0x52004000U -#define JPEG_BASE 0x52003000U -#define FLASH_MEM_INTERFACE_BASE 0x52002000U -#define CHROMART_BASE 0x52001000U -#define MDMA_BASE 0x52000000U -#define GPV_BASE 0x51000000U - -/* APB3 Peripherals */ -#define WWDG1_BASE 0x50003000U -#define LTDC_BASE 0x50001000U - -/* AHB2 Peripherals */ -#define DELAY_SDMMC2_BASE 0x48022800U -#define SDMMC2_BASE 0x48022400U -#define RNG_BASE 0x48021800U -#define HASH_BASE 0x48021400U -#define CRYPTO_BASE 0x48021000U -#define DCMI_BASE 0x48020000U - -/* AHB1 Peripherals */ -#define USB2_OTG_FS_BASE 0x40080000U -#define USB1_OTG_HS_BASE 0x40040000U -#define ETHERNET_MAC_BASE 0x40028000U -#define ADC1_ADC2_BASE 0x40022000U -#define DMAMUX1_BASE 0x40020800U -#define DMA2_BASE 0x40020400U -#define DMA1_BASE 0x40020000U - -/* APB2 Peripherals */ -#define HRTIM_BASE 0x40017400U -#define DFSDM1_BASE 0x40017000U -#define SAI3_BASE 0x40016000U -#define SAI2_BASE 0x40015C00U -#define SAI1_BASE 0x40015800U -#define SPI5_BASE 0x40015000U -#define TIM17_BASE 0x40014800U -#define TIM16_BASE 0x40014400U -#define TIM15_BASE 0x40014000U -#define SPI4_BASE 0x40013400U -#define SPI1_BASE 0x40013000U -#define USART6_BASE 0x40011400U -#define USART1_BASE 0x40011000U -#define TIM8_BASE 0x40010400U -#define TIM1_BASE 0x40010000U - -/* APB1 Peripherals */ -#define CAN_MSG_BASE 0x4000AC00U -#define CAN_CCU_BASE 0x4000A800U -#define FDCAN2_BASE 0x4000A400U -#define FDCAN1_BASE 0x4000A000U -#define MDIOS_BASE 0x40009400U -#define OPAMP_BASE 0x40009000U -#define SWPMI_BASE 0x40008800U -#define CRS_BASE 0x40008400U -#define UART8_BASE 0x40007C00U -#define UART7_BASE 0x40007800U -#define DAC_BASE 0x40007400U -#define HDMI_CEC_BASE 0x40006C00U -#define I2C3_BASE 0x40005C00U -#define I2C2_BASE 0x40005800U -#define I2C1_BASE 0x40005400U -#define UART5_BASE 0x40005000U -#define UART4_BASE 0x40004C00U -#define USART3_BASE 0x40004800U -#define USART2_BASE 0x40004400U -#define SPDIFRX1_BASE 0x40004000U -#define SPI3_BASE 0x40003C00U -#define SPI2_BASE 0x40003800U -#define LPTIM1_BASE 0x40002400U -#define TIM14_BASE 0x40002000U -#define TIM13_BASE 0x40001C00U -#define TIM12_BASE 0x40001800U -#define TIM7_BASE 0x40001400U -#define TIM6_BASE 0x40001000U -#define TIM5_BASE 0x40000C00U -#define TIM4_BASE 0x40000800U -#define TIM3_BASE 0x40000400U -#define TIM2_BASE 0x40000000U - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/pwr.h b/libopencm3/include/libopencm3/stm32/h7/pwr.h deleted file mode 100644 index e0ef4db..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/pwr.h +++ /dev/null @@ -1,134 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32H7xx Power Control - -@ingroup STM32H7xx_defines - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Brian Viele - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -/**@{*/ - -/** @defgroup pwr_registers PWR Registers -@{*/ -/** Power control register. */ -#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) - -/** Power control/status register. */ -#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04) - -/** Power control register 2. */ -#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08) - -/** Power control register 3. */ -#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C) - -/** CPU Power control register 3. */ -#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10) - -/** D3 Domain Power Control register. */ -#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18) - -/** Wakeup Domain Power Control register. */ -#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20) - -/*@}*/ - -/** VOS[15:14]: Regulator voltage scaling output selection */ -#define PWR_CR1_SVOS_SHIFT 14 -#define PWR_CR1_SVOS_SCALE_3 (0x3) -#define PWR_CR1_SVOS_SCALE_4 (0x2) -#define PWR_CR1_SVOS_SCALE_5 (0x1) - -#define PWR_CR1_SVOS_MASK (0x3) - -/** DBP[8]: Disable backup domain write protection. */ -#define PWR_CR1_DBP (1 << 8) - -/** CSR1 Register Bits */ -#define PWR_CSR1_AVDO BIT16 -#define PWR_CSR1_ACTVOS_SHIFT 14 -#define PWR_CSR1_ACTVOSRDY BIT13 -#define PWR_CSR1_PVDO BIT4 - -/** CR3 Register Bits */ -#define PWR_CR3_USB33RDY BIT26 -#define PWR_CR3_USBREGEN BIT25 -#define PWR_CR3_USB33DEN BIT24 -#define PWR_CR3_VBRS BIT9 -#define PWR_CR3_VBE BIT8 -#define PWR_CR3_SCUEN BIT2 -#define PWR_CR3_LDOEN BIT1 -#define PWR_CR3_BYPASS BIT0 - -/** D3CR Register Bits */ -#define PWR_D3CR_VOS_SHIFT 14 -#define PWR_D3CR_VOSRDY BIT13 - -#define PWR_D3CR_VOS_SCALE_3 (0x1) -#define PWR_D3CR_VOS_SCALE_2 (0x2) -#define PWR_D3CR_VOS_SCALE_1 (0x3) -#define PWR_D3CR_VOS_MASK (0x03) - -enum pwr_svos_scale { - PWR_SVOS_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT, - PWR_SVOS_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT, - PWR_SVOS_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT, -}; - -enum pwr_vos_scale { - PWR_VOS_SCALE_0 = 0, /* Note: This state requires SYSCFG ODEN set. */ - PWR_VOS_SCALE_1 = (PWR_D3CR_VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT), - PWR_VOS_SCALE_2 = (PWR_D3CR_VOS_SCALE_2 << PWR_D3CR_VOS_SHIFT), - PWR_VOS_SCALE_3 = (PWR_D3CR_VOS_SCALE_3 << PWR_D3CR_VOS_SHIFT) -}; - -BEGIN_DECLS - -/** @defgroup pwr_peripheral_api PWR Peripheral API - * @ingroup peripheral_apis -@{*/ - -/** Set power subsystem to utilize the LDO for CPU. */ -void pwr_set_mode_ldo(void); - -/** Set the voltage scaling/strength for the internal LDO when in Stop mode. - * @param[in] scale Voltage scale value to set. - */ -void pwr_set_svos_scale(enum pwr_svos_scale scale); - -/** Set the voltage scaling/strength for the internal LDO while running. - * @param[in] scale Voltage scale value to set. - */ -void pwr_set_vos_scale(enum pwr_vos_scale scale); -/**@}*/ - - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/rcc.h b/libopencm3/include/libopencm3/stm32/h7/rcc.h deleted file mode 100644 index 0612b3f..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/rcc.h +++ /dev/null @@ -1,782 +0,0 @@ -/** @defgroup rcc_defines RCC Defines -@brief Defined Constants and Types for the STM32H7xx Reset and Clock -Control -@ingroup STM32H7xx_defines -@version 1.0.0 -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Brian Viele - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include -#include - -/**@{*/ - -/** @defgroup rcc_registers RCC Registers -@{*/ -#define RCC_CR MMIO32(RCC_BASE + 0x000) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x004) /* Y-devices only */ -#define RCC_HSICFGR MMIO32(RCC_BASE + 0x004) /* V-devices only */ -#define RCC_CRRCR MMIO32(RCC_BASE + 0x008) -#define RCC_CSICFGR MMIO32(RCC_BASE + 0x00C) /* V-devices only */ -#define RCC_CFGR MMIO32(RCC_BASE + 0x010) -#define RCC_D1CFGR MMIO32(RCC_BASE + 0x018) -#define RCC_D2CFGR MMIO32(RCC_BASE + 0x01C) -#define RCC_D3CFGR MMIO32(RCC_BASE + 0x020) -#define RCC_PLLCKSELR MMIO32(RCC_BASE + 0x028) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x02C) -/* PLLs are 1-based, so reference macros to 1..3, using index 0 will give undefined behavior. */ -#define RCC_PLLDIVR(n) MMIO32(RCC_BASE + 0x030 + (0x08 * ((n) - 1))) -#define RCC_PLLFRACR(n) MMIO32(RCC_BASE + 0x030 + (0x08 * ((n) - 1))) -#define RCC_PLL1DIVR RCC_PLLDIVR(1) -#define RCC_PLL1FRACR RCC_PLLFRACR(1) -#define RCC_PLL2DIVR RCC_PLLDIVR(2) -#define RCC_PLL2FRACR RCC_PLLFRACR(2) -#define RCC_PLL3DIVR RCC_PLLDIVR(3) -#define RCC_PLL3FRACR RCC_PLLFRACR(3) -#define RCC_D1CCIPR MMIO32(RCC_BASE + 0x04C) -#define RCC_D2CCIP1R MMIO32(RCC_BASE + 0x050) -#define RCC_D2CCIP2R MMIO32(RCC_BASE + 0x054) -#define RCC_D3CCIPR MMIO32(RCC_BASE + 0x058) -#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x080) -#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x084) -#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x07C) -#define RCC_AHB4RSTR MMIO32(RCC_BASE + 0x088) -#define RCC_APB1LRSTR MMIO32(RCC_BASE + 0x090) -#define RCC_APB1HRSTR MMIO32(RCC_BASE + 0x094) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x098) -#define RCC_APB3RSTR MMIO32(RCC_BASE + 0x08C) -#define RCC_APB4RSTR MMIO32(RCC_BASE + 0x09C) -#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x0D8) -#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x0DC) -#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x0D4) -#define RCC_AHB4ENR MMIO32(RCC_BASE + 0x0E0) -#define RCC_APB1LENR MMIO32(RCC_BASE + 0x0E8) -#define RCC_APB1HENR MMIO32(RCC_BASE + 0x0EC) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x0F0) -#define RCC_APB3ENR MMIO32(RCC_BASE + 0x0E4) -#define RCC_APB4ENR MMIO32(RCC_BASE + 0x0F4) -#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x100) -#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x104) -#define RCC_AHB4LPENR MMIO32(RCC_BASE + 0x108) -#define RCC_APB1LLPENR MMIO32(RCC_BASE + 0x110) -#define RCC_APB1HLPENR MMIO32(RCC_BASE + 0x114) -#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x118) -#define RCC_APB3LPENR MMIO32(RCC_BASE + 0x10C) -#define RCC_APB4LPENR MMIO32(RCC_BASE + 0x11C) -#define RCC_BDCR MMIO32(RCC_BASE + 0x70) -#define RCC_CSR MMIO32(RCC_BASE + 0x74) -#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) -#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) -#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88) -#define RCC_DCKCFGR1 MMIO32(RCC_BASE + 0x8C) -#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x90) -/**@}*/ - -/** @defgroup rcc_cr_values RCC_CR Values - * @ingroup rcc_registers -@{*/ -#define RCC_CR_PLL3RDY BIT29 -#define RCC_CR_PLL3ON BIT28 -#define RCC_CR_PLL2RDY BIT27 -#define RCC_CR_PLL2ON BIT26 -#define RCC_CR_PLL1RDY BIT25 -#define RCC_CR_PLL1ON BIT24 -#define RCC_CR_HSECSSON BIT19 -#define RCC_CR_HSEBYP BIT18 -#define RCC_CR_HSERDY BIT17 -#define RCC_CR_HSEON BIT16 -#define RCC_CR_D2CKRDY BIT15 -#define RCC_CR_D1CKRDY BIT14 -#define RCC_CR_HSI48RDY BIT13 -#define RCC_CR_HSI48ON BIT12 -#define RCC_CR_CSIKERON BIT9 -#define RCC_CR_CSIRDY BIT8 -#define RCC_CR_CSION BIT7 -#define RCC_CR_HSIDIVF BIT5 -#define RCC_CR_HSIDIV_MASK (0x03) -#define RCC_CR_HSIDIV_SHIFT 3 -#define RCC_CR_HSIDIV(n) (((n) & RCC_CR_HSIDIV_MASK) << RCC_CR_HSIDIV_MASK) -#define RCC_CR_HSIRDY BIT2 -#define RCC_CR_HSIKERON BIT1 -#define RCC_CR_HSION BIT0 -/**@}*/ - - -/** @defgroup rcc_cfgr_values RCC_CFGR Values - * @ingroup rcc_registers -@{*/ -/* MCO2: Microcontroller clock output 2 */ -#define RCC_CFGR_MCO2_MASK 0x7 -#define RCC_CFGR_MCO2_SHIFT 29 -#define RCC_CFGR_MCO2_SYSCLK 0x0 -#define RCC_CFGR_MCO2_PLL2 0x1 -#define RCC_CFGR_MCO2_HSE 0x2 -#define RCC_CFGR_MCO2_PLL1 0x3 -#define RCC_CFGR_MCO2_CSI 0x4 -#define RCC_CFGR_MCO2_LSI 0x5 - -/* MCO1/2PRE: MCO Prescalers */ -#define RCC_CFGR_MCOPRE_MASK 0xf -#define RCC_CFGR_MCO2PRE_SHIFT 25 -#define RCC_CFGR_MCO1PRE_SHIFT 18 -#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 -#define RCC_CFGR_MCOPRE_DIV_BYP 0x1 -#define RCC_CFGR_MCOPRE_DIV_2 0x2 -#define RCC_CFGR_MCOPRE_DIV_3 0x3 -#define RCC_CFGR_MCOPRE_DIV_4 0x4 -/* Note: MCOPRE_DIV can go from 1 - 15 */ - -/* MCO1: Microcontroller clock output 1 */ -#define RCC_CFGR_MCO1_MASK 0x7 -#define RCC_CFGR_MCO1_SHIFT 22 -#define RCC_CFGR_MCO1_HSI 0x0 -#define RCC_CFGR_MCO1_LSE 0x1 -#define RCC_CFGR_MCO1_HSE 0x2 -#define RCC_CFGR_MCO1_PLL1 0x3 -#define RCC_CFGR_MCO1_HSI48 0x4 -#define RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT -#define RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK - -/* RTCPRE: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_SHIFT 8 -#define RCC_CFGR_RTCPRE_MASK 0x3f - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 3 -#define RCC_CFGR_SWS_MASK 0x7 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_CSI 0x1 -#define RCC_CFGR_SWS_HSE 0x2 -#define RCC_CFGR_SWS_PLL1 0x3 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_MASK 0x7 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_CSI 0x1 -#define RCC_CFGR_SW_HSE 0x2 -#define RCC_CFGR_SW_PLL1 0x3 -/**@}*/ - -/** @defgroup rcc_d1cfgr_values RCC_D1CFGR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D1CFGR_D1CPRE_BYP 0x0 -#define RCC_D1CFGR_D1CPRE_DIV2 0x8 -#define RCC_D1CFGR_D1CPRE_DIV4 0x9 -#define RCC_D1CFGR_D1CPRE_DIV8 0xA -#define RCC_D1CFGR_D1CPRE_DIV16 0xB -#define RCC_D1CFGR_D1CPRE_DIV64 0xC -#define RCC_D1CFGR_D1CPRE_DIV128 0xD -#define RCC_D1CFGR_D1CPRE_DIV256 0xE -#define RCC_D1CFGR_D1CPRE_DIV512 0xF -#define RCC_D1CFGR_D1PPRE_BYP 0x0 -#define RCC_D1CFGR_D1PPRE_DIV2 0x4 -#define RCC_D1CFGR_D1PPRE_DIV4 0x5 -#define RCC_D1CFGR_D1PPRE_DIV8 0x6 -#define RCC_D1CFGR_D1PPRE_DIV16 0x7 -#define RCC_D1CFGR_D1HPRE_BYP 0x0 -#define RCC_D1CFGR_D1HPRE_DIV2 0x8 -#define RCC_D1CFGR_D1HPRE_DIV4 0x9 -#define RCC_D1CFGR_D1HPRE_DIV8 0xA -#define RCC_D1CFGR_D1HPRE_DIV16 0xB -#define RCC_D1CFGR_D1HPRE_DIV64 0xC -#define RCC_D1CFGR_D1HPRE_DIV128 0xD -#define RCC_D1CFGR_D1HPRE_DIV256 0xE -#define RCC_D1CFGR_D1HPRE_DIV512 0xF - -#define RCC_D1CFGR_D1CPRE_SHIFT 8 -#define RCC_D1CFGR_D1PPRE_SHIFT 4 -#define RCC_D1CFGR_D1CPRE(cpre) (cpre << RCC_D1CFGR_D1CPRE_SHIFT) -#define RCC_D1CFGR_D1PPRE(ppre) (ppre << RCC_D1CFGR_D1PPRE_SHIFT) -#define RCC_D1CFGR_D1HPRE(hpre) (hpre) -/**@}*/ - -/** @defgroup rcc_d2cfgr_values RCC_D2CFGR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D2CFGR_D2PPRE_BYP 0x0 -#define RCC_D2CFGR_D2PPRE_DIV2 0x4 -#define RCC_D2CFGR_D2PPRE_DIV4 0x5 -#define RCC_D2CFGR_D2PPRE_DIV8 0x6 -#define RCC_D2CFGR_D2PPRE_DIV16 0x7 - -#define RCC_D2CFGR_D2PPRE2_SHIFT 8 -#define RCC_D2CFGR_D2PPRE1_SHIFT 4 -#define RCC_D2CFGR_D2PPRE2(ppre) (ppre << RCC_D2CFGR_D2PPRE2_SHIFT) -#define RCC_D2CFGR_D2PPRE1(ppre) (ppre << RCC_D2CFGR_D2PPRE1_SHIFT) -/**@}*/ - -/** @defgroup rcc_d3cfgr_values RCC_D3CFGR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D3CFGR_D3PPRE_BYP 0x0 -#define RCC_D3CFGR_D3PPRE_DIV2 0x4 -#define RCC_D3CFGR_D3PPRE_DIV4 0x5 -#define RCC_D3CFGR_D3PPRE_DIV8 0x6 -#define RCC_D3CFGR_D3PPRE_DIV16 0x7 -#define RCC_D3CFGR_D3PPRE_SHIFT 4 -#define RCC_D3CFGR_D3PPRE(ppre) (ppre << RCC_D3CFGR_D3PPRE_SHIFT) -/**@}*/ - -/** @defgroup rcc_pllckselr_values RCC_PLLCKSELR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_PLLCKSELR_PLLSRC_HSI 0x0 -#define RCC_PLLCKSELR_PLLSRC_CSI 0x1 -#define RCC_PLLCKSELR_PLLSRC_HSE 0x2 -#define RCC_PLLCKSELR_PLLSRC_NONE 0x3 -#define RCC_PLLCKSELR_DIVM_DIS 0 -#define RCC_PLLCKSELR_DIVM_BYP 1 -#define RCC_PLLCKSELR_DIVM_MASK 0x3f - -#define RCC_PLLCKSELR_DIVM3_SHIFT 20 -#define RCC_PLLCKSELR_DIVM2_SHIFT 12 -#define RCC_PLLCKSELR_DIVM1_SHIFT 4 - -#define RCC_PLLCKSELR_DIVM3(n) ((n) << RCC_PLLCKSELR_DIVM3_SHIFT) -#define RCC_PLLCKSELR_DIVM2(n) ((n) << RCC_PLLCKSELR_DIVM2_SHIFT) -#define RCC_PLLCKSELR_DIVM1(n) ((n) << RCC_PLLCKSELR_DIVM1_SHIFT) -/**@}*/ - -/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_PLLCFGR_PLLRGE_1_2MHZ 0 -#define RCC_PLLCFGR_PLLRGE_2_4MHZ 1 -#define RCC_PLLCFGR_PLLRGE_4_8MHZ 2 -#define RCC_PLLCFGR_PLLRGE_8_16MHZ 3 - -#define RCC_PLLCFGR_DIVR3EN BIT24 -#define RCC_PLLCFGR_DIVQ3EN BIT23 -#define RCC_PLLCFGR_DIVP3EN BIT22 -#define RCC_PLLCFGR_DIVR2EN BIT21 -#define RCC_PLLCFGR_DIVQ2EN BIT20 -#define RCC_PLLCFGR_DIVP2EN BIT19 -#define RCC_PLLCFGR_DIVR1EN BIT18 -#define RCC_PLLCFGR_DIVQ1EN BIT17 -#define RCC_PLLCFGR_DIVP1EN BIT16 -#define RCC_PLLCFGR_PLL3RGE_SHIFT 10 -#define RCC_PLLCFGR_PLL3VCO_WIDE 0 /* 192 - 836MHz base output. */ -#define RCC_PLLCFGR_PLL3VCO_MED BIT9 /* 150 - 420MHz base output. */ -#define RCC_PLLCFGR_PLL3FRACEN BIT8 -#define RCC_PLLCFGR_PLL2RGE_SHIFT 6 -#define RCC_PLLCFGR_PLL2VCO_WIDE 0 /* 192 - 836MHz base output. */ -#define RCC_PLLCFGR_PLL2VCO_MED BIT5 /* 150 - 420MHz base output. */ -#define RCC_PLLCFGR_PLL2FRACEN BIT4 -#define RCC_PLLCFGR_PLL1RGE_SHIFT 2 -#define RCC_PLLCFGR_PLL1VCO_WIDE 0 /* 192 - 836MHz base output. */ -#define RCC_PLLCFGR_PLL1VCO_MED BIT1 /* 150 - 420MHz base output. */ -#define RCC_PLLCFGR_PLL1FRACEN BIT0 -/**@}*/ - -/** @defgroup rcc_plldivr_values RCC_PLLnDIVR Values - * @ingroup rcc_registers - * @{*/ -#define RCC_PLLNDIVR_DIVR_SHIFT 24 -#define RCC_PLLNDIVR_DIVQ_SHIFT 16 -#define RCC_PLLNDIVR_DIVP_SHIFT 9 -#define RCC_PLLNDIVR_DIVN_SHIFT 0 - -/* Need to preserve reserved bits, so give easy mask shortcut. */ -#define RCC_PLLNDIVR_DIVR(n) (((n) - 1) << RCC_PLLNDIVR_DIVR_SHIFT) -#define RCC_PLLNDIVR_DIVQ(n) (((n) - 1) << RCC_PLLNDIVR_DIVQ_SHIFT) -#define RCC_PLLNDIVR_DIVP(n) (((n) - 1) << RCC_PLLNDIVR_DIVP_SHIFT) -#define RCC_PLLNDIVR_DIVN(n) (((n) - 1) << RCC_PLLNDIVR_DIVN_SHIFT) -/**@}*/ - -/** @defgroup rcc_bdcr_values RCC_BDCR Values - * @ingroup rcc_registers -@{*/ -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -#define RCC_BDCR_RTCSEL_MASK 0x3 -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSE 3 -#define RCC_BDCR_LSEDRV_MASK 0x3 -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV_LOW 0 -#define RCC_BDCR_LSEDRV_MEDH 1 /* good job st */ -#define RCC_BDCR_LSEDRV_MEDL 2 -#define RCC_BDCR_LSEDRV_HIGH 3 -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) -/**@}*/ - -/** @defgroup rcc_csr_values RCC_CSR Values. - * @ingroup rcc_registers -@{*/ -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) -/**@}*/ - -/** @defgroup rcc_d1ccipr_values RCC_D1CCIP1R Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D1CCIPR_CKPERSEL_HSI 0 -#define RCC_D1CCIPR_CKPERSEL_CSI 1 -#define RCC_D1CCIPR_CKPERSEL_HSE 2 -#define RCC_D1CCIPR_CKPERSEL_DISABLE 3 -/**@}*/ -#define RCC_D1CCIPR_CKPERSEL_SHIFT 28 -#define RCC_D1CCIPR_CKPERSEL_MASK 3 - -#define RCC_D2CCIP1R_SWPSEL_SHIFT 31 -#define RCC_D2CCIP1R_FDCANSEL_SHIFT 28 -#define RCC_D2CCIP1R_FDCANSEL_MASK 0x3 -#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT 24 -#define RCC_D2CCIP1R_SPDIFSEL_SHIFT 20 -#define RCC_D2CCIP1R_SPI45SEL_SHIFT 16 -#define RCC_D2CCIP1R_SPI45SEL_MASK 0x7 -#define RCC_D2CCIP1R_SPI123SEL_SHIFT 12 -#define RCC_D2CCIP1R_SPI123SEL_MASK 0x7 -#define RCC_D2CCIP1R_SAI23SEL_SHIFT 6 -#define RCC_D2CCIP1R_SAISEL_MASK 0x7 - -/** @defgroup rcc_d2ccip1r_values RCC_D2CCIP1R Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D2CCIP1R_SWPSEL_PCLK 0x0 -#define RCC_D2CCIP1R_SWPSEL_HSI 0x1 -#define RCC_D2CCIP1R_FDCANSEL_HSE 0x0 -#define RCC_D2CCIP1R_FDCANSEL_PLL1Q 0x1 -#define RCC_D2CCIP1R_FDCANSEL_PLL2Q 0x2 -#define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 0x0 -#define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK 0x1 -#define RCC_D2CCIP1R_SPDIFSEL_PLL1Q 0x0 -#define RCC_D2CCIP1R_SPDIFSEL_PLL2R 0x1 -#define RCC_D2CCIP1R_SPDIFSEL_PLL3R 0x2 -#define RCC_D2CCIP1R_SPDIFSEL_HSI 0x3 -#define RCC_D2CCIP1R_SPI45SEL_APB4 0x0 -#define RCC_D2CCIP1R_SPI45SEL_PLL2Q 0x1 -#define RCC_D2CCIP1R_SPI45SEL_PLL3Q 0x2 -#define RCC_D2CCIP1R_SPI45SEL_HSI 0x3 -#define RCC_D2CCIP1R_SPI45SEL_CSI 0x4 -#define RCC_D2CCIP1R_SPI45SEL_HSE 0x5 -#define RCC_D2CCIP1R_SPI123SEL_PLL1Q 0x0 -#define RCC_D2CCIP1R_SPI123SEL_PLL2P 0x1 -#define RCC_D2CCIP1R_SPI123SEL_PLL3P 0x2 -#define RCC_D2CCIP1R_SPI123SEL_I2SCKIN 0x3 -#define RCC_D2CCIP1R_SPI123SEL_PERCK 0x4 -#define RCC_D2CCIP1R_SAISEL_PLL1Q 0x0 -#define RCC_D2CCIP1R_SAISEL_PLL2P 0x1 -#define RCC_D2CCIP1R_SAISEL_PLL3P 0x2 -#define RCC_D2CCIP1R_SAISEL_I2SCKIN 0x3 -#define RCC_D2CCIP1R_SAISEL_PERCK 0x4 -/**@}*/ - -#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT 28 -#define RCC_D2CCIP2R_CECSEL_SHIFT 22 -#define RCC_D2CCIP2R_USBSEL_SHIFT 20 -#define RCC_D2CCIP2R_I2C123SEL_SHIFT 12 -#define RCC_D2CCIP2R_RNGSEL_SHIFT 8 -#define RCC_D2CCIP2R_USART16SEL_SHIFT 3 -#define RCC_D2CCIP2R_USART234578SEL_SHIFT 0 -#define RCC_D2CCIP2R_USARTSEL_MASK 7 - -/** @defgroup rcc_d2ccip2r_values RCC_D2CCIP2R Values - * @ingroup rcc_registers - * @{*/ -#define RCC_D2CCIP2R_USART16SEL_PCLK2 0 -#define RCC_D2CCIP2R_USART234578SEL_PCLK1 0 -#define RCC_D2CCIP2R_USARTSEL_PLL2Q 1 -#define RCC_D2CCIP2R_USARTSEL_PLL3Q 2 -#define RCC_D2CCIP2R_USARTSEL_HSI 3 -#define RCC_D2CCIP2R_USARTSEL_CSI 4 -#define RCC_D2CCIP2R_USARTSEL_LSE 5 -/**@}*/ - - -#define RCC_HSI_BASE_FREQUENCY 64000000UL - -/** Enumerations for core system/bus clocks for user/driver/system access to base bus clocks - * not directly associated with a peripheral. */ -enum rcc_clock_source { - RCC_CPUCLK, - RCC_SYSCLK, - RCC_PERCLK, - RCC_SYSTICKCLK, - RCC_HCLK3, - RCC_AHBCLK, /* AHB1,2,4 all share base HCLK. */ - RCC_APB1CLK, /* Note: APB1 and PCLK1 in manual */ - RCC_APB2CLK, /* Note: APB2 and PCLK2 in manual */ - RCC_APB3CLK, /* Note: APB3 and PCLK3 in manual */ - RCC_APB4CLK, /* Note: APB4 and PCLK4 in manual */ -}; - -enum rcc_osc { - RCC_PLL, - RCC_HSE, - RCC_HSI, - RCC_LSE, - RCC_LSI -}; - -/** PLL Configuration structure. */ -struct rcc_pll_config { - enum rcc_osc sysclock_source; /**< SYSCLK source input selection. */ - uint8_t pll_source; /**< RCC_PLLCKSELR_PLLSRC_xxx value. */ - uint32_t hse_frequency; /**< User specified HSE frequency, 0 if none. */ - struct pll_config { - uint8_t divm; /**< Pre-divider value for each PLL. 0-64 integers. */ - uint16_t divn; /**< Multiplier, 0-512 integer. */ - uint8_t divp; /**< Post divider for PLLP clock. */ - uint8_t divq; /**< Post divider for PLLQ clock. */ - uint8_t divr; /**< Post divider for PLLR clock. */ - } pll1, pll2, pll3; /**< PLL1-PLL3 configurations. */ - uint8_t core_pre; /**< Core prescaler note: domain 1. */ - uint8_t hpre; /**< HCLK3 prescaler note: domain 1. */ - uint8_t ppre1; /**< APB1 Peripheral prescaler note: domain 2. */ - uint8_t ppre2; /**< APB2 Peripheral prescaler note: domain 2. */ - uint8_t ppre3; /**< APB3 Peripheral prescaler note: domain 1. */ - uint8_t ppre4; /**< APB4 Peripheral prescaler note: domain 3. */ - uint8_t flash_waitstates; /**< Latency Value to set for flahs. */ - enum pwr_vos_scale voltage_scale; /**< LDO Voltage scale used for this frequency. */ -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB1 peripherals */ - RCC_DMA1 = _REG_BIT(0xD8, 0), - RCC_DMA2 = _REG_BIT(0xD8, 1), - RCC_ADC12 = _REG_BIT(0xD8, 5), - RCC_ETH1MAC = _REG_BIT(0xD8, 15), - RCC_ETH1TX = _REG_BIT(0xD8, 16), - RCC_ETH1RX = _REG_BIT(0xD8, 17), - RCC_USB2OTGHSULPIEN = _REG_BIT(0xD8, 18), - RCC_USB1OTGHSEN = _REG_BIT(0xD8, 25), - RCC_USB1OTGHSULPIEN = _REG_BIT(0xD8, 26), - RCC_USB2OTGHSEN = _REG_BIT(0xD8, 27), - - /* AHB2 peripherals */ - RCC_DCMI = _REG_BIT(0xDC, 0), - RCC_CRYP = _REG_BIT(0xDC, 4), - RCC_HASH = _REG_BIT(0xDC, 5), - RCC_RNG = _REG_BIT(0xDC, 6), - RCC_SDMMC2 = _REG_BIT(0xDC, 9), - RCC_SRAM1 = _REG_BIT(0xDC, 29), - RCC_SRAM2 = _REG_BIT(0xDC, 30), - RCC_SRAM3 = _REG_BIT(0xDC, 31), - - /* AHB3 peripherals */ - RCC_MDMA = _REG_BIT(0xD4, 0), - RCC_DMA2D = _REG_BIT(0xD4, 4), - RCC_JPGDEC = _REG_BIT(0xD4, 5), - RCC_FMC = _REG_BIT(0xD4, 12), - RCC_QSPI = _REG_BIT(0xD4, 14), - RCC_SDMMC1 = _REG_BIT(0xD4, 16), - - /* AHB4 peripherals*/ - RCC_GPIOA = _REG_BIT(0xE0, 0), - RCC_GPIOB = _REG_BIT(0xE0, 1), - RCC_GPIOC = _REG_BIT(0xE0, 2), - RCC_GPIOD = _REG_BIT(0xE0, 3), - RCC_GPIOE = _REG_BIT(0xE0, 4), - RCC_GPIOF = _REG_BIT(0xE0, 5), - RCC_GPIOG = _REG_BIT(0xE0, 6), - RCC_GPIOH = _REG_BIT(0xE0, 7), - RCC_GPIOI = _REG_BIT(0xE0, 8), - RCC_GPIOJ = _REG_BIT(0xE0, 9), - RCC_GPIOK = _REG_BIT(0xE0, 10), - RCC_CRC = _REG_BIT(0xE0, 19), - RCC_BDMA = _REG_BIT(0xE0, 21), - RCC_ADC3 = _REG_BIT(0xE0, 24), - RCC_HSEM = _REG_BIT(0xE0, 25), - RCC_BKPSRAM = _REG_BIT(0xE0, 28), - - /* APB1L peripherals*/ - RCC_TIM2 = _REG_BIT(0xE8, 0), - RCC_TIM3 = _REG_BIT(0xE8, 1), - RCC_TIM4 = _REG_BIT(0xE8, 2), - RCC_TIM5 = _REG_BIT(0xE8, 3), - RCC_TIM6 = _REG_BIT(0xE8, 4), - RCC_TIM7 = _REG_BIT(0xE8, 5), - RCC_TIM12 = _REG_BIT(0xE8, 6), - RCC_TIM13 = _REG_BIT(0xE8, 7), - RCC_TIM14 = _REG_BIT(0xE8, 8), - RCC_LPTIM1 = _REG_BIT(0xE8, 9), - RCC_SPI2 = _REG_BIT(0xE8, 14), - RCC_SPI3 = _REG_BIT(0xE8, 15), - RCC_SPDIFRX = _REG_BIT(0xE8, 16), - RCC_USART2 = _REG_BIT(0xE8, 17), - RCC_USART3 = _REG_BIT(0xE8, 18), - RCC_UART4 = _REG_BIT(0xE8, 19), - RCC_UART5 = _REG_BIT(0xE8, 20), - RCC_I2C1 = _REG_BIT(0xE8, 21), - RCC_I2C2 = _REG_BIT(0xE8, 22), - RCC_I2C3 = _REG_BIT(0xE8, 23), - RCC_CEC = _REG_BIT(0xE8, 27), - RCC_DAC = _REG_BIT(0xE8, 29), - RCC_UART7 = _REG_BIT(0xE8, 30), - RCC_UART8 = _REG_BIT(0xE8, 31), - - /* APB1H peripherals*/ - RCC_CRS = _REG_BIT(0xEC, 1), - RCC_SWP = _REG_BIT(0xEC, 2), - RCC_OPAMP = _REG_BIT(0xEC, 4), - RCC_MDIO = _REG_BIT(0xEC, 5), - RCC_FDCAN = _REG_BIT(0xEC, 8), - - /* APB2 peripherals */ - RCC_TIM1 = _REG_BIT(0xF0, 0), - RCC_TIM8 = _REG_BIT(0xF0, 1), - RCC_USART1 = _REG_BIT(0xF0, 4), - RCC_USART6 = _REG_BIT(0xF0, 5), - RCC_SPI1 = _REG_BIT(0xF0, 12), - RCC_SPI4 = _REG_BIT(0xF0, 13), - RCC_TIM15 = _REG_BIT(0xF0, 16), - RCC_TIM16 = _REG_BIT(0xF0, 17), - RCC_TIM17 = _REG_BIT(0xF0, 18), - RCC_SPI5 = _REG_BIT(0xF0, 20), - RCC_SAI1 = _REG_BIT(0xF0, 22), - RCC_SAI2 = _REG_BIT(0xF0, 23), - RCC_SAI3 = _REG_BIT(0xF0, 24), - RCC_DFSDM = _REG_BIT(0xF0, 28), - RCC_HRTIM = _REG_BIT(0xF0, 29), - - /* APB3 peripherals */ - RCC_LTDCEN = _REG_BIT(0xE4, 3), - RCC_WWDG1EN = _REG_BIT(0xE4, 6), - - /* APB4 peripherals */ - RCC_SYSCFG = _REG_BIT(0xF4, 1), - RCC_LPUART1 = _REG_BIT(0xF4, 3), - RCC_SPI6 = _REG_BIT(0xF4, 5), - RCC_I2C4 = _REG_BIT(0xF4, 7), - RCC_LPTIM2 = _REG_BIT(0xF4, 9), - RCC_LPTIM3 = _REG_BIT(0xF4, 10), - RCC_LPTIM4 = _REG_BIT(0xF4, 11), - RCC_LPTIM5 = _REG_BIT(0xF4, 12), - RCC_COMP12 = _REG_BIT(0xF4, 14), - RCC_VREF = _REG_BIT(0xF4, 15), - RCC_RTCAPB = _REG_BIT(0xF4, 16), - RCC_SAI4 = _REG_BIT(0xF4, 21), -}; - -enum rcc_periph_rst { - /* AHB1 peripherals */ - RST_DMA1 = _REG_BIT(0x80, 0), - RST_DMA2 = _REG_BIT(0x80, 1), - RST_ADC12 = _REG_BIT(0x80, 5), - RST_ETH1MAC = _REG_BIT(0x80, 15), - RST_USB1OTGRST = _REG_BIT(0x80, 25), - RST_USB2OTGRST = _REG_BIT(0x80, 27), - - /* AHB2 peripherals */ - RST_DCMI = _REG_BIT(0xDC, 0), - RST_CRYP = _REG_BIT(0xDC, 4), - RST_HASH = _REG_BIT(0xDC, 5), - RST_RNG = _REG_BIT(0xDC, 6), - RST_SDMMC2 = _REG_BIT(0xDC, 9), - - /* AHB3 peripherals */ - RST_MDMA = _REG_BIT(0x7C, 0), - RST_DMA2D = _REG_BIT(0x7C, 4), - RST_JPGDEC = _REG_BIT(0x7C, 5), - RST_FMC = _REG_BIT(0x7C, 12), - RST_QSPI = _REG_BIT(0x7C, 14), - RST_SDMMC1 = _REG_BIT(0x7C, 16), - - /* AHB4 peripherals*/ - RST_GPIOA = _REG_BIT(0x88, 0), - RST_GPIOB = _REG_BIT(0x88, 1), - RST_GPIOC = _REG_BIT(0x88, 2), - RST_GPIOD = _REG_BIT(0x88, 3), - RST_GPIOE = _REG_BIT(0x88, 4), - RST_GPIOF = _REG_BIT(0x88, 5), - RST_GPIOG = _REG_BIT(0x88, 6), - RST_GPIOH = _REG_BIT(0x88, 7), - RST_GPIOI = _REG_BIT(0x88, 8), - RST_GPIOJ = _REG_BIT(0x88, 9), - RST_GPIOK = _REG_BIT(0x88, 10), - RST_CRC = _REG_BIT(0x88, 19), - RST_BDMA = _REG_BIT(0x88, 21), - RST_ADC3 = _REG_BIT(0x88, 24), - RST_HSEM = _REG_BIT(0x88, 25), - - /* APB1L peripherals*/ - RST_TIM2 = _REG_BIT(0x90, 0), - RST_TIM3 = _REG_BIT(0x90, 1), - RST_TIM4 = _REG_BIT(0x90, 2), - RST_TIM5 = _REG_BIT(0x90, 3), - RST_TIM6 = _REG_BIT(0x90, 4), - RST_TIM7 = _REG_BIT(0x90, 5), - RST_TIM12 = _REG_BIT(0x90, 6), - RST_TIM13 = _REG_BIT(0x90, 7), - RST_TIM14 = _REG_BIT(0x90, 8), - RST_LPTIM1 = _REG_BIT(0x90, 9), - RST_SPI2 = _REG_BIT(0x90, 14), - RST_SPI3 = _REG_BIT(0x90, 15), - RST_SPDIFRX = _REG_BIT(0x90, 16), - RST_USART2 = _REG_BIT(0x90, 17), - RST_USART3 = _REG_BIT(0x90, 18), - RST_UART4 = _REG_BIT(0x90, 19), - RST_UART5 = _REG_BIT(0x90, 20), - RST_I2C1 = _REG_BIT(0x90, 21), - RST_I2C2 = _REG_BIT(0x90, 22), - RST_I2C3 = _REG_BIT(0x90, 23), - RST_CEC = _REG_BIT(0x90, 27), - RST_DAC = _REG_BIT(0x90, 29), - RST_UART7 = _REG_BIT(0x90, 30), - RST_UART8 = _REG_BIT(0x90, 31), - - /* APB1H peripherals*/ - RST_CRS = _REG_BIT(0x94, 1), - RST_SWP = _REG_BIT(0x94, 2), - RST_OPAMP = _REG_BIT(0x94, 4), - RST_MDIO = _REG_BIT(0x94, 5), - RST_FDCAN = _REG_BIT(0x94, 8), - - /* APB2 peripherals */ - RST_TIM1 = _REG_BIT(0x98, 0), - RST_TIM8 = _REG_BIT(0x98, 1), - RST_USART1 = _REG_BIT(0x98, 4), - RST_USART6 = _REG_BIT(0x98, 5), - RST_SPI1 = _REG_BIT(0x98, 12), - RST_SPI4 = _REG_BIT(0x98, 13), - RST_TIM15 = _REG_BIT(0x98, 16), - RST_TIM16 = _REG_BIT(0x98, 17), - RST_TIM17 = _REG_BIT(0x98, 18), - RST_SPI5 = _REG_BIT(0x98, 20), - RST_SAI1 = _REG_BIT(0x98, 22), - RST_SAI2 = _REG_BIT(0x98, 23), - RST_SAI3 = _REG_BIT(0x98, 24), - RST_DFSDM = _REG_BIT(0x98, 28), - RST_HRTIM = _REG_BIT(0x98, 29), - - /* APB3 peripherals */ - RST_LTDCRST = _REG_BIT(0x8C, 3), - - /* APB4 peripherals */ - RST_SYSCFG = _REG_BIT(0x9C, 1), - RST_LPUART1 = _REG_BIT(0x9C, 3), - RST_SPI6 = _REG_BIT(0x9C, 5), - RST_I2C4 = _REG_BIT(0x9C, 7), - RST_LPTIM2 = _REG_BIT(0x9C, 9), - RST_LPTIM3 = _REG_BIT(0x9C, 10), - RST_LPTIM4 = _REG_BIT(0x9C, 11), - RST_LPTIM5 = _REG_BIT(0x9C, 12), - RST_COMP12 = _REG_BIT(0x9C, 14), - RST_VREF = _REG_BIT(0x9C, 15), - RST_SAI4 = _REG_BIT(0x9C, 21), -}; - -#undef _REG_BIT -/**@}*/ - - -/** @defgroup rcc_file RCC peripheral API - * - * @ingroup peripheral_apis - * @{ - */ -#include - -BEGIN_DECLS - -/** - * Setup the base PLLs and clock domains for the STM32H7. This function will - * utilize the users input parameters to configure all 3 PLLs, as well as the - * core clock domains (namely SYSCLK, CPU, HCLK, AHB, PCLK1-4) with the - * specified dividers. Given the dividers, the RCC module will track the - * the configured frequency for each of these clock domains. - * - * Note: If clock sources, configs, divider, etc. are modified outside of - * this module, the frequency tracking may be undefined. - * Note: Clock tree is fairly complex, see RM0433 Section 7 - * for details. - * @param[in] config Input config structure defining desired setup. - */ -void rcc_clock_setup_pll(const struct rcc_pll_config *config); - -/** - * Get the clock rate (in Hz) of the specified clock source. There are - * numerous clock sources and configurations on the H7, so rates for each - * configured peripheral clock are aimed to be discoverd/calculated by this - * module such that the user does not need to know how the MCU is configured - * in order to utilize a peripheral clock. - * @param[in] source Clock source desired to be fetched. - * @return Clock rate in Hz for the specified clock. 0 if undefined or error. - */ -uint32_t rcc_get_bus_clk_freq(enum rcc_clock_source source); - -/** - * Get the clock rate (in Hz) of the specified peripheral. This will pull the - * proper sources out of the clock tree and calculate the clock for the - * peripheral for return to the user, based on current settings. - * @param[in] periph Peripheral base address to get the clock rate for. - * @return Clock rate in Hz for the specified peripheral. 0 if undefined or error. - */ -uint32_t rcc_get_peripheral_clk_freq(uint32_t periph); - -/** - * Set the clksel value for the specified peripheral. This code will determine - * the appropriate register, shift and mask values to apply to the selection to - * and set the values appropriately. - * - * Peripheral specific clksels functions are also available, - * eg rcc_set__clksel. These provide the same functionality, you only - * need one of them. for instance @ref rcc_set_fdcan_clksel or - * @ref rcc_set_spi123_clksel - * @param[in] periph Base address of the peripheral to set the clock sel for - * @param[in] clksel Raw, unshifted selection value for the clock, depending - * on peripheral, see @ref rcc_d1ccipr_values or @ref rcc_d2ccip1r_values or - * @ref rcc_d2ccip2r_values - */ -void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t clksel); - -/** - * Set the clock select for the FDCAN devices. - * @param[in] clksel Clock source to configure for, @ref rcc_d2ccip1r_values - * appropriate for the FDCAN peripherals, eg RCC_D2CCIP1R_FDCANSEL_XXX - * @sa rcc_set_peripheral_clk_sel for equivalent generic functionality - */ -void rcc_set_fdcan_clksel(uint8_t clksel); - -/** - * Set the clock select for the SPI 1/2/3 devices. - * @param[in] clksel Clock source to configure for, @ref rcc_d2ccip1r_values - * appropriate for the SPI1/2/3 peripherals, eg RCC_D2CCIP1R_SPI123_XXX - * @sa rcc_set_peripheral_clk_sel for equivalent generic functionality - */ -void rcc_set_spi123_clksel(uint8_t clksel); - -/** - * Set the clock select for the SPI 4/5 devices. - * @param[in] clksel Clock source to configure for. @ref rcc_d2ccip1r_values - * @sa rcc_set_peripheral_clk_sel for equivalent generic functionality - */ -void rcc_set_spi45_clksel(uint8_t clksel); - - -END_DECLS -/**@}*/ -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/spi.h b/libopencm3/include/libopencm3/stm32/h7/spi.h deleted file mode 100644 index 7cabf40..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/spi.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @defgroup spi_defines SPI Defines -@brief Defined Constants and Types for the STM32H7xx SPI -@ingroup STM32H7xx_defines -@version 1.0.0 -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/h7/syscfg.h b/libopencm3/include/libopencm3/stm32/h7/syscfg.h deleted file mode 100644 index 110df1f..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/syscfg.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32H7xx_defines - * - * @brief Defined Constants and Types for the STM32H7xx System Configuration controller - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2019 - * Brian Viele - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -/**@{*/ -/**@defgroup syscfg_registers SYSCFG Registers - @{*/ -#define SYSCFG_PMCR MMIO32(SYSCFG_BASE + 0x04) -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) -#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08) -#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0C) -#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10) -#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14) -#define SYSCFG_CFGR MMIO32(SYSCFG_BASE + 0x18) -#define SYSCFG_CCSR MMIO32(SYSCFG_BASE + 0x20) -#define SYSCFG_CCVR MMIO32(SYSCFG_BASE + 0x24) -#define SYSCFG_CCCR MMIO32(SYSCFG_BASE + 0x28) -#define SYSCFG_PWRCR MMIO32(SYSCFG_BASE + 0x2C) -#define SYSCFG_PKGR MMIO32(SYSCFG_BASE + 0x124) -#define SYSCFG_UR(n) MMIO32(SYSCFG_BASE + 0x300 + (4 * (n))) - -#define SYSCFG_EXTICR_FIELDSIZE 4 -/**@}*/ - - - -/** @defgroup syscfg_pwrcr PWRCR SYSCFG configuration register - * @ingroup syscfg_registers - * @{*/ -#define SYSCFG_PWRCR_ODEN BIT0 -/**@}*/ - - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/timer.h b/libopencm3/include/libopencm3/stm32/h7/timer.h deleted file mode 100644 index 62a636a..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/timer.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @defgroup timer_defines SPI Defines -@brief Defined Constants and Types for the STM32H7xx Timers -@ingroup STM32H7xx_defines -@version 1.0.0 -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/h7/usart.h b/libopencm3/include/libopencm3/stm32/h7/usart.h deleted file mode 100644 index f47a273..0000000 --- a/libopencm3/include/libopencm3/stm32/h7/usart.h +++ /dev/null @@ -1,58 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32H7xx USART - * - * @ingroup STM32H7xx_defines - * - * @version 1.0.0 - * - * @date 6 November 2019 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include - -/**@{*/ -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -#define USART6 USART6_BASE -#define UART7 UART7_BASE -#define UART8 UART8_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/hash.h b/libopencm3/include/libopencm3/stm32/hash.h deleted file mode 100644 index 8f7d19c..0000000 --- a/libopencm3/include/libopencm3/stm32/hash.h +++ /dev/null @@ -1,30 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#else -# error "hash processor is supported only" \ - "in stm32f21, stm32f41 and stm32f43 families." -#endif diff --git a/libopencm3/include/libopencm3/stm32/hrtim.h b/libopencm3/include/libopencm3/stm32/hrtim.h deleted file mode 100644 index 3eb8653..0000000 --- a/libopencm3/include/libopencm3/stm32/hrtim.h +++ /dev/null @@ -1,27 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F3) -# include -#else -# error "HRTIM only defined for STM32F3" -#endif diff --git a/libopencm3/include/libopencm3/stm32/i2c.h b/libopencm3/include/libopencm3/stm32/i2c.h deleted file mode 100644 index 880ca49..0000000 --- a/libopencm3/include/libopencm3/stm32/i2c.h +++ /dev/null @@ -1,46 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/iwdg.h b/libopencm3/include/libopencm3/stm32/iwdg.h deleted file mode 100644 index b94b874..0000000 --- a/libopencm3/include/libopencm3/stm32/iwdg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l0/adc.h b/libopencm3/include/libopencm3/stm32/l0/adc.h deleted file mode 100644 index 7fd99f3..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/adc.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the STM32L0xx Analog to Digital - * Converter - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * @date 16 Oct 2015 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/** @defgroup adc_reg_base ADC register base addresses - * @ingroup adc_defines - * - *@{*/ -#define ADC1 ADC1_BASE -/**@}*/ - - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_VLCD 16 -#define ADC_CHANNEL_VREF 17 -#define ADC_CHANNEL_TEMP 18 -/**@}*/ - -/* Calibration Factors */ -#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4) - -/* Register values */ -/* ADC_CFGR2 Values ---------------------------------------------------------*/ - -#define ADC_CFGR2_CKMODE_SHIFT 30 -#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT) -#define ADC_CFGR2_CKMODE_PCLK (3 << ADC_CFGR2_CKMODE_SHIFT) - -/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_1DOT5CYC 0x0 -#define ADC_SMPR_SMP_3DOT5CYC 0x1 -#define ADC_SMPR_SMP_7DOT5CYC 0x2 -#define ADC_SMPR_SMP_12DOT5CYC 0x3 -#define ADC_SMPR_SMP_19DOT5CYC 0x4 -#define ADC_SMPR_SMP_39DOT5CYC 0x5 -#define ADC_SMPR_SMP_79DOT5CYC 0x6 -#define ADC_SMPR_SMP_160DOT5CYC 0x7 -/**@}*/ - -BEGIN_DECLS - - -END_DECLS - - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/crc.h b/libopencm3/include/libopencm3/stm32/l0/crc.h deleted file mode 100644 index a1c7ee0..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/crc.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief Defined Constants and Types for the STM32L0xx CRC Generator - * - * @ingroup STM32L0xx_defines - * - * @date 11 October 2019 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/dma.h b/libopencm3/include/libopencm3/stm32/l0/dma.h deleted file mode 100644 index 344f4d4..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/dma.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32L0xx_defines - * - * @brief Defined Constants and Types for the STM32L0xx DMA Controller - * - * @version 1.0.0 - * - * @date 29 April 2018 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l0/doc-stm32l0.h b/libopencm3/include/libopencm3/stm32/l0/doc-stm32l0.h deleted file mode 100644 index 0813bcd..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/doc-stm32l0.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32L0 - -@version 1.0.0 - -@date 15 November 2014 - -API documentation for ST Microelectronics STM32L0 Cortex M0 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32L0xx STM32L0xx -Libraries for ST Microelectronics STM32L0xx series. - -@version 1.0.0 - -@date 15 November 2014 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32L0xx_defines STM32L0xx Defines - -@brief Defined Constants and Types for the STM32L0xx series - -@version 1.0.0 - -@date 7 September 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/l0/exti.h b/libopencm3/include/libopencm3/stm32/l0/exti.h deleted file mode 100644 index c1d9015..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/exti.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32L0xx External Interrupts - * - * - * @ingroup STM32L0xx_defines - * - * @author @htmlonly © @endhtmlonly 2015 - * Robin Kreis - * - * @version 1.0.0 - * - * @date 15 July 2015 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Robin Kreis - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/flash.h b/libopencm3/include/libopencm3/stm32/l0/flash.h deleted file mode 100644 index ef1d188..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/flash.h +++ /dev/null @@ -1,63 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @brief Defined Constants and Types for the STM32L0xx Flash memory - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H -/**@{*/ - -#include -#include - -/* --- FLASH registers ----------------------------------------------------- */ -/* L0 has some alternative names for the same registers */ -#define FLASH_OPTR FLASH_OBR -#define FLASH_WRPROT1 FLASH_WRPR1 -#define FLASH_WRPROT2 FLASH_WRPR2 - -/* --- FLASH_ACR values ---------------------------------------------------- */ -#define FLASH_ACR_PRE_READ (1 << 6) -#define FLASH_ACR_DISAB_BUF (1 << 5) - -/* --- FLASH_PECR values ---------------------------------------------------- */ -#define FLASH_PECR_NZDISABLE (1 << 23) - -/* --- FLASH_SR values ----------------------------------------------------- */ -#define FLASH_SR_RDERR (1 << 13) -#define FLASH_SR_NOTZEROERR (1 << 16) -#define FLASH_SR_FWWERR (1 << 17) - -/* --- FLASH_OPTR values ----------------------------------------------------- */ -#define FLASH_OPTR_NBOOT1 (1 << 31) - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/gpio.h b/libopencm3/include/libopencm3/stm32/l0/gpio.h deleted file mode 100644 index da2f420..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/gpio.h +++ /dev/null @@ -1,76 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the STM32F0xx General Purpose I/O - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * @date 1 July 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define GPIO_BRR(port) MMIO32((port) + 0x28) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOH_BRR GPIO_BRR(GPIOH) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @defgroup gpio_speed GPIO Output Pin Speed -@ingroup gpio_defines -@{*/ -#define GPIO_OSPEED_LOW 0x0 -#define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x2 -#define GPIO_OSPEED_VERYHIGH 0x3 -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/i2c.h b/libopencm3/include/libopencm3/stm32/l0/i2c.h deleted file mode 100644 index f2bf276..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/i2c.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32L0xx I2C - -@ingroup STM32L0xx_defines - -@version 1.0.0 - -@date 1 December 2016 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l0/irq.json b/libopencm3/include/libopencm3/stm32/l0/irq.json deleted file mode 100644 index 3073ea1..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/irq.json +++ /dev/null @@ -1,39 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "rtc", - "flash", - "rcc", - "exti0_1", - "exti2_3", - "exti4_15", - "tsc", - "dma1_channel1", - "dma1_channel2_3", - "dma1_channel4_5", - "adc_comp", - "lptim1", - "usart4_5", - "tim2", - "tim3", - "tim6_dac", - "tim7", - "reserved4", - "tim21", - "i2c3", - "tim22", - "i2c1", - "i2c2", - "spi1", - "spi2", - "usart1", - "usart2", - "lpuart1_aes_rng", - "lcd", - "usb" - ], - "partname_humanreadable": "STM32 L0 series", - "partname_doxygen": "STM32L0", - "includeguard": "LIBOPENCM3_STM32_L0_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/l0/iwdg.h b/libopencm3/include/libopencm3/stm32/l0/iwdg.h deleted file mode 100644 index b56c391..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/iwdg.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @brief Defined Constants and Types for the STM32L0xx Independent Watchdog - * Timer - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * @date 28 March 2018 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/lptimer.h b/libopencm3/include/libopencm3/stm32/l0/lptimer.h deleted file mode 100644 index e6d99d8..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/lptimer.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @defgroup lptimer_defines LPTIM Defines - * - * @ingroup STM32L0xx_defines - * - * @brief libopencm3 Defined Constants and Types for the STM32L0xx Low Power Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPTIMER_H -#define LIBOPENCM3_LPTIMER_H -/**@{*/ - -#include - -/** @defgroup lptim_reg_base Low Power Timer register base addresses -@{*/ -#define LPTIM1 LPTIM1_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/memorymap.h b/libopencm3/include/libopencm3/stm32/l0/memorymap.h deleted file mode 100644 index e384c5c..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/memorymap.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define IOPORT_BASE (0x50000000U) -#define INFO_BASE (0x1ff80000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x4800) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -#define CRS_BASE (PERIPH_BASE_APB1 + 0x6C00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800) -#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) - - -/* APB2 */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define TIM21_BASE (PERIPH_BASE_APB2 + 0x0800) -#define TIM22_BASE (PERIPH_BASE_APB2 + 0x1400) -#define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00) -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800) - -/* AHB */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) -#define RCC_BASE (PERIPH_BASE_AHB + 0x01000) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) -#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) -#define TSC_BASE (PERIPH_BASE_AHB + 0x04000) -#define RNG_BASE (PERIPH_BASE_AHB + 0x05000) -#define AES_BASE (PERIPH_BASE_AHB + 0x06000) - -#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) -#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) -#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) -#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) -#define GPIO_PORT_H_BASE (IOPORT_BASE + 0x01C00) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7C) -#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x50) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14) - -/* ST provided factory calibration values @ 3.0V */ -#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x78)) -#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x7A)) -#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x7E)) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/pwr.h b/libopencm3/include/libopencm3/stm32/l0/pwr.h deleted file mode 100644 index bb2ff9a..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/pwr.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - * - * @brief Defined Constants and Types for the STM32L0xx PWR Control - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * @date 21 May 2015 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l0/rcc.h b/libopencm3/include/libopencm3/stm32/l0/rcc.h deleted file mode 100644 index 5919442..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/rcc.h +++ /dev/null @@ -1,713 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @ingroup STM32L0xx_defines - * - * @brief Defined Constants and Types for the STM32L0xx Reset and Clock - * Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Karl Palsson - * - * @date 17 November 2014 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include -#include -#include - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) -#define RCC_CRRCR MMIO32(RCC_BASE + 0x08) -#define RCC_CFGR MMIO32(RCC_BASE + 0x0c) -#define RCC_CIER MMIO32(RCC_BASE + 0x10) -#define RCC_CIFR MMIO32(RCC_BASE + 0x14) -#define RCC_CICR MMIO32(RCC_BASE + 0x18) -#define RCC_IOPRSTR MMIO32(RCC_BASE + 0x1c) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x20) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x28) -#define RCC_IOPENR MMIO32(RCC_BASE + 0x2c) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x30) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x34) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x38) -#define RCC_IOPSMEN MMIO32(RCC_BASE + 0x3c) -#define RCC_AHBSMENR MMIO32(RCC_BASE + 0x40) -#define RCC_APB2SMENR MMIO32(RCC_BASE + 0x44) -#define RCC_APB1SMENR MMIO32(RCC_BASE + 0x48) -#define RCC_CCIPR MMIO32(RCC_BASE + 0x4c) -#define RCC_CSR MMIO32(RCC_BASE + 0x50) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_RTCPRE_SHIFT 20 -#define RCC_CR_RTCPRE_MASK 0x3 -#define RCC_CR_RTCPRE_DIV2 0 -#define RCC_CR_RTCPRE_DIV4 1 -#define RCC_CR_RTCPRE_DIV8 2 -#define RCC_CR_RTCPRE_DIV16 3 -#define RCC_CR_CSSHSEON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_MSIRDY (1 << 9) -#define RCC_CR_MSION (1 << 8) -#define RCC_CR_HSI16DIVF (1 << 4) -#define RCC_CR_HSI16DIVEN (1 << 3) -#define RCC_CR_HSI16RDY (1 << 2) -#define RCC_CR_HSI16KERON (1 << 1) -#define RCC_CR_HSI16ON (1 << 0) - - -/* --- RCC_ICSCR values ---------------------------------------------------- */ - -#define RCC_ICSCR_MSITRIM_SHIFT 24 -#define RCC_ICSCR_MSITRIM_MASK 0xff -#define RCC_ICSCR_MSICAL_SHIFT 16 -#define RCC_ICSCR_MSICAL_MASK 0xff - -#define RCC_ICSCR_MSIRANGE_SHIFT 13 -#define RCC_ICSCR_MSIRANGE_MASK 0x7 -#define RCC_ICSCR_MSIRANGE_65KHZ 0x0 -#define RCC_ICSCR_MSIRANGE_131KHZ 0x1 -#define RCC_ICSCR_MSIRANGE_262KHZ 0x2 -#define RCC_ICSCR_MSIRANGE_524KHZ 0x3 -#define RCC_ICSCR_MSIRANGE_1MHZ 0x4 -#define RCC_ICSCR_MSIRANGE_2MHZ 0x5 -#define RCC_ICSCR_MSIRANGE_4MHZ 0x6 - -#define RCC_ICSCR_HSI16TRIM_SHIFT 8 -#define RCC_ICSCR_HSI16TRIM_MASK 0x1f -#define RCC_ICSCR_HSI16CAL_SHIFT 0 -#define RCC_ICSCR_HSI16CAL_MASK 0xff - -/* --- RCC_CRRCR register */ - -#define RCC_CRRCR_HSI48CAL_SHIFT 8 -#define RCC_CRRCR_HSI48CAL_MASK 0xff -#define RCC_CRRCR_HSI48RDY (1<<1) -#define RCC_CRRCR_HSI48ON (1<<0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCOPRE */ -#define RCC_CFGR_MCOPRE_DIV1 0 -#define RCC_CFGR_MCOPRE_DIV2 1 -#define RCC_CFGR_MCOPRE_DIV4 2 -#define RCC_CFGR_MCOPRE_DIV8 3 -#define RCC_CFGR_MCOPRE_DIV16 4 - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x1 -#define RCC_CFGR_MCO_HSI16 0x2 -#define RCC_CFGR_MCO_MSI 0x3 -#define RCC_CFGR_MCO_HSE 0x4 -#define RCC_CFGR_MCO_PLL 0x5 -#define RCC_CFGR_MCO_LSI 0x6 -#define RCC_CFGR_MCO_LSE 0x7 -#define RCC_CFGR_MCO_HSI48 0x8 -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf - -/** @defgroup rcc_cfgr_pdf PLLDIV PLL division factor - @{*/ -#define RCC_CFGR_PLLDIV_DIV2 0x1 -#define RCC_CFGR_PLLDIV_DIV3 0x2 -#define RCC_CFGR_PLLDIV_DIV4 0x3 -/**@}*/ -#define RCC_CFGR_PLLDIV_SHIFT 22 -#define RCC_CFGR_PLLDIV_MASK 0x3 - -/** @defgroup rcc_cfgr_pmf PLLMUL PLL multiplication factor - @{*/ -#define RCC_CFGR_PLLMUL_MUL3 0x0 -#define RCC_CFGR_PLLMUL_MUL4 0x1 -#define RCC_CFGR_PLLMUL_MUL6 0x2 -#define RCC_CFGR_PLLMUL_MUL8 0x3 -#define RCC_CFGR_PLLMUL_MUL12 0x4 -#define RCC_CFGR_PLLMUL_MUL16 0x5 -#define RCC_CFGR_PLLMUL_MUL24 0x6 -#define RCC_CFGR_PLLMUL_MUL32 0x7 -#define RCC_CFGR_PLLMUL_MUL48 0x8 -/**@}*/ -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLMUL_MASK 0xf - -/* PLLSRC: PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI16_CLK 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 - -/* Wakeup from stop clock selection */ -#define RCC_CFGR_STOPWUCK_MSI (0<<15) -#define RCC_CFGR_STOPWUCK_HSI16 (1<<15) - -/* PPRE2: APB high-speed prescaler (APB2) */ -/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors -@{*/ -#define RCC_CFGR_PPRE2_NODIV 0x0 -#define RCC_CFGR_PPRE2_DIV2 0x4 -#define RCC_CFGR_PPRE2_DIV4 0x5 -#define RCC_CFGR_PPRE2_DIV8 0x6 -#define RCC_CFGR_PPRE2_DIV16 0x7 -/**@}*/ -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE2_SHIFT 11 - -/* PPRE1: APB low-speed prescaler (APB1) */ -/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors -@{*/ -#define RCC_CFGR_PPRE1_NODIV 0x0 -#define RCC_CFGR_PPRE1_DIV2 0x4 -#define RCC_CFGR_PPRE1_DIV4 0x5 -#define RCC_CFGR_PPRE1_DIV8 0x6 -#define RCC_CFGR_PPRE1_DIV16 0x7 -/**@}*/ -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 8 - -/* HPRE: AHB prescaler */ -/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors -@{*/ -#define RCC_CFGR_HPRE_NODIV 0x0 -#define RCC_CFGR_HPRE_DIV2 0x8 -#define RCC_CFGR_HPRE_DIV4 0x9 -#define RCC_CFGR_HPRE_DIV8 0xa -#define RCC_CFGR_HPRE_DIV16 0xb -#define RCC_CFGR_HPRE_DIV64 0xc -#define RCC_CFGR_HPRE_DIV128 0xd -#define RCC_CFGR_HPRE_DIV256 0xe -#define RCC_CFGR_HPRE_DIV512 0xf -/**@}*/ -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_SHIFT 4 - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_MSI 0x0 -#define RCC_CFGR_SWS_HSI16 0x1 -#define RCC_CFGR_SWS_HSE 0x2 -#define RCC_CFGR_SWS_PLL 0x3 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_SHIFT 2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_MSI 0x0 -#define RCC_CFGR_SW_HSI16 0x1 -#define RCC_CFGR_SW_HSE 0x2 -#define RCC_CFGR_SW_PLL 0x3 -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_SHIFT 0 - -/* --- RCC_CIER - Clock interrupt enable register */ - -#define RCC_CIER_CSSLSE (1 << 7) -/* OSC ready interrupt enable bits */ -#define RCC_CIER_HSI48RDYIE (1 << 6) -#define RCC_CIER_MSIRDYIE (1 << 5) -#define RCC_CIER_PLLRDYIE (1 << 4) -#define RCC_CIER_HSERDYIE (1 << 3) -#define RCC_CIER_HSI16RDYIE (1 << 2) -#define RCC_CIER_LSERDYIE (1 << 1) -#define RCC_CIER_LSIRDYIE (1 << 0) - -/* --- RCC_CIFR - Clock interrupt flag register */ - -#define RCC_CIFR_CSSHSEF (1 << 8) -#define RCC_CIFR_CSSLSEF (1 << 7) -#define RCC_CIFR_HSI48RDYF (1 << 6) -#define RCC_CIFR_MSIRDYF (1 << 5) -#define RCC_CIFR_PLLRDYF (1 << 4) -#define RCC_CIFR_HSERDYF (1 << 3) -#define RCC_CIFR_HSI16RDYF (1 << 2) -#define RCC_CIFR_LSERDYF (1 << 1) -#define RCC_CIFR_LSIRDYF (1 << 0) - -/* --- RCC_CICR - Clock interrupt clear register */ - -#define RCC_CICR_CSSHSEC (1 << 8) -#define RCC_CICR_CSSLSEC (1 << 7) -#define RCC_CICR_HSI48RDYC (1 << 6) -#define RCC_CICR_MSIRDYC (1 << 5) -#define RCC_CICR_PLLRDYC (1 << 4) -#define RCC_CICR_HSERDYC (1 << 3) -#define RCC_CICR_HSI16RDYC (1 << 2) -#define RCC_CICR_LSERDYC (1 << 1) -#define RCC_CICR_LSIRDYC (1 << 0) - -/* --- RCC_IOPRSTR - GPIO Reset Register */ - -#define RCC_IOPPRSTR_IOPHRST (1<<7) -#define RCC_IOPPRSTR_IOPERST (1<<4) -#define RCC_IOPPRSTR_IOPDRST (1<<3) -#define RCC_IOPPRSTR_IOPCRST (1<<2) -#define RCC_IOPPRSTR_IOPBRST (1<<1) -#define RCC_IOPPRSTR_IOPARST (1<<0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values -@{*/ -#define RCC_AHBRSTR_CRYPRST (1 << 24) -#define RCC_AHBRSTR_RNGRST (1 << 20) -#define RCC_AHBRSTR_TSCRST (1 << 16) -#define RCC_AHBRSTR_CRCRST (1 << 12) -#define RCC_AHBRSTR_MIFRST (1 << 8) -#define RCC_AHBRSTR_DMARST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_DBGRST (1 << 22) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_ADC1RST (1 << 9) -#define RCC_APB2RSTR_TIM22RST (1 << 5) -#define RCC_APB2RSTR_TIM21RST (1 << 2) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values -@{*/ -#define RCC_APB1RSTR_LPTIM1RST (1 << 31) -#define RCC_APB1RSTR_I2C3RST (1 << 30) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_CRSRST (1 << 27) -#define RCC_APB1RSTR_USBRST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART5RST (1 << 20) -#define RCC_APB1RSTR_USART4RST (1 << 19) -#define RCC_APB1RSTR_LPUART1RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_LCDRST (1 << 9) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/* --- RCC_IOPENR - GPIO clock enable register */ - -#define RCC_IOPENR_IOPHEN (1<<7) -#define RCC_IOPENR_IOPEEN (1<<4) -#define RCC_IOPENR_IOPDEN (1<<3) -#define RCC_IOPENR_IOPCEN (1<<2) -#define RCC_IOPENR_IOPBEN (1<<1) -#define RCC_IOPENR_IOPAEN (1<<0) - -/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values -@{*/ -#define RCC_AHBENR_CRYPEN (1 << 24) -#define RCC_AHBENR_RNGEN (1 << 20) -#define RCC_AHBENR_TSCEN (1 << 16) -#define RCC_AHBENR_CRCEN (1 << 12) -#define RCC_AHBENR_MIFEN (1 << 8) -#define RCC_AHBENR_DMAEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values -@{*/ -#define RCC_APB2ENR_DBGEN (1 << 22) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_MIFEN (1 << 7) -#define RCC_APB2ENR_TIM22EN (1 << 5) -#define RCC_APB2ENR_TIM21EN (1 << 2) -#define RCC_APB2ENR_SYSCFGEN (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@{*/ -#define RCC_APB1ENR_LPTIM1EN (1 << 31) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_CRSEN (1 << 27) -#define RCC_APB1ENR_USBEN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART5EN (1 << 20) -#define RCC_APB1ENR_USART4EN (1 << 19) -#define RCC_APB1ENR_LPUART1EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_LCDEN (1 << 9) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/**@}*/ - -/* --- RCC_IOPSMENR - GPIO Clock enable in sleep mode */ - -#define RCC_IOPSMENR_IOPHSMEN (1<<7) -#define RCC_IOPSMENR_IOPESMEN (1<<4) -#define RCC_IOPSMENR_IOPDSMEN (1<<3) -#define RCC_IOPSMENR_IOPCSMEN (1<<2) -#define RCC_IOPSMENR_IOPBSMEN (1<<1) -#define RCC_IOPSMENR_IOPASMEN (1<<0) - -/* --- RCC_AHBSMENR - AHB periph clock in sleep mode */ - -#define RCC_AHBSMENR_CRYPSMEN (1 << 24) -#define RCC_AHBSMENR_RNGSMEN (1 << 20) -#define RCC_AHBSMENR_TSCSMEN (1 << 16) -#define RCC_AHBSMENR_CRCSMEN (1 << 12) -#define RCC_AHBSMENR_MIFSMEN (1 << 8) -#define RCC_AHBSMENR_DMASMEN (1 << 0) - -/* --- RCC_APB2SMENR - APB2 periph clock in sleep mode */ - -#define RCC_APB2SMENR_DBGSMEN (1 << 22) -#define RCC_APB2SMENR_USART1SMEN (1 << 14) -#define RCC_APB2SMENR_SPI1SMEN (1 << 12) -#define RCC_APB2SMENR_ADC1SMEN (1 << 9) -#define RCC_APB2SMENR_MIFSMEN (1 << 7) -#define RCC_APB2SMENR_TIM22SMEN (1 << 5) -#define RCC_APB2SMENR_TIM21SMEN (1 << 2) -#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) - -/* --- RCC_APB1SMENR - APB1 periph clock in sleep mode */ - -#define RCC_APB1SMENR_LPTIM1SMEN (1 << 31) -#define RCC_APB1SMENR_I2C3SMEN (1 << 30) -#define RCC_APB1SMENR_DACSMEN (1 << 29) -#define RCC_APB1SMENR_PWRSMEN (1 << 28) -#define RCC_APB1SMENR_CRSSMEN (1 << 27) -#define RCC_APB1SMENR_USBSMEN (1 << 23) -#define RCC_APB1SMENR_I2C2SMEN (1 << 22) -#define RCC_APB1SMENR_I2C1SMEN (1 << 21) -#define RCC_APB1SMENR_USART5SMEN (1 << 20) -#define RCC_APB1SMENR_USART4SMEN (1 << 19) -#define RCC_APB1SMENR_LPUART1SMEN (1 << 18) -#define RCC_APB1SMENR_USART2SMEN (1 << 17) -#define RCC_APB1SMENR_SPI2SMEN (1 << 14) -#define RCC_APB1SMENR_WWDGSMEN (1 << 11) -#define RCC_APB1SMENR_LCDSMEN (1 << 9) -#define RCC_APB1SMENR_TIM7SMEN (1 << 5) -#define RCC_APB1SMENR_TIM6SMEN (1 << 4) -#define RCC_APB1SMENR_TIM3SMEN (1 << 1) -#define RCC_APB1SMENR_TIM2SMEN (1 << 0) - -/* --- RCC_CCIPR - Clock config register */ - -#define RCC_CCIPR_HSI48SEL (1<<26) - -#define RCC_CCIPR_LPTIM1SEL_APB 0 -#define RCC_CCIPR_LPTIM1SEL_LSI 1 -#define RCC_CCIPR_LPTIM1SEL_HSI16 2 -#define RCC_CCIPR_LPTIM1SEL_LSE 3 -#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 -#define RCC_CCIPR_LPTIM1SEL_MASK 0x3 - -#define RCC_CCIPR_I2C3SEL_APB 0 -#define RCC_CCIPR_I2C3SEL_SYS 1 -#define RCC_CCIPR_I2C3SEL_HSI16 2 -#define RCC_CCIPR_I2C3SEL_SHIFT 16 -#define RCC_CCIPR_I2C3SEL_MASK 0x3 - -#define RCC_CCIPR_I2C1SEL_APB 0 -#define RCC_CCIPR_I2C1SEL_SYS 1 -#define RCC_CCIPR_I2C1SEL_HSI16 2 -#define RCC_CCIPR_I2C1SEL_SHIFT 12 -#define RCC_CCIPR_I2C1SEL_MASK 0x3 - -#define RCC_CCIPR_LPUART1SEL_APB 0 -#define RCC_CCIPR_LPUART1SEL_SYS 1 -#define RCC_CCIPR_LPUART1SEL_HSI16 2 -#define RCC_CCIPR_LPUART1SEL_LSE 3 -#define RCC_CCIPR_LPUART1SEL_SHIFT 10 -#define RCC_CCIPR_LPUART1SEL_MASK 0x3 - -#define RCC_CCIPR_USART2SEL_APB 0 -#define RCC_CCIPR_USART2SEL_SYS 1 -#define RCC_CCIPR_USART2SEL_HSI16 2 -#define RCC_CCIPR_USART2SEL_LSE 3 -#define RCC_CCIPR_USART2SEL_SHIFT 2 -#define RCC_CCIPR_USART2SEL_MASK 0x3 - -#define RCC_CCIPR_USART1SEL_APB 0 -#define RCC_CCIPR_USART1SEL_SYS 1 -#define RCC_CCIPR_USART1SEL_HSI16 2 -#define RCC_CCIPR_USART1SEL_LSE 3 -#define RCC_CCIPR_USART1SEL_SHIFT 0 -#define RCC_CCIPR_USART1SEL_MASK 0x3 - -/* --- RCC_CSRT - Control/Status register */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_FWRSTF (1 << 24) -#define RCC_CSR_RMVF (1 << 23) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF) -#define RCC_CSR_RTCRST (1 << 19) -#define RCC_CSR_RTCEN (1 << 18) -#define RCC_CSR_RTCSEL_SHIFT (16) -#define RCC_CSR_RTCSEL_MASK (0x3) -#define RCC_CSR_RTCSEL_NONE (0x0) -#define RCC_CSR_RTCSEL_LSE (0x1) -#define RCC_CSR_RTCSEL_LSI (0x2) -#define RCC_CSR_RTCSEL_HSE (0x3) -#define RCC_CSR_CSSLSED (1 << 14) -#define RCC_CSR_CSSLSEON (1 << 13) -#define RCC_CSR_LSEDRV_SHIFT 11 -#define RCC_CSR_LSEDRV_MASK 0x3 -#define RCC_CSR_LSEDRV_LOWEST 0 -#define RCC_CSR_LSEDRV_MLOW 1 -#define RCC_CSR_LSEDRV_MHIGH 2 -#define RCC_CSR_LSEDRV_HIGHEST 3 -#define RCC_CSR_LSEBYP (1 << 10) -#define RCC_CSR_LSERDY (1 << 9) -#define RCC_CSR_LSEON (1 << 8) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -struct rcc_clock_scale { - uint8_t pll_mul; - uint16_t pll_div; - uint8_t pll_source; - uint8_t flash_waitstates; - enum pwr_vos_scale voltage_scale; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - // FIXME enum pwr_vos_scale voltage_scale; - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; - uint8_t msi_range; -}; - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI48, RCC_HSI16, RCC_MSI, RCC_LSE, RCC_LSI -}; - - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* GPIO peripherals */ - RCC_GPIOA = _REG_BIT(0x2c, 0), - RCC_GPIOB = _REG_BIT(0x2c, 1), - RCC_GPIOC = _REG_BIT(0x2c, 2), - RCC_GPIOD = _REG_BIT(0x2c, 3), - RCC_GPIOE = _REG_BIT(0x2c, 4), - RCC_GPIOH = _REG_BIT(0x2c, 7), - - /* AHB peripherals */ - RCC_DMA = _REG_BIT(0x30, 0), - RCC_MIF = _REG_BIT(0x30, 8), - RCC_CRC = _REG_BIT(0x30, 12), - RCC_TSC = _REG_BIT(0x30, 16), - RCC_RNG = _REG_BIT(0x30, 20), - RCC_CRYPT = _REG_BIT(0x30, 24), - - /* APB2 peripherals */ - RCC_SYSCFG = _REG_BIT(0x34, 0), - RCC_TIM21 = _REG_BIT(0x34, 2), - RCC_TIM22 = _REG_BIT(0x34, 5), - RCC_FW = _REG_BIT(0x34, 7), - RCC_ADC1 = _REG_BIT(0x34, 9), - RCC_SPI1 = _REG_BIT(0x34, 12), - RCC_USART1 = _REG_BIT(0x34, 14), - RCC_DBG = _REG_BIT(0x34, 22), - - /* APB1 peripherals */ - RCC_TIM2 = _REG_BIT(0x38, 0), - RCC_TIM3 = _REG_BIT(0x38, 1), - RCC_TIM6 = _REG_BIT(0x38, 4), - RCC_TIM7 = _REG_BIT(0x38, 5), - RCC_LCD = _REG_BIT(0x38, 9), - RCC_WWDG = _REG_BIT(0x38, 11), - RCC_SPI2 = _REG_BIT(0x38, 14), - RCC_USART2 = _REG_BIT(0x38, 17), - RCC_LPUART1 = _REG_BIT(0x38, 18), - RCC_USART4 = _REG_BIT(0x38, 19), - RCC_USART5 = _REG_BIT(0x38, 20), - RCC_I2C1 = _REG_BIT(0x38, 21), - RCC_I2C2 = _REG_BIT(0x38, 22), - RCC_USB = _REG_BIT(0x38, 23), - RCC_CRS = _REG_BIT(0x38, 27), - RCC_PWR = _REG_BIT(0x38, 28), - RCC_DAC = _REG_BIT(0x38, 29), - RCC_I2C3 = _REG_BIT(0x38, 30), - RCC_LPTIM1 = _REG_BIT(0x38, 31), - - /* GPIO peripherals in sleep mode */ - SCC_GPIOA = _REG_BIT(0x3c, 0), - SCC_GPIOB = _REG_BIT(0x3c, 1), - SCC_GPIOC = _REG_BIT(0x3c, 2), - SCC_GPIOD = _REG_BIT(0x3c, 3), - SCC_GPIOE = _REG_BIT(0x3c, 4), - SCC_GPIOH = _REG_BIT(0x3c, 7), - - /* AHB peripherals in sleep mode */ - SCC_DMA = _REG_BIT(0x40, 0), - SCC_MIF = _REG_BIT(0x40, 8), - SCC_SRAM = _REG_BIT(0x40, 12), - SCC_CRC = _REG_BIT(0x40, 12), - SCC_TSC = _REG_BIT(0x40, 16), - SCC_RNG = _REG_BIT(0x40, 20), - SCC_CRYPT = _REG_BIT(0x40, 24), - - /* APB2 peripherals in sleep mode */ - SCC_SYSCFG = _REG_BIT(0x44, 0), - SCC_TIM21 = _REG_BIT(0x44, 2), - SCC_TIM22 = _REG_BIT(0x44, 5), - SCC_ADC1 = _REG_BIT(0x44, 9), - SCC_SPI1 = _REG_BIT(0x44, 12), - SCC_USART1 = _REG_BIT(0x44, 14), - SCC_DBG = _REG_BIT(0x44, 22), - - /* APB1 peripherals in sleep mode */ - SCC_TIM2 = _REG_BIT(0x48, 0), - SCC_TIM3 = _REG_BIT(0x48, 1), - SCC_TIM6 = _REG_BIT(0x48, 4), - SCC_TIM7 = _REG_BIT(0x48, 5), - SCC_LCD = _REG_BIT(0x48, 9), - SCC_WWDG = _REG_BIT(0x48, 11), - SCC_SPI2 = _REG_BIT(0x48, 14), - SCC_USART2 = _REG_BIT(0x48, 17), - SCC_LPUART1 = _REG_BIT(0x48, 18), - SCC_USART4 = _REG_BIT(0x48, 19), - SCC_USART5 = _REG_BIT(0x48, 20), - SCC_I2C1 = _REG_BIT(0x48, 21), - SCC_I2C2 = _REG_BIT(0x48, 22), - SCC_USB = _REG_BIT(0x48, 23), - SCC_CRS = _REG_BIT(0x48, 27), - SCC_PWR = _REG_BIT(0x48, 28), - SCC_DAC = _REG_BIT(0x48, 29), - SCC_I2C3 = _REG_BIT(0x48, 30), - SCC_LPTIM1 = _REG_BIT(0x48, 31), -}; - -enum rcc_periph_rst { - /* GPIO peripherals */ - RST_GPIOA = _REG_BIT(0x1c, 0), - RST_GPIOB = _REG_BIT(0x1c, 1), - RST_GPIOC = _REG_BIT(0x1c, 2), - RST_GPIOD = _REG_BIT(0x1c, 3), - RST_GPIOE = _REG_BIT(0x1c, 4), - RST_GPIOH = _REG_BIT(0x1c, 7), - - /* AHB peripherals */ - RST_DMA = _REG_BIT(0x20, 0), - RST_MIF = _REG_BIT(0x20, 8), - RST_CRC = _REG_BIT(0x20, 12), - RST_TSC = _REG_BIT(0x20, 16), - RST_RNG = _REG_BIT(0x20, 20), - RST_CRYPT = _REG_BIT(0x20, 24), - - /* APB2 peripherals */ - RST_SYSCFG = _REG_BIT(0x24, 0), - RST_TIM21 = _REG_BIT(0x24, 2), - RST_TIM22 = _REG_BIT(0x24, 5), - RST_ADC1 = _REG_BIT(0x24, 9), - RST_SPI1 = _REG_BIT(0x24, 12), - RST_USART1 = _REG_BIT(0x24, 14), - RST_DBG = _REG_BIT(0x24, 22), - - /* APB1 peripherals*/ - RST_TIM2 = _REG_BIT(0x28, 0), - RST_TIM3 = _REG_BIT(0x28, 1), - RST_TIM6 = _REG_BIT(0x28, 4), - RST_TIM7 = _REG_BIT(0x28, 5), - RST_LCD = _REG_BIT(0x28, 9), - RST_WWDG = _REG_BIT(0x28, 11), - RST_SPI2 = _REG_BIT(0x28, 14), - RST_USART2 = _REG_BIT(0x28, 17), - RST_LPUART1 = _REG_BIT(0x28, 18), - RST_USART4 = _REG_BIT(0x28, 19), - RST_USART5 = _REG_BIT(0x28, 20), - RST_I2C1 = _REG_BIT(0x28, 21), - RST_I2C2 = _REG_BIT(0x28, 22), - RST_USB = _REG_BIT(0x28, 23), - RST_CRS = _REG_BIT(0x28, 27), - RST_PWR = _REG_BIT(0x28, 28), - RST_DAC = _REG_BIT(0x28, 29), - RST_I2C3 = _REG_BIT(0x28, 30), - RST_LPTIM1 = _REG_BIT(0x28, 31), -}; -#include - -BEGIN_DECLS - -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_set_hsi48_source_rc48(void); -void rcc_set_hsi48_source_pll(void); -void rcc_set_sysclk_source(enum rcc_osc osc); -void rcc_set_pll_multiplier(uint32_t factor); -void rcc_set_pll_divider(uint32_t factor); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); - -void rcc_set_msi_range(uint32_t msi_range); - -void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); - -void rcc_set_lptim1_sel(uint32_t lptim1_sel); -void rcc_set_lpuart1_sel(uint32_t lpupart1_sel); -void rcc_set_usart1_sel(uint32_t usart1_sel); -void rcc_set_usart2_sel(uint32_t usart2_sel); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/rng.h b/libopencm3/include/libopencm3/stm32/l0/rng.h deleted file mode 100644 index 09d014d..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/rng.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/rtc.h b/libopencm3/include/libopencm3/stm32/l0/rtc.h deleted file mode 100644 index 6f71152..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/rtc.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - * - * @brief Defined Constants and Types for the STM32L0xx RTC - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/spi.h b/libopencm3/include/libopencm3/stm32/l0/spi.h deleted file mode 100644 index 7dda07b..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32L0xx SPI - -@ingroup STM32L0xx_defines - -@version 1.0.0 - -@date 20 January 2017 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l0/st_usbfs.h b/libopencm3/include/libopencm3/stm32/l0/st_usbfs.h deleted file mode 100644 index 7b65d2b..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/syscfg.h b/libopencm3/include/libopencm3/stm32/l0/syscfg.h deleted file mode 100644 index 767ddf4..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/syscfg.h +++ /dev/null @@ -1,135 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @brief Defined Constants and Types for the STM32L0xx System Config - * - * @ingroup STM32L0xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2015 - * Robin Kreis - * - * @date 1 May 2015 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Robin Kreis - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H -/**@{*/ - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x00) -#define SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x04) -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) -#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) -#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) -#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) -#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) -#define COMP1_CTRL MMIO32(SYSCFG_BASE + 0x18) -#define COMP2_CTRL MMIO32(SYSCFG_BASE + 0x1C) -#define SYSCFG_CFGR3 MMIO32(SYSCFG_BASE + 0x20) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/ - -#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0 -#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) -#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) - -#define SYSCFG_CFGR1_UFB (1<<3) - -#define SYSCFG_CFGR1_BOOT_MODE_SHIFT 8 -#define SYSCFG_CFGR1_BOOT_MODE (3 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) -#define SYSCFG_CFGR1_BOOT_MODE_FLASH (0 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) -#define SYSCFG_CFGR1_BOOT_MODE_SYSTEM (1 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) -#define SYSCFG_CFGR1_BOOT_MODE_SRAM (3 << SYSCFG_CFGR1_BOOT_MODE_SHIFT) - -/* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/ - -#define SYSCFG_CFGR2_FWDIS (1 << 0) - -#define SYSCFG_CFGR2_I2C_PB6_FMP (1 << 8) -#define SYSCFG_CFGR2_I2C_PB7_FMP (1 << 9) -#define SYSCFG_CFGR2_I2C_PB8_FMP (1 << 10) -#define SYSCFG_CFGR2_I2C_PB9_FMP (1 << 11) - -#define SYSCFG_CFGR2_I2C1_FMP (1 << 12) -#define SYSCFG_CFGR2_I2C2_FMP (1 << 13) -#define SYSCFG_CFGR2_I2C3_FMP (1 << 14) - -/* REF_CFGR3 Values -- ---------------------------------------------------*/ - -#define SYSCFG_CFGR3_EN_VREFINT (1 << 0) - -#define SYSCFG_CFGR3_SEL_VREF_OUT_SHIFT 4 -#define SYSCFG_CFGR3_SEL_VREF_OUT (3 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) -#define SYSCFG_CFGR3_SEL_VREF_OUT_PB0 (1 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) -#define SYSCFG_CFGR3_SEL_VREF_OUT_PB1 (2 << SYSCFG_CFGR3_EN_VREFINT_SHIFT) - -#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC (1 << 8) -#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC (1 << 9) -#define SYSCFG_CFGR3_ENBUF_VREFINT_COMP (1 << 12) -#define SYSCFG_CFGR3_ENREF_HSI48 (1 << 13) - -#define SYSCFG_CFGR3_REF_HSI48_RDYF (1 << 26) -#define SYSCFG_CFGR3_SENSOR_ADC_RDYF (1 << 27) -#define SYSCFG_CFGR3_VREFINT_ADC_RDYF (1 << 28) -#define SYSCFG_CFGR3_VREFINT_COMP_RDYF (1 << 29) -#define SYSCFG_CFGR3_VREFINT_RDYF (1 << 30) -#define SYSCFG_CFGR3_REF_LOCK (1 << 31) - -/* SYSCFG_EXTICR Values -- --------------------------------------------------*/ - -#define SYSCFG_EXTICR_FIELDSIZE 4 -#define SYSCFG_EXTICR_GPIOA 0 -#define SYSCFG_EXTICR_GPIOB 1 -#define SYSCFG_EXTICR_GPIOC 2 -#define SYSCFG_EXTICR_GPIOD 3 -#define SYSCFG_EXTICR_GPIOE 4 -#define SYSCFG_EXTICR_GPIOH 5 - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l0/timer.h b/libopencm3/include/libopencm3/stm32/l0/timer.h deleted file mode 100644 index 9877281..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/timer.h +++ /dev/null @@ -1,103 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32L0xx Timers - -@ingroup STM32L0xx_defines - -@version 1.0.0 - -@date 17 May 2015 - -@author @htmlonly © @endhtmlonly 2015 Robin Kreis - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Robin Kreis - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -/**@{*/ - -/** Timer 2/21/22 option register (TIMx_OR) */ - -#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) -#define TIM2_OR TIM_OR(TIM2) -#define TIM21_OR TIM_OR(TIM21) -#define TIM22_OR TIM_OR(TIM22) - -#define TIM2_OR_ETR_RMP_SHIFT 0 -#define TIM2_OR_ETR_RMP (7 << TIM2_OR_ETR_RMP_SHIFT) -#define TIM2_OR_ETR_RMP_GPIO (0 << TIM2_OR_ETR_RMP_SHIFT) -#define TIM2_OR_ETR_RMP_HSI48 (4 << TIM2_OR_ETR_RMP_SHIFT) -#define TIM2_OR_ETR_RMP_LSE (5 << TIM2_OR_ETR_RMP_SHIFT) -#define TIM2_OR_ETR_RMP_COMP2_OUT (6 << TIM2_OR_ETR_RMP_SHIFT) -#define TIM2_OR_ETR_RMP_COMP1_OUT (7 << TIM2_OR_ETR_RMP_SHIFT) - -#define TIM2_OR_TI4_RMP_SHIFT 3 -#define TIM2_OR_TI4_RMP (3 << TIM2_OR_TI4_RMP_SHIFT) -#define TIM2_OR_TI4_RMP_GPIO (0 << TIM2_OR_TI4_RMP_GPIO) -#define TIM2_OR_TI4_RMP_COMP2_OUT (1 << TIM2_OR_TI4_RMP_GPIO) -#define TIM2_OR_TI4_RMP_COMP1_OUT (2 << TIM2_OR_TI4_RMP_GPIO) - -#define TIM21_OR_ETR_RMP_SHIFT 0 -#define TIM21_OR_ETR_RMP (3 << TIM21_OR_ETR_RMP_SHIFT) -#define TIM21_OR_ETR_RMP_GPIO (0 << TIM21_OR_ETR_RMP_SHIFT) -#define TIM21_OR_ETR_RMP_COMP2_OUT (1 << TIM21_OR_ETR_RMP_SHIFT) -#define TIM21_OR_ETR_RMP_COMP1_OUT (2 << TIM21_OR_ETR_RMP_SHIFT) -#define TIM21_OR_ETR_RMP_LSE (3 << TIM21_OR_ETR_RMP_SHIFT) - -#define TIM21_OR_TI1_RMP_SHIFT 2 -#define TIM21_OR_TI1_RMP (7 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_GPIO (0 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_RTC_WAKEUP (1 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_HSE_RTC (2 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_MSI (3 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_LSE (4 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_LSI (5 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_COMP1_OUT (6 << TIM21_OR_TI1_RMP_SHIFT) -#define TIM21_OR_TI1_RMP_MCO (7 << TIM21_OR_TI1_RMP_SHIFT) - -#define TIM21_OR_TI2_RMP_SHIFT 5 -#define TIM21_OR_TI2_RMP (1 << TIM21_OR_TI2_RMP_SHIFT) -#define TIM21_OR_TI2_RMP_GPIO (0 << TIM21_OR_TI2_RMP_SHIFT) -#define TIM21_OR_TI2_RMP_COMP2_OUT (1 << TIM21_OR_TI2_RMP_SHIFT) - -#define TIM22_OR_ETR_RMP_SHIFT 0 -#define TIM22_OR_ETR_RMP (3 << TIM22_OR_ETR_RMP_SHIFT) -#define TIM22_OR_ETR_GPIO (0 << TIM22_OR_ETR_RMP_SHIFT) -#define TIM22_OR_ETR_COMP2_OUT (1 << TIM22_OR_ETR_RMP_SHIFT) -#define TIM22_OR_ETR_COMP1_OUT (2 << TIM22_OR_ETR_RMP_SHIFT) -#define TIM22_OR_ETR_LSE (3 << TIM22_OR_ETR_RMP_SHIFT) - -#define TIM22_OR_TI1_RMP_SHIFT 2 -#define TIM22_OR_TI1_RMP (3 << TIM22_OR_TI1_RMP_SHIFT) -#define TIM22_OR_TI1_RMP_GPIO (0 << TIM22_OR_TI1_RMP_SHIFT) -#define TIM22_OR_TI1_RMP_COMP2_OUT (1 << TIM22_OR_TI1_RMP_SHIFT) -#define TIM22_OR_TI1_RMP_COMP1_OUT (2 << TIM22_OR_TI1_RMP_SHIFT) - -/**@}*/ - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l0/usart.h b/libopencm3/include/libopencm3/stm32/l0/usart.h deleted file mode 100644 index 6ab4906..0000000 --- a/libopencm3/include/libopencm3/stm32/l0/usart.h +++ /dev/null @@ -1,51 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32L0xx USART - * - * @ingroup STM32L0xx_defines - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/**@{*/ - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART4 USART4_BASE -#define USART5 USART5_BASE -#define LPUART1 LPUART1_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/adc.h b/libopencm3/include/libopencm3/stm32/l1/adc.h deleted file mode 100644 index fe2fa58..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/adc.h +++ /dev/null @@ -1,190 +0,0 @@ -/** @defgroup adc_defines ADC Defines - -@brief Defined Constants and Types for the STM32L1xx Analog to -Digital Converters - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2013 Karl Palsson - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include - -#define ADC_MAX_REGULAR_SEQUENCE 28 -/* 26 in L/M, but 32 in two banks for M+/H density */ -#define ADC_MAX_CHANNELS 32 - -/* ADC sample time register 3 (ADC_SMPR3) */ -#define ADC_SMPR3(block) MMIO32((block) + 0x14) -#define ADC1_SMPR3 ADC_SMPR3(ADC1) - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32((block) + 0x18) -#define ADC_JOFR2(block) MMIO32((block) + 0x1c) -#define ADC_JOFR3(block) MMIO32((block) + 0x20) -#define ADC_JOFR4(block) MMIO32((block) + 0x24) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32((block) + 0x28) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32((block) + 0x2c) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32((block) + 0x30) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32((block) + 0x34) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32((block) + 0x38) - -/* ADC regular sequence register 4 (ADC_SQR4) */ -#define ADC_SQR4(block) MMIO32((block) + 0x3c) -#define ADC1_SQR4 ADC_SQR4(ADC1) - -/* ADC regular sequence register 5 (ADC_SQR5) */ -#define ADC_SQR5(block) MMIO32((block) + 0x40) -#define ADC1_SQR5 ADC_SQR5(ADC1) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32((block) + 0x44) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32((block) + 0x48) -#define ADC_JDR2(block) MMIO32((block) + 0x4c) -#define ADC_JDR3(block) MMIO32((block) + 0x50) -#define ADC_JDR4(block) MMIO32((block) + 0x54) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32((block) + 0x58) - -/* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */ -#define ADC_SMPR0(block) MMIO32((block) + 0x5c) -#define ADC1_SMPR0 ADC_SMPR0(ADC1) - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_TEMP ADC_CHANNEL16 -#define ADC_CHANNEL_VREF ADC_CHANNEL17 -/**@}*/ - -/* --- ADC_SR values ------------------------------------------------------- */ -/****************************************************************************/ -/** @defgroup adc_sr_values ADC Status Register Flags - * @ingroup adc_defines - * - *@{*/ - -/* JCNR:*//** Injected channel not ready */ -#define ADC_SR_JCNR (1 << 9) - -/* RCNR:*//** Regular channel not ready */ -#define ADC_SR_RCNR (1 << 8) - -/* ADONS:*//** ADC ON status */ -#define ADC_SR_ADONS (1 << 6) - -/**@}*/ - -/* --- ADC_CR1 values ------------------------------------------------------- */ -#define ADC_CR1_PDI (1 << 17) -#define ADC_CR1_PDD (1 << 16) - -#define ADC_CR1_AWDCH_MAX 26 - -/* EXTSEL[3:0]: External event selection for regular group. */ -/****************************************************************************/ -/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group -@ingroup adc_defines - -@{*/ -#define ADC_CR2_EXTSEL_TIM9_CC2 (0 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM9_TRGO (1 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM2_CC3 (2 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM2_TRGO (6 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM3_CC1 (7 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM3_CC3 (8 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM4_TRGO (9 << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_TIM6_TRGO (10 << ADC_CR2_EXTSEL_SHIFT) -/* reserved.... */ -#define ADC_CR2_EXTSEL_EXTI11 (15 << ADC_CR2_EXTSEL_SHIFT) -/**@}*/ - - -/* FIXME - JEXTSEL values here */ - -/* FIXME- add the values here */ -#define ADC_CR2_DELS_SHIFT 4 -#define ADC_CR2_DELS_MASK 0x7 - -#define ADC_CR2_ADC_CFG (1 << 2) - - - - -/* --- ADC_SMPRx generic values -------------------------------------------- */ -/****************************************************************************/ -/* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_4CYC 0x0 -#define ADC_SMPR_SMP_9CYC 0x1 -#define ADC_SMPR_SMP_16CYC 0x2 -#define ADC_SMPR_SMP_24CYC 0x3 -#define ADC_SMPR_SMP_48CYC 0x4 -#define ADC_SMPR_SMP_96CYC 0x5 -#define ADC_SMPR_SMP_192CYC 0x6 -#define ADC_SMPR_SMP_384CYC 0x7 -/**@}*/ - -#define ADC_SQR_MASK 0x1f -#define ADC_SQR_MAX_CHANNELS_REGULAR 28 /* m+/h only, otherwise 27 */ - -/** @defgroup adc_ccr_adcpre ADC Prescale -@ingroup adc_defines -@{*/ -#define ADC_CCR_ADCPRE_BY1 (0x0 << 16) -#define ADC_CCR_ADCPRE_BY2 (0x1 << 16) -#define ADC_CCR_ADCPRE_BY4 (0x2 << 16) -/**@}*/ -#define ADC_CCR_ADCPRE_MASK (0x3 << 16) -#define ADC_CCR_ADCPRE_SHIFT 16 - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/crc.h b/libopencm3/include/libopencm3/stm32/l1/crc.h deleted file mode 100644 index e019c34..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup crc_defines CRC Defines - -@brief libopencm3 Defined Constants and Types for the STM32L1xx CRC -Generator - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/dac.h b/libopencm3/include/libopencm3/stm32/l1/dac.h deleted file mode 100644 index 207c59d..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/dac.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32L1xx DAC - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l1/dma.h b/libopencm3/include/libopencm3/stm32/l1/dma.h deleted file mode 100644 index c1728d1..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/dma.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32L1xx_defines - * - * @brief Defined Constants and Types for the STM32L1xx DMA Controller - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2011 - * Fergus Noble - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies - * - * @date 18 October 2012 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h b/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h deleted file mode 100644 index fddc501..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32L1 - -@version 1.0.0 - -@date 12 November 2012 - -API documentation for ST Microelectronics STM32L1 Cortex M3 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32L1xx STM32L1xx -Libraries for ST Microelectronics STM32L1xx series. - -@version 1.0.0 - -@date 12 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32L1xx_defines STM32L1xx Defines - -@brief Defined Constants and Types for the STM32L1xx series - -@version 1.0.0 - -@date 12 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/l1/exti.h b/libopencm3/include/libopencm3/stm32/l1/exti.h deleted file mode 100644 index 8191576..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/exti.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @brief Defined Constants and Types for the STM32L1xx External Interrupts - * - * - * @ingroup STM32L1xx_defines - * - * @author @htmlonly © @endhtmlonly 2013 - * Piotr Esden-Tempski - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/flash.h b/libopencm3/include/libopencm3/stm32/l1/flash.h deleted file mode 100644 index a84a55b..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/flash.h +++ /dev/null @@ -1,69 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32L1xx_defines - * - * @brief Defined Constants and Types for the STM32L1xx FLASH Memory - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2012 - * Karl Palsson - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming - * manual. - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H -/**@{*/ - -#include -#include - -/* --- FLASH registers ----------------------------------------------------- */ -#define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84) - -/* --- FLASH_ACR values ---------------------------------------------------- */ -#define FLASH_ACR_ACC64 (1 << 2) - -/* --- FLASH_SR values ----------------------------------------------------- */ -#define FLASH_SR_OPTVERRUSR (1 << 12) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_64bit_enable(void); -void flash_64bit_disable(void); - -END_DECLS -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/gpio.h b/libopencm3/include/libopencm3/stm32/l1/gpio.h deleted file mode 100644 index ca0b71b..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/gpio.h +++ /dev/null @@ -1,263 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32L1xx General Purpose I/O - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 Piotr Esden-Tempski - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -/* GPIO port base addresses (for convenience) */ -/** @defgroup gpio_port_id GPIO Port IDs -@ingroup gpio_defines - -@{*/ -#define GPIOA GPIO_PORT_A_BASE -#define GPIOB GPIO_PORT_B_BASE -#define GPIOC GPIO_PORT_C_BASE -#define GPIOD GPIO_PORT_D_BASE -#define GPIOE GPIO_PORT_E_BASE -#define GPIOH GPIO_PORT_H_BASE -/**@}*/ - -/* --- GPIO registers ------------------------------------------------------ */ - -/* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32((port) + 0x00) -#define GPIOA_MODER GPIO_MODER(GPIOA) -#define GPIOB_MODER GPIO_MODER(GPIOB) -#define GPIOC_MODER GPIO_MODER(GPIOC) -#define GPIOD_MODER GPIO_MODER(GPIOD) -#define GPIOE_MODER GPIO_MODER(GPIOE) -#define GPIOH_MODER GPIO_MODER(GPIOH) - -/* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32((port) + 0x04) -#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) -#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) -#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) -#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) -#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) -#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) - -/* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) -#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) -#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) -#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) -#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) -#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) -#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) - -/* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) -#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) -#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) -#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) -#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) -#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) -#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) - -/* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32((port) + 0x10) -#define GPIOA_IDR GPIO_IDR(GPIOA) -#define GPIOB_IDR GPIO_IDR(GPIOB) -#define GPIOC_IDR GPIO_IDR(GPIOC) -#define GPIOD_IDR GPIO_IDR(GPIOD) -#define GPIOE_IDR GPIO_IDR(GPIOE) -#define GPIOH_IDR GPIO_IDR(GPIOH) - -/* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32((port) + 0x14) -#define GPIOA_ODR GPIO_ODR(GPIOA) -#define GPIOB_ODR GPIO_ODR(GPIOB) -#define GPIOC_ODR GPIO_ODR(GPIOC) -#define GPIOD_ODR GPIO_ODR(GPIOD) -#define GPIOE_ODR GPIO_ODR(GPIOE) -#define GPIOH_ODR GPIO_ODR(GPIOH) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32((port) + 0x18) -#define GPIOA_BSRR GPIO_BSRR(GPIOA) -#define GPIOB_BSRR GPIO_BSRR(GPIOB) -#define GPIOC_BSRR GPIO_BSRR(GPIOC) -#define GPIOD_BSRR GPIO_BSRR(GPIOD) -#define GPIOE_BSRR GPIO_BSRR(GPIOE) -#define GPIOH_BSRR GPIO_BSRR(GPIOH) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32((port) + 0x1C) -#define GPIOA_LCKR GPIO_LCKR(GPIOA) -#define GPIOB_LCKR GPIO_LCKR(GPIOB) -#define GPIOC_LCKR GPIO_LCKR(GPIOC) -#define GPIOD_LCKR GPIO_LCKR(GPIOD) -#define GPIOE_LCKR GPIO_LCKR(GPIOE) -#define GPIOH_LCKR GPIO_LCKR(GPIOH) - -/* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32((port) + 0x20) -#define GPIOA_AFRL GPIO_AFRL(GPIOA) -#define GPIOB_AFRL GPIO_AFRL(GPIOB) -#define GPIOC_AFRL GPIO_AFRL(GPIOC) -#define GPIOD_AFRL GPIO_AFRL(GPIOD) -#define GPIOE_AFRL GPIO_AFRL(GPIOE) -#define GPIOH_AFRL GPIO_AFRL(GPIOH) - -/* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32((port) + 0x24) -#define GPIOA_AFRH GPIO_AFRH(GPIOA) -#define GPIOB_AFRH GPIO_AFRH(GPIOB) -#define GPIOC_AFRH GPIO_AFRH(GPIOC) -#define GPIOD_AFRH GPIO_AFRH(GPIOD) -#define GPIOE_AFRH GPIO_AFRH(GPIOE) -#define GPIOH_AFRH GPIO_AFRH(GPIOH) - -/* --- GPIOx_MODER values-------------------------------------------- */ - -#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) -#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode -@ingroup gpio_defines -@{*/ -#define GPIO_MODE_INPUT 0x00 /* Default */ -#define GPIO_MODE_OUTPUT 0x01 -#define GPIO_MODE_AF 0x02 -#define GPIO_MODE_ANALOG 0x03 -/**@}*/ - -/* --- GPIOx_OTYPER values -------------------------------------------- */ -/* Output type (OTx values) */ -/** @defgroup gpio_output_type GPIO Output Pin Driver Type -@ingroup gpio_defines -@{*/ -/** Push-Pull */ -#define GPIO_OTYPE_PP 0x0 -/** Open Drain */ -#define GPIO_OTYPE_OD 0x1 -/**@}*/ - -/* Output speed values */ -#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) -#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_speed GPIO Output Pin Speed -@ingroup gpio_defines -@{*/ -#define GPIO_OSPEED_400KHZ 0x0 -#define GPIO_OSPEED_2MHZ 0x1 -#define GPIO_OSPEED_10MHZ 0x2 -#define GPIO_OSPEED_40MHZ 0x3 -/**@}*/ - -/* --- GPIOx_PUPDR values ------------------------------------------- */ - -#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) -#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) -/** @defgroup gpio_pup GPIO Output Pin Pullup -@ingroup gpio_defines -@{*/ -#define GPIO_PUPD_NONE 0x0 -#define GPIO_PUPD_PULLUP 0x1 -#define GPIO_PUPD_PULLDOWN 0x2 -/**@}*/ - -/* --- GPIO_IDR values ----------------------------------------------------- */ - -/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ - -/* --- GPIO_ODR values ----------------------------------------------------- */ - -/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ - -/* --- GPIO_BSRR values ---------------------------------------------------- */ - -/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ -/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ - -/* --- GPIO_LCKR values ---------------------------------------------------- */ - -#define GPIO_LCKK (1 << 16) -/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ - -/* --- GPIOx_AFRL/H values ------------------------------------------------- */ - -/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ -/* See datasheet table 5, page 35 for the definitions */ - -#define GPIO_AFR(n, af) ((af) << ((n) * 4)) -#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) -/** @defgroup gpio_af_num Alternate Function Pin Selection -@ingroup gpio_defines -@{*/ -#define GPIO_AF0 0x0 -#define GPIO_AF1 0x1 -#define GPIO_AF2 0x2 -#define GPIO_AF3 0x3 -#define GPIO_AF4 0x4 -#define GPIO_AF5 0x5 -#define GPIO_AF6 0x6 -#define GPIO_AF7 0x7 -#define GPIO_AF8 0x8 -#define GPIO_AF9 0x9 -#define GPIO_AF10 0xa -#define GPIO_AF11 0xb -#define GPIO_AF12 0xc -#define GPIO_AF13 0xd -#define GPIO_AF14 0xe -#define GPIO_AF15 0xf -/**@}*/ - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -/* - * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style - * however the number of ports is reduced and H port naming is different. - * TODO: this should all really be moved to a "common" gpio header - */ - -void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, - uint16_t gpios); -void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, - uint16_t gpios); -void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); - -END_DECLS - -#endif -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/l1/i2c.h b/libopencm3/include/libopencm3/stm32/l1/i2c.h deleted file mode 100644 index 04ac1c7..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/i2c.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32L1xx I2C - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l1/irq.json b/libopencm3/include/libopencm3/stm32/l1/irq.json deleted file mode 100644 index abea8db..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/irq.json +++ /dev/null @@ -1,64 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd", - "tamper_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_channel1", - "dma1_channel2", - "dma1_channel3", - "dma1_channel4", - "dma1_channel5", - "dma1_channel6", - "dma1_channel7", - "adc1", - "usb_hp", - "usb_lp", - "dac", - "comp", - "exti9_5", - "lcd", - "tim9", - "tim10", - "tim11", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "usb_fs_wakeup", - "tim6", - "tim7", - "sdio", - "tim5", - "spi3", - "uart4", - "uart5", - "dma2_ch1", - "dma2_ch2", - "dma2_ch3", - "dma2_ch4", - "dma2_ch5", - "aes", - "comp_acq" - ], - "partname_humanreadable": "STM32 L1 series", - "partname_doxygen": "STM32L1", - "includeguard": "LIBOPENCM3_STM32_L1_NVIC_H" -} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/l1/iwdg.h b/libopencm3/include/libopencm3/stm32/l1/iwdg.h deleted file mode 100644 index 699849a..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/iwdg.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - -@brief Defined Constants and Types for the STM32L1xx Independent Watchdog -Timer - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l1/lcd.h b/libopencm3/include/libopencm3/stm32/l1/lcd.h deleted file mode 100644 index 27c1246..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/lcd.h +++ /dev/null @@ -1,227 +0,0 @@ -/** @defgroup lcd_defines LCD Defines - * - * @ingroup STM32L1xx_defines - * - * @brief Defined Constants and Types for the STM32L1xx LCD Controller - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Nikolay Merinov - * - * @date 2 March 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_LCD_H -#define LIBOPENCM3_LCD_H - -#include -#include - -/** @defgroup lcd_registers LCD registers - * @{ */ -/** Control register */ -#define LCD_CR MMIO32(LCD_BASE + 0x00) -/** Frame control register */ -#define LCD_FCR MMIO32(LCD_BASE + 0x04) -/** Status register */ -#define LCD_SR MMIO32(LCD_BASE + 0x08) -/** Clear register */ -#define LCD_CLR MMIO32(LCD_BASE + 0x0C) -/**@}*/ - -/* --- LCD display memory ------------------------------------------------- */ -/* Base address of display memory */ -#define LCD_RAM_BASE (LCD_BASE + 0x14) - -/* COM0 memory */ -#define LCD_RAM_COM0 MMIO64(LCD_RAM_BASE + 0x00) -/* COM1 memory */ -#define LCD_RAM_COM1 MMIO64(LCD_RAM_BASE + 0x08) -/* COM2 memory */ -#define LCD_RAM_COM2 MMIO64(LCD_RAM_BASE + 0x10) -/* COM3 memory */ -#define LCD_RAM_COM3 MMIO64(LCD_RAM_BASE + 0x18) -/* COM4 memory */ -#define LCD_RAM_COM4 MMIO64(LCD_RAM_BASE + 0x20) -/* COM5 memory */ -#define LCD_RAM_COM5 MMIO64(LCD_RAM_BASE + 0x28) -/* COM6 memory */ -#define LCD_RAM_COM6 MMIO64(LCD_RAM_BASE + 0x30) -/* COM7 memory */ -#define LCD_RAM_COM7 MMIO64(LCD_RAM_BASE + 0x38) - -/* --- LCD_CR values ------------------------------------------------------ */ -#define LCD_CR_LCDEN (1 << 0) -#define LCD_CR_VSEL (1 << 1) - -#define LCD_CR_DUTY_SHIFT 2 -#define LCD_CR_DUTY_MASK 0x7 -#define LCD_CR_DUTY_STATIC 0x0 -#define LCD_CR_DUTY_1_2 0x1 -#define LCD_CR_DUTY_1_3 0x2 -#define LCD_CR_DUTY_1_4 0x3 -#define LCD_CR_DUTY_1_8 0x4 - -#define LCD_CR_BIAS_SHIFT 5 -#define LCD_CR_BIAS_MASK 0x3 -#define LCD_CR_BIAS_1_4 0x0 -#define LCD_CR_BIAS_1_2 0x1 -#define LCD_CR_BIAS_1_3 0x2 - -#define LCD_CR_MUX_SEG (1 << 7) - -/* --- LCD_FCR values ------------------------------------------------------ */ -#define LCD_FCR_HD (1 << 0) -#define LCD_FCR_SOFIE (1 << 1) -#define LCD_FCR_UDDIE (1 << 3) - -#define LCD_FCR_PON_SHIFT 4 -#define LCD_FCR_PON_MASK 0x7 -#define LCD_FCR_PON_0 0x0 -#define LCD_FCR_PON_1 0x1 -#define LCD_FCR_PON_2 0x2 -#define LCD_FCR_PON_3 0x3 -#define LCD_FCR_PON_4 0x4 -#define LCD_FCR_PON_5 0x5 -#define LCD_FCR_PON_6 0x6 -#define LCD_FCR_PON_7 0x7 - -#define LCD_FCR_DEAD_SHIFT 7 -#define LCD_FCR_DEAD_MASK 0x7 -#define LCD_FCR_DEAD_NONE 0x0 -#define LCD_FCR_DEAD_1_PHASE 0x1 -#define LCD_FCR_DEAD_2_PHASE 0x2 -#define LCD_FCR_DEAD_3_PHASE 0x3 -#define LCD_FCR_DEAD_4_PHASE 0x4 -#define LCD_FCR_DEAD_5_PHASE 0x5 -#define LCD_FCR_DEAD_6_PHASE 0x6 -#define LCD_FCR_DEAD_7_PHASE 0x7 - -#define LCD_FCR_CC_SHIFT 10 -#define LCD_FCR_CC_MASK 0x7 -#define LCD_FCR_CC_0 0x0 -#define LCD_FCR_CC_1 0x1 -#define LCD_FCR_CC_2 0x2 -#define LCD_FCR_CC_3 0x3 -#define LCD_FCR_CC_4 0x4 -#define LCD_FCR_CC_5 0x5 -#define LCD_FCR_CC_6 0x6 -#define LCD_FCR_CC_7 0x7 - -#define LCD_FCR_BLINKF_SHIFT 13 -#define LCD_FCR_BLINKF_MASK 0x7 -#define LCD_FCR_BLINKF_8 0x0 -#define LCD_FCR_BLINKF_16 0x1 -#define LCD_FCR_BLINKF_32 0x2 -#define LCD_FCR_BLINKF_64 0x3 -#define LCD_FCR_BLINKF_128 0x4 -#define LCD_FCR_BLINKF_256 0x5 -#define LCD_FCR_BLINKF_512 0x6 -#define LCD_FCR_BLINKF_1024 0x7 - -#define LCD_FCR_BLINK_SHIFT 16 -#define LCD_FCR_BLINK_MASK 0x3 -#define LCD_FCR_BLINK_DISABLE 0x0 -#define LCD_FCR_BLINK_SEG0_COM0_ENABLE 0x1 -#define LCD_FCR_BLINK_SEG0_ENABLE 0x2 -#define LCD_FCR_BLINK_ALL_ENABLE 0x3 - -#define LCD_FCR_DIV_SHIFT 18 -#define LCD_FCR_DIV_MASK 0xF -#define LCD_FCR_DIV_16 0x0 -#define LCD_FCR_DIV_17 0x1 -#define LCD_FCR_DIV_18 0x2 -#define LCD_FCR_DIV_19 0x3 -#define LCD_FCR_DIV_20 0x4 -#define LCD_FCR_DIV_21 0x5 -#define LCD_FCR_DIV_22 0x6 -#define LCD_FCR_DIV_23 0x7 -#define LCD_FCR_DIV_24 0x8 -#define LCD_FCR_DIV_25 0x9 -#define LCD_FCR_DIV_26 0xA -#define LCD_FCR_DIV_27 0xB -#define LCD_FCR_DIV_28 0xC -#define LCD_FCR_DIV_29 0xD -#define LCD_FCR_DIV_30 0xE -#define LCD_FCR_DIV_31 0xF - -#define LCD_FCR_PS_SHIFT 22 -#define LCD_FCR_PS_MASK 0xF -#define LCD_FCR_PS_1 0x0 -#define LCD_FCR_PS_2 0x1 -#define LCD_FCR_PS_4 0x2 -#define LCD_FCR_PS_8 0x3 -#define LCD_FCR_PS_16 0x4 -#define LCD_FCR_PS_32 0x5 -#define LCD_FCR_PS_64 0x6 -#define LCD_FCR_PS_128 0x7 -#define LCD_FCR_PS_256 0x8 -#define LCD_FCR_PS_512 0x9 -#define LCD_FCR_PS_1024 0xA -#define LCD_FCR_PS_2048 0xB -#define LCD_FCR_PS_4096 0xC -#define LCD_FCR_PS_8192 0xD -#define LCD_FCR_PS_16384 0xE -#define LCD_FCR_PS_32768 0xF - -/* --- LCD_SR values ------------------------------------------------------ */ -#define LCD_SR_ENS (1 << 0) -#define LCD_SR_SOF (1 << 1) -#define LCD_SR_UDR (1 << 2) -#define LCD_SR_UDD (1 << 3) -#define LCD_SR_RDY (1 << 4) -#define LCD_SR_FCRSF (1 << 5) - -/* --- LCD_CLR values ----------------------------------------------------- */ -#define LCD_CLR_SOFC (1 << 1) -#define LCD_CLR_UDDC (1 << 3) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void lcd_enable(void); -void lcd_update(void); - -void lcd_wait_for_lcd_enabled(void); -void lcd_wait_for_step_up_ready(void); -void lcd_wait_for_update_ready(void); - -int lcd_is_enabled(void); -int lcd_is_step_up_ready(void); -int lcd_is_for_update_ready(void); - -void lcd_set_contrast(uint8_t contrast); -void lcd_set_bias(uint8_t bias); -void lcd_set_duty(uint8_t duty); -void lcd_set_prescaler(uint8_t ps); -void lcd_set_divider(uint8_t div); -void lcd_enable_segment_multiplexing(void); -void lcd_disable_segment_multiplexing(void); -void lcd_set_refresh_frequency(uint32_t frequency); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l1/memorymap.h b/libopencm3/include/libopencm3/stm32/l1/memorymap.h deleted file mode 100644 index 88974e2..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/memorymap.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define INFO_BASE (0x1ff00000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) -/* gap */ -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c) -#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00) -#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04) - -/* APB2 */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000) -/* gap */ -#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400) -/* ADC is the name in the L1 refman, but all other stm32's use ADC1 */ -#define ADC1_BASE ADC_BASE -/* gap */ -#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -/* gap */ -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) - -/* AHB */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00) -/* gap */ -#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) -/* gap */ -#define RCC_BASE (PERIPH_BASE_AHB + 0x03800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00) -/* gap */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000) -#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* FSMC */ -#define FSMC_BASE (PERIPH_BASE + 0x60000000) -/* AES */ -#define AES_BASE (PERIPH_BASE + 0x10000000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE_CAT12 (INFO_BASE + 0x8004C) -#define DESIG_FLASH_SIZE_BASE_CAT3456 (INFO_BASE + 0x800CC) -#define DESIG_UNIQUE_ID_BASE_CAT12 (INFO_BASE + 0x80050) -#define DESIG_UNIQUE_ID_BASE_CAT3456 (INFO_BASE + 0x800D0) - -/* ST provided factory calibration values @ 3.0V */ -#define ST_VREFINT_CAL MMIO16(0x1FF80078) -#define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A) -#define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/pwr.h b/libopencm3/include/libopencm3/stm32/l1/pwr.h deleted file mode 100644 index 4a694e8..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/pwr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - -@brief Defined Constants and Types for the STM32L1xx Power Control - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2011 Stephen Caudle -@author @htmlonly © @endhtmlonly 2012 Karl Palsson - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Stephen Caudle - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include - -/* - * This file extends the common STM32 version with definitions only - * applicable to the STM32L1 series of devices. - */ - -/* --- PWR_CSR values ------------------------------------------------------- */ - -/* Bits [31:11]: Reserved */ -/* EWUP3: Enable WKUP3 pin */ -#define PWR_CSR_EWUP3 (1 << 10) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/rcc.h b/libopencm3/include/libopencm3/stm32/l1/rcc.h deleted file mode 100644 index 6540c6a..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/rcc.h +++ /dev/null @@ -1,640 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @ingroup STM32L1xx_defines - * - * @brief Defined Constants and Types for the STM32L1xx Reset and Clock - * Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2009 - * Federico Ruiz-Ugalde \ - * @author @htmlonly © @endhtmlonly 2009 - * Uwe Hermann - * @author @htmlonly © @endhtmlonly 2012 - * Karl Palsson - * - * @date 11 November 2012 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * Copyright (C) 2012 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - * Originally based on the F1 code, as it seemed most similar to the L1 - * TODO: very incomplete still! - */ - -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_CIR MMIO32(RCC_BASE + 0x0c) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28) -#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c) -#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30) -#define RCC_CSR MMIO32(RCC_BASE + 0x34) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_RTCPRE_SHIFT 29 -#define RCC_CR_RTCPRE_MASK 0x3 -#define RCC_CR_CSSON (1 << 28) -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_MSIRDY (1 << 9) -#define RCC_CR_MSION (1 << 8) -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -#define RCC_CR_RTCPRE_DIV2 0 -#define RCC_CR_RTCPRE_DIV4 1 -#define RCC_CR_RTCPRE_DIV8 2 -#define RCC_CR_RTCPRE_DIV16 3 -#define RCC_CR_RTCPRE_SHIFT 29 -#define RCC_CR_RTCPRE_MASK 0x3 - -/** @defgroup rcc_icscr_defines RCC_ICSCR definitions - * @brief Internal clock sources calibration register - * @ingroup rcc_defines - *@{*/ -#define RCC_ICSCR_MSITRIM_SHIFT 24 -#define RCC_ICSCR_MSITRIM_MASK 0xff -#define RCC_ICSCR_MSICAL_SHIFT 16 -#define RCC_ICSCR_MSICAL_MASK 0xff - -#define RCC_ICSCR_MSIRANGE_SHIFT 13 -#define RCC_ICSCR_MSIRANGE_MASK 0x7 -/** @defgroup rcc_icscr_msirange MSI Ranges - * @ingroup rcc_icscr_defines - *@{*/ -#define RCC_ICSCR_MSIRANGE_65KHZ 0x0 -#define RCC_ICSCR_MSIRANGE_131KHZ 0x1 -#define RCC_ICSCR_MSIRANGE_262KHZ 0x2 -#define RCC_ICSCR_MSIRANGE_524KHZ 0x3 -#define RCC_ICSCR_MSIRANGE_1MHZ 0x4 -#define RCC_ICSCR_MSIRANGE_2MHZ 0x5 -#define RCC_ICSCR_MSIRANGE_4MHZ 0x6 -/**@}*/ -#define RCC_ICSCR_HSITRIM_SHIFT 8 -#define RCC_ICSCR_HSITRIM_MASK 0x1f -#define RCC_ICSCR_HSICAL_SHIFT 0 -#define RCC_ICSCR_HSICAL_MASK 0xff -/**@}*/ - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCOPRE */ -#define RCC_CFGR_MCOPRE_DIV1 0 -#define RCC_CFGR_MCOPRE_DIV2 1 -#define RCC_CFGR_MCOPRE_DIV4 2 -#define RCC_CFGR_MCOPRE_DIV8 3 -#define RCC_CFGR_MCOPRE_DIV16 4 -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE_MASK 0x7 - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x1 -#define RCC_CFGR_MCO_HSI 0x2 -#define RCC_CFGR_MCO_MSI 0x3 -#define RCC_CFGR_MCO_HSE 0x4 -#define RCC_CFGR_MCO_PLL 0x5 -#define RCC_CFGR_MCO_LSI 0x6 -#define RCC_CFGR_MCO_LSE 0x7 -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0x7 - -/* PLL Output division selection */ -#define RCC_CFGR_PLLDIV_DIV2 0x1 -#define RCC_CFGR_PLLDIV_DIV3 0x2 -#define RCC_CFGR_PLLDIV_DIV4 0x3 -#define RCC_CFGR_PLLDIV_SHIFT 22 -#define RCC_CFGR_PLLDIV_MASK 0x3 - -/* PLLMUL: PLL multiplication factor */ -#define RCC_CFGR_PLLMUL_MUL3 0x0 -#define RCC_CFGR_PLLMUL_MUL4 0x1 -#define RCC_CFGR_PLLMUL_MUL6 0x2 -#define RCC_CFGR_PLLMUL_MUL8 0x3 -#define RCC_CFGR_PLLMUL_MUL12 0x4 -#define RCC_CFGR_PLLMUL_MUL16 0x5 -#define RCC_CFGR_PLLMUL_MUL24 0x6 -#define RCC_CFGR_PLLMUL_MUL32 0x7 -#define RCC_CFGR_PLLMUL_MUL48 0x8 -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLMUL_MASK 0xf - -/* PLLSRC: PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI_CLK 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 - -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE2_SHIFT 11 - -/* PPRE1: APB low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 8 - -/* HPRE: AHB prescaler */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_SHIFT 4 - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0 -#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1 -#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2 -#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_SHIFT 2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0 -#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1 -#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2 -#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3 -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_SHIFT 0 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_MSIRDYC (1 << 21) -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_MSIRDYIE (1 << 13) -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */ -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values values -@{*/ -#define RCC_AHBRSTR_DMA1RST (1 << 24) -#define RCC_AHBRSTR_FLITFRST (1 << 15) -#define RCC_AHBRSTR_CRCRST (1 << 12) -#define RCC_AHBRSTR_GPIOHRST (1 << 5) -#define RCC_AHBRSTR_GPIOERST (1 << 4) -#define RCC_AHBRSTR_GPIODRST (1 << 3) -#define RCC_AHBRSTR_GPIOCRST (1 << 2) -#define RCC_AHBRSTR_GPIOBRST (1 << 1) -#define RCC_AHBRSTR_GPIOARST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values values -@{*/ -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_ADC1RST (1 << 9) -#define RCC_APB2RSTR_TIM11RST (1 << 4) -#define RCC_APB2RSTR_TIM10RST (1 << 3) -#define RCC_APB2RSTR_TIM9RST (1 << 2) -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values values -@{*/ -#define RCC_APB1RSTR_COMPRST (1 << 31) -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_USBRST (1 << 23) -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_LCDRST (1 << 9) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) -/**@}*/ - -/* --- RCC_AHBENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@ingroup STM32L1xx_rcc_defines - -@{*/ -#define RCC_AHBENR_DMA1EN (1 << 24) -#define RCC_AHBENR_FLITFEN (1 << 15) -#define RCC_AHBENR_CRCEN (1 << 12) -#define RCC_AHBENR_GPIOHEN (1 << 5) -#define RCC_AHBENR_GPIOEEN (1 << 4) -#define RCC_AHBENR_GPIODEN (1 << 3) -#define RCC_AHBENR_GPIOCEN (1 << 2) -#define RCC_AHBENR_GPIOBEN (1 << 1) -#define RCC_AHBENR_GPIOAEN (1 << 0) -/*@}*/ - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@ingroup STM32L1xx_rcc_defines - -@{*/ -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_TIM11EN (1 << 4) -#define RCC_APB2ENR_TIM10EN (1 << 3) -#define RCC_APB2ENR_TIM9EN (1 << 2) -#define RCC_APB2ENR_SYSCFGEN (1 << 0) -/*@}*/ - -/* --- RCC_APB1ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@ingroup STM32L1xx_rcc_defines - -@{*/ -#define RCC_APB1ENR_COMPEN (1 << 31) -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_USBEN (1 << 23) -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_LCDEN (1 << 9) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) -/*@}*/ - -/* --- RCC_AHBLPENR -------------------------------------------------------- */ -#define RCC_AHBLPENR_DMA1LPEN (1 << 24) -#define RCC_AHBLPENR_SRAMLPEN (1 << 16) -#define RCC_AHBLPENR_FLITFLPEN (1 << 15) -#define RCC_AHBLPENR_CRCLPEN (1 << 12) -#define RCC_AHBLPENR_GPIOHLPEN (1 << 5) -#define RCC_AHBLPENR_GPIOELPEN (1 << 4) -#define RCC_AHBLPENR_GPIODLPEN (1 << 3) -#define RCC_AHBLPENR_GPIOCLPEN (1 << 2) -#define RCC_AHBLPENR_GPIOBLPEN (1 << 1) -#define RCC_AHBLPENR_GPIOALPEN (1 << 0) - -#define RCC_APB2LPENR_USART1LPEN (1 << 14) -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) -#define RCC_APB2LPENR_ADC1LPEN (1 << 9) -#define RCC_APB2LPENR_TIM11LPEN (1 << 4) -#define RCC_APB2LPENR_TIM10LPEN (1 << 3) -#define RCC_APB2LPENR_TIM9LPEN (1 << 2) -#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0) - -#define RCC_APB1LPENR_COMPLPEN (1 << 31) -#define RCC_APB1LPENR_DACLPEN (1 << 29) -#define RCC_APB1LPENR_PWRLPEN (1 << 28) -#define RCC_APB1LPENR_USBLPEN (1 << 23) -#define RCC_APB1LPENR_I2C2LPEN (1 << 22) -#define RCC_APB1LPENR_I2C1LPEN (1 << 21) -#define RCC_APB1LPENR_USART3LPEN (1 << 18) -#define RCC_APB1LPENR_USART2LPEN (1 << 17) -#define RCC_APB1LPENR_SPI2LPEN (1 << 14) -#define RCC_APB1LPENR_WWDGLPEN (1 << 11) -#define RCC_APB1LPENR_LCDLPEN (1 << 9) -#define RCC_APB1LPENR_TIM7LPEN (1 << 5) -#define RCC_APB1LPENR_TIM6LPEN (1 << 4) -#define RCC_APB1LPENR_TIM4LPEN (1 << 2) -#define RCC_APB1LPENR_TIM3LPEN (1 << 1) -#define RCC_APB1LPENR_TIM2LPEN (1 << 0) - - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF) -#define RCC_CSR_RTCRST (1 << 23) -#define RCC_CSR_RTCEN (1 << 22) -#define RCC_CSR_RTCSEL_SHIFT (16) -#define RCC_CSR_RTCSEL_MASK (0x3) -#define RCC_CSR_RTCSEL_NONE (0x0) -#define RCC_CSR_RTCSEL_LSE (0x1) -#define RCC_CSR_RTCSEL_LSI (0x2) -#define RCC_CSR_RTCSEL_HSI (0x3) -#define RCC_CSR_LSECSSD (1 << 12) -#define RCC_CSR_LSECSSON (1 << 11) -#define RCC_CSR_LSEBYP (1 << 10) -#define RCC_CSR_LSERDY (1 << 9) -#define RCC_CSR_LSEON (1 << 8) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -struct rcc_clock_scale { - uint8_t pll_mul; - uint16_t pll_div; - uint8_t pll_source; - uint8_t flash_waitstates; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - enum pwr_vos_scale voltage_scale; - uint32_t ahb_frequency; - uint32_t apb1_frequency; - uint32_t apb2_frequency; - uint8_t msi_range; -}; - -enum rcc_clock_config_entry { - RCC_CLOCK_VRANGE1_HSI_PLL_24MHZ, - RCC_CLOCK_VRANGE1_HSI_PLL_32MHZ, - RCC_CLOCK_VRANGE1_HSI_RAW_16MHZ, - RCC_CLOCK_VRANGE1_HSI_RAW_4MHZ, - RCC_CLOCK_VRANGE1_MSI_RAW_4MHZ, - RCC_CLOCK_VRANGE1_MSI_RAW_2MHZ, - RCC_CLOCK_CONFIG_END -}; - -extern const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END]; - - -/* --- Variable definitions ------------------------------------------------ */ -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI, RCC_MSI, RCC_LSE, RCC_LSI -}; - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - /* AHB peripherals */ - RCC_GPIOA = _REG_BIT(0x1c, 0), - RCC_GPIOB = _REG_BIT(0x1c, 1), - RCC_GPIOC = _REG_BIT(0x1c, 2), - RCC_GPIOD = _REG_BIT(0x1c, 3), - RCC_GPIOE = _REG_BIT(0x1c, 4), - RCC_GPIOH = _REG_BIT(0x1c, 5), - RCC_GPIOF = _REG_BIT(0x1c, 6), - RCC_GPIOG = _REG_BIT(0x1c, 7), - RCC_CRC = _REG_BIT(0x1c, 12), - RCC_FLITF = _REG_BIT(0x1c, 15), - RCC_DMA1 = _REG_BIT(0x1c, 24), - RCC_DMA2 = _REG_BIT(0x1c, 25), - RCC_AES = _REG_BIT(0x1c, 27), - RCC_FSMC = _REG_BIT(0x1c, 30), - - /* APB2 peripherals */ - RCC_SYSCFG = _REG_BIT(0x20, 0), - RCC_TIM9 = _REG_BIT(0x20, 2), - RCC_TIM10 = _REG_BIT(0x20, 3), - RCC_TIM11 = _REG_BIT(0x20, 4), - RCC_ADC1 = _REG_BIT(0x20, 9), - RCC_SDIO = _REG_BIT(0x20, 11), - RCC_SPI1 = _REG_BIT(0x20, 12), - RCC_USART1 = _REG_BIT(0x20, 14), - - /* APB1 peripherals*/ - RCC_TIM2 = _REG_BIT(0x24, 0), - RCC_TIM3 = _REG_BIT(0x24, 1), - RCC_TIM4 = _REG_BIT(0x24, 2), - RCC_TIM5 = _REG_BIT(0x24, 3), - RCC_TIM6 = _REG_BIT(0x24, 4), - RCC_TIM7 = _REG_BIT(0x24, 5), - RCC_LCD = _REG_BIT(0x24, 9), - RCC_WWDG = _REG_BIT(0x24, 11), - RCC_SPI2 = _REG_BIT(0x24, 14), - RCC_SPI3 = _REG_BIT(0x24, 15), - RCC_USART2 = _REG_BIT(0x24, 17), - RCC_USART3 = _REG_BIT(0x24, 18), - RCC_UART4 = _REG_BIT(0x24, 19), - RCC_UART5 = _REG_BIT(0x24, 20), - RCC_I2C1 = _REG_BIT(0x24, 21), - RCC_I2C2 = _REG_BIT(0x24, 22), - RCC_USB = _REG_BIT(0x24, 23), - RCC_PWR = _REG_BIT(0x24, 28), - RCC_DAC = _REG_BIT(0x24, 29), - RCC_COMP = _REG_BIT(0x24, 31), - - /* AHB peripherals */ - SCC_GPIOA = _REG_BIT(0x28, 0), - SCC_GPIOB = _REG_BIT(0x28, 1), - SCC_GPIOC = _REG_BIT(0x28, 2), - SCC_GPIOD = _REG_BIT(0x28, 3), - SCC_GPIOE = _REG_BIT(0x28, 4), - SCC_GPIOH = _REG_BIT(0x28, 5), - SCC_GPIOF = _REG_BIT(0x28, 6), - SCC_GPIOG = _REG_BIT(0x28, 7), - SCC_CRC = _REG_BIT(0x28, 12), - SCC_FLITF = _REG_BIT(0x28, 15), - SCC_SRAM = _REG_BIT(0x28, 16), - SCC_DMA1 = _REG_BIT(0x28, 24), - SCC_DMA2 = _REG_BIT(0x28, 25), - SCC_AES = _REG_BIT(0x28, 27), - SCC_FSMC = _REG_BIT(0x28, 30), - - /* APB2 peripherals */ - SCC_SYSCFG = _REG_BIT(0x2c, 0), - SCC_TIM9 = _REG_BIT(0x2c, 2), - SCC_TIM10 = _REG_BIT(0x2c, 3), - SCC_TIM11 = _REG_BIT(0x2c, 4), - SCC_ADC1 = _REG_BIT(0x2c, 9), - SCC_SDIO = _REG_BIT(0x2c, 11), - SCC_SPI1 = _REG_BIT(0x2c, 12), - SCC_USART1 = _REG_BIT(0x2c, 14), - - /* APB1 peripherals*/ - SCC_TIM2 = _REG_BIT(0x24, 0), - SCC_TIM3 = _REG_BIT(0x24, 1), - SCC_TIM4 = _REG_BIT(0x24, 2), - SCC_TIM5 = _REG_BIT(0x24, 3), - SCC_TIM6 = _REG_BIT(0x24, 4), - SCC_TIM7 = _REG_BIT(0x24, 5), - SCC_LCD = _REG_BIT(0x24, 9), - SCC_WWDG = _REG_BIT(0x24, 11), - SCC_SPI2 = _REG_BIT(0x24, 14), - SCC_SPI3 = _REG_BIT(0x24, 15), - SCC_USART2 = _REG_BIT(0x24, 17), - SCC_USART3 = _REG_BIT(0x24, 18), - SCC_UART4 = _REG_BIT(0x24, 19), - SCC_UART5 = _REG_BIT(0x24, 20), - SCC_I2C1 = _REG_BIT(0x24, 21), - SCC_I2C2 = _REG_BIT(0x24, 22), - SCC_USB = _REG_BIT(0x24, 23), - SCC_PWR = _REG_BIT(0x24, 28), - SCC_DAC = _REG_BIT(0x24, 29), - SCC_COMP = _REG_BIT(0x24, 31), -}; - -enum rcc_periph_rst { - /* AHB peripherals */ - RST_GPIOA = _REG_BIT(0x10, 0), - RST_GPIOB = _REG_BIT(0x10, 1), - RST_GPIOC = _REG_BIT(0x10, 2), - RST_GPIOD = _REG_BIT(0x10, 3), - RST_GPIOE = _REG_BIT(0x10, 4), - RST_GPIOH = _REG_BIT(0x10, 5), - RST_GPIOF = _REG_BIT(0x10, 6), - RST_GPIOG = _REG_BIT(0x10, 7), - RST_CRC = _REG_BIT(0x10, 12), - RST_FLITF = _REG_BIT(0x10, 15), - RST_DMA1 = _REG_BIT(0x10, 24), - RST_DMA2 = _REG_BIT(0x10, 25), - RST_AES = _REG_BIT(0x10, 27), - RST_FSMC = _REG_BIT(0x10, 30), - - /* APB2 peripherals */ - RST_SYSCFG = _REG_BIT(0x14, 0), - RST_TIM9 = _REG_BIT(0x14, 2), - RST_TIM10 = _REG_BIT(0x14, 3), - RST_TIM11 = _REG_BIT(0x14, 4), - RST_ADC1 = _REG_BIT(0x14, 9), - RST_SDIO = _REG_BIT(0x14, 11), - RST_SPI1 = _REG_BIT(0x14, 12), - RST_USART1 = _REG_BIT(0x14, 14), - - /* APB1 peripherals*/ - RST_TIM2 = _REG_BIT(0x18, 0), - RST_TIM3 = _REG_BIT(0x18, 1), - RST_TIM4 = _REG_BIT(0x18, 2), - RST_TIM5 = _REG_BIT(0x18, 3), - RST_TIM6 = _REG_BIT(0x18, 4), - RST_TIM7 = _REG_BIT(0x18, 5), - RST_LCD = _REG_BIT(0x18, 9), - RST_WWDG = _REG_BIT(0x18, 11), - RST_SPI2 = _REG_BIT(0x18, 14), - RST_SPI3 = _REG_BIT(0x18, 15), - RST_USART2 = _REG_BIT(0x18, 17), - RST_USART3 = _REG_BIT(0x18, 18), - RST_UART4 = _REG_BIT(0x18, 19), - RST_UART5 = _REG_BIT(0x18, 20), - RST_I2C1 = _REG_BIT(0x18, 21), - RST_I2C2 = _REG_BIT(0x18, 22), - RST_USB = _REG_BIT(0x18, 23), - RST_PWR = _REG_BIT(0x18, 28), - RST_DAC = _REG_BIT(0x18, 29), - RST_COMP = _REG_BIT(0x18, 31), -}; -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_msi_range(uint32_t range); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, - uint32_t divisor); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_adcpre(uint32_t adcpre); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_usbpre(uint32_t usbpre); -void rcc_set_rtcpre(uint32_t rtcpre); -uint32_t rcc_system_clock_source(void); -void rcc_rtc_select_clock(uint32_t clock); -void rcc_clock_setup_msi(const struct rcc_clock_scale *clock); -void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock); -void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); -void rcc_backupdomain_reset(void); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/ri.h b/libopencm3/include/libopencm3/stm32/l1/ri.h deleted file mode 100644 index 7d1b1bc..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/ri.h +++ /dev/null @@ -1,386 +0,0 @@ -/** @defgroup ri_defines Routing Interface registers - * - * @brief Register definitions for the STM32L1xx Routing Interface - * - * @ingroup STM32L1xx - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Marek Koza - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - * Based on the RM0038 Reference manual - * (STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM®-based - * 32-bit MCUs) - */ -/**@{*/ - -/* - * There is a mismatch in the RM0038 in the RI register offset addresses (they - * are relative to the COMP base address instead of the RI base address for an - * unknown reason). We are subtracting 4 in order to use them with ROUTING_BASE. - */ -#define RI_BASE ROUTING_BASE - 0x04 - -#define RI_ICR MMIO32(RI_BASE + 0x04) -#define RI_ASCR1 MMIO32(RI_BASE + 0x08) -#define RI_ASCR2 MMIO32(RI_BASE + 0x0c) -#define RI_HYSCR1 MMIO32(RI_BASE + 0x10) -#define RI_HYSCR2 MMIO32(RI_BASE + 0x14) -#define RI_HYSCR3 MMIO32(RI_BASE + 0x18) -#define RI_HYSCR4 MMIO32(RI_BASE + 0x1c) -#define RI_ASMR1 MMIO32(RI_BASE + 0x20) -#define RI_CMR1 MMIO32(RI_BASE + 0x24) -#define RI_CICR1 MMIO32(RI_BASE + 0x28) -#define RI_ASMR2 MMIO32(RI_BASE + 0x2c) -#define RI_CMR2 MMIO32(RI_BASE + 0x30) -#define RI_CICR2 MMIO32(RI_BASE + 0x34) -#define RI_ASMR3 MMIO32(RI_BASE + 0x38) -#define RI_CMR3 MMIO32(RI_BASE + 0x3c) -#define RI_CICR3 MMIO32(RI_BASE + 0x40) -#define RI_ASMR4 MMIO32(RI_BASE + 0x44) -#define RI_CMR4 MMIO32(RI_BASE + 0x48) -#define RI_CICR4 MMIO32(RI_BASE + 0x4c) -#define RI_ASMR5 MMIO32(RI_BASE + 0x50) -#define RI_CMR5 MMIO32(RI_BASE + 0x54) -#define RI_CICR5 MMIO32(RI_BASE + 0x58) - -/** - * RI input capture register - * - * The RI_ICR register is used to select the routing of 4 full ports to the - * input captures of TIM2, TIM3 and TIM4. - */ -#define RI_ICR_IC1IOS_SHIFT 0 -#define RI_ICR_IC1IOS_MASK 0xf -#define RI_ICR_IC2IOS_SHIFT 4 -#define RI_ICR_IC2IOS_MASK 0xf -#define RI_ICR_IC3IOS_SHIFT 8 -#define RI_ICR_IC3IOS_MASK 0xf -#define RI_ICR_IC4IOS_SHIFT 12 -#define RI_ICR_IC4IOS_MASK 0xf -#define RI_ICR_TIM_SHIFT 16 -#define RI_ICR_TIM_MASK 0x3 -#define RI_ICR_IC1 (1 << 18) -#define RI_ICR_IC2 (1 << 19) -#define RI_ICR_IC3 (1 << 20) -#define RI_ICR_IC4 (1 << 21) -/* bits 22-31 reserved */ - -/** - * RI analog switches control register 1 - * - * The RI_ASCR1 register is used to configure the analog switches of the I/Os - * linked to the ADC. These I/Os are pointed to by the ADC channel number. - */ -#define RI_ASCR1_CH0_GR1_1 (1 << 0) -#define RI_ASCR1_CH1_GR1_2 (1 << 1) -#define RI_ASCR1_CH2_GR1_3 (1 << 2) -#define RI_ASCR1_CH3_GR1_4 (1 << 3) -#define RI_ASCR1_CH4 (1 << 4) -#define RI_ASCR1_CH5 (1 << 5) -#define RI_ASCR1_CH6_GR2_1 (1 << 6) -#define RI_ASCR1_CH7_GR2_2 (1 << 7) -#define RI_ASCR1_CH8_GR3_1 (1 << 8) -#define RI_ASCR1_CH9_GR3_2 (1 << 9) -#define RI_ASCR1_CH10_GR8_1 (1 << 10) -#define RI_ASCR1_CH11_GR8_2 (1 << 11) -#define RI_ASCR1_CH12_GR8_3 (1 << 12) -#define RI_ASCR1_CH13_GR8_4 (1 << 13) -#define RI_ASCR1_CH14_GR9_1 (1 << 14) -#define RI_ASCR1_CH15_GR9_2 (1 << 15) -#define RI_ASCR1_CH31_GR11_5 (1 << 16) -/* bit 17 reserved */ -#define RI_ASCR1_CH18_GR7_1 (1 << 18) -#define RI_ASCR1_CH19_GR7_2 (1 << 19) -#define RI_ASCR1_CH20_GR7_3 (1 << 20) -#define RI_ASCR1_CH21_GR7_4 (1 << 21) -#define RI_ASCR1_CH22 (1 << 22) -#define RI_ASCR1_CH23 (1 << 23) -#define RI_ASCR1_CH24 (1 << 24) -#define RI_ASCR1_CH25 (1 << 25) -#define RI_ASCR1_VCOMP (1 << 26) -#define RI_ASCR1_CH27_GR11_1 (1 << 27) -#define RI_ASCR1_CH28_GR11_2 (1 << 28) -#define RI_ASCR1_CH29_GR11_3 (1 << 29) -#define RI_ASCR1_CH30_GR11_4 (1 << 30) -#define RI_ASCR1_SCM (1 << 31) - -/** - * RI analog switches control register 2 - * - * The RI_ASCR2 register is used to configure the analog switches of groups of - * I/Os not linked to the ADC. In this way, predefined groups of I/Os can be - * connected together. - */ -#define RI_ASCR2_GR10_1 (1 << 0) -#define RI_ASCR2_GR10_2 (1 << 1) -#define RI_ASCR2_GR10_3 (1 << 2) -#define RI_ASCR2_GR10_4 (1 << 3) -#define RI_ASCR2_GR6_1 (1 << 4) -#define RI_ASCR2_GR6_2 (1 << 5) -#define RI_ASCR2_GR5_1 (1 << 6) -#define RI_ASCR2_GR5_2 (1 << 7) -#define RI_ASCR2_GR5_3 (1 << 8) -#define RI_ASCR2_GR4_1 (1 << 9) -#define RI_ASCR2_GR4_2 (1 << 10) -#define RI_ASCR2_GR4_3 (1 << 11) -/* bits 12-15 reserved */ -#define RI_ASCR2_CH0B_GR3_3 (1 << 16) -#define RI_ASCR2_CH1B_GR3_4 (1 << 17) -#define RI_ASCR2_CH2B_GR3_5 (1 << 18) -#define RI_ASCR2_CH3B_GR9_3 (1 << 19) -#define RI_ASCR2_CH6B_GR9_4 (1 << 20) -#define RI_ASCR2_CH7B_GR2_3 (1 << 21) -#define RI_ASCR2_CH8B_GR2_4 (1 << 22) -#define RI_ASCR2_CH9B_GR2_5 (1 << 23) -#define RI_ASCR2_CH10B_GR7_5 (1 << 24) -#define RI_ASCR2_CH11B_GR7_6 (1 << 25) -#define RI_ASCR2_CH12B_GR7_7 (1 << 26) -#define RI_ASCR2_GR6_3 (1 << 27) -#define RI_ASCR2_GR6_4 (1 << 28) -/* bits 29-31 reserved */ - -/** - * RI hysteresis control register 1 - * - * The RI_HYSCR1 register is used to enable/disable the hysteresis of the input - * Schmitt trigger of ports A and B. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_HYSCR1_PA(x) (x) -#define RI_HYSCR1_PB(x) (x << 16) - -/** - * RI hysteresis control register 2 - * - * RI_HYSCR2 register allows to enable/disable hysteresis of input Schmitt - * trigger of ports C and D. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_HYSCR2_PC(x) (x) -#define RI_HYSCR2_PD(x) (x << 16) - -/** - * RI hysteresis control register 3 - * - * The RI_HYSCR3 register is used to enable/disable the hysteresis of the input - * Schmitt trigger of the entire port E and F. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_HYSCR3_PE(x) (x) -#define RI_HYSCR3_PF(x) (x << 16) - -/** - * RI hysteresis control register 4 - * - * The RI_HYSCR4 register is used to enable/disable the hysteresis of the input - * Schmitt trigger of the entire port G. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_HYSCR2_PG(x) (x) -/* bits 16-31 reserved */ - -/** - * Analog switch mode register (RI_ASMR1) - * - * The RI_ASMR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used to select if analog switches of port A are to be controlled - * by the timer OC or through the ADC interface or RI_ASCRx registers. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_ASMR1_PA(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel mask register (RI_CMR1) - * - * RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is - * used to mask a port A channel designated as a timer input capture (after - * acquisition completion to avoid triggering multiple detections). - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CMR1_PA(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel identification for capture register (RI_CICR1) - * - * The RI_CICR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used when analog switches are controlled by a timer OC. RI_CICR1 - * allows a channel to be identified for timer input capture. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CICR1_PA(x) (x) -/* bits 16-31 reserved */ - -/** - * Analog switch mode register (RI_ASMR2) - * - * The RI_ASMR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used to select if analog switches of port B are to be controlled - * by the timer OC or through the ADC interface or RI_ASCRx registers. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_ASMR2_PB(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel mask register (RI_CMR2) - * - * RI_CMR2 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is - * used to mask a port B channel designated as a timer input capture (after - * acquisition completion to avoid triggering multiple detections). - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CMR2_PB(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel identification for capture register (RI_CICR2) - * - * The RI_CICR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used when analog switches are controlled by a timer OC. RI_CICR2 - * allows a channel to be identified for timer input capture. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CICR2_PB(x) (x) -/* bits 16-31 reserved */ - -/** - * Analog switch mode register (RI_ASMR3) - * - * The RI_ASMR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used to select if analog switches of port C are to be controlled - * by the timer OC or through the ADC interface or RI_ASCRx registers. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_ASMR3_PC(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel mask register (RI_CMR3) - * - * RI_CMR3 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is - * used to mask a port C channel designated as a timer input capture (after - * acquisition completion to avoid triggering multiple detections). - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CMR3_PC(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel identification for capture register (RI_CICR3) - * - * The RI_CICR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used when analog switches are controlled by a timer OC. RI_CICR3 - * allows a channel to be identified for timer input capture. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CICR3_PC(x) (x) -/* bits 16-31 reserved */ - -/** - * Analog switch mode register (RI_ASMR4) - * - * The RI_ASMR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used to select if analog switches of port F are to be controlled - * by the timer OC or through the ADC interface or RI_ASCRx registers. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_ASMR4_PF(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel mask register (RI_CMRF) - * - * RI_CMR4 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is - * used to mask a port F channel designated as a timer input capture (after - * acquisition completion to avoid triggering multiple detections). - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CMR4_PF(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel identification for capture register (RI_CICR4) - * - * The RI_CICR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used when analog switches are controlled by a timer OC. RI_CICR4 - * allows a channel to be identified for timer input capture. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CICR4_PF(x) (x) -/* bits 16-31 reserved */ - -/** - * Analog switch mode register (RI_ASMR5) - * - * The RI_ASMR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used to select if analog switches of port G are to be controlled - * by the timer OC or through the ADC interface or RI_ASCRx registers. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_ASMR5_PG(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel mask register (RI_CMR5) - * - * RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is - * used to mask a port G channel designated as a timer input capture (after - * acquisition completion to avoid triggering multiple detections). - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CMR5_PG(x) (x) -/* bits 16-31 reserved */ - -/** - * Channel identification for capture register (RI_CICR5) - * - * The RI_CICR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices - * only and is used when analog switches are controlled by a timer OC. RI_CICR5 - * allows a channel to be identified for timer input capture. - * - * GPIO0-GPIO15 defines should be used as parameters. - */ -#define RI_CICR5_PG(x) (x) -/* bits 16-31 reserved */ - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/stm32/l1/rtc.h b/libopencm3/include/libopencm3/stm32/l1/rtc.h deleted file mode 100644 index 3ba885c..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - -@brief Defined Constants and Types for the STM32L1xx RTC - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/spi.h b/libopencm3/include/libopencm3/stm32/l1/spi.h deleted file mode 100644 index 6e8dd31..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/spi.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32L1xx SPI - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l1/st_usbfs.h b/libopencm3/include/libopencm3/stm32/l1/st_usbfs.h deleted file mode 100644 index 7da73f2..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/syscfg.h b/libopencm3/include/libopencm3/stm32/l1/syscfg.h deleted file mode 100644 index d8ce0ae..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/syscfg.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32L1xx_defines - * - * @brief Defined Constants and Types for the STM32L1xx Sysconfig - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 - * Frantisek Burian - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H - -#include - -/** Enable internal USB pullup iff USB periph is not powered down */ -#define SYSCFG_PMC_USB_PU (1<<0) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/timer.h b/libopencm3/include/libopencm3/stm32/l1/timer.h deleted file mode 100644 index faef434..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/timer.h +++ /dev/null @@ -1,88 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32L1xx Timers - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 8 March 2013 - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -/**@{*/ - -/* - * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: - * CNT, ARR, CCR1, CCR2, CCR3, CCR4 - */ - -/* Timer 2/3 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) -#define TIM2_OR TIM_OR(TIM2) -#define TIM3_OR TIM_OR(TIM3) - -/* --- TIMx_OR values ---------------------------------------------------- */ - -/* ITR1_RMP */ -/****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Internal Trigger 1 Remap -@{*/ -/** Internal Trigger 1 remapped to timer 10 output compare */ -#define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) -/** Internal Trigger 1 remapped to timer 5 TGO */ -#define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0) -/**@}*/ -#define TIM2_OR_ITR1_RMP_MASK (0x1 << 0) - -/* --- TIMx_OR values ---------------------------------------------------- */ - -/* ITR2_RMP */ -/****************************************************************************/ -/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Internal Trigger 2 Remap -@{*/ -/** Internal Trigger 1 remapped to timer 11 output compare */ -#define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) -/** Internal Trigger 1 remapped to timer 5 TGO */ -#define TIM3_OR_ITR2_RMP_PTP (0x1 << 0) -/**@}*/ -#define TIM3_OR_ITR2_RMP_MASK (0x1 << 0) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void timer_set_option(uint32_t timer_peripheral, uint32_t option); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/usart.h b/libopencm3/include/libopencm3/stm32/l1/usart.h deleted file mode 100644 index 6fdce0e..0000000 --- a/libopencm3/include/libopencm3/stm32/l1/usart.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup usart_defines USART Defines - -@brief Defined Constants and Types for the STM32L1xx USART - -@ingroup STM32L1xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l4/adc.h b/libopencm3/include/libopencm3/stm32/l4/adc.h deleted file mode 100644 index e01852f..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/adc.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @defgroup adc_defines ADC Defines - * - * @brief Defined Constants and Types for the STM32L4xx Analog to Digital - * Converter - * - * @ingroup STM32L4xx_defines - * - * @version 1.0.0 - * - * @date 24 Oct 2015 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/** @defgroup adc_reg_base ADC register base addresses - * @ingroup adc_defines - * - *@{*/ -#define ADC1 ADC1_BASE -#define ADC2 ADC2_BASE -#define ADC3 ADC3_BASE -/**@}*/ - -/** @defgroup adc_channel ADC Channel Numbers - * @ingroup adc_defines - * - *@{*/ -#define ADC_CHANNEL_VREF 0 -#define ADC_CHANNEL_TEMP 17 -#define ADC_CHANNEL_VBAT 18 -/**@}*/ - -/* ADC_CR Values ------------------------------------------------------------*/ - -/* DEEPPWD: Deep power down */ -#define ADC_CR_DEEPPWD (1 << 29) - -/* ADVREGEN: Voltage regulator enable bit */ -#define ADC_CR_ADVREGEN (1 << 28) - - -/****************************************************************************/ -/* ADC_SMPRx ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample ADC Sample Time Selection values -@ingroup adc_defines - -@{*/ -#define ADC_SMPR_SMP_2DOT5CYC 0x0 -#define ADC_SMPR_SMP_6DOT5CYC 0x1 -#define ADC_SMPR_SMP_12DOT5CYC 0x2 -#define ADC_SMPR_SMP_24DOT5CYC 0x3 -#define ADC_SMPR_SMP_47DOT5CYC 0x4 -#define ADC_SMPR_SMP_92DOT5CYC 0x5 -#define ADC_SMPR_SMP_247DOT5CYC 0x6 -#define ADC_SMPR_SMP_640DOT5CYC 0x7 -/**@}*/ - - -BEGIN_DECLS - - -END_DECLS - - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/crc.h b/libopencm3/include/libopencm3/stm32/l4/crc.h deleted file mode 100644 index 63c7b95..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/crc.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup crc_defines CRC Defines - * - * @brief Defined Constants and Types for the STM32L4xx CRC Generator - * - * @ingroup STM32L4xx_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/dac.h b/libopencm3/include/libopencm3/stm32/l4/dac.h deleted file mode 100644 index 10b275a..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/dac.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32L4xx DAC - -@ingroup STM32L4xx_defines - -@version 1.0.0 - -@date 8 June 2019 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l4/dma.h b/libopencm3/include/libopencm3/stm32/l4/dma.h deleted file mode 100644 index d8485a4..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/dma.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup dma_defines DMA Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx DMA Controller - * - * @version 1.0.0 - * - * @date 15 December 2017 - * - * LGPL License Terms @ref lgpl_license - * - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/doc-stm32l4.h b/libopencm3/include/libopencm3/stm32/l4/doc-stm32l4.h deleted file mode 100644 index c491034..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/doc-stm32l4.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @page libopencm3 STM32L4 - -@version 1.0.0 - -@date 12 February 2015 - -API documentation for ST Microelectronics STM32L4 Cortex M4 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup STM32L4xx STM32L4xx -Libraries for ST Microelectronics STM32L4xx series. - -@version 1.0.0 - -@date 12 February 2015 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup STM32L4xx_defines STM32L4xx Defines - -@brief Defined Constants and Types for the STM32L4xx series - -@version 1.0.0 - -@date 12 February 2015 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/stm32/l4/exti.h b/libopencm3/include/libopencm3/stm32/l4/exti.h deleted file mode 100644 index 7ba30b2..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/exti.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup exti_defines EXTI Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx EXTI Control - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - **/ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/flash.h b/libopencm3/include/libopencm3/stm32/l4/flash.h deleted file mode 100644 index fb028a3..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/flash.h +++ /dev/null @@ -1,240 +0,0 @@ -/** @defgroup flash_defines FLASH Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx Flash Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2016 Benjamin Levine - * - * @date 12 February 2016 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Benjamin Levine - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * For details see: - * RM0351 Reference manual: STM32L4x6 advanced ARM®-based 32-bit MCUs - * December 2015, Doc ID 024597 Rev 3 - */ - -/**@{*/ -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include -#include - -/* --- FLASH registers ----------------------------------------------------- */ - -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) -#define FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -#define FLASH_PCROP1SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24) -#define FLASH_PCROP1ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28) -#define FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2C) -#define FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30) -#define FLASH_PCROP2SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) -#define FLASH_PCROP2ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x48) -#define FLASH_WRP2AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) -#define FLASH_WRP2BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_ACR_SLEEP_PD (1 << 14) -#define FLASH_ACR_RUN_PD (1 << 13) -#define FLASH_ACR_PRFTEN (1 << 8) - -#define FLASH_ACR_LATENCY_SHIFT 0 -#define FLASH_ACR_LATENCY_MASK 0x07 - -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -#define FLASH_ACR_LATENCY_2WS 0x02 -#define FLASH_ACR_LATENCY_3WS 0x03 -#define FLASH_ACR_LATENCY_4WS 0x04 - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_SR_BSY (1 << 16) -#define FLASH_SR_OPTVERR (1 << 15) -#define FLASH_SR_RDERR (1 << 14) -#define FLASH_SR_FASTERR (1 << 9) -#define FLASH_SR_MISERR (1 << 8) -#define FLASH_SR_PGSERR (1 << 7) -#define FLASH_SR_SIZERR (1 << 6) -#define FLASH_SR_PGAERR (1 << 5) -#define FLASH_SR_WRPERR (1 << 4) -#define FLASH_SR_PROGERR (1 << 3) -#define FLASH_SR_OPERR (1 << 1) -#define FLASH_SR_EOP (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_CR_LOCK (1 << 31) -#define FLASH_CR_OPTLOCK (1 << 30) -#define FLASH_CR_OBL_LAUNCH (1 << 27) -#define FLASH_CR_RDERRIE (1 << 26) -#define FLASH_CR_ERRIE (1 << 25) -#define FLASH_CR_EOPIE (1 << 24) -#define FLASH_CR_FSTPG (1 << 18) -#define FLASH_CR_OPTSTRT (1 << 17) -#define FLASH_CR_START (1 << 16) -#define FLASH_CR_MER2 (1 << 15) -#define FLASH_CR_BKER (1 << 11) -#define FLASH_CR_MER1 (1 << 2) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_PG (1 << 0) - -#define FLASH_CR_PNB_SHIFT 3 -#define FLASH_CR_PNB_MASK 0xff - -/* --- FLASH_ECCR values -------------------------------------------------- */ - -#define FLASH_ECCR_ECCD (1 << 31) -#define FLASH_ECCR_ECCC (1 << 30) -#define FLASH_ECCR_ECCIE (1 << 24) -#define FLASH_ECCR_SYSF_ECC (1 << 20) -#define FLASH_ECCR_BK_ECC (1 << 19) - -#define FLASH_ECCR_ADDR_ECC_SHIFT 0 -#define FLASH_ECCR_ADDR_ECC_MASK 0x7ffff - -/* --- FLASH_OPTR values -------------------------------------------------- */ - -#define FLASH_OPTR_SRAM2_RST (1 << 25) -#define FLASH_OPTR_SRAM2_PE (1 << 24) -#define FLASH_OPTR_nBOOT1 (1 << 23) -#define FLASH_OPTR_DUALBANK (1 << 21) -#define FLASH_OPTR_BFB2 (1 << 20) -#define FLASH_OPTR_WWDG_SW (1 << 19) -#define FLASH_OPTR_IWDG_STDBY (1 << 18) -#define FLASH_OPTR_IWDG_STOP (1 << 17) -#define FLASH_OPTR_IDWG_SW (1 << 16) -#define FLASH_OPTR_nRST_SHDW (1 << 14) -#define FLASH_OPTR_nRST_STDBY (1 << 13) -#define FLASH_OPTR_nRST_STOP (1 << 12) - -#define FLASH_OPTR_BOR_SHIFT 8 -#define FLASH_OPTR_BOR_MASK 0x700 -#define FLASH_OPTR_BOR_LEVEL_0 0 -#define FLASH_OPTR_BOR_LEVEL_1 1 -#define FLASH_OPTR_BOR_LEVEL_2 2 -#define FLASH_OPTR_BOR_LEVEL_3 3 -#define FLASH_OPTR_BOR_LEVEL_4 4 - -#define FLASH_OPTR_RDP_SHIFT 0 -#define FLASH_OPTR_RDP_MASK 0xff -#define FLASH_OPTR_RDP_LEVEL_0 0xAA -#define FLASH_OPTR_RDP_LEVEL_1 0xBB -#define FLASH_OPTR_RDP_LEVEL_2 0xCC - -/* --- FLASH_PCROP1SR values -------------------------------------------------- */ - -#define FLASH_PCROP1SR_PCROP1_STRT_SHIFT 0 -#define FLASH_PCROP1SR_PCROP1_STRT_MASK 0xffff - -/* --- FLASH_PCROP1ER values -------------------------------------------------- */ - -#define FLASH_PCROP1ER_PCROP_RDP (1 << 31) -#define FLASH_PCROP1ER_PCROP1_END_SHIFT 0 -#define FLASH_PCROP1ER_PCROP1_END_MASK 0xffff - -/* --- FLASH_WRP1AR values -------------------------------------------------- */ - -#define FLASH_WRP1AR_WRP1A_END_SHIFT 16 -#define FLASH_WRP1AR_WRP1A_END_MASK 0xff - -#define FLASH_WRP1AR_WRP1A_STRT_SHIFT 0 -#define FLASH_WRP1AR_WRP1A_STRT_MASK 0xff - -/* --- FLASH_WRP1BR values -------------------------------------------------- */ - -#define FLASH_WRP1BR_WRP1B_END_SHIFT 16 -#define FLASH_WRP1BR_WRP1B_END_MASK 0xff - -#define FLASH_WRP1BR_WRP1B_STRT_SHIFT 0 -#define FLASH_WRP1BR_WRP1B_STRT_MASK 0xff - -/* --- FLASH_PCROP2SR values -------------------------------------------------- */ - -#define FLASH_PCROP2SR_PCROP2_STRT_SHIFT 0 -#define FLASH_PCROP2SR_PCROP2_STRT_MASK 0xffff - -/* --- FLASH_PCROP2ER values -------------------------------------------------- */ - -#define FLASH_PCROP2ER_PCROP2_END_SHIFT 0 -#define FLASH_PCROP2ER_PCROP2_END_MASK 0xffff - -/* --- FLASH_WRP2AR values -------------------------------------------------- */ - -#define FLASH_WRP2AR_WRP2A_END_SHIFT 16 -#define FLASH_WRP2AR_WRP2A_END_MASK 0xff - -#define FLASH_WRP2AR_WRP2A_STRT_SHIFT 0 -#define FLASH_WRP2AR_WRP2A_STRT_MASK 0xff - -/* --- FLASH_WRP2BR values -------------------------------------------------- */ - -#define FLASH_WRP2BR_WRP2B_END_SHIFT 16 -#define FLASH_WRP2BR_WRP2B_END_MASK 0xff - -#define FLASH_WRP2BR_WRP2B_STRT_SHIFT 0 -#define FLASH_WRP2BR_WRP2B_STRT_MASK 0xff - -/* --- FLASH Keys -----------------------------------------------------------*/ - -#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) -#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xfafbfcfd) - -#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) - -#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) -#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void flash_clear_progerr_flag(void); -void flash_clear_pgserr_flag(void); -void flash_clear_size_flag(void); -void flash_clear_pgaerr_flag(void); -void flash_clear_wrperr_flag(void); -void flash_lock_option_bytes(void); -void flash_program_double_word(uint32_t address, uint64_t data); -void flash_program(uint32_t address, uint8_t *data, uint32_t len); -void flash_erase_page(uint32_t page); -void flash_erase_all_pages(void); -void flash_program_option_bytes(uint32_t data); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l4/gpio.h b/libopencm3/include/libopencm3/stm32/l4/gpio.h deleted file mode 100644 index 3f70b18..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/gpio.h +++ /dev/null @@ -1,92 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the STM32L4xx General Purpose I/O - * - * @ingroup STM32L4xx_defines - * - * @version 1.0.0 - * - * @date 12 November 2015 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include - -/*****************************************************************************/ -/* Module definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Register definitions */ -/*****************************************************************************/ - -#define GPIO_BRR(port) MMIO32((port) + 0x28) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) -#define GPIOG_BRR GPIO_BRR(GPIOG) -#define GPIOH_BRR GPIO_BRR(GPIOH) - -/* Analog Switch Control Register */ -#define GPIO_ASCR(port) MMIO32((port) + 0x2c) -#define GPIOA_ASCR GPIO_ASCR(GPIOA) -#define GPIOB_ASCR GPIO_ASCR(GPIOB) -#define GPIOC_ASCR GPIO_ASCR(GPIOC) -#define GPIOD_ASCR GPIO_ASCR(GPIOD) -#define GPIOE_ASCR GPIO_ASCR(GPIOE) -#define GPIOF_ASCR GPIO_ASCR(GPIOF) -#define GPIOG_ASCR GPIO_ASCR(GPIOG) -#define GPIOH_ASCR GPIO_ASCR(GPIOH) - -/*****************************************************************************/ -/* Register values */ -/*****************************************************************************/ - -/** @defgroup gpio_speed GPIO Output Pin Speed -@ingroup gpio_defines -@{*/ -#define GPIO_OSPEED_LOW 0x0 -#define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x2 -#define GPIO_OSPEED_VERYHIGH 0x3 -/**@}*/ - -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -BEGIN_DECLS - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l4/i2c.h b/libopencm3/include/libopencm3/stm32/l4/i2c.h deleted file mode 100644 index 033d570..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/i2c.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32L4xx I2C - -@ingroup STM32L4xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include - -/**@{*/ - -/**@}*/ - -#endif - diff --git a/libopencm3/include/libopencm3/stm32/l4/irq.json b/libopencm3/include/libopencm3/stm32/l4/irq.json deleted file mode 100644 index 85d9372..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/irq.json +++ /dev/null @@ -1,98 +0,0 @@ -{ - "irqs": [ - "wwdg", - "pvd_pvm", - "tamp_stamp", - "rtc_wkup", - "flash", - "rcc", - "exti0", - "exti1", - "exti2", - "exti3", - "exti4", - "dma1_channel1", - "dma1_channel2", - "dma1_channel3", - "dma1_channel4", - "dma1_channel5", - "dma1_channel6", - "dma1_channel7", - "adc1_2", - "can1_tx", - "can1_rx0", - "can1_rx1", - "can1_sce", - "exti9_5", - "tim1_brk_tim15", - "tim1_up_tim16", - "tim1_trg_com_tim17", - "tim1_cc", - "tim2", - "tim3", - "tim4", - "i2c1_ev", - "i2c1_er", - "i2c2_ev", - "i2c2_er", - "spi1", - "spi2", - "usart1", - "usart2", - "usart3", - "exti15_10", - "rtc_alarm", - "dfsdm3", - "tim8_brk", - "tim8_up", - "tim8_trg_com", - "tim8_cc", - "adc3", - "fmc", - "sdmmc1", - "tim5", - "spi3", - "uart4", - "uart5", - "tim6_dacunder", - "tim7", - "dma2_channel1", - "dma2_channel2", - "dma2_channel3", - "dma2_channel4", - "dma2_channel5", - "dfsdm0", - "dfsdm1", - "dfsdm2", - "comp", - "lptim1", - "lptim2", - "otg_fs", - "dma2_channel6", - "dma2_channel7", - "lpuart1", - "quadspi", - "i2c3_ev", - "i2c3_er", - "sai1", - "sai2", - "swpmi1", - "tsc", - "lcd", - "aes", - "rng", - "fpu", - "hash_crs", - "i2c4_ev", - "i2c4_er", - "dcmi", - "can2_tx", - "can2_rx0", - "can2_rx1", - "can2_sce", - "dma2d" - ], - "partname_humanreadable": "STM32 L4 series", - "partname_doxygen": "STM32L4", - "includeguard": "LIBOPENCM3_STM32_L4_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/stm32/l4/iwdg.h b/libopencm3/include/libopencm3/stm32/l4/iwdg.h deleted file mode 100644 index e96cfd5..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/iwdg.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @defgroup iwdg_defines IWDG Defines - * - * @brief Defined Constants and Types for the STM32L4xx Independent Watchdog - * Timer - * - * @ingroup STM32L4xx_defines - * - * @version 1.0.0 - * - * @date 18 December 2017 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/lptimer.h b/libopencm3/include/libopencm3/stm32/l4/lptimer.h deleted file mode 100644 index 1dc78c9..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/lptimer.h +++ /dev/null @@ -1,47 +0,0 @@ -/** @defgroup lptimer_defines LPTIM Defines - * - * @ingroup STM32L4xx_defines - * - * @brief libopencm3 Defined Constants and Types for the STM32L4xx Low Power Timer - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPTIMER_H -#define LIBOPENCM3_LPTIMER_H -/**@{*/ - -#include - -/** @defgroup lptim_reg_base Low Power Timer register base addresses -@{*/ -#define LPTIM1 LPTIM1_BASE -#define LPTIM2 LPTIM2_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -/**@}*/ -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/memorymap.h b/libopencm3/include/libopencm3/stm32/l4/memorymap.h deleted file mode 100644 index baaa32f..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/memorymap.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define FMC1_BANK_BASE (0x60000000U) -#define FMC3_BANK_BASE (0x80000000U) -#define QUADSPI_BANK_BASE (0x90000000U) -#define FMC_QUADSPI_BASE (0xA0000000U) -#define INFO_BASE (0x1fff0000U) -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 (0x48000000U) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define CRS_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800) -#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800) -#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) -#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) -#define SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800) -#define LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400) - - -/* APB2 */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) -#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030) -#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00) -#define SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) -#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400) -#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5800) -#define DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000) - -/* AHB1 */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) - -/* AHB2 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00) -/* Still AHB2, good job ST */ -#define OTG_FS_BASE (0x50000000U + 0x00000) -#define ADC1_BASE (0x50000000U + 0x40000) -#define AES_BASE (0x50000000U + 0x60000) -#define RNG_BASE (0x50000000U + 0x60800) - -/* Private peripherals */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* Device Electronic Signature */ -#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0) -#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590) -#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) -#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) -#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14) -#define DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500)) - -/* ST provided factory calibration values @ 3.0V */ -#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa)) -#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8)) -#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca)) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/pwr.h b/libopencm3/include/libopencm3/stm32/l4/pwr.h deleted file mode 100644 index 0491932..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/pwr.h +++ /dev/null @@ -1,179 +0,0 @@ -/** @defgroup pwr_defines PWR Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx Power Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2016 Benjamin Levine - * - * @date 12 February 2016 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2016 Benjamin Levine - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H -The order of header inclusion is important. pwr.h includes the device -specific memorymap.h header before including this header file.*/ - -/**@{*/ -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - - - -/* --- PWR registers ------------------------------------------------------- */ - -#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) -#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04) -#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08) -#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0C) -#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10) -#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14) -#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18) - -#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20) -#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28) -#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30) -#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38) -#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40) -#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48) -#define PWR_PORT_G MMIO32(POWER_CONTROL_BASE + 0x50) -#define PWR_PORT_H MMIO32(POWER_CONTROL_BASE + 0x58) - -#define PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00) -#define PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04) - -/* --- PWR_CR1 values ------------------------------------------------------- */ - -#define PWR_CR1_LPR (1 << 14) - -#define PWR_CR1_VOS_SHIFT 9 -#define PWR_CR1_VOS_MASK 0x3 -#define PWR_CR1_VOS_RANGE_1 1 -#define PWR_CR1_VOS_RANGE_2 2 - -#define PWR_CR1_DBP (1 << 8) - -#define PWR_CR1_LPMS_SHIFT 0 -#define PWR_CR1_LPMS_MASK 0x07 -#define PWR_CR1_LPMS_STOP_0 0 -#define PWR_CR1_LPMS_STOP_1 1 -#define PWR_CR1_LPMS_STOP_2 2 -#define PWR_CR1_LPMS_STANDBY 3 -#define PWR_CR1_LPMS_SHUTDOWN 4 - -/* --- PWR_CR2 values ------------------------------------------------------- */ - -#define PWR_CR2_USV (1 << 10) -#define PWR_CR2_IOSV (1 << 9) -#define PWR_CR2_PVME4 (1 << 7) -#define PWR_CR2_PVME3 (1 << 6) -#define PWR_CR2_PVME2 (1 << 5) -#define PWR_CR2_PVME1 (1 << 4) - -#define PWR_CR2_PLS_SHIFT 1 -#define PWR_CR2_PLS_MASK 0x07 -/** @defgroup pwr_pls PVD level selection -@ingroup STM32L4_pwr_defines -@{*/ -#define PWR_CR2_PLS_2V0 0x00 -#define PWR_CR2_PLS_2V2 0x01 -#define PWR_CR2_PLS_2V4 0x02 -#define PWR_CR2_PLS_2V5 0x03 -#define PWR_CR2_PLS_2V6 0x04 -#define PWR_CR2_PLS_2V8 0x05 -#define PWR_CR2_PLS_2V9 0x06 -#define PWR_CR2_PLS_PVD_IN 0x07 -/**@}*/ - -#define PWR_CR2_PVDE (1 << 0) - -/* --- PWR_CR3 values ------------------------------------------------------- */ - -#define PWR_CR3_EIWUL (1 << 15) -#define PWR_CR3_APC (1 << 10) -#define PWR_CR3_RRS (1 << 8) -#define PWR_CR3_EWUP5 (1 << 4) -#define PWR_CR3_EWUP4 (1 << 3) -#define PWR_CR3_EWUP3 (1 << 2) -#define PWR_CR3_EWUP2 (1 << 1) -#define PWR_CR3_EWUP1 (1 << 0) - -/* --- PWR_CR4 values ------------------------------------------------------- */ - -#define PWR_CR4_VBRS (1 << 9) -#define PWR_CR4_VBE (1 << 8) -#define PWR_CR4_WP5 (1 << 4) -#define PWR_CR4_WP4 (1 << 3) -#define PWR_CR4_WP3 (1 << 2) -#define PWR_CR4_WP2 (1 << 1) -#define PWR_CR4_WP1 (1 << 0) - -/* --- PWR_SR1 values ------------------------------------------------------- */ - -#define PWR_SR1_WUFI (1 << 15) -#define PWR_SR1_SBF (1 << 8) -#define PWR_SR1_WUF5 (1 << 4) -#define PWR_SR1_WUF4 (1 << 3) -#define PWR_SR1_WUF3 (1 << 2) -#define PWR_SR1_WUF2 (1 << 1) -#define PWR_SR1_WUF1 (1 << 0) - -/* --- PWR_SR2 values ------------------------------------------------------- */ - -#define PWR_SR2_PVMO4 (1 << 15) -#define PWR_SR2_PVMO3 (1 << 14) -#define PWR_SR2_PVMO2 (1 << 13) -#define PWR_SR2_PVMO1 (1 << 12) -#define PWR_SR2_PVDO (1 << 11) -#define PWR_SR2_VOSF (1 << 10) -#define PWR_SR2_REGLPF (1 << 9) -#define PWR_SR2_REGLPS (1 << 8) - -/* --- PWR_SCR values ------------------------------------------------------- */ - -#define PWR_SCR_CSBF (1 << 8) -#define PWR_SCR_CWUF5 (1 << 4) -#define PWR_SCR_CWUF4 (1 << 3) -#define PWR_SCR_CWUF3 (1 << 2) -#define PWR_SCR_CWUF2 (1 << 1) -#define PWR_SCR_CWUF1 (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -enum pwr_vos_scale { - PWR_SCALE1, - PWR_SCALE2, -}; - -BEGIN_DECLS - -void pwr_set_vos_scale(enum pwr_vos_scale scale); -void pwr_disable_backup_domain_write_protect(void); -void pwr_enable_backup_domain_write_protect(void); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l4/rcc.h b/libopencm3/include/libopencm3/stm32/l4/rcc.h deleted file mode 100644 index 09b9d9b..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/rcc.h +++ /dev/null @@ -1,995 +0,0 @@ -/** @defgroup rcc_defines RCC Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx Reset and Clock - * Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2015 Karl Palsson - * - * @date 12 November 2015 - * - * LGPL License Terms @ref lgpl_license - * */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - * - */ - -/**@{*/ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) -#define RCC_CFGR MMIO32(RCC_BASE + 0x08) -#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) -#define RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10) -#define RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14) -#define RCC_CIER MMIO32(RCC_BASE + 0x18) -#define RCC_CIFR MMIO32(RCC_BASE + 0x1c) -#define RCC_CICR MMIO32(RCC_BASE + 0x20) -#define RCC_AHB1RSTR_OFFSET 0x28 -#define RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET) -#define RCC_AHB2RSTR_OFFSET 0x2c -#define RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET) -#define RCC_AHB3RSTR_OFFSET 0x30 -#define RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET) -#define RCC_APB1RSTR1_OFFSET 0x38 -#define RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET) -#define RCC_APB1RSTR2_OFFSET 0x3c -#define RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET) -#define RCC_APB2RSTR_OFFSET 0x40 -#define RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET) -#define RCC_AHB1ENR_OFFSET 0x48 -#define RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET) -#define RCC_AHB2ENR_OFFSET 0x4c -#define RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET) -#define RCC_AHB3ENR_OFFSET 0x50 -#define RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET) -#define RCC_APB1ENR1_OFFSET 0x58 -#define RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET) -#define RCC_APB1ENR2_OFFSET 0x5c -#define RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET) -#define RCC_APB2ENR_OFFSET 0x60 -#define RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET) -#define RCC_AHB1SMENR_OFFSET 0x68 -#define RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET) -#define RCC_AHB2SMENR_OFFSET 0x6c -#define RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET) -#define RCC_AHB3SMENR_OFFSET 0x70 -#define RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET) -#define RCC_APB1SMENR1_OFFSET 0x78 -#define RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET) -#define RCC_APB1SMENR2_OFFSET 0x7c -#define RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET) -#define RCC_APB2SMENR_OFFSET 0x80 -#define RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET) -#define RCC_CCIPR MMIO32(RCC_BASE + 0x88) -#define RCC_BDCR MMIO32(RCC_BASE + 0x90) -#define RCC_CSR MMIO32(RCC_BASE + 0x94) -#define RCC_CRRCR MMIO32(RCC_BASE + 0x98) - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLLSAI2RDY (1 << 29) -#define RCC_CR_PLLSAI2ON (1 << 28) -#define RCC_CR_PLLSAI1RDY (1 << 27) -#define RCC_CR_PLLSAI1ON (1 << 26) -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSIASFS (1 << 11) -#define RCC_CR_HSIRDY (1 << 10) -#define RCC_CR_HSIKERON (1 << 9) -#define RCC_CR_HSION (1 << 8) -/** @defgroup rcc_cr_msirange MSI Range - * @ingroup STM32L4xx_rcc_defines - * @brief Range of the MSI oscillator -Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, -1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz -@sa rcc_csr_msirange -@{*/ -#define RCC_CR_MSIRANGE_SHIFT 4 -#define RCC_CR_MSIRANGE_MASK 0xf -#define RCC_CR_MSIRANGE_100KHZ 0 -#define RCC_CR_MSIRANGE_200KHZ 1 -#define RCC_CR_MSIRANGE_400KHZ 2 -#define RCC_CR_MSIRANGE_800KHZ 3 -#define RCC_CR_MSIRANGE_1MHZ 4 -#define RCC_CR_MSIRANGE_2MHZ 5 -#define RCC_CR_MSIRANGE_4MHZ 6 -#define RCC_CR_MSIRANGE_8MHZ 7 -#define RCC_CR_MSIRANGE_16MHZ 8 -#define RCC_CR_MSIRANGE_24MHZ 9 -#define RCC_CR_MSIRANGE_32MHZ 10 -#define RCC_CR_MSIRANGE_48MHZ 11 -/*@}*/ -#define RCC_CR_MSIRGSEL (1 << 3) -#define RCC_CR_MSIPLLEN (1 << 2) -#define RCC_CR_MSIRDY (1 << 1) -#define RCC_CR_MSION (1 << 0) - -/* --- RCC_CRRCR values ---------------------------------------------------- */ - -#define RCC_CRRCR_HSI48ON (1 << 0) -#define RCC_CRRCR_HSI48RDY (1 << 1) - -/* --- RCC_ICSCR values ---------------------------------------------------- */ - -#define RCC_ICSCR_HSITRIM_SHIFT 24 -#define RCC_ICSCR_HSITRIM_MASK 0x1f -#define RCC_ICSCR_HSICAL_SHIFT 16 -#define RCC_ICSCR_HSICAL_MASK 0xff - -#define RCC_ICSCR_MSITRIM_SHIFT 8 -#define RCC_ICSCR_MSITRIM_MASK 0xff -#define RCC_ICSCR_MSICAL_SHIFT 0 -#define RCC_ICSCR_MSICAL_MASK 0xff - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCOPRE */ -#define RCC_CFGR_MCOPRE_DIV1 0 -#define RCC_CFGR_MCOPRE_DIV2 1 -#define RCC_CFGR_MCOPRE_DIV4 2 -#define RCC_CFGR_MCOPRE_DIV8 3 -#define RCC_CFGR_MCOPRE_DIV16 4 -#define RCC_CFGR_MCOPRE_SHIFT 28 -#define RCC_CFGR_MCOPRE_MASK 0x7 - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x1 -#define RCC_CFGR_MCO_MSI 0x2 -#define RCC_CFGR_MCO_HSI16 0x3 -#define RCC_CFGR_MCO_HSE 0x4 -#define RCC_CFGR_MCO_PLL 0x5 -#define RCC_CFGR_MCO_LSI 0x6 -#define RCC_CFGR_MCO_LSE 0x7 -#define RCC_CFGR_MCO_HSI48 0x8 -#define RCC_CFGR_MCO_SHIFT 24 -#define RCC_CFGR_MCO_MASK 0xf - -/* Wakeup from stop clock selection */ -#define RCC_CFGR_STOPWUCK_MSI (0 << 15) -#define RCC_CFGR_STOPWUCK_HSI16 (1 << 15) - -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_NODIV 0x0 -#define RCC_CFGR_PPRE2_DIV2 0x4 -#define RCC_CFGR_PPRE2_DIV4 0x5 -#define RCC_CFGR_PPRE2_DIV8 0x6 -#define RCC_CFGR_PPRE2_DIV16 0x7 -#define RCC_CFGR_PPRE2_MASK 0x7 -#define RCC_CFGR_PPRE2_SHIFT 11 - -/* PPRE1: APB low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_NODIV 0x0 -#define RCC_CFGR_PPRE1_DIV2 0x4 -#define RCC_CFGR_PPRE1_DIV4 0x5 -#define RCC_CFGR_PPRE1_DIV8 0x6 -#define RCC_CFGR_PPRE1_DIV16 0x7 -#define RCC_CFGR_PPRE1_MASK 0x7 -#define RCC_CFGR_PPRE1_SHIFT 8 - -/* HPRE: AHB prescaler */ -#define RCC_CFGR_HPRE_NODIV 0x0 -#define RCC_CFGR_HPRE_DIV2 0x8 -#define RCC_CFGR_HPRE_DIV4 0x9 -#define RCC_CFGR_HPRE_DIV8 0xa -#define RCC_CFGR_HPRE_DIV16 0xb -#define RCC_CFGR_HPRE_DIV64 0xc -#define RCC_CFGR_HPRE_DIV128 0xd -#define RCC_CFGR_HPRE_DIV256 0xe -#define RCC_CFGR_HPRE_DIV512 0xf -#define RCC_CFGR_HPRE_MASK 0xf -#define RCC_CFGR_HPRE_SHIFT 4 - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_MSI 0x0 -#define RCC_CFGR_SWS_HSI16 0x1 -#define RCC_CFGR_SWS_HSE 0x2 -#define RCC_CFGR_SWS_PLL 0x3 -#define RCC_CFGR_SWS_MASK 0x3 -#define RCC_CFGR_SWS_SHIFT 2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_MSI 0x0 -#define RCC_CFGR_SW_HSI16 0x1 -#define RCC_CFGR_SW_HSE 0x2 -#define RCC_CFGR_SW_PLL 0x3 -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_SHIFT 0 - -/* --- RCC_PLLCFGR - PLL Configuration Register */ -#define RCC_PLLCFGR_PLLR_SHIFT 25 -#define RCC_PLLCFGR_PLLR_MASK 0x3 -#define RCC_PLLCFGR_PLLR_DIV2 0 -#define RCC_PLLCFGR_PLLR_DIV4 1 -#define RCC_PLLCFGR_PLLR_DIV6 2 -#define RCC_PLLCFGR_PLLR_DIV8 3 -#define RCC_PLLCFGR_PLLREN (1<<24) - -#define RCC_PLLCFGR_PLLQ_SHIFT 21 -#define RCC_PLLCFGR_PLLQ_MASK 0x3 -#define RCC_PLLCFGR_PLLQ_DIV2 0 -#define RCC_PLLCFGR_PLLQ_DIV4 1 -#define RCC_PLLCFGR_PLLQ_DIV6 2 -#define RCC_PLLCFGR_PLLQ_DIV8 3 -#define RCC_PLLCFGR_PLLQEN (1 << 20) - -/* Division for PLLSAI3CLK, 0 == 7, 1 == 17 */ -#define RCC_PLLCFGR_PLLP (1 << 17) -#define RCC_PLLCFGR_PLLP_DIV7 0 -#define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP -#define RCC_PLLPEN (1 << 16) - -/** @defgroup rcc_pllcfgr_plln RCC_PLLCFGR PLLN values -@ingroup STM32L4xx_rcc_defines - * Allowed values 8 <= n <= 86 -@{*/ -#define RCC_PLLCFGR_PLLN_SHIFT 0x8 -#define RCC_PLLCFGR_PLLN_MASK 0x7f -/*@}*/ - -/** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values -@ingroup STM32L4xx_rcc_defines - * Allowed values 1 <= m <= 8 -@{*/ -#define RCC_PLLCFGR_PLLM_SHIFT 0x4 -#define RCC_PLLCFGR_PLLM_MASK 0x7 -#define RCC_PLLCFGR_PLLM(x) ((x)-1) -/*@}*/ - -#define RCC_PLLCFGR_PLLSRC_SHIFT 0 -#define RCC_PLLCFGR_PLLSRC_MASK 0x3 -#define RCC_PLLCFGR_PLLSRC_NONE 0 -#define RCC_PLLCFGR_PLLSRC_MSI 1 -#define RCC_PLLCFGR_PLLSRC_HSI16 2 -#define RCC_PLLCFGR_PLLSRC_HSE 3 - -/* --- RCC_PLLSAI1CFGR ----------------------------------------------------- */ -/* TODO */ -/* --- RCC_PLLSAI2CFGR ----------------------------------------------------- */ -/* TODO */ - -/* --- RCC_CIER - Clock interrupt enable register -------------------------- */ - -#define RCC_CIER_HSI48RDYIE (1 << 10) -#define RCC_CIER_LSE_CSSIE (1 << 9) -/* OSC ready interrupt enable bits */ -#define RCC_CIER_PLLSAI2RDYIE (1 << 7) -#define RCC_CIER_PLLSAI1RDYIE (1 << 6) -#define RCC_CIER_PLLRDYIE (1 << 5) -#define RCC_CIER_HSERDYIE (1 << 4) -#define RCC_CIER_HSIRDYIE (1 << 3) -#define RCC_CIER_MSIRDYIE (1 << 2) -#define RCC_CIER_LSERDYIE (1 << 1) -#define RCC_CIER_LSIRDYIE (1 << 0) - -/* --- RCC_CIFR - Clock interrupt flag register */ - -#define RCC_CIFR_HSI48RDYF (1 << 10) -#define RCC_CIFR_LSECSSF (1 << 9) -#define RCC_CIFR_CSSF (1 << 8) -#define RCC_CIFR_PLLSAI2RDYF (1 << 7) -#define RCC_CIFR_PLLSAI1RDYF (1 << 6) -#define RCC_CIFR_PLLRDYF (1 << 5) -#define RCC_CIFR_HSERDYF (1 << 4) -#define RCC_CIFR_HSIRDYF (1 << 3) -#define RCC_CIFR_MSIRDYF (1 << 2) -#define RCC_CIFR_LSERDYF (1 << 1) -#define RCC_CIFR_LSIRDYF (1 << 0) - -/* --- RCC_CICR - Clock interrupt clear register */ - -#define RCC_CICR_HSI48RDYC (1 << 10) -#define RCC_CICR_LSECSSC (1 << 9) -#define RCC_CICR_CSSC (1 << 8) -#define RCC_CICR_PLLSAI2RDYC (1 << 7) -#define RCC_CICR_PLLSAI1RDYC (1 << 6) -#define RCC_CICR_PLLRDYC (1 << 5) -#define RCC_CICR_HSERDYC (1 << 4) -#define RCC_CICR_HSIRDYC (1 << 3) -#define RCC_CICR_MSIRDYC (1 << 2) -#define RCC_CICR_LSERDYC (1 << 1) -#define RCC_CICR_LSIRDYC (1 << 0) - -/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) -@{*/ -/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values -@{*/ -#define RCC_AHB1RSTR_TSCRST (1 << 16) -#define RCC_AHB1RSTR_CRCRST (1 << 12) -#define RCC_AHB1RSTR_FLASHRST (1 << 8) -#define RCC_AHB1RSTR_DMA2RST (1 << 1) -#define RCC_AHB1RSTR_DMA1RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values -@{*/ -#define RCC_AHB2RSTR_RNGRST (1 << 18) -#define RCC_AHB2RSTR_AESRST (1 << 16) -#define RCC_AHB2RSTR_ADCRST (1 << 13) -#define RCC_AHB2RSTR_OTGFSRST (1 << 12) -#define RCC_AHB2RSTR_GPIOHRST (1 << 7) -#define RCC_AHB2RSTR_GPIOGRST (1 << 6) -#define RCC_AHB2RSTR_GPIOFRST (1 << 5) -#define RCC_AHB2RSTR_GPIOERST (1 << 4) -#define RCC_AHB2RSTR_GPIODRST (1 << 3) -#define RCC_AHB2RSTR_GPIOCRST (1 << 2) -#define RCC_AHB2RSTR_GPIOBRST (1 << 1) -#define RCC_AHB2RSTR_GPIOARST (1 << 0) - -/**@}*/ - -/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values -@{*/ -#define RCC_AHB3RSTR_QSPIRST (1 << 8) -#define RCC_AHB3RSTR_FMCRST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTRx reset values (full set) -@{*/ -/** @defgroup rcc_apb1rstr1_rst RCC_APB1RSTR1 reset values -@{*/ -#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) -#define RCC_APB1RSTR1_OPAMPRST (1 << 30) -#define RCC_APB1RSTR1_DAC1RST (1 << 29) -#define RCC_APB1RSTR1_PWRRST (1 << 28) -#define RCC_APB1RSTR1_CAN1RST (1 << 25) -#define RCC_APB1RSTR1_I2C3RST (1 << 23) -#define RCC_APB1RSTR1_I2C2RST (1 << 22) -#define RCC_APB1RSTR1_I2C1RST (1 << 21) -#define RCC_APB1RSTR1_UART5RST (1 << 20) -#define RCC_APB1RSTR1_UART4RST (1 << 19) -#define RCC_APB1RSTR1_USART3RST (1 << 18) -#define RCC_APB1RSTR1_USART2RST (1 << 17) -#define RCC_APB1RSTR1_SPI3RST (1 << 15) -#define RCC_APB1RSTR1_SPI2RST (1 << 14) -#define RCC_APB1RSTR1_LCDRST (1 << 9) -#define RCC_APB1RSTR1_TIM7RST (1 << 5) -#define RCC_APB1RSTR1_TIM6RST (1 << 4) -#define RCC_APB1RSTR1_TIM5RST (1 << 3) -#define RCC_APB1RSTR1_TIM4RST (1 << 2) -#define RCC_APB1RSTR1_TIM3RST (1 << 1) -#define RCC_APB1RSTR1_TIM2RST (1 << 0) -/**@}*/ - -/** @defgroup rcc_apb1rstr2_rst RCC_APB1RSTR2 reset values -@{*/ -#define RCC_APB1RSTR2_LPTIM2RST (1 << 5) -#define RCC_APB1RSTR2_SWPMI1RST (1 << 2) -#define RCC_APB1RSTR2_LPUART1RST (1 << 0) -/**@}*/ -/**@}*/ - -/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values -@{*/ -#define RCC_APB2RSTR_DFSDMRST (1 << 24) -#define RCC_APB2RSTR_SAI2RST (1 << 22) -#define RCC_APB2RSTR_SAI1RST (1 << 21) -#define RCC_APB2RSTR_TIM17RST (1 << 18) -#define RCC_APB2RSTR_TIM16RST (1 << 17) -#define RCC_APB2RSTR_TIM15RST (1 << 16) -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_SDMMC1RST (1 << 10) -/* Suspect FW_RST at bit 7 to match APB2_ENR ... */ -#define RCC_APB2RSTR_SYSCFGRST (1 << 0) -/**@}*/ - -/* --- RCC_AHB1ENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) - *@{*/ -/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_AHB1ENR_TSCEN (1 << 16) -#define RCC_AHB1ENR_CRCEN (1 << 12) -#define RCC_AHB1ENR_FLASHEN (1 << 8) -#define RCC_AHB1ENR_DMA2EN (1 << 1) -#define RCC_AHB1ENR_DMA1EN (1 << 0) -/*@}*/ - -/* --- RCC_AHB2ENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_AHB2ENR_RNGEN (1 << 18) -#define RCC_AHB2ENR_AESEN (1 << 16) -#define RCC_AHB2ENR_ADCEN (1 << 13) -#define RCC_AHB2ENR_OTGFSEN (1 << 12) -#define RCC_AHB2ENR_GPIOHEN (1 << 7) -#define RCC_AHB2ENR_GPIOGEN (1 << 6) -#define RCC_AHB2ENR_GPIOFEN (1 << 5) -#define RCC_AHB2ENR_GPIOEEN (1 << 4) -#define RCC_AHB2ENR_GPIODEN (1 << 3) -#define RCC_AHB2ENR_GPIOCEN (1 << 2) -#define RCC_AHB2ENR_GPIOBEN (1 << 1) -#define RCC_AHB2ENR_GPIOAEN (1 << 0) -/*@}*/ - -/* --- RCC_AHB3ENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_AHB3ENR_QSPIEN (1 << 8) -#define RCC_AHB3ENR_FMCEN (1 << 0) -/*@}*/ - -/**@}*/ - -/* --- RCC_APB1ENR1 values -------------------------------------------------- */ - -/** @defgroup rcc_apb1enr_en RCC_APB1ENRx enable values (full set) - *@{*/ -/** @defgroup rcc_apb1enr1_en RCC_APB1ENR1 enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_APB1ENR1_LPTIM1EN (1 << 31) -#define RCC_APB1ENR1_OPAMPEN (1 << 30) -#define RCC_APB1ENR1_DAC1EN (1 << 29) -#define RCC_APB1ENR1_PWREN (1 << 28) -#define RCC_APB1ENR1_CAN1EN (1 << 25) -#define RCC_APB1ENR1_I2C3EN (1 << 23) -#define RCC_APB1ENR1_I2C2EN (1 << 22) -#define RCC_APB1ENR1_I2C1EN (1 << 21) -#define RCC_APB1ENR1_UART5EN (1 << 20) -#define RCC_APB1ENR1_UART4EN (1 << 19) -#define RCC_APB1ENR1_USART3EN (1 << 18) -#define RCC_APB1ENR1_USART2EN (1 << 17) -#define RCC_APB1ENR1_SPI3EN (1 << 15) -#define RCC_APB1ENR1_SPI2EN (1 << 14) -#define RCC_APB1ENR1_LCDEN (1 << 9) -#define RCC_APB1ENR1_TIM7EN (1 << 5) -#define RCC_APB1ENR1_TIM6EN (1 << 4) -#define RCC_APB1ENR1_TIM5EN (1 << 3) -#define RCC_APB1ENR1_TIM4EN (1 << 2) -#define RCC_APB1ENR1_TIM3EN (1 << 1) -#define RCC_APB1ENR1_TIM2EN (1 << 0) -/*@}*/ - -/* --- RCC_APB1ENR2 values -------------------------------------------------- */ - -/** @defgroup rcc_apb1enr2_en RCC_APB1ENR2 enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_APB1ENR2_LPTIM2EN (1 << 5) -#define RCC_APB1ENR2_SWPMI1EN (1 << 2) -#define RCC_APB1ENR2_LPUART1EN (1 << 0) -/*@}*/ -/*@}*/ - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@ingroup STM32L4xx_rcc_defines - -@{*/ -#define RCC_APB2ENR_DFSDMEN (1 << 24) -#define RCC_APB2ENR_SAI2EN (1 << 22) -#define RCC_APB2ENR_SAI1EN (1 << 21) -#define RCC_APB2ENR_TIM17EN (1 << 18) -#define RCC_APB2ENR_TIM16EN (1 << 17) -#define RCC_APB2ENR_TIM15EN (1 << 16) -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_SDMMC1EN (1 << 10) -#define RCC_APB2ENR_FWEN (1 << 7) -#define RCC_APB2ENR_SYSCFGEN (1 << 0) -/*@}*/ - -/* --- RCC_AHB1SMENR - AHB1 periph clock in sleep mode --------------------- */ - -#define RCC_AHB1SMENR_TSCSMEN (1 << 16) -#define RCC_AHB1SMENR_CRCSMEN (1 << 12) -#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) -#define RCC_AHB1SMENR_FLASHSMEN (1 << 8) -#define RCC_AHB1SMENR_DMA2SMEN (1 << 1) -#define RCC_AHB1SMENR_DMA1SMEN (1 << 0) - -/* --- RCC_AHB2SMENR - AHB2 periph clock in sleep mode --------------------- */ - -#define RCC_AHB2SMENR_RNGSMEN (1 << 18) -#define RCC_AHB2SMENR_AESSMEN (1 << 16) -#define RCC_AHB2SMENR_ADCSMEN (1 << 13) -#define RCC_AHB2SMENR_OTGFSSMEN (1 << 12) -#define RCC_AHB2SMENR_SRAM2SMEN (1 << 9) -#define RCC_AHB2SMENR_GPIOHSMEN (1 << 7) -#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6) -#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5) -#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) -#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) -#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) -#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) -#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) - -/* --- RCC_AHB3SMENR - AHB3 periph clock in sleep mode --------------------- */ - -#define RCC_AHB3SMENR_QSPISMEN (1 << 8) -#define RCC_AHB3SMENR_FMCSMEN (1 << 0) - -/* --- RCC_APB1SMENR1 - APB1 periph clock in sleep mode -------------------- */ - -#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) -#define RCC_APB1SMENR1_OPAMPSMEN (1 << 30) -#define RCC_APB1SMENR1_DAC1SMEN (1 << 29) -#define RCC_APB1SMENR1_PWRSMEN (1 << 28) -#define RCC_APB1SMENR1_CAN1SMEN (1 << 25) -#define RCC_APB1SMENR1_I2C3SMEN (1 << 23) -#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) -#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) -#define RCC_APB1SMENR1_UART5SMEN (1 << 20) -#define RCC_APB1SMENR1_UART4SMEN (1 << 19) -#define RCC_APB1SMENR1_USART3SMEN (1 << 18) -#define RCC_APB1SMENR1_USART2SMEN (1 << 17) -#define RCC_APB1SMENR1_SPI3SMEN (1 << 15) -#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) -#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) -#define RCC_APB1SMENR1_LCDSMEN (1 << 9) -#define RCC_APB1SMENR1_TIM7SMEN (1 << 5) -#define RCC_APB1SMENR1_TIM6SMEN (1 << 4) -#define RCC_APB1SMENR1_TIM5SMEN (1 << 3) -#define RCC_APB1SMENR1_TIM4SMEN (1 << 2) -#define RCC_APB1SMENR1_TIM3SMEN (1 << 1) -#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) - -/* --- RCC_APB1SMENR2 - APB1 periph clock in sleep mode -------------------- */ - -#define RCC_APB1SMENR2_LPTIM2SMEN (1 << 5) -#define RCC_APB1SMENR2_SWPMI1SMEN (1 << 2) -#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) - -/* --- RCC_APB2SMENR - APB2 periph clock in sleep mode --------------------- */ - -#define RCC_APB2SMENR_DFSDMSMEN (1 << 24) -#define RCC_APB2SMENR_SAI2SMEN (1 << 22) -#define RCC_APB2SMENR_SAI1SMEN (1 << 21) -#define RCC_APB2SMENR_TIM17SMEN (1 << 18) -#define RCC_APB2SMENR_TIM16SMEN (1 << 17) -#define RCC_APB2SMENR_TIM15SMEN (1 << 16) -#define RCC_APB2SMENR_USART1SMEN (1 << 14) -#define RCC_APB2SMENR_TIM8SMEN (1 << 13) -#define RCC_APB2SMENR_SPI1SMEN (1 << 12) -#define RCC_APB2SMENR_TIM1SMEN (1 << 11) -#define RCC_APB2SMENR_SDMMC1SMEN (1 << 10) -#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) - -/* --- RCC_CCIPR - Peripherals independent clock config register ----------- */ - -#define RCC_CCIPR_DFSDMSEL (1 << 31) -#define RCC_CCIPR_SWPMI1SEL (1 << 30) - -#define RCC_CCIPR_ADCSEL_NONE 0 -#define RCC_CCIPR_ADCSEL_PLLSAI1R 1 -#define RCC_CCIPR_ADCSEL_PLLSAI2R 2 -#define RCC_CCIPR_ADCSEL_SYS 3 -#define RCC_CCIPR_ADCSEL_MASK 0x3 -#define RCC_CCIPR_ADCSEL_SHIFT 28 - -#define RCC_CCIPR_CLK48SEL_HSI48 0 -#define RCC_CCIPR_CLK48SEL_PLLSAI1Q 1 -#define RCC_CCIPR_CLK48SEL_PLL 2 -#define RCC_CCIPR_CLK48SEL_MSI 3 -#define RCC_CCIPR_CLK48SEL_MASK 0x3 -#define RCC_CCIPR_CLK48SEL_SHIFT 26 - -#define RCC_CCIPR_SAIxSEL_PLLSAI1P 0 -#define RCC_CCIPR_SAIxSEL_PLLSAI2P 1 -#define RCC_CCIPR_SAIxSEL_PLL 2 -#define RCC_CCIPR_SAIxSEL_EXT 3 -#define RCC_CCIPR_SAIxSEL_MASK 0x3 -#define RCC_CCIPR_SAI2SEL_SHIFT 24 -#define RCC_CCIPR_SAI1SEL_SHIFT 22 - -#define RCC_CCIPR_LPTIMxSEL_APB 0 -#define RCC_CCIPR_LPTIMxSEL_LSI 1 -#define RCC_CCIPR_LPTIMxSEL_HSI16 2 -#define RCC_CCIPR_LPTIMxSEL_LSE 3 -#define RCC_CCIPR_LPTIMxSEL_MASK 0x3 -#define RCC_CCIPR_LPTIM2SEL_SHIFT 20 -#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 - -#define RCC_CCIPR_I2CxSEL_APB 0 -#define RCC_CCIPR_I2CxSEL_SYS 1 -#define RCC_CCIPR_I2CxSEL_HSI16 2 -#define RCC_CCIPR_I2CxSEL_MASK 0x3 -#define RCC_CCIPR_I2C3SEL_SHIFT 16 -#define RCC_CCIPR_I2C2SEL_SHIFT 14 -#define RCC_CCIPR_I2C1SEL_SHIFT 12 - -#define RCC_CCIPR_LPUART1SEL_APB 0 -#define RCC_CCIPR_LPUART1SEL_SYS 1 -#define RCC_CCIPR_LPUART1SEL_HSI16 2 -#define RCC_CCIPR_LPUART1SEL_LSE 3 -#define RCC_CCIPR_LPUART1SEL_MASK 0x3 -#define RCC_CCIPR_LPUART1SEL_SHIFT 10 - -#define RCC_CCIPR_USARTxSEL_APB 0 -#define RCC_CCIPR_USARTxSEL_SYS 1 -#define RCC_CCIPR_USARTxSEL_HSI16 2 -#define RCC_CCIPR_USARTxSEL_LSE 3 -#define RCC_CCIPR_USARTxSEL_MASK 0x3 -#define RCC_CCIPR_UARTxSEL_APB RCC_CCIPR_USARTxSEL_APB -#define RCC_CCIPR_UARTxSEL_SYS RCC_CCIPR_USARTxSEL_SYS -#define RCC_CCIPR_UARTxSEL_HSI16 RCC_CCIPR_USARTxSEL_HSI16 -#define RCC_CCIPR_UARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE -#define RCC_CCIPR_UARTxSEL_MASK RCC_CCIPR_USARTxSEL_MASK -#define RCC_CCIPR_UART5SEL_SHIFT 8 -#define RCC_CCIPR_UART4SEL_SHIFT 6 -#define RCC_CCIPR_USART3SEL_SHIFT 4 -#define RCC_CCIPR_USART2SEL_SHIFT 2 -#define RCC_CCIPR_USART1SEL_SHIFT 0 - -#define RCC_CCIPR_USART1SEL_APB 0 -#define RCC_CCIPR_USART1SEL_SYS 1 -#define RCC_CCIPR_USART1SEL_HSI16 2 -#define RCC_CCIPR_USART1SEL_LSE 3 -#define RCC_CCIPR_USART1SEL_SHIFT 0 -#define RCC_CCIPR_USART1SEL_MASK 0x3 - -/* --- RCC_BDCR - Backup domain control register --------------------------- */ - -#define RCC_BDCR_LSCOSEL (1 << 25) -#define RCC_BDCR_LSCOEN (1 << 24) -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) - -#define RCC_BDCR_RTCSEL_NONE 0 -#define RCC_BDCR_RTCSEL_LSE 1 -#define RCC_BDCR_RTCSEL_LSI 2 -#define RCC_BDCR_RTCSEL_HSEDIV32 3 -#define RCC_BDCR_RTCSEL_SHIFT 8 -#define RCC_BDCR_RTCSEL_MASK 0x3 - -#define RCC_BDCR_LSESYSDIS (1 << 7) -#define RCC_BDCR_LSECSSD (1 << 6) -#define RCC_BDCR_LSECSSON (1 << 5) - -#define RCC_BDCR_LSEDRV_LOW 0 -#define RCC_BDCR_LSEDRV_MEDLOW 1 -#define RCC_BDCR_LSEDRV_MEDHIGH 2 -#define RCC_BDCR_LSEDRV_HIGH 3 -#define RCC_BDCR_LSEDRV_SHIFT 3 -#define RCC_BDCR_LSEDRV_MASK 0x3 - -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR - Control/Status register ----------------------------------- */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_BORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_OBLRSTF (1 << 25) -#define RCC_CSR_FWRSTF (1 << 24) -#define RCC_CSR_RMVF (1 << 23) -#define RCC_CSR_RESET_FLAGS (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\ - RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_BORRSTF |\ - RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF) - -/** @defgroup rcc_csr_msirange MSI Range after standby values -@brief Range of the MSI oscillator after returning from standby -@ingroup STM32L4xx_rcc_defines -@sa rcc_cr_msirange -@{*/ -#define RCC_CSR_MSIRANGE_MASK 0xf -#define RCC_CSR_MSIRANGE_SHIFT 8 -#define RCC_CSR_MSIRANGE_1MHZ 4 -#define RCC_CSR_MSIRANGE_2MHZ 5 -#define RCC_CSR_MSIRANGE_4MHZ 6 -#define RCC_CSR_MSIRANGE_8MHZ 7 -/*@}*/ - -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- Variable definitions ------------------------------------------------ */ - -extern uint32_t rcc_ahb_frequency; -extern uint32_t rcc_apb1_frequency; -extern uint32_t rcc_apb2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -// Note: RCC_HSI48 not available on all STM32L4 devices - -enum rcc_osc { - RCC_PLL, RCC_HSE, RCC_HSI16, RCC_MSI, RCC_LSE, RCC_LSI, RCC_HSI48 -}; - - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum rcc_periph_clken { - - /* AHB1 peripherals */ - RCC_TSC = _REG_BIT(RCC_AHB1ENR_OFFSET, 16), - RCC_CRC = _REG_BIT(RCC_AHB1ENR_OFFSET, 12), - RCC_FLASH = _REG_BIT(RCC_AHB1ENR_OFFSET, 8), - RCC_DMA2 = _REG_BIT(RCC_AHB1ENR_OFFSET, 1), - RCC_DMA1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 0), - - /* AHB2 peripherals */ - RCC_RNG = _REG_BIT(RCC_AHB2ENR_OFFSET, 18), - RCC_AES = _REG_BIT(RCC_AHB2ENR_OFFSET, 16), - RCC_ADC = _REG_BIT(RCC_AHB2ENR_OFFSET, 13), - RCC_ADC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13), /* Compatibility */ - RCC_OTGFS = _REG_BIT(RCC_AHB2ENR_OFFSET, 12), - RCC_GPIOH = _REG_BIT(RCC_AHB2ENR_OFFSET, 7), - RCC_GPIOG = _REG_BIT(RCC_AHB2ENR_OFFSET, 6), - RCC_GPIOF = _REG_BIT(RCC_AHB2ENR_OFFSET, 5), - RCC_GPIOE = _REG_BIT(RCC_AHB2ENR_OFFSET, 4), - RCC_GPIOD = _REG_BIT(RCC_AHB2ENR_OFFSET, 3), - RCC_GPIOC = _REG_BIT(RCC_AHB2ENR_OFFSET, 2), - RCC_GPIOB = _REG_BIT(RCC_AHB2ENR_OFFSET, 1), - RCC_GPIOA = _REG_BIT(RCC_AHB2ENR_OFFSET, 0), - - /* AHB3 peripherals */ - RCC_QSPI = _REG_BIT(RCC_AHB3ENR_OFFSET, 8), - RCC_FMC = _REG_BIT(RCC_AHB3ENR_OFFSET, 0), - - /* APB1 peripherals */ - RCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31), - RCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30), - RCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29), - RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28), - RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 26), - RCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25), - RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 24), - RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23), - RCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22), - RCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21), - RCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20), - RCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19), - RCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18), - RCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17), - RCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15), - RCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14), - RCC_LCD = _REG_BIT(RCC_APB1ENR1_OFFSET, 9), - RCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5), - RCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4), - RCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3), - RCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2), - RCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1), - RCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0), - /* apb1-2 */ - RCC_LPTIM2 = _REG_BIT(RCC_APB1ENR2_OFFSET, 5), - RCC_SWPMI1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 2), - RCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0), - - /* APB2 peripherals */ - RCC_DFSDM = _REG_BIT(RCC_APB2ENR_OFFSET, 24), - RCC_SAI2 = _REG_BIT(RCC_APB2ENR_OFFSET, 22), - RCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21), - RCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18), - RCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17), - RCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16), - RCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14), - RCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13), - RCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12), - RCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11), - RCC_SDMMC1 = _REG_BIT(RCC_APB2ENR_OFFSET, 10), - RCC_FW = _REG_BIT(RCC_APB2ENR_OFFSET, 7), - RCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0), - - /* AHB1 peripherals in sleep mode */ - SCC_TSC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 16), - SCC_CRC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 12), - SCC_SRAM1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 9), - SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8), - SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1), - SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0), - - /* AHB2 peripherals in sleep mode */ - SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18), - SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16), - SCC_ADC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13), - SCC_ADC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13), /* Compatibility */ - SCC_OTGFS = _REG_BIT(RCC_AHB2SMENR_OFFSET, 12), - SCC_SRAM2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 9), - SCC_GPIOH = _REG_BIT(RCC_AHB2SMENR_OFFSET, 7), - SCC_GPIOG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 6), - SCC_GPIOF = _REG_BIT(RCC_AHB2SMENR_OFFSET, 5), - SCC_GPIOE = _REG_BIT(RCC_AHB2SMENR_OFFSET, 4), - SCC_GPIOD = _REG_BIT(RCC_AHB2SMENR_OFFSET, 3), - SCC_GPIOC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 2), - SCC_GPIOB = _REG_BIT(RCC_AHB2SMENR_OFFSET, 1), - SCC_GPIOA = _REG_BIT(RCC_AHB2SMENR_OFFSET, 0), - - /* AHB3 peripherals in sleep mode */ - SCC_QSPI = _REG_BIT(RCC_AHB3SMENR_OFFSET, 8), - SCC_FMC = _REG_BIT(RCC_AHB3SMENR_OFFSET, 0), - - /* APB1 peripherals in sleep mode */ - SCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31), - SCC_OPAMP = _REG_BIT(RCC_APB1ENR1_OFFSET, 30), - SCC_DAC1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 29), - SCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28), - SCC_CAN1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 25), - SCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 23), - SCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22), - SCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21), - SCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20), - SCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19), - SCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18), - SCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17), - SCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15), - SCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14), - SCC_WWDG = _REG_BIT(RCC_APB1ENR1_OFFSET, 11), - SCC_LCD = _REG_BIT(RCC_APB1ENR1_OFFSET, 9), - SCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5), - SCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4), - SCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3), - SCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2), - SCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1), - SCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0), - /* apb1-2 */ - SCC_LPTIM2 = _REG_BIT(RCC_APB1ENR2_OFFSET, 5), - SCC_SWPMI1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 2), - SCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0), - - /* APB2 peripherals in sleep mode */ - SCC_DFSDM = _REG_BIT(RCC_APB2ENR_OFFSET, 24), - SCC_SAI2 = _REG_BIT(RCC_APB2ENR_OFFSET, 22), - SCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21), - SCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18), - SCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17), - SCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16), - SCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14), - SCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13), - SCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12), - SCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11), - SCC_SDMMC1 = _REG_BIT(RCC_APB2ENR_OFFSET, 10), - SCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0), -}; - -enum rcc_periph_rst { - /* AHB1 peripherals */ - RST_TSC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 16), - RST_CRC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 12), - RST_FLASH = _REG_BIT(RCC_AHB1RSTR_OFFSET, 8), - RST_DMA2 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 1), - RST_DMA1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 0), - - /* AHB2 peripherals */ - RST_RNG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 18), - RST_AES = _REG_BIT(RCC_AHB2RSTR_OFFSET, 16), - RST_ADC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13), - RST_ADC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13), /* Compatibility */ - RST_OTGFS = _REG_BIT(RCC_AHB2RSTR_OFFSET, 12), - RST_GPIOH = _REG_BIT(RCC_AHB2RSTR_OFFSET, 7), - RST_GPIOG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 6), - RST_GPIOF = _REG_BIT(RCC_AHB2RSTR_OFFSET, 5), - RST_GPIOE = _REG_BIT(RCC_AHB2RSTR_OFFSET, 4), - RST_GPIOD = _REG_BIT(RCC_AHB2RSTR_OFFSET, 3), - RST_GPIOC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 2), - RST_GPIOB = _REG_BIT(RCC_AHB2RSTR_OFFSET, 1), - RST_GPIOA = _REG_BIT(RCC_AHB2RSTR_OFFSET, 0), - - /* AHB3 peripherals */ - RST_QSPI = _REG_BIT(RCC_AHB3RSTR_OFFSET, 8), - RST_FMC = _REG_BIT(RCC_AHB3RSTR_OFFSET, 0), - - /* APB1 peripherals */ - RST_LPTIM1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 31), - RST_OPAMP = _REG_BIT(RCC_APB1RSTR1_OFFSET, 30), - RST_DAC1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 29), - RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28), - RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 26), - RST_CAN1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25), - RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 24), - RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23), - RST_I2C2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 22), - RST_I2C1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 21), - RST_UART5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 20), - RST_UART4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 19), - RST_USART3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 18), - RST_USART2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 17), - RST_SPI3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 15), - RST_SPI2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 14), - RST_LCD = _REG_BIT(RCC_APB1RSTR1_OFFSET, 9), - RST_TIM7 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 5), - RST_TIM6 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 4), - RST_TIM5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 3), - RST_TIM4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 2), - RST_TIM3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 1), - RST_TIM2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 0), - /* apb1-2 */ - RST_LPTIM2 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 5), - RST_SWPMI1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 2), - RST_LPUART1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 0), - - /* APB2 peripherals */ - RST_DFSDM = _REG_BIT(RCC_APB2RSTR_OFFSET, 24), - RST_SAI2 = _REG_BIT(RCC_APB2RSTR_OFFSET, 22), - RST_SAI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 21), - RST_TIM17 = _REG_BIT(RCC_APB2RSTR_OFFSET, 18), - RST_TIM16 = _REG_BIT(RCC_APB2RSTR_OFFSET, 17), - RST_TIM15 = _REG_BIT(RCC_APB2RSTR_OFFSET, 16), - RST_USART1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 14), - RST_TIM8 = _REG_BIT(RCC_APB2RSTR_OFFSET, 13), - RST_SPI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 12), - RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11), - RST_SDMMC1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 10), - RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0), - -}; -#include - -BEGIN_DECLS - -void rcc_osc_ready_int_clear(enum rcc_osc osc); -void rcc_osc_ready_int_enable(enum rcc_osc osc); -void rcc_osc_ready_int_disable(enum rcc_osc osc); -int rcc_osc_ready_int_flag(enum rcc_osc osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_sysclk_status(enum rcc_osc osc); -void rcc_osc_on(enum rcc_osc osc); -void rcc_osc_off(enum rcc_osc osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_set_sysclk_source(uint32_t clk); -void rcc_set_pll_source(uint32_t pllsrc); -void rcc_set_ppre2(uint32_t ppre2); -void rcc_set_ppre1(uint32_t ppre1); -void rcc_set_hpre(uint32_t hpre); -void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr); -uint32_t rcc_system_clock_source(void); -void rcc_set_msi_range(uint32_t msi_range); -void rcc_set_msi_range_standby(uint32_t msi_range); -void rcc_pll_output_enable(uint32_t pllout); -void rcc_set_clock48_source(uint32_t clksel); -void rcc_enable_rtc_clock(void); -void rcc_disable_rtc_clock(void); -void rcc_set_rtc_clock_source(enum rcc_osc clk); - -END_DECLS - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/rng.h b/libopencm3/include/libopencm3/stm32/l4/rng.h deleted file mode 100644 index 09d014d..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/rng.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RNG_H -#define LIBOPENCM3_RNG_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/rtc.h b/libopencm3/include/libopencm3/stm32/l4/rtc.h deleted file mode 100644 index a5fabe9..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup rtc_defines RTC Defines - -@brief Defined Constants and Types for the STM32L4xx RTC - -@ingroup STM32L4xx_defines - -@version 1.0.0 - -@date 18 December 2017 - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/spi.h b/libopencm3/include/libopencm3/stm32/l4/spi.h deleted file mode 100644 index 1b66664..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/spi.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @defgroup spi_defines SPI Defines - * - * @brief Defined Constants and Types for the STM32L4xx SPI - * - * @ingroup STM32L4xx_defines - * - * @version 1.0.0 - * - * @date 15 December 2017 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/st_usbfs.h b/libopencm3/include/libopencm3/stm32/l4/st_usbfs.h deleted file mode 100644 index 7b65d2b..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/st_usbfs.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY ! - * Use top-level - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -# error Do not include directly ! -#else - -#include - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/syscfg.h b/libopencm3/include/libopencm3/stm32/l4/syscfg.h deleted file mode 100644 index d11510b..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/syscfg.h +++ /dev/null @@ -1,122 +0,0 @@ -/** @defgroup syscfg_defines SYSCFG Defines - * - * @ingroup STM32L4xx_defines - * - * @brief Defined Constants and Types for the STM32L4xx Sysconfig - * - * @version 1.0.0 - * - * @date 28 December 2017 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) Bruno Randolf - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SYSCFG_H -#define LIBOPENCM3_SYSCFG_H -/**@{*/ - -/* --- SYSCFG registers ---------------------------------------------------- */ - -#define SYSCFG_MEMRMP MMIO32(SYSCFG_BASE + 0x00) -#define SYSCFG_CFGR1 MMIO32(SYSCFG_BASE + 0x04) -#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) -#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) -#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) -#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) -#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) -#define SYSCFG_SCSR MMIO32(SYSCFG_BASE + 0x18) -#define SYSCFG_CFGR2 MMIO32(SYSCFG_BASE + 0x1C) -#define SYSCFG_SWPR MMIO32(SYSCFG_BASE + 0x20) -#define SYSCFG_SKR MMIO32(SYSCFG_BASE + 0x24) -#define SYSCFG_SWPR2 MMIO32(SYSCFG_BASE + 0x29) - -/* --- SYSCFG_MEMRMP Values ------------------------------------------------ */ - -#define SYSCFG_MEMRMP_MEM_MODE_MASK 7 -#define SYSCFG_MEMRMP_MEM_MODE_FLASH 0 -#define SYSCFG_MEMRMP_MEM_MODE_SYSTEM 1 -#define SYSCFG_MEMRMP_MEM_MODE_FMC 2 -#define SYSCFG_MEMRMP_MEM_MODE_SRAM 3 -#define SYSCFG_MEMRMP_MEM_MODE_QSPI 6 - -/* --- SYSCFG_CFGR1 Values ------------------------------------------------- */ - -#define SYSCFG_CFGR1_FPU_IE_INEXACT (1 << 31) -#define SYSCFG_CFGR1_FPU_IE_DENORMAL (1 << 30) -#define SYSCFG_CFGR1_FPU_IE_OVERFLOW (1 << 29) -#define SYSCFG_CFGR1_FPU_IE_UNDERFLOW (1 << 28) -#define SYSCFG_CFGR1_FPU_IE_DIVZERO (1 << 27) -#define SYSCFG_CFGR1_FPU_IE_INVALID (1 << 26) - -#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) -#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) -#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) - -#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) -#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) -#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) -#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) - -#define SYSCFG_CFGR1_BOOSTEN (1 << 8) -#define SYSCFG_CFGR1_FWDIS (1 << 0) - -/* --- SYSCFG_EXTICR Values -------------------------------------------------*/ - -#define SYSCFG_EXTICR_FIELDSIZE 4 -#define SYSCFG_EXTICR_GPIOA 0 -#define SYSCFG_EXTICR_GPIOB 1 -#define SYSCFG_EXTICR_GPIOC 2 -#define SYSCFG_EXTICR_GPIOD 3 -#define SYSCFG_EXTICR_GPIOE 4 -#define SYSCFG_EXTICR_GPIOH 7 - -/* --- SYSCFG_SCSR Values -------------------------------------------------- */ - -#define SYSCFG_SCSR_SRAM2BSY (1 << 1) -#define SYSCFG_SCSR_SRAM2ER (1 << 0) - -/* --- SYSCFG_CFGR2 Values ------------------------------------------------- */ - -#define SYSCFG_CFGR2_SPF (1 << 8) -#define SYSCFG_CFGR2_ECCL (1 << 3) -#define SYSCFG_CFGR2_PVDL (1 << 2) -#define SYSCFG_CFGR2_SPL (1 << 1) -#define SYSCFG_CFGR2_CCL (1 << 0) - -/* --- SYSCFG_SWPR Values -------------------------------------------------- */ - -/* 0 - 15 or 0 - 32 depending on L4 version */ -#define SYSCFG_SWPR_PxWP(x) (1 << x) - -/* --- SYSCFG_SKR Values --------------------------------------------------- */ - -#define SYSCFG_SKR_KEY1 0xCA -#define SYSCFG_SKR_KEY2 0x53 - -/* --- SYSCFG_SWPR2 Values -------------------------------------------------- */ - -/* 32 - 63 or not available depending on L4 version */ -#define SYSCFG_SWPR2_PxWP(x) (1 << (x - 32)) - -/**@}*/ - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/timer.h b/libopencm3/include/libopencm3/stm32/l4/timer.h deleted file mode 100644 index 355c1ca..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/timer.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32L4xx Timers - -@ingroup STM32L4xx_defines - -@version 1.0.0 - -@date 30 November 2015 - -@author @htmlonly © @endhtmlonly 2015 Karl Palsson - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/l4/usart.h b/libopencm3/include/libopencm3/stm32/l4/usart.h deleted file mode 100644 index 7a546f6..0000000 --- a/libopencm3/include/libopencm3/stm32/l4/usart.h +++ /dev/null @@ -1,49 +0,0 @@ -/** @defgroup usart_defines USART Defines - * - * @brief Defined Constants and Types for the STM32L4xx USART - * - * @ingroup STM32L4xx_defines - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/** @defgroup usart_reg_base USART register base addresses - * Holds all the U(S)ART peripherals supported. - * @{ - */ -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE -#define LPUART1 LPUART1_BASE -/**@}*/ - -BEGIN_DECLS - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/stm32/lptimer.h b/libopencm3/include/libopencm3/stm32/lptimer.h deleted file mode 100644 index f2c6b97..0000000 --- a/libopencm3/include/libopencm3/stm32/lptimer.h +++ /dev/null @@ -1,38 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Guillaume Revaillot - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/ltdc.h b/libopencm3/include/libopencm3/stm32/ltdc.h deleted file mode 100644 index 8a9f615..0000000 --- a/libopencm3/include/libopencm3/stm32/ltdc.h +++ /dev/null @@ -1,29 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#else -# error "LCD-TFT not defined for this family" -#endif diff --git a/libopencm3/include/libopencm3/stm32/memorymap.h b/libopencm3/include/libopencm3/stm32/memorymap.h deleted file mode 100644 index 724114e..0000000 --- a/libopencm3/include/libopencm3/stm32/memorymap.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H -#define LIBOPENCM3_MEMORYMAP_COMMON_H - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32G4) -# include -#elif defined(STM32H7) -# include -#elif defined(GD32F1X0) -# include -#else -# error "stm32 family not defined." -#endif - -#endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */ diff --git a/libopencm3/include/libopencm3/stm32/pwr.h b/libopencm3/include/libopencm3/stm32/pwr.h deleted file mode 100644 index 69547ee..0000000 --- a/libopencm3/include/libopencm3/stm32/pwr.h +++ /dev/null @@ -1,48 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/quadspi.h b/libopencm3/include/libopencm3/stm32/quadspi.h deleted file mode 100644 index 99d74d9..0000000 --- a/libopencm3/include/libopencm3/stm32/quadspi.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F4) -# include -#else -# error "quadspi.h not available for this family." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/rcc.h b/libopencm3/include/libopencm3/stm32/rcc.h deleted file mode 100644 index e1eb243..0000000 --- a/libopencm3/include/libopencm3/stm32/rcc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32G4) -# include -#elif defined(STM32H7) -# include -#elif defined(GD32F1X0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/rng.h b/libopencm3/include/libopencm3/stm32/rng.h deleted file mode 100644 index 58878c7..0000000 --- a/libopencm3/include/libopencm3/stm32/rng.h +++ /dev/null @@ -1,37 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#else -# error "stm32 family not defined." -#endif diff --git a/libopencm3/include/libopencm3/stm32/rtc.h b/libopencm3/include/libopencm3/stm32/rtc.h deleted file mode 100644 index d6ab18a..0000000 --- a/libopencm3/include/libopencm3/stm32/rtc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/sdio.h b/libopencm3/include/libopencm3/stm32/sdio.h deleted file mode 100644 index 4b7b945..0000000 --- a/libopencm3/include/libopencm3/stm32/sdio.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Felix Held - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_SDIO_H -#define LIBOPENCM3_SDIO_H - -#include -#include - -/* --- SDIO registers ------------------------------------------------------ */ - -/* SDIO power control register (SDIO_POWER) */ -#define SDIO_POWER MMIO32(SDIO_BASE + 0x00) - -/* SDI clock control register (SDIO_CLKCR) */ -#define SDIO_CLKCR MMIO32(SDIO_BASE + 0x04) - -/* SDIO argument register (SDIO_ARG) */ -#define SDIO_ARG MMIO32(SDIO_BASE + 0x08) - -/* SDIO command register (SDIO_CMD) */ -#define SDIO_CMD MMIO32(SDIO_BASE + 0x0C) - -/* SDIO command response register (SDIO_RESPCMD) */ -#define SDIO_RESPCMD MMIO32(SDIO_BASE + 0x10) - -/* SDIO response 1..4 register (SDIO_RESPx) */ -#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x14) -#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x18) -#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x1C) -#define SDIO_RESP4 MMIO32(SDIO_BASE + 0x20) - -/* SDIO data timer register (SDIO_DTIMER) */ -#define SDIO_DTIMER MMIO32(SDIO_BASE + 0x24) - -/* SDIO data length register (SDIO_DLEN) */ -#define SDIO_DLEN MMIO32(SDIO_BASE + 0x28) - -/* SDIO data control register (SDIO_DCTRL) */ -#define SDIO_DCTRL MMIO32(SDIO_BASE + 0x2C) - -/* SDIO data counter register (SDIO_DCOUNT) */ -/* read only, write has no effect */ -#define SDIO_DCOUNT MMIO32(SDIO_BASE + 0x30) - -/* SDIO status register (SDIO_STA) */ -#define SDIO_STA MMIO32(SDIO_BASE + 0x34) - -/* SDIO interrupt clear register (SDIO_ICR) */ -#define SDIO_ICR MMIO32(SDIO_BASE + 0x38) - -/* SDIO mask register (SDIO_MASK) */ -#define SDIO_MASK MMIO32(SDIO_BASE + 0x3C) - -/* SDIO FIFO counter register (SDIO_FIFOCNT) */ -#define SDIO_FIFOCNT MMIO32(SDIO_BASE + 0x48) - -/* SDIO data FIFO register (SDIO_FIFO) */ -/* the SDIO data FIFO is 32 32bit words long, beginning at this address */ -#define SDIO_FIFO MMIO32(SDIO_BASE + 0x80) - - -/* --- SDIO_POWER values --------------------------------------------------- */ - -#define SDIO_POWER_PWRCTRL_SHIFT 0 -#define SDIO_POWER_PWRCTRL_MASK 0x3 -#define SDIO_POWER_PWRCTRL_PWROFF (0x0 << SDIO_POWER_PWRCTRL_SHIFT) -/* what does "10: Reserved power-up" mean? */ -#define SDIO_POWER_PWRCTRL_RSVPWRUP (0x2 << SDIO_POWER_PWRCTRL_SHIFT) -#define SDIO_POWER_PWRCTRL_PWRON (0x3 << SDIO_POWER_PWRCTRL_SHIFT) - - -/* --- SDIO_CLKCR values --------------------------------------------------- */ - -/* HWFC_EN: HW Flow Control enable */ -#define SDIO_CLKCR_HWFC_EN (1 << 14) - -/* NEGEDGE: SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_NEGEDGE (1 << 13) - -/* WIDBUS: Wide bus mode enable bit */ -/* set the width of the data bus */ -#define SDIO_CLKCR_WIDBUS_SHIFT 11 -#define SDIO_CLKCR_WIDBUS_MASK 0x3 -#define SDIO_CLKCR_WIDBUS_1 (0x0 << SDIO_CLKCR_WIDBUS_SHIFT) -#define SDIO_CLKCR_WIDBUS_4 (0x1 << SDIO_CLKCR_WIDBUS_SHIFT) -#define SDIO_CLKCR_WIDBUS_8 (0x2 << SDIO_CLKCR_WIDBUS_SHIFT) - -/* BYPASS: Clock divider bypass enable bit */ -#define SDIO_CLKCR_BYPASS (1 << 10) - -/* PWRSAV: Power saving configuration bit */ -#define SDIO_CLKCR_PWRSAV (1 << 9) - -/* CLKEN: Clock enable bit */ -#define SDIO_CLKCR_CLKEN (1 << 8) - -/* CLKDIV: Clock divide factor */ -#define SDIO_CLKCR_CLKDIV_SHIFT 0 -#define SDIO_CLKCR_CLKDIV_MASK 0xFF - - -/* --- SDIO_CMD values ---------------------------------------------------- */ - -/* ATACMD: CE-ATA command */ -#define SDIO_CMD_ATACMD (1 << 14) - -/* nIEN: not Interrupt Enable */ -#define SDIO_CMD_NIEN (1 << 13) - -/* ENCMDcompl: Enable CMD completion */ -#define SDIO_CMD_ENCMDCOMPL (1 << 12) - -/* SDIOSuspend: SD I/O suspend command */ -#define SDIO_CMD_SDIOSUSPEND (1 << 11) - -/* CPSMEN: Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_CPSMEN (1 << 10) - -/* WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_WAITPEND (1 << 9) - -/* WAITINT: CPSM waits for interrupt request */ -#define SDIO_CMD_WAITINT (1 << 8) - -/* WAITRESP: Wait for response bits */ -#define SDIO_CMD_WAITRESP_SHIFT 6 -#define SDIO_CMD_WAITRESP_MASK 0x3 -/* 00: No response, expect CMDSENT flag */ -#define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT) -/* 01: Short response, expect CMDREND or CCRCFAIL flag */ -#define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT) -/* 10: No response, expect CMDSENT flag */ -#define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT) -/* 11: Long response, expect CMDREND or CCRCFAIL flag */ -#define SDIO_CMD_WAITRESP_LONG (0x3 << SDIO_CMD_WAITRESP_SHIFT) - -/* CMDINDEX: Command index */ -#define SDIO_CMD_CMDINDEX_SHIFT 0 -#define SDIO_CMD_CMDINDEX_MASK 0x3F - - -/* --- SDIO_RESPCMD values ------------------------------------------------ */ - -#define SDIO_RESPCMD_SHIFT 0 -#define SDIO_RESPCMD_MASK 0x3F - - -/* --- SDIO_DLEN values --------------------------------------------------- */ - -/* DATALENGTH: Data length value */ -#define SDIO_DLEN_DATALENGTH_SHIFT 0 -#define SDIO_DLEN_DATALENGTH_MASK 0x1FFFFFF - - -/* --- SDIO_DCTRL values -------------------------------------------------- */ - -/* SDIOEN: SD I/O enable functions */ -#define SDIO_DCTRL_SDIOEN (1 << 11) - -/* RWMOD: Read wait mode */ -/* 0: Read Wait control stopping SDIO_D2 - * 1: Read Wait control using SDIO_CK - */ -#define SDIO_DCTRL_RWMOD (1 << 10) - -/* RWSTOP: Read wait stop */ -/* 0: Read wait in progress if RWSTART bit is set - * 1: Enable for read wait stop if RWSTART bit is set - */ -#define SDIO_DCTRL_RWSTOP (1 << 9) - -/* RWSTART: Read wait start */ -#define SDIO_DCTRL_RWSTART (1 << 8) - -/* DBLOCKSIZE: Data block size */ -/* SDIO_DCTRL_DBLOCKSIZE_n - * block size is 2**n bytes with 0<=n<=14 - */ -#define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4 -#define SDIO_DCTRL_DBLOCKSIZE_MASK 0xF -#define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_1 (0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_2 (0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_3 (0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_4 (0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_5 (0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_6 (0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_7 (0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_8 (0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_9 (0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_10 (0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_11 (0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_12 (0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_13 (0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_DBLOCKSIZE_14 (0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT) - -/* DMAEN: DMA enable bit */ -#define SDIO_DCTRL_DMAEN (1 << 3) - -/* DTMODE: Data transfer mode selection 1: Stream or SDIO multi byte transfer */ -#define SDIO_DCTRL_DTMODE (1 << 2) - -/* DTDIR: Data transfer direction selection */ -/* 0: From controller to card. - * 1: From card to controller. - */ -#define SDIO_DCTRL_DTDIR (1 << 1) - -/* DTEN: Data transfer enabled bit */ -#define SDIO_DCTRL_DTEN (1 << 0) - - -/* --- SDIO_STA values ---------------------------------------------------- */ - -/* CEATAEND: CE-ATA command completion signal received for CMD61 */ -#define SDIO_STA_CEATAEND (1 << 23) - -/* SDIOIT: SDIO interrupt received */ -#define SDIO_STA_SDIOIT (1 << 22) - -/* RXDAVL: Data available in receive FIFO */ -#define SDIO_STA_RXDAVL (1 << 21) - -/* TXDAVL: Data available in transmit FIFO */ -#define SDIO_STA_TXDAVL (1 << 20) - -/* RXFIFOE: Receive FIFO empty */ -#define SDIO_STA_RXFIFOE (1 << 19) - -/* TXFIFOE: Transmit FIFO empty */ -/* HW Flow Control enabled -> TXFIFOE signals becomes activated when the FIFO - * contains 2 words. - */ -#define SDIO_STA_TXFIFOE (1 << 18) - -/* RXFIFOF: Receive FIFO full */ -/* HW Flow Control enabled => RXFIFOF signals becomes activated 2 words before - * the FIFO is full. - */ -#define SDIO_STA_RXFIFOF (1 << 17) - -/* TXFIFOF: Transmit FIFO full */ -#define SDIO_STA_TXFIFOF (1 << 16) - -/* RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO */ -#define SDIO_STA_RXFIFOHF (1 << 15) - -/* TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into - * the FIFO - */ -#define SDIO_STA_TXFIFOHE (1 << 14) - -/* RXACT: Data receive in progress */ -#define SDIO_STA_RXACT (1 << 13) - -/* TXACT: Data transmit in progress */ -#define SDIO_STA_TXACT (1 << 12) - -/* CMDACT: Command transfer in progress */ -#define SDIO_STA_CMDACT (1 << 11) - -/* DBCKEND: Data block sent/received (CRC check passed) */ -#define SDIO_STA_DBCKEND (1 << 10) - -/* STBITERR: Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_STBITERR (1 << 9) - -/* DATAEND: Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_DATAEND (1 << 8) - -/* CMDSENT: Command sent (no response required) */ -#define SDIO_STA_CMDSENT (1 << 7) - -/* CMDREND: Command response received (CRC check passed) */ -#define SDIO_STA_CMDREND (1 << 6) - -/* RXOVERR: Received FIFO overrun error */ -#define SDIO_STA_RXOVERR (1 << 5) - -/* TXUNDERR: Transmit FIFO underrun error */ -#define SDIO_STA_TXUNDERR (1 << 4) - -/* DTIMEOUT: Data timeout */ -#define SDIO_STA_DTIMEOUT (1 << 3) - -/* CTIMEOUT: Command response timeout */ -#define SDIO_STA_CTIMEOUT (1 << 2) - -/* DCRCFAIL: Data block sent/received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL (1 << 1) - -/* CCRCFAIL: Command response received (CRC check failed) */ -#define SDIO_STA_CCRCFAIL (1 << 0) - - -/* --- SDIO_ICR values ---------------------------------------------------- */ - -/* CEATAENDC: CEATAEND flag clear bit */ -#define SDIO_ICR_CEATAENDC (1 << 23) - -/* SDIOITC: SDIOIT flag clear bit */ -#define SDIO_ICR_SDIOITC (1 << 22) - -/* DBCKENDC: DBCKEND flag clear bit */ -#define SDIO_ICR_DBCKENDC (1 << 10) - -/* STBITERRC: STBITERR flag clear bit */ -#define SDIO_ICR_STBITERRC (1 << 9) - -/* DATAENDC: DATAEND flag clear bit */ -#define SDIO_ICR_DATAENDC (1 << 8) - -/* CMDSENTC: CMDSENT flag clear bit */ -#define SDIO_ICR_CMDSENTC (1 << 7) - -/* CMDRENDC: CMDREND flag clear bit */ -#define SDIO_ICR_CMDRENDC (1 << 6) - -/* RXOVERRC: RXOVERR flag clear bit */ -#define SDIO_ICR_RXOVERRC (1 << 5) - -/* TXUNDERRC: TXUNDERR flag clear bit */ -#define SDIO_ICR_TXUNDERRC (1 << 4) - -/* DTIMEOUTC: DTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC (1 << 3) - -/* CTIMEOUTC: CTIMEOUT flag clear bit */ -#define SDIO_ICR_CTIMEOUTC (1 << 2) - -/* DCRCFAILC: DCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC (1 << 1) - -/* CCRCFAILC: CCRCFAIL flag clear bit */ -#define SDIO_ICR_CCRCFAILC (1 << 0) - - -/* --- SDIO_MASK values --------------------------------------------------- */ - -/* CEATAENDIE: CE-ATA command completion signal received interrupt enable */ -#define SDIO_MASK_CEATAENDIE (1 << 23) - -/* SDIOITIE: SDIO mode interrupt received interrupt enable */ -#define SDIO_MASK_SDIOITIE (1 << 22) - -/* RXDAVLIE: Data available in Rx FIFO interrupt enable */ -#define SDIO_MASK_RXDAVLIE (1 << 21) - -/* TXDAVLIE: Data available in Tx FIFO interrupt enable */ -#define SDIO_MASK_TXDAVLIE (1 << 20) - -/* RXFIFOEIE: Rx FIFO empty interrupt enable */ -#define SDIO_MASK_RXFIFOEIE (1 << 19) - -/* TXFIFOEIE: Tx FIFO empty interrupt enable */ -#define SDIO_MASK_TXFIFOEIE (1 << 18) - -/* RXFIFOFIE: Rx FIFO full interrupt enable */ -#define SDIO_MASK_RXFIFOFIE (1 << 17) - -/* TXFIFOFIE: Tx FIFO full interrupt enable */ -#define SDIO_MASK_TXFIFOFIE (1 << 16) - -/* RXFIFOHFIE: Rx FIFO half full interrupt enable */ -#define SDIO_MASK_RXFIFOHFIE (1 << 15) - -/* TXFIFOHEIE: Tx FIFO half empty interrupt enable */ -#define SDIO_MASK_TXFIFOHEIE (1 << 14) - -/* RXACTIE: Data receive acting interrupt enable */ -#define SDIO_MASK_RXACTIE (1 << 13) - -/* TXACTIE: Data transmit acting interrupt enable */ -#define SDIO_MASK_TXACTIE (1 << 12) - -/* CMDACTIE: Command acting interrupt enable */ -#define SDIO_MASK_CMDACTIE (1 << 11) - -/* DBCKENDIE: Data block end interrupt enable */ -#define SDIO_MASK_DBCKENDIE (1 << 10) - -/* STBITERRIE: Start bit error interrupt enable */ -#define SDIO_MASK_STBITERRIE (1 << 9) - -/* DATAENDIE: Data end interrupt enable */ -#define SDIO_MASK_DATAENDIE (1 << 8) - -/* CMDSENTIE: Command sent interrupt enable */ -#define SDIO_MASK_CMDSENTIE (1 << 7) - -/* CMDRENDIE: Command response received interrupt enable */ -#define SDIO_MASK_CMDRENDIE (1 << 6) - -/* RXOVERRIE: Rx FIFO overrun error interrupt enable */ -#define SDIO_MASK_RXOVERRIE (1 << 5) - -/* TXUNDERRIE: Tx FIFO underrun error interrupt enable */ -#define SDIO_MASK_TXUNDERRIE (1 << 4) - -/* DTIMEOUTIE: Data timeout interrupt enable */ -#define SDIO_MASK_DTIMEOUTIE (1 << 3) - -/* CTIMEOUTIE: Command timeout interrupt enable */ -#define SDIO_MASK_CTIMEOUTIE (1 << 2) - -/* DCRCFAILIE: Data CRC fail interrupt enable */ -#define SDIO_MASK_DCRCFAILIE (1 << 1) - -/* CCRCFAILIE: Command CRC fail interrupt enable */ -#define SDIO_MASK_CCRCFAILIE (1 << 0) - - -/* --- SDIO_FIFOCNT values ------------------------------------------------- */ - -/* FIFOCOUNT: Remaining number of words to be written to or read from the - * FIFO - */ -#define SDIO_FIFOCNT_FIFOCOUNT_SHIFT 0 -#define SDIO_FIFOCNT_FIFOCOUNT_MASK 0xFFFFFF - - -/* --- Function prototypes ------------------------------------------------- */ - - -/* TODO */ - - -#endif diff --git a/libopencm3/include/libopencm3/stm32/spi.h b/libopencm3/include/libopencm3/stm32/spi.h deleted file mode 100644 index c0a2730..0000000 --- a/libopencm3/include/libopencm3/stm32/spi.h +++ /dev/null @@ -1,48 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/st_usbfs.h b/libopencm3/include/libopencm3/stm32/st_usbfs.h deleted file mode 100644 index 08f5d24..0000000 --- a/libopencm3/include/libopencm3/stm32/st_usbfs.h +++ /dev/null @@ -1,42 +0,0 @@ -/* This provides unification of USB code for supported STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ST_USBFS_H -#define LIBOPENCM3_ST_USBFS_H - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#else -# error "STM32 family not defined or not supported." -#endif - -#endif diff --git a/libopencm3/include/libopencm3/stm32/syscfg.h b/libopencm3/include/libopencm3/stm32/syscfg.h deleted file mode 100644 index a3c3bfd..0000000 --- a/libopencm3/include/libopencm3/stm32/syscfg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/timer.h b/libopencm3/include/libopencm3/stm32/timer.h deleted file mode 100644 index 32ddd15..0000000 --- a/libopencm3/include/libopencm3/stm32/timer.h +++ /dev/null @@ -1,50 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/tools.h b/libopencm3/include/libopencm3/stm32/tools.h deleted file mode 100644 index ef8d7b0..0000000 --- a/libopencm3/include/libopencm3/stm32/tools.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_TOOLS_H -#define LIBOPENCM3_TOOLS_H - -/* - * Register accessors / manipulators - */ - -/* Get register content. */ -#define GET_REG(REG) ((uint16_t) *(REG)) - -/* Set register content. */ -#define SET_REG(REG, VAL) (*(REG) = (uint16_t)(VAL)) - -/* Clear register bit. */ -#define CLR_REG_BIT(REG, BIT) SET_REG((REG), (~(BIT))) - -/* Clear register bit masking out some bits that must not be touched. */ -#define CLR_REG_BIT_MSK_AND_SET(REG, MSK, BIT, EXTRA_BITS) \ - SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS)) - -#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ - CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0) - -/* Get masked out bit value. */ -#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & (BIT)) - -/* - * Set/reset a bit in a masked window by using toggle mechanism. - * - * This means that we look at the bits in the bit window designated by - * the mask. If the bit in the masked window is not matching the - * bit mask BIT then we write 1 and if the bit in the masked window is - * matching the bit mask BIT we write 0. - * - * TODO: We may need a faster implementation of that one? - */ -#define TOG_SET_REG_BIT_MSK_AND_SET(REG, MSK, BIT, EXTRA_BITS) \ -do { \ - register uint16_t toggle_mask = GET_REG(REG) & (MSK); \ - toggle_mask ^= BIT; \ - SET_REG((REG), toggle_mask | (EXTRA_BITS)); \ -} while (0) - -#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ - TOG_SET_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0) - -#endif diff --git a/libopencm3/include/libopencm3/stm32/tsc.h b/libopencm3/include/libopencm3/stm32/tsc.h deleted file mode 100644 index 1895621..0000000 --- a/libopencm3/include/libopencm3/stm32/tsc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/usart.h b/libopencm3/include/libopencm3/stm32/usart.h deleted file mode 100644 index c6cb5f9..0000000 --- a/libopencm3/include/libopencm3/stm32/usart.h +++ /dev/null @@ -1,48 +0,0 @@ -/* This provides unification of code over STM32 subfamilies */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include -#elif defined(STM32H7) -# include -#else -# error "stm32 family not defined." -#endif - diff --git a/libopencm3/include/libopencm3/stm32/wwdg.h b/libopencm3/include/libopencm3/stm32/wwdg.h deleted file mode 100644 index ef75f09..0000000 --- a/libopencm3/include/libopencm3/stm32/wwdg.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_WWDG_H -#define LIBOPENCM3_WWDG_H - -#include -#include - -/* --- WWDG registers ------------------------------------------------------ */ - -/* Control register (WWDG_CR) */ -#define WWDG_CR MMIO32(WWDG_BASE + 0x00) - -/* Configuration register (WWDG_CFR) */ -#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) - -/* Status register (WWDG_SR) */ -#define WWDG_SR MMIO32(WWDG_BASE + 0x08) - -/* --- WWDG_CR values ------------------------------------------------------ */ - -/* Bits [31:8]: Reserved */ - -/* WDGA: Activation bit */ -#define WWDG_CR_WDGA (1 << 7) - -/* T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_LSB 0 -#define WWDG_CR_T0 (1 << 0) -#define WWDG_CR_T1 (1 << 1) -#define WWDG_CR_T2 (1 << 2) -#define WWDG_CR_T3 (1 << 3) -#define WWDG_CR_T4 (1 << 4) -#define WWDG_CR_T5 (1 << 5) -#define WWDG_CR_T6 (1 << 6) - -/* --- WWDG_CFR values ----------------------------------------------------- */ - -/* Bits [31:10]: Reserved */ - -/* EWI: Early wakeup interrupt */ -#define WWDG_CFR_EWI (1 << 9) - -/* WDGTB[8:7]: Timer base */ -#define WWDG_CFR_WDGTB_LSB 7 -#define WWDG_CFR_WDGTB_CK_DIV1 0x0 -#define WWDG_CFR_WDGTB_CK_DIV2 0x1 -#define WWDG_CFR_WDGTB_CK_DIV4 0x2 -#define WWDG_CFR_WDGTB_CK_DIV8 0x3 - -/* W[6:0]: 7-bit window value */ -#define WWDG_CFG_W_LSB 0 -#define WWDG_CFG_W (1 << 0) - -/* --- WWDG_SR values ------------------------------------------------------ */ - -/* Bits [31:1]: Reserved */ - -/* EWIF: Early wakeup interrupt flag */ -#define WWDG_SR_EWIF (1 << 0) - -/* --- WWDG function prototypes---------------------------------------------- */ - -/* TODO */ - -#endif diff --git a/libopencm3/include/libopencm3/swm050/clk.h b/libopencm3/include/libopencm3/swm050/clk.h deleted file mode 100644 index 417fa37..0000000 --- a/libopencm3/include/libopencm3/swm050/clk.h +++ /dev/null @@ -1,55 +0,0 @@ -/** @defgroup clk_defines Clock Defines - * - * @brief Defined Constants and Types for the SWM050 System Clock - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_CLK_H -#define LIBOPENCM3_CLK_H -#include -#include - -/* Clock speed definitions */ -/** @defgroup clk_speeds Base Clock Speeds -@{*/ -enum clk_speeds { - CLK_18MHZ, - CLK_36MHZ -}; -/*@}*/ - -/* Clock divider mask */ -/** @defgroup clk_mask Mask used to set the clock divider -@{*/ -#define CLK_MASK 0xFFFFFC00 -/*@}*/ - -BEGIN_DECLS - -void clk_speed(enum clk_speeds mhz, uint16_t div); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/doc-swm050.h b/libopencm3/include/libopencm3/swm050/doc-swm050.h deleted file mode 100644 index 4ec7c4e..0000000 --- a/libopencm3/include/libopencm3/swm050/doc-swm050.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @page libopencm3 SWM050 - -@version 1.0.0 - -API documentation for Synwit SWM050 series. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup peripheral_apis Peripheral APIs - * APIs for device peripherals - */ - -/** @defgroup SWM050 SWM050 -Libraries for Synwit SWM050 series. - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup SWM050_defines SWM050 Defines - -@brief Defined Constants and Types for the SWM050 series - -@version 1.0.0 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/swm050/flash.h b/libopencm3/include/libopencm3/swm050/flash.h deleted file mode 100644 index 4c01ea7..0000000 --- a/libopencm3/include/libopencm3/swm050/flash.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @defgroup flash_defines Flash Defines - * - * @brief Defined Constants and Types for the SWM050 Flash API - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include - -BEGIN_DECLS - -uint32_t flash_write(uint32_t *dest, uint32_t *src, uint8_t cnt); -uint32_t flash_read(uint32_t *src, uint32_t *dest, uint8_t cnt); -uint32_t flash_erase(void); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/gpio.h b/libopencm3/include/libopencm3/swm050/gpio.h deleted file mode 100644 index 8b01a2e..0000000 --- a/libopencm3/include/libopencm3/swm050/gpio.h +++ /dev/null @@ -1,132 +0,0 @@ -/** @defgroup gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the SWM050 General Purpose I/O - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Icenowy Zheng - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H -#include -#include - -/* GPIO number definitions (for convenience) */ -/** @defgroup gpio_pin_id GPIO Pin Identifiers -@{*/ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO_ALL 0x3ff -/**@}*/ - -/* GPIO direction definitions */ -/** @defgroup gpio_dir GPIO Pin Direction -@{*/ -enum gpio_dir { - GPIO_INPUT, - GPIO_OUTPUT -}; -/**@}*/ - -/* GPIO polarity definitions */ -/** @defgroup gpio_pol GPIO Polarity -@{*/ -enum gpio_pol { - GPIO_POL_LOW, - GPIO_POL_HIGH -}; -/*@}*/ - -/* GPIO interrupt trigger definitions */ -/** @defgroup gpio_trig_type GPIO Interrupt Trigger Type -@{*/ -enum gpio_trig_type { - GPIO_TRIG_LEVEL, - GPIO_TRIG_EDGE -}; -/*@}*/ - -/* GPIO interrupt mask definitions */ -/** @defgroup gpio_int_masked GPIO Interrupt Mask -@{*/ -enum gpio_int_masked { - GPIO_UNMASKED, - GPIO_MASKED -}; -/*@}*/ - -/* GPIO Registers */ -/** @defgroup gpio_registers GPIO Registers -@{*/ -/** Data register */ -#define GPIO_ADATA MMIO32(GPIO_BASE + 0x0) -/** Direction register */ -#define GPIO_ADIR MMIO32(GPIO_BASE + 0x4) -/** Interrupt enable register */ -#define GPIO_INTEN_A MMIO32(GPIO_BASE + 0x30) -/** Interrupt mask register */ -#define GPIO_INTMASK_A MMIO32(GPIO_BASE + 0x34) -/** Interrupt trigger mode register */ -#define GPIO_INTLEVEL_A MMIO32(GPIO_BASE + 0x38) -/** Interrupt polarity register */ -#define GPIO_INTPOLARITY_A MMIO32(GPIO_BASE + 0x3c) -/** Interrupt status after masking */ -#define GPIO_INTSTAT_A MMIO32(GPIO_BASE + 0x40) -/** Interrupt status before masking */ -#define GPIO_RAWINTSTAT_A MMIO32(GPIO_BASE + 0x44) -/** Interrupt clear register */ -#define GPIO_INTEOI_A MMIO32(GPIO_BASE + 0x48) -/** External register (wat) */ -#define GPIO_AEXT MMIO32(GPIO_BASE + 0x4c) -/*@}*/ - -BEGIN_DECLS - -void gpio_set(uint16_t gpios); -void gpio_clear(uint16_t gpios); -uint16_t gpio_get(uint16_t gpios); -void gpio_toggle(uint16_t gpios); - -void gpio_input(uint16_t gpios); -void gpio_output(uint16_t gpios); - -void gpio_int_enable(uint16_t gpios, bool en); -void gpio_int_mask(uint16_t gpios, enum gpio_int_masked masked); -void gpio_int_type(uint16_t gpios, enum gpio_trig_type type); -void gpio_int_pol(uint16_t gpios, enum gpio_pol pol); -uint16_t gpio_int_status(void); -uint16_t gpio_int_raw_status(void); -void gpio_int_clear(uint16_t gpios); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/irq.json b/libopencm3/include/libopencm3/swm050/irq.json deleted file mode 100644 index 339d81e..0000000 --- a/libopencm3/include/libopencm3/swm050/irq.json +++ /dev/null @@ -1,21 +0,0 @@ -{ - "irqs": [ - "timer_se0", - "timer_se1", - "wdt", - "cp", - "gpioa0", - "gpioa1", - "gpioa2", - "gpioa3", - "gpioa4", - "gpioa5", - "gpioa6", - "gpioa7", - "gpioa8", - "gpioa9" - ], - "partname_humanreadable": "SWM050 series", - "partname_doxygen": "SWM050", - "includeguard": "LIBOPENCM3_SWM050_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/swm050/memorymap.h b/libopencm3/include/libopencm3/swm050/memorymap.h deleted file mode 100644 index 8f76ba7..0000000 --- a/libopencm3/include/libopencm3/swm050/memorymap.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @defgroup mmap_defines Memory Map - * - * @brief Defined Constants for the SWM050 Memory Map - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Icenowy Zheng - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H -#include - -/* Memory map for all buses */ -/** @defgroup memory_map Memory Map for All Buses -@{*/ -#define PERIPH_BASE (0x40000000U) - -#define SYSTEM_CON_BASE (PERIPH_BASE + 0x0) -#define GPIO_BASE (PERIPH_BASE + 0x1000) -#define TIMER_SE0_BASE (PERIPH_BASE + 0x2000) -#define TIMER_SE1_BASE (PERIPH_BASE + 0x2400) -#define WDT_BASE (PERIPH_BASE + 0x19000) -#define SYSCTL_BASE (PERIPH_BASE + 0xf0000) -/*@}*/ - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/pwr.h b/libopencm3/include/libopencm3/swm050/pwr.h deleted file mode 100644 index 0a135da..0000000 --- a/libopencm3/include/libopencm3/swm050/pwr.h +++ /dev/null @@ -1,40 +0,0 @@ -/** @defgroup pwr_defines Power/Sleep Defines - * - * @brief Defined Constants and Types for the SWM050 Power/Sleep API - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H -#include -#include - -BEGIN_DECLS - -void pwr_sleep(void); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/syscon.h b/libopencm3/include/libopencm3/swm050/syscon.h deleted file mode 100644 index a9276dd..0000000 --- a/libopencm3/include/libopencm3/swm050/syscon.h +++ /dev/null @@ -1,57 +0,0 @@ -/** @defgroup syscon_defines SYSCON Defines - * - * @brief Defined Constants and Types for the SWM050 SYSCON peripheral - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Icenowy Zheng - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_SYSCON_H -#define LIBOPENCM3_SYSCON_H -#include -#include - -/* SYSCON Registers */ -/** @defgroup syscon_registers SYSCON Registers -@{*/ -/** SWD Enable register */ -#define SYSCON_SWD_SEL MMIO32(SYSTEM_CON_BASE + 0x30) -/** Pin Alternate function selection register */ -#define SYSCON_PORTA_SEL MMIO32(SYSTEM_CON_BASE + 0x80) -/** Pin Pull up register */ -#define SYSCON_PORTA_PULLUP MMIO32(SYSTEM_CON_BASE + 0x90) -/** Pin Input enable register */ -#define SYSCON_PORTA_INEN MMIO32(SYSTEM_CON_BASE + 0xe0) -/*@}*/ - -BEGIN_DECLS - -void syscon_sel_af(uint16_t gpios, bool af_en); -void syscon_pullup(uint16_t gpios, bool en); -void syscon_input_enable(uint16_t gpios, bool en); -void syscon_sel_swd(bool en); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/sysctl.h b/libopencm3/include/libopencm3/swm050/sysctl.h deleted file mode 100644 index 0877315..0000000 --- a/libopencm3/include/libopencm3/swm050/sysctl.h +++ /dev/null @@ -1,58 +0,0 @@ -/** @defgroup sysctl_defines SYSCTL Defines - * - * @brief Defined Constants and Types for the SWM050 SYSCTL Registers - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ -#ifndef LIBOPENCM3_SYSCTL_H -#define LIBOPENCM3_SYSCTL_H -#include -#include - -/** @defgroup sysctl_bit_defs SYSCTL register bit definitions -@{*/ -#define SYSCTL_SYS_CFG_2_SLEEP (1 << 4) -#define SYSCTL_SYS_CFG_1_TIMERSE1 (1 << 17) -#define SYSCTL_SYS_CFG_1_TIMERSE0 (1 << 6) -#define SYSCTL_SYS_CFG_1_WDT (1 << 4) -/**@}*/ - -/** @defgroup sysctl_register SYSCTL Registers - * @note System configuration registers - * @{*/ -/** Clock dividers for TIMERSE and SCLK */ -#define SYSCTL_SYS_CFG_0 MMIO32(SYSCTL_BASE + 0x0) -/** TIMERSE0, TIMERSE1, and WDT enable */ -#define SYSCTL_SYS_CFG_1 MMIO32(SYSCTL_BASE + 0x4) -/** SCLK multiplier (18Mhz and 36Mhz) */ -#define SYSCTL_SYS_DBLF MMIO32(SYSCTL_BASE + 0x8) -/** MOS Disconnect (Synwit says that this subregister is unused), Sleep Mode, - and Internal Oscillator Disconnect. Oscillator Disconnect should probably - not be used on the SWM050, because it has no external oscillator support */ -#define SYSCTL_SYS_CFG_2 MMIO32(SYSCTL_BASE + 0xC) -/*@}*/ - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/timer.h b/libopencm3/include/libopencm3/swm050/timer.h deleted file mode 100644 index f353574..0000000 --- a/libopencm3/include/libopencm3/swm050/timer.h +++ /dev/null @@ -1,197 +0,0 @@ -/** @defgroup timer_defines Timer Defines - * - * @brief Defined Constants and Types for the SWM050 Timer - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2020 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H -#include -#include - -/** @defgroup timer_select Timer Select -@{*/ -#define TIMER_SE0 TIMER_SE0_BASE -#define TIMER_SE1 TIMER_SE1_BASE -/*@}*/ - -/** Timer Level */ -enum timer_level { - TIMER_LEVEL_LOW, - TIMER_LEVEL_HIGH -}; - -/** Timer Edge Modes */ -enum timer_edge_modes { - /** Trigger on rising edge */ - TIMER_EDGE_RISING, - /** Trigger on falling edge */ - TIMER_EDGE_FALLING -}; - -/** Timer Operation Modes */ -enum timer_operation_modes { - TIMER_MODE_COUNTER, - TIMER_MODE_PWM, - TIMER_MODE_PULSE_CAPTURE, - TIMER_MODE_DUTY_CYCLE_CAPTURE -}; - -/** Timer Clock Source */ -enum timer_clk_src { - TIMER_CLK_INTERNAL, - TIMER_CLK_EXTERNAL -}; - -/** Timer Interrupt Mask */ -enum timer_int_masked { - TIMER_UNMASKED, - TIMER_MASKED -}; - -/** Timer Loop Modes */ -enum timer_loop_modes { - TIMER_LOOP_MODE, - TIMER_SINGLE_MODE -}; - -/** Timer Output Modes */ -enum timer_output_modes { - TIMER_OUTPUT_NONE, - TIMER_OUTPUT_INVERT, - TIMER_OUTPUT_HIGH, - TIMER_OUTPUT_LOW -}; - -/** Timer PWM Periods */ -enum timer_pwm_period { - TIMER_PERIOD_0, - TIMER_PERIOD_1 -}; - -/** Timer Clock Divider Mask */ -#define TIMER_DIV_MASK (0x3F << 16) - -/** @defgroup timer_registers Timer Registers -@{*/ -/** Timer control register */ -#define TIMER_CTRL(x) MMIO32(x + 0x0) -/** The target value(s). Treated as uint32_t in counter mode (0), and as 2 - uint16_t values in PWM mode (1) */ -#define TIMER_TARVAL(x) MMIO32(x + 0x4) -/** Current count value in modes 0, 2, and 3 */ -#define TIMER_CURVAL(x) MMIO32(x + 0x8) -/** Cycle width in mode 3 */ -#define TIMER_CAPW(x) MMIO32(x + 0xC) -/** Pulse width in modes 2 and 3 */ -#define TIMER_CAPLH(x) MMIO32(x + 0x10) -/** PWM state in mode 1 */ -#define TIMER_MOD2LF(x) MMIO32(x + 0x14) -/** Timer output pin value */ -#define TIMER_OUTPVAL(x) MMIO32(x + 0x80) -/** Interrupt enable and mask */ -#define TIMER_INTCTL(x) MMIO32(x + 0x84) -/** Interrupt status before masking */ -#define TIMER_INTSTAT(x) MMIO32(x + 0x88) -/** Interrupt status after masking */ -#define TIMER_INTMSKSTAT(x) MMIO32(x + 0x8C) -/** Interrupt overflow; 1 if interrupt occurs again without being cleared */ -#define TIMER_INTFLAG(x) MMIO32(x + 0x90) -/*@}*/ - -/** @defgroup timer_reg_values Timer Register Values -@{*/ -#define TIMER_CTRL_EN 1 -/** Clock source selection */ -#define TIMER_CTRL_OSCMOD (1 << 8) -/** Valid edge selection */ -#define TIMER_CTRL_TMOD (1 << 16) -/** Loop mode selection */ -#define TIMER_CTRL_LMOD (1 << 28) -/** Timer Output Mode Mask */ -#define TIMER_CTRL_OUTMOD_MASK 0x3 -#define TIMER_CTRL_OUTMOD_SHIFT 12 -/** Timer Operation Mode Mask */ -#define TIMER_CTRL_WMOD_MASK 0x3 -#define TIMER_CTRL_WMOD_SHIFT 4 -/** Interrupt mask */ -#define TIMER_INTCTL_INTMSK (1 << 1) -/** Interrupt enable */ -#define TIMER_INTCTL_INTEN 1 -/*@}*/ - -BEGIN_DECLS - -void timer_counter_setup(uint32_t timer, - bool timer_int_en, - enum timer_edge_modes edge_mode, - enum timer_loop_modes loop_mode, - enum timer_clk_src clk_src, - enum timer_output_modes output_mode, - enum timer_level output_level, - uint32_t target); - -void timer_pwm_setup(uint32_t timer, - bool timer_int_en, - enum timer_edge_modes edge_mode, - enum timer_clk_src clk_src, - enum timer_level output_level, - uint16_t target1, - uint16_t target2); - -void timer_pulse_capture_setup(uint32_t timer, - bool timer_int_en, - enum timer_edge_modes edge_mode, - enum timer_loop_modes loop_mode); - -void timer_duty_cycle_capture_setup(uint32_t timer, - bool timer_int_en, - enum timer_edge_modes edge_mode, - enum timer_loop_modes loop_mode); - -void timer_clock_div(uint8_t div); -void timer_enable(uint32_t timer, bool en); -void timer_clock_enable(uint32_t timer, bool en); -void timer_operation_mode(uint32_t timer, enum timer_operation_modes mode); -void timer_output_mode(uint32_t timer, enum timer_output_modes mode); -void timer_output_level(uint32_t timer, enum timer_level level); -void timer_edge_mode(uint32_t timer, enum timer_edge_modes mode); -void timer_loop_mode(uint32_t timer, enum timer_loop_modes mode); -void timer_clock_source(uint32_t timer, enum timer_clk_src src); -void timer_counter_target_value(uint32_t timer, uint32_t target); -void timer_pwm_target_value(uint32_t timer, uint16_t period0, uint16_t period1); -void timer_int_enable(uint32_t timer, bool en); -void timer_int_mask(uint32_t timer, enum timer_int_masked masked); -uint32_t timer_get_current_value(uint32_t timer); -uint32_t timer_get_cycle_width(uint32_t timer); -uint32_t timer_get_pulse_width(uint32_t timer); -enum timer_pwm_period timer_get_pwm_period(uint32_t timer); -bool timer_int_status(uint32_t timer); -bool timer_int_raw_status(uint32_t timer); -bool timer_int_overflow_status(uint32_t timer); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/swm050/wdt.h b/libopencm3/include/libopencm3/swm050/wdt.h deleted file mode 100644 index b67becf..0000000 --- a/libopencm3/include/libopencm3/swm050/wdt.h +++ /dev/null @@ -1,71 +0,0 @@ -/** @defgroup wdt_defines Watchdog Defines - * - * @brief Defined Constants and Types for the SWM050 Watchdog - * - * @ingroup SWM050_defines - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2019 Caleb Szalacinski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ -#ifndef LIBOPENCM3_WDT_H -#define LIBOPENCM3_WDT_H - -#include -#include - -/* Watchdog mode definitions */ -/** @defgroup wdt_modes Watchdog mode -@{*/ -enum wdt_modes { - /** On timeout, reset the system */ - WDT_MODE_RESET, - /** On timeout, generate an interrupt. If another timeout (time2) occurs without - the interrupt being cleared, reset the system. */ - WDT_MODE_INT -}; -/**@}*/ - -/** @defgroup wdt_registers Watchdog Registers -@{*/ -#define WDT_CR MMIO32(WDT_BASE + 0x0) -#define WDT_TORR MMIO32(WDT_BASE + 0x04) -#define WDT_CCVR MMIO32(WDT_BASE + 0x08) -#define WDT_CRR MMIO32(WDT_BASE + 0x0C) -#define WDT_STAT MMIO32(WDT_BASE + 0x10) -#define WDT_EOI MMIO32(WDT_BASE + 0x14) -/**@}*/ - -BEGIN_DECLS - -void wdt_setup(enum wdt_modes mode, uint8_t time1, uint8_t time2); -void wdt_enable(bool en); -void wdt_mode(enum wdt_modes mode); -void wdt_reset(void); -bool wdt_int_status(void); -void wdt_clear_int(void); -void wdt_clock_enable(bool en); -uint32_t wdt_get_value(void); -void wdt_set_time(uint8_t time1, uint8_t time2); - -END_DECLS - -#endif -/**@}*/ diff --git a/libopencm3/include/libopencm3/usb/audio.h b/libopencm3/include/libopencm3/usb/audio.h deleted file mode 100644 index 02cdeab..0000000 --- a/libopencm3/include/libopencm3/usb/audio.h +++ /dev/null @@ -1,233 +0,0 @@ -/** @defgroup usb_audio_defines USB Audio Type Definitions - -@brief Defined Constants and Types for the USB Audio Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2014 -Daniel Thompson -Seb Holzapfel - -@date 19 April 2014 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Daniel Thompson - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_USB_AUDIO_H -#define LIBOPENCM3_USB_AUDIO_H - -/* - * Definitions from the USB_AUDIO_ or usb_audio_ namespace come from: - * "Universal Serial Bus Class Definitions for Audio Devices, Revision 1.0" - */ - -/* Table A-1: Audio Interface Class Code */ -#define USB_CLASS_AUDIO 0x01 - -/* Table A-2: Audio Interface Subclass Codes */ -#define USB_AUDIO_SUBCLASS_UNDEFINED 0x00 -#define USB_AUDIO_SUBCLASS_CONTROL 0x01 -#define USB_AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 -#define USB_AUDIO_SUBCLASS_MIDISTREAMING 0x03 - -/* Table A-4: Audio Class-specific Descriptor Types */ -#define USB_AUDIO_DT_CS_UNDEFINED 0x20 -#define USB_AUDIO_DT_CS_DEVICE 0x21 -#define USB_AUDIO_DT_CS_CONFIGURATION 0x22 -#define USB_AUDIO_DT_CS_STRING 0x23 -#define USB_AUDIO_DT_CS_INTERFACE 0x24 -#define USB_AUDIO_DT_CS_ENDPOINT 0x25 - -/* Table A-5: Audio Class-Specific AC Interface Descriptor Subtypes */ -#define USB_AUDIO_TYPE_AC_DESCRIPTOR_UNDEFINED 0x00 -#define USB_AUDIO_TYPE_HEADER 0x01 -#define USB_AUDIO_TYPE_INPUT_TERMINAL 0x02 -#define USB_AUDIO_TYPE_OUTPUT_TERMINAL 0x03 -#define USB_AUDIO_TYPE_MIXER_UNIT 0x04 -#define USB_AUDIO_TYPE_SELECTOR_UNIT 0x05 -#define USB_AUDIO_TYPE_FEATURE_UNIT 0x06 -#define USB_AUDIO_TYPE_PROCESSING_UNIT 0x07 -#define USB_AUDIO_TYPE_EXTENSION_UNIT 0x08 - -/* Table 4-2: Class-Specific AC Interface Header Descriptor (head) */ -struct usb_audio_header_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint16_t bcdADC; - uint16_t wTotalLength; - uint8_t binCollection; - /* ... */ -} __attribute__((packed)); - -/* Table 4-2: Class-Specific AC Interface Header Descriptor (body) */ -struct usb_audio_header_descriptor_body { - /* ... */ - uint8_t baInterfaceNr; -} __attribute__((packed)); - -/* Table 4-3: Input Terminal Descriptor */ -struct usb_audio_input_terminal_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bTerminalID; - uint16_t wTerminalType; - uint8_t bAssocTerminal; - uint8_t bNrChannels; - uint16_t wChannelConfig; - uint8_t iChannelNames; - uint8_t iTerminal; -} __attribute__((packed)); - -/* Table 4-3: Output Terminal Descriptor */ -struct usb_audio_output_terminal_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bTerminalID; - uint16_t wTerminalType; - uint8_t bAssocTerminal; - uint8_t bSourceID; - uint8_t iTerminal; -} __attribute__((packed)); - -/* Table 4-7: Feature Unit Descriptor (head) */ -struct usb_audio_feature_unit_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bUnitID; - uint8_t bSourceID; - uint8_t bControlSize; - uint16_t bmaControlMaster; /* device can assume 16-bit, given highest - * defined bit in spec is bit #9. - * (it is thus required bControlSize=2) */ - /* ... */ -} __attribute__((packed)); - -/* Table 4-7: Feature Unit Descriptor (body) */ -struct usb_audio_feature_unit_descriptor_body { - /* ... */ - uint16_t bmaControl; - /* ... */ -} __attribute__((packed)); - -/* Table 4-7: Feature Unit Descriptor (tail) */ -struct usb_audio_feature_unit_descriptor_tail { - /* ... */ - uint8_t iFeature; -} __attribute__((packed)); - -/* Table 4-7: Feature Unit Descriptor (2-channel) - * - * This structure is a convenience covering the (common) case where - * there are 2 channels associated with the feature unit - */ -struct usb_audio_feature_unit_descriptor_2ch { - struct usb_audio_feature_unit_descriptor_head head; - struct usb_audio_feature_unit_descriptor_body channel_control[2]; - struct usb_audio_feature_unit_descriptor_tail tail; -} __attribute__((packed)); - -/* Table 4-19: Class-Specific AS Interface Descriptor */ -struct usb_audio_stream_interface_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bTerminalLink; - uint8_t bDelay; - uint16_t wFormatTag; -} __attribute__((packed)); - -/* Table 4-20: Standard AS Isochronous Audio Data Endpoint Descriptor */ -struct usb_audio_stream_endpoint_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; - uint8_t bRefresh; - uint8_t bSynchAddress; -} __attribute__((packed)); - -/* Table 4-21: Class-Specific AS Isochronous Audio Data Endpoint Descriptor */ -struct usb_audio_stream_audio_endpoint_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmAttributes; - uint8_t bLockDelayUnits; - uint16_t wLockDelay; -} __attribute__((packed)); - -/* - * Definitions from the USB_AUDIO_FORMAT_ or usb_audio_format_ namespace come from: - * "Universal Serial Bus Device Class Definition for Audio Data Formats, Revision 1.0" - */ - -/* Table 2-1: Type I Format Type Descriptor (head) */ -struct usb_audio_format_type1_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bFormatType; - uint8_t bNrChannels; - uint8_t bSubFrameSize; - uint8_t bBitResolution; - uint8_t bSamFreqType; - /* ... */ -} __attribute__((packed)); - -/* Table 2-2: Continuous Sampling Frequency */ -struct usb_audio_format_continuous_sampling_frequency { - /* ... */ - uint32_t tLowerSamFreq : 24; - uint32_t tUpperSamFreq : 24; -} __attribute__((packed)); - -/* Table 2-3: Discrete Number of Sampling Frequencies */ -struct usb_audio_format_discrete_sampling_frequency { - /* ... */ - uint32_t tSamFreq : 24; -} __attribute__((packed)); - -/* Table 2-1: Type I Format Type Descriptor (1 sampling frequency) - * - * This structure is a convenience covering the (common) case where - * only 1 discrete sampling frequency is used - */ -struct usb_audio_format_type1_descriptor_1freq { - struct usb_audio_format_type1_descriptor_head head; - struct usb_audio_format_discrete_sampling_frequency freqs[1]; -} __attribute__((packed)); - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/cdc.h b/libopencm3/include/libopencm3/usb/cdc.h deleted file mode 100644 index 20b7836..0000000 --- a/libopencm3/include/libopencm3/usb/cdc.h +++ /dev/null @@ -1,162 +0,0 @@ -/** @defgroup usb_cdc_defines USB CDC Type Definitions - -@brief Defined Constants and Types for the USB CDC Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __CDC_H -#define __CDC_H - -/* Definitions of Communications Device Class from - * "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2" - */ - -/* Table 2: Communications Device Class Code */ -#define USB_CLASS_CDC 0x02 - -/* Table 4: Class Subclass Code */ -#define USB_CDC_SUBCLASS_DLCM 0x01 -#define USB_CDC_SUBCLASS_ACM 0x02 -/* ... */ - -/* Table 5 Communications Interface Class Control Protocol Codes */ -#define USB_CDC_PROTOCOL_NONE 0x00 -#define USB_CDC_PROTOCOL_AT 0x01 -/* ... */ - -/* Table 6: Data Interface Class Code */ -#define USB_CLASS_DATA 0x0A - -/* Table 12: Type Values for the bDescriptorType Field */ -#define CS_INTERFACE 0x24 -#define CS_ENDPOINT 0x25 - -/* Table 13: bDescriptor SubType in Communications Class Functional - * Descriptors */ -#define USB_CDC_TYPE_HEADER 0x00 -#define USB_CDC_TYPE_CALL_MANAGEMENT 0x01 -#define USB_CDC_TYPE_ACM 0x02 -/* ... */ -#define USB_CDC_TYPE_UNION 0x06 -/* ... */ - -/* Table 15: Class-Specific Descriptor Header Format */ -struct usb_cdc_header_descriptor { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint16_t bcdCDC; -} __attribute__((packed)); - -/* Table 16: Union Interface Functional Descriptor */ -struct usb_cdc_union_descriptor { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bControlInterface; - uint8_t bSubordinateInterface0; - /* ... */ -} __attribute__((packed)); - - -/* Definitions for Abstract Control Model devices from: - * "Universal Serial Bus Communications Class Subclass Specification for - * PSTN Devices" - */ - -/* Table 3: Call Management Functional Descriptor */ -struct usb_cdc_call_management_descriptor { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; - uint8_t bDataInterface; -} __attribute__((packed)); - -/* Table 4: Abstract Control Management Functional Descriptor */ -struct usb_cdc_acm_descriptor { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; -} __attribute__((packed)); - -/* Table 13: Class-Specific Request Codes for PSTN subclasses */ -/* ... */ -#define USB_CDC_REQ_SET_LINE_CODING 0x20 -/* ... */ -#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22 -/* ... */ - -/* Table 17: Line Coding Structure */ -struct usb_cdc_line_coding { - uint32_t dwDTERate; - uint8_t bCharFormat; - uint8_t bParityType; - uint8_t bDataBits; -} __attribute__((packed)); - -enum usb_cdc_line_coding_bCharFormat { - USB_CDC_1_STOP_BITS = 0, - USB_CDC_1_5_STOP_BITS = 1, - USB_CDC_2_STOP_BITS = 2, -}; - -enum usb_cdc_line_coding_bParityType { - USB_CDC_NO_PARITY = 0, - USB_CDC_ODD_PARITY = 1, - USB_CDC_EVEN_PARITY = 2, - USB_CDC_MARK_PARITY = 3, - USB_CDC_SPACE_PARITY = 4, -}; - -/* Table 30: Class-Specific Notification Codes for PSTN subclasses */ -/* ... */ -#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 -/* ... */ - -/* Notification Structure */ -struct usb_cdc_notification { - uint8_t bmRequestType; - uint8_t bNotification; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} __attribute__((packed)); - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/dfu.h b/libopencm3/include/libopencm3/usb/dfu.h deleted file mode 100644 index 1d0fc3f..0000000 --- a/libopencm3/include/libopencm3/usb/dfu.h +++ /dev/null @@ -1,104 +0,0 @@ -/** @defgroup usb_dfu_defines USB DFU Type Definitions - -@brief Defined Constants and Types for the USB DFU Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __DFU_H -#define __DFU_H - -#define USB_CLASS_DFU 0xFE - -enum dfu_req { - DFU_DETACH, - DFU_DNLOAD, - DFU_UPLOAD, - DFU_GETSTATUS, - DFU_CLRSTATUS, - DFU_GETSTATE, - DFU_ABORT, -}; - -enum dfu_status { - DFU_STATUS_OK, - DFU_STATUS_ERR_TARGET, - DFU_STATUS_ERR_FILE, - DFU_STATUS_ERR_WRITE, - DFU_STATUS_ERR_ERASE, - DFU_STATUS_ERR_CHECK_ERASED, - DFU_STATUS_ERR_PROG, - DFU_STATUS_ERR_VERIFY, - DFU_STATUS_ERR_ADDRESS, - DFU_STATUS_ERR_NOTDONE, - DFU_STATUS_ERR_FIRMWARE, - DFU_STATUS_ERR_VENDOR, - DFU_STATUS_ERR_USBR, - DFU_STATUS_ERR_POR, - DFU_STATUS_ERR_UNKNOWN, - DFU_STATUS_ERR_STALLEDPKT, -}; - -enum dfu_state { - STATE_APP_IDLE, - STATE_APP_DETACH, - STATE_DFU_IDLE, - STATE_DFU_DNLOAD_SYNC, - STATE_DFU_DNBUSY, - STATE_DFU_DNLOAD_IDLE, - STATE_DFU_MANIFEST_SYNC, - STATE_DFU_MANIFEST, - STATE_DFU_MANIFEST_WAIT_RESET, - STATE_DFU_UPLOAD_IDLE, - STATE_DFU_ERROR, -}; - -#define DFU_FUNCTIONAL 0x21 -struct usb_dfu_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bmAttributes; -#define USB_DFU_CAN_DOWNLOAD 0x01 -#define USB_DFU_CAN_UPLOAD 0x02 -#define USB_DFU_MANIFEST_TOLERANT 0x04 -#define USB_DFU_WILL_DETACH 0x08 - - uint16_t wDetachTimeout; - uint16_t wTransferSize; - uint16_t bcdDFUVersion; -} __attribute__((packed)); - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/doc-usb.h b/libopencm3/include/libopencm3/usb/doc-usb.h deleted file mode 100644 index 2093cb9..0000000 --- a/libopencm3/include/libopencm3/usb/doc-usb.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 Generic USB - -@version 1.0.0 - -@date 10 March 2013 - -API documentation for Generic USB. - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup USB Generic USB -Libraries for Generic USB. - -@version 1.0.0 - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/** @defgroup USB_defines Generic USB Defines - -@brief Defined Constants and Types for Generic USB. - -@version 1.0.0 - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - diff --git a/libopencm3/include/libopencm3/usb/dwc/otg_common.h b/libopencm3/include/libopencm3/usb/dwc/otg_common.h deleted file mode 100644 index 8a70371..0000000 --- a/libopencm3/include/libopencm3/usb/dwc/otg_common.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This file is intended to be included by either otg_hs.h or otg_fs.h - * It contains register definitions common to chips using DesignWare - * USB OTG controllers, including STM32 and EFM32 - */ - -#ifndef LIBOPENCM3_USB_DWC_OTG_COMMON_H -#define LIBOPENCM3_USB_DWC_OTG_COMMON_H - -/* Core Global Control and Status Registers */ -#define OTG_GOTGCTL 0x000 -#define OTG_GOTGINT 0x004 -#define OTG_GAHBCFG 0x008 -#define OTG_GUSBCFG 0x00C -#define OTG_GRSTCTL 0x010 -#define OTG_GINTSTS 0x014 -#define OTG_GINTMSK 0x018 -#define OTG_GRXSTSR 0x01C -#define OTG_GRXSTSP 0x020 -#define OTG_GRXFSIZ 0x024 -#define OTG_GNPTXFSIZ 0x028 -#define OTG_GNPTXSTS 0x02C -#define OTG_GCCFG 0x038 -#define OTG_CID 0x03C -#define OTG_HPTXFSIZ 0x100 -#define OTG_DIEPTXF(x) (0x104 + 4*((x)-1)) - -/* Host-mode Control and Status Registers */ -#define OTG_HCFG 0x400 -#define OTG_HFIR 0x404 -#define OTG_HFNUM 0x408 -#define OTG_HPTXSTS 0x410 -#define OTG_HAINT 0x414 -#define OTG_HAINTMSK 0x418 -#define OTG_HPRT 0x440 -#define OTG_HCCHAR(x) (0x500 + 0x20*(x)) -#define OTG_HCINT(x) (0x508 + 0x20*(x)) -#define OTG_HCINTMSK(x) (0x50C + 0x20*(x)) -#define OTG_HCTSIZ(x) (0x510 + 0x20*(x)) - - -/* Device-mode Control and Status Registers */ -#define OTG_DCFG 0x800 -#define OTG_DCTL 0x804 -#define OTG_DSTS 0x808 -#define OTG_DIEPMSK 0x810 -#define OTG_DOEPMSK 0x814 -#define OTG_DAINT 0x818 -#define OTG_DAINTMSK 0x81C -#define OTG_DVBUSDIS 0x828 -#define OTG_DVBUSPULSE 0x82C -#define OTG_DIEPEMPMSK 0x834 - -#define OTG_DIEPCTL0 0x900 -#define OTG_DIEPCTL(x) (0x900 + 0x20*(x)) -#define OTG_DOEPCTL0 0xB00 -#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x)) -#define OTG_DIEPINT(x) (0x908 + 0x20*(x)) -#define OTG_DOEPINT(x) (0xB08 + 0x20*(x)) -#define OTG_DIEPTSIZ0 0x910 -#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x)) -#define OTG_DOEPTSIZ0 0xB10 -#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x)) -#define OTG_DTXFSTS(x) (0x918 + 0x20*(x)) - -/* Power and clock gating control and status register */ -#define OTG_PCGCCTL 0xE00 - -/* Data FIFO */ -#define OTG_FIFO(x) (((x) + 1) << 12) - - -/* Global CSRs */ -/* OTG USB control registers (OTG_GOTGCTL) */ -#define OTG_GOTGCTL_BSVLD (1 << 19) -#define OTG_GOTGCTL_ASVLD (1 << 18) -#define OTG_GOTGCTL_DBCT (1 << 17) -#define OTG_GOTGCTL_CIDSTS (1 << 16) -#define OTG_GOTGCTL_DHNPEN (1 << 11) -#define OTG_GOTGCTL_HSHNPEN (1 << 10) -#define OTG_GOTGCTL_HNPRQ (1 << 9) -#define OTG_GOTGCTL_HNGSCS (1 << 8) -#define OTG_GOTGCTL_SRQ (1 << 1) -#define OTG_GOTGCTL_SRQSCS (1 << 0) - -/* OTG USB control registers (OTG_GOTGINT) */ -#define OTG_GOTGINT_DBCDNE (1 << 19) -#define OTG_GOTGINT_ADTOCHG (1 << 18) -#define OTG_GOTGINT_HNGDET (1 << 17) -#define OTG_GOTGINT_HNSSCHG (1 << 9) -#define OTG_GOTGINT_SRSSCHG (1 << 8) -#define OTG_GOTGINT_SEDET (1 << 2) - -/* OTG AHB configuration register (OTG_GAHBCFG) */ -#define OTG_GAHBCFG_GINT 0x0001 -#define OTG_GAHBCFG_TXFELVL 0x0080 -#define OTG_GAHBCFG_PTXFELVL 0x0100 - -/* OTG USB configuration register (OTG_GUSBCFG) */ -#define OTG_GUSBCFG_TOCAL 0x00000003 -#define OTG_GUSBCFG_SRPCAP 0x00000100 -#define OTG_GUSBCFG_HNPCAP 0x00000200 -#define OTG_GUSBCFG_TRDT_MASK (0xf << 10) -#define OTG_GUSBCFG_NPTXRWEN 0x00004000 -#define OTG_GUSBCFG_FHMOD 0x20000000 -#define OTG_GUSBCFG_FDMOD 0x40000000 -#define OTG_GUSBCFG_CTXPKT 0x80000000 -#define OTG_GUSBCFG_PHYSEL (1 << 6) - -/* OTG reset register (OTG_GRSTCTL) */ -#define OTG_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define OTG_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define OTG_GRSTCTL_TXFNUM_ALL (0x10 << 6) -#define OTG_GRSTCTL_TXFFLSH (1 << 5) -#define OTG_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define OTG_GRSTCTL_FCRST (1 << 2) -#define OTG_GRSTCTL_HSRST (1 << 1) -#define OTG_GRSTCTL_CSRST (1 << 0) - -/* OTG interrupt status register (OTG_GINTSTS) */ -#define OTG_GINTSTS_WKUPINT (1 << 31) -#define OTG_GINTSTS_SRQINT (1 << 30) -#define OTG_GINTSTS_DISCINT (1 << 29) -#define OTG_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define OTG_GINTSTS_PTXFE (1 << 26) -#define OTG_GINTSTS_HCINT (1 << 25) -#define OTG_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define OTG_GINTSTS_IPXFR (1 << 21) -#define OTG_GINTSTS_INCOMPISOOUT (1 << 21) -#define OTG_GINTSTS_IISOIXFR (1 << 20) -#define OTG_GINTSTS_OEPINT (1 << 19) -#define OTG_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define OTG_GINTSTS_EOPF (1 << 15) -#define OTG_GINTSTS_ISOODRP (1 << 14) -#define OTG_GINTSTS_ENUMDNE (1 << 13) -#define OTG_GINTSTS_USBRST (1 << 12) -#define OTG_GINTSTS_USBSUSP (1 << 11) -#define OTG_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define OTG_GINTSTS_GONAKEFF (1 << 7) -#define OTG_GINTSTS_GINAKEFF (1 << 6) -#define OTG_GINTSTS_NPTXFE (1 << 5) -#define OTG_GINTSTS_RXFLVL (1 << 4) -#define OTG_GINTSTS_SOF (1 << 3) -#define OTG_GINTSTS_OTGINT (1 << 2) -#define OTG_GINTSTS_MMIS (1 << 1) -#define OTG_GINTSTS_CMOD (1 << 0) - -/* OTG interrupt mask register (OTG_GINTMSK) */ -#define OTG_GINTMSK_MMISM 0x00000002 -#define OTG_GINTMSK_OTGINT 0x00000004 -#define OTG_GINTMSK_SOFM 0x00000008 -#define OTG_GINTMSK_RXFLVLM 0x00000010 -#define OTG_GINTMSK_NPTXFEM 0x00000020 -#define OTG_GINTMSK_GINAKEFFM 0x00000040 -#define OTG_GINTMSK_GONAKEFFM 0x00000080 -#define OTG_GINTMSK_ESUSPM 0x00000400 -#define OTG_GINTMSK_USBSUSPM 0x00000800 -#define OTG_GINTMSK_USBRST 0x00001000 -#define OTG_GINTMSK_ENUMDNEM 0x00002000 -#define OTG_GINTMSK_ISOODRPM 0x00004000 -#define OTG_GINTMSK_EOPFM 0x00008000 -#define OTG_GINTMSK_EPMISM 0x00020000 -#define OTG_GINTMSK_IEPINT 0x00040000 -#define OTG_GINTMSK_OEPINT 0x00080000 -#define OTG_GINTMSK_IISOIXFRM 0x00100000 -#define OTG_GINTMSK_IISOOXFRM 0x00200000 -#define OTG_GINTMSK_IPXFRM 0x00200000 -#define OTG_GINTMSK_PRTIM 0x01000000 -#define OTG_GINTMSK_HCIM 0x02000000 -#define OTG_GINTMSK_PTXFEM 0x04000000 -#define OTG_GINTMSK_CIDSCHGM 0x10000000 -#define OTG_GINTMSK_DISCINT 0x20000000 -#define OTG_GINTMSK_SRQIM 0x40000000 -#define OTG_GINTMSK_WUIM 0x80000000 - -/* OTG Receive Status Pop Register (OTG_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define OTG_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_GRXSTSP_PKTSTS_IN (0x2 << 17) -#define OTG_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define OTG_GRXSTSP_PKTSTS_IN_COMP (0x3 << 17) -#define OTG_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_GRXSTSP_PKTSTS_DTERR (0x5 << 17) -#define OTG_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_GRXSTSP_PKTSTS_CHH (0x7 << 17) -#define OTG_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* Bits 31:22 - Reserved */ -/** Only on cores < 0x2000 */ -#define OTG_GCCFG_NOVBUSSENS (1 << 21) -/** Only on cores >= 0x2000 */ -#define OTG_GCCFG_VBDEN (1 << 21) -#define OTG_GCCFG_SOFOUTEN (1 << 20) -#define OTG_GCCFG_VBUSBSEN (1 << 19) -#define OTG_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define OTG_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - -/* OTG FS Product ID register (OTG_CID) */ -#define OTG_CID_HAS_VBDEN 0x00002000 - -/* Device-mode CSRs */ -/* OTG device control register (OTG_DCTL) */ -/* Bits 31:12 - Reserved */ -#define OTG_DCTL_POPRGDNE (1 << 11) -#define OTG_DCTL_CGONAK (1 << 10) -#define OTG_DCTL_SGONAK (1 << 9) -#define OTG_DCTL_SGINAK (1 << 8) -#define OTG_DCTL_TCTL_MASK (7 << 4) -#define OTG_DCTL_GONSTS (1 << 3) -#define OTG_DCTL_GINSTS (1 << 2) -#define OTG_DCTL_SDIS (1 << 1) -#define OTG_DCTL_RWUSIG (1 << 0) - -/* OTG device configuration register (OTG_DCFG) */ -#define OTG_DCFG_DSPD 0x0003 -#define OTG_DCFG_NZLSOHSK 0x0004 -#define OTG_DCFG_DAD 0x07F0 -#define OTG_DCFG_PFIVL 0x1800 - -/* OTG Device IN Endpoint Common Interrupt Mask Register (OTG_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_DIEPMSK_BIM (1 << 9) -#define OTG_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_DIEPMSK_INEPNEM (1 << 6) -#define OTG_DIEPMSK_INEPNMM (1 << 5) -#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) -#define OTG_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_DIEPMSK_EPDM (1 << 1) -#define OTG_DIEPMSK_XFRCM (1 << 0) - -/* OTG Device OUT Endpoint Common Interrupt Mask Register (OTG_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_DOEPMSK_BOIM (1 << 9) -#define OTG_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_DOEPMSK_OTEPDM (1 << 4) -#define OTG_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_DOEPMSK_EPDM (1 << 1) -#define OTG_DOEPMSK_XFRCM (1 << 0) - -/* OTG Device Control IN Endpoint 0 Control Register (OTG_DIEPCTL0) */ -#define OTG_DIEPCTL0_EPENA (1 << 31) -#define OTG_DIEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_DIEPCTLX_SD0PID (1 << 28) -#define OTG_DIEPCTL0_SNAK (1 << 27) -#define OTG_DIEPCTL0_CNAK (1 << 26) -#define OTG_DIEPCTL0_TXFNUM_MASK (0xf << 22) -#define OTG_DIEPCTL0_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define OTG_DIEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_DIEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_DIEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_DIEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_DIEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_DIEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_DIEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_DIEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG Device Control OUT Endpoint 0 Control Register (OTG_DOEPCTL0) */ -#define OTG_DOEPCTL0_EPENA (1 << 31) -#define OTG_DOEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_DOEPCTLX_SD0PID (1 << 28) -#define OTG_DOEPCTL0_SNAK (1 << 27) -#define OTG_DOEPCTL0_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define OTG_DOEPCTL0_STALL (1 << 21) -#define OTG_DOEPCTL0_SNPM (1 << 20) -#define OTG_DOEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_DOEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_DOEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_DOEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_DOEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_DOEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_DOEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_DOEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG Device IN Endpoint Interrupt Register (OTG_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define OTG_DIEPINTX_TXFE (1 << 7) -#define OTG_DIEPINTX_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_DIEPINTX_ITTXFE (1 << 4) -#define OTG_DIEPINTX_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_DIEPINTX_EPDISD (1 << 1) -#define OTG_DIEPINTX_XFRC (1 << 0) - -/* OTG Device IN Endpoint Interrupt Register (OTG_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define OTG_DOEPINTX_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_DOEPINTX_OTEPDIS (1 << 4) -#define OTG_DOEPINTX_STUP (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_DOEPINTX_EPDISD (1 << 1) -#define OTG_DOEPINTX_XFRC (1 << 0) - -/* OTG Device OUT Endpoint 0 Transfer Size Register (OTG_DOEPTSIZ0) */ -/* Bit 31 - Reserved */ -#define OTG_DIEPSIZ0_STUPCNT_1 (0x1 << 29) -#define OTG_DIEPSIZ0_STUPCNT_2 (0x2 << 29) -#define OTG_DIEPSIZ0_STUPCNT_3 (0x3 << 29) -#define OTG_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define OTG_DIEPSIZ0_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define OTG_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) - - - -/* Host-mode CSRs */ -/* OTG Host non-periodic transmit FIFO size register -(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) */ -#define OTG_HNPTXFSIZ_PTXFD_MASK (0xffff0000) -#define OTG_HNPTXFSIZ_PTXSA_MASK (0x0000ffff) - -/* OTG Host periodic transmit FIFO size register (OTG_HPTXFSIZ) */ -#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff0000) -#define OTG_HPTXFSIZ_PTXSA_MASK (0x0000ffff) - -/* OTG Host Configuration Register (OTG_HCFG) */ -/* Bits 31:3 - Reserved */ -#define OTG_HCFG_FSLSS (1 << 2) -#define OTG_HCFG_FSLSPCS_48MHz (0x1 << 0) -#define OTG_HCFG_FSLSPCS_6MHz (0x2 << 0) -#define OTG_HCFG_FSLSPCS_MASK (0x3 << 0) - -/* OTG Host Frame Interval Register (OTG_HFIR) */ -/* Bits 31:16 - Reserved */ -#define OTG_HFIR_FRIVL_MASK (0x0000ffff) - -/* OTG Host frame number/frame time remaining register (OTG_HFNUM) */ -#define OTG_HFNUM_FTREM_MASK (0xffff0000) -#define OTG_HFNUM_FRNUM_MASK (0x0000ffff) - -/* OTG Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) */ -#define OTG_HPTXSTS_PTXQTOP_MASK (0xff000000) -#define OTG_HPTXSTS_PTXQTOP_ODDFRM (1<<31) -#define OTG_HPTXSTS_PTXQTOP_EVENFRM (0<<31) -#define OTG_HPTXSTS_PTXQTOP_CHANNEL_NUMBER_MASK (0xf<<27) -#define OTG_HPTXSTS_PTXQTOP_ENDPOINT_NUMBER_MASK (0xf<<27) -#define OTG_HPTXSTS_PTXQTOP_TYPE_INOUT (0x00<<25) -#define OTG_HPTXSTS_PTXQTOP_TYPE_ZEROLENGTH (0x01<<25) -#define OTG_HPTXSTS_PTXQTOP_TYPE_DISABLECMD (0x11<<25) -#define OTG_HPTXSTS_PTXQTOP_TERMINATE (1<<24) -#define OTG_HPTXSTS_PTXQSAV_MASK (0x00ff0000) -#define OTG_HPTXSTS_PTXFSAVL_MASK (0x0000ffff) - -/* OTG Host all channels interrupt mask register (OTG_HAINT) */ -/* Bits 31:16 - Reserved */ -#define OTG_HAINTMSK_HAINT_MASK (0x0000ffff) - -/* OTG Host all channels interrupt mask register (OTG_HAINTMSK) */ -/* Bits 31:16 - Reserved */ -#define OTG_HAINTMSK_HAINTM_MASK (0x0000ffff) - -/* OTG Host port control and status register (OTG_HPRT) */ -/* Bits 31:19 - Reserved */ -#define OTG_HPRT_PSPD_HIGH (0x0 << 17) -#define OTG_HPRT_PSPD_FULL (0x1 << 17) -#define OTG_HPRT_PSPD_LOW (0x2 << 17) -#define OTG_HPRT_PSPD_MASK (0x3 << 17) -#define OTG_HPRT_PTCTL_DISABLED (0x0 << 13) -#define OTG_HPRT_PTCTL_J (0x1 << 13) -#define OTG_HPRT_PTCTL_K (0x2 << 13) -#define OTG_HPRT_PTCTL_SE0_NAK (0x3 << 13) -#define OTG_HPRT_PTCTL_PACKET (0x4 << 13) -#define OTG_HPRT_PTCTL_FORCE_ENABLE (0x5 << 13) -#define OTG_HPRT_PPWR (1 << 12) -#define OTG_HPRT_PLSTS_DM (1 << 11) -#define OTG_HPRT_PLSTS_DP (1 << 10) -/* Bit 9 - Reserved */ -#define OTG_HPRT_PRST (1 << 8) -#define OTG_HPRT_PSUSP (1 << 7) -#define OTG_HPRT_PRES (1 << 6) -#define OTG_HPRT_POCCHNG (1 << 5) -#define OTG_HPRT_POCA (1 << 4) -#define OTG_HPRT_PENCHNG (1 << 3) -#define OTG_HPRT_PENA (1 << 2) -#define OTG_HPRT_PCDET (1 << 1) -#define OTG_HPRT_PCSTS (1 << 0) - -/* OTG Host channel-x characteristics register (OTG_HCCHARx) */ -#define OTG_HCCHAR_CHENA (1 << 31) -#define OTG_HCCHAR_CHDIS (1 << 30) -#define OTG_HCCHAR_ODDFRM (1 << 29) -#define OTG_HCCHAR_DAD_MASK (0x7f << 22) -#define OTG_HCCHAR_MCNT_1 (0x1 << 20) -#define OTG_HCCHAR_MCNT_2 (0x2 << 20) -#define OTG_HCCHAR_MCNT_3 (0x3 << 20) -#define OTG_HCCHAR_MCNT_MASK (0x3 << 20) -#define OTG_HCCHAR_EPTYP_CONTROL (0 << 18) -#define OTG_HCCHAR_EPTYP_ISOCHRONOUS (1 << 18) -#define OTG_HCCHAR_EPTYP_BULK (2 << 18) -#define OTG_HCCHAR_EPTYP_INTERRUPT (3 << 18) -#define OTG_HCCHAR_EPTYP_MASK (3 << 18) -#define OTG_HCCHAR_LSDEV (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_HCCHAR_EPDIR_OUT (0 << 15) -#define OTG_HCCHAR_EPDIR_IN (1 << 15) -#define OTG_HCCHAR_EPDIR_MASK (1 << 15) -#define OTG_HCCHAR_EPNUM_MASK (0xf << 11) -#define OTG_HCCHAR_MPSIZ_MASK (0x7ff << 0) - -/* OTG Host channel-x interrupt register (OTG_HCINTx) */ -/* Bits 31:11 - Reserved */ -#define OTG_HCINT_DTERR (1 << 10) -#define OTG_HCINT_FRMOR (1 << 9) -#define OTG_HCINT_BBERR (1 << 8) -#define OTG_HCINT_TXERR (1 << 7) -/* Note: OTG_HCINT_NYET: Only in OTG_HS */ -#define OTG_HCINT_NYET (1 << 6) -#define OTG_HCINT_ACK (1 << 5) -#define OTG_HCINT_NAK (1 << 4) -#define OTG_HCINT_STALL (1 << 3) -/* Note: OTG_HCINT_AHBERR: Only in OTG_HS */ -#define OTG_HCINT_AHBERR (1 << 2) -#define OTG_HCINT_CHH (1 << 1) -#define OTG_HCINT_XFRC (1 << 0) - -/* OTG Host channel-x interrupt mask register (OTG_HCINTMSKx) */ -/* Bits 31:11 - Reserved */ -#define OTG_HCINTMSK_DTERRM (1 << 10) -#define OTG_HCINTMSK_FRMORM (1 << 9) -#define OTG_HCINTMSK_BBERRM (1 << 8) -#define OTG_HCINTMSK_TXERRM (1 << 7) -/* Note: OTG_HCINTMSK_NYET: Only in OTG_HS */ -#define OTG_HCINTMSK_NYET (1 << 6) -#define OTG_HCINTMSK_ACKM (1 << 5) -#define OTG_HCINTMSK_NAKM (1 << 4) -#define OTG_HCINTMSK_STALLM (1 << 3) -/* Note: OTG_HCINTMSK_AHBERR: Only in OTG_HS */ -#define OTG_HCINTMSK_AHBERR (1 << 2) -#define OTG_HCINTMSK_CHHM (1 << 1) -#define OTG_HCINTMSK_XFRCM (1 << 0) - -/* OTG Host channel-x transfer size register (OTG_HCTSIZx) */ -/* Note: OTG_HCTSIZ_DOPING: Only in OTG_HS */ -#define OTG_HCTSIZ_DOPING (1 << 31) -#define OTG_HCTSIZ_DPID_DATA0 (0x0 << 29) -#define OTG_HCTSIZ_DPID_DATA1 (0x2 << 29) -#define OTG_HCTSIZ_DPID_DATA2 (0x1 << 29) -#define OTG_HCTSIZ_DPID_MDATA (0x3 << 29) -#define OTG_HCTSIZ_DPID_MASK (0x3 << 29) -#define OTG_HCTSIZ_PKTCNT_MASK (0x3ff << 19) -#define OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << 0) - - - -#endif diff --git a/libopencm3/include/libopencm3/usb/dwc/otg_fs.h b/libopencm3/include/libopencm3/usb/dwc/otg_fs.h deleted file mode 100644 index 6736c0e..0000000 --- a/libopencm3/include/libopencm3/usb/dwc/otg_fs.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This file covers definitions for DesignWare USB OTG HS peripherals. - */ - -#ifndef LIBOPENCM3_USB_DWC_OTG_FS_H -#define LIBOPENCM3_USB_DWC_OTG_FS_H - -#include -#include - -/* Memory map is required for USB_OTG_FS_BASE address */ -#if defined(STM32F1) || defined(STM32F2) || defined(STM32F4) -# include -#elif defined(EFM32HG) -# include -#else -# error "device family not supported by dwc/otg_fs." -#endif - -/***********************************************************************/ - -/* Core Global Control and Status Registers */ -#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL) -#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT) -#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG) -#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG) -#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL) -#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS) -#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK) -#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR) -#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP) -#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ) -#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ) -#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS) -#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + OTG_GCCFG) -#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + OTG_CID) -#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ) -#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x)) - - -/* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + OTG_HCFG) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + OTG_HFIR) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + OTG_HFNUM) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + OTG_HAINT) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + OTG_HPRT) -#define OTG_FS_HCCHAR(x) MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x)) -#define OTG_FS_HCINT(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x)) -#define OTG_FS_HCINTMSK(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x)) -#define OTG_FS_HCTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x)) - -/* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + OTG_DCFG) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + OTG_DCTL) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + OTG_DSTS) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + OTG_DAINT) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x)) - -/* Power and clock gating control and status register */ -#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL) - -/* Data FIFO */ -#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ - + (((x) + 1) \ - << 12))) - - -#endif diff --git a/libopencm3/include/libopencm3/usb/dwc/otg_hs.h b/libopencm3/include/libopencm3/usb/dwc/otg_hs.h deleted file mode 100644 index 7b5124c..0000000 --- a/libopencm3/include/libopencm3/usb/dwc/otg_hs.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This file covers definitions for DesignWare USB OTG HS peripherals. - */ - -#ifndef LIBOPENCM3_USB_DWC_OTG_HS_H -#define LIBOPENCM3_USB_DWC_OTG_HS_H - -#include -#include - -/* Memory map is required for USB_OTG_HS_BASE address */ -#if defined(STM32F2) || defined(STM32F4) -# include -#else -# error "device family not supported by dwc/otg_hs." -#endif - -/* OTG_HS specific registers */ - -/* Host-mode Control and Status Registers */ -#define OTG_HCSPLT(x) (0x504 + 0x20*(x)) -#define OTG_HCDMA(x) (0x514 + 0x20*(x)) - -/* Device-mode Control and Status Registers */ -#define OTG_DEACHHINT 0x838 -#define OTG_DEACHHINTMSK 0x83C -#define OTG_DIEPEACHMSK1 0x844 -#define OTG_DOEPEACHMSK1 0x884 -#define OTG_DIEPDMA(x) (0x914 + 0x20*(x)) -#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x)) - - - -/***********************************************************************/ - -/* Core Global Control and Status Registers */ -#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL) -#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT) -#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG) -#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG) -#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL) -#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS) -#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK) -#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR) -#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP) -#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ) -#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ) -#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS) -#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG) -#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID) -#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ) -#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x)) - -/* Host-mode Control and Status Registers */ -#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG) -#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR) -#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM) -#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS) -#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT) -#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK) -#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT) -#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x)) -#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x)) -#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x)) -#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x)) -#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x)) -#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x)) - -/* Device-mode Control and Status Registers */ -#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG) -#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL) -#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS) -#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK) -#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK) -#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT) -#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK) -#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS) -#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE) -#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK) -#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0) -#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x)) -#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0) -#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x)) -#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x)) -#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x)) -#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0) -#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0) -#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ - OTG_DIEPTSIZ(x)) -#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x)) -#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ - OTG_DOEPTSIZ(x)) -#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT) -#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK) -#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1) -#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1) -#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x)) -#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x)) - -/* Power and clock gating control and status register */ -#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL) - -/* Data FIFO */ -#define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x))) - -/* Device-mode CSRs*/ -/* OTG device each endpoint interrupt register (OTG_DEACHINT) */ -/* Bits 31:18 - Reserved */ -#define OTG_DEACHHINT_OEP1INT (1 << 17) -/* Bits 16:2 - Reserved */ -#define OTG_DEACHHINT_IEP1INT (1 << 1) -/* Bit 0 - Reserved */ - -/* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */ -/* Bits 31:14 - Reserved */ -#define OTG_DIEPEACHMSK1_NAKM (1 << 13) -/* Bits 12:10 - Reserved */ -#define OTG_DIEPEACHMSK1_BIM (1 << 9) -#define OTG_DIEPEACHMSK1_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6) -#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5) -#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4) -#define OTG_DIEPEACHMSK1_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_DIEPEACHMSK1_EPDM (1 << 1) -#define OTG_DIEPEACHMSK1_XFRCM (1 << 0) - -/* OTG device each OUT endpoint-1 interrupt register (OTG_DOEPEACHMSK1) */ -/* Bits 31:15 - Reserved */ -#define OTG_DOEPEACHMSK1_NYETM (1 << 14) -#define OTG_DOEPEACHMSK1_NAKM (1 << 13) -#define OTG_DOEPEACHMSK1_BERRM (1 << 12) -/* Bits 11:10 - Reserved */ -#define OTG_DOEPEACHMSK1_BIM (1 << 9) -#define OTG_DOEPEACHMSK1_OPEM (1 << 8) -/* Bits 7:3 - Reserved */ -#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2) -#define OTG_DOEPEACHMSK1_EPDM (1 << 1) -#define OTG_DOEPEACHMSK1_XFRCM (1 << 0) - -/* Host-mode CSRs */ -/* OTG host channel-x split control register (OTG_HCSPLTx) */ -#define OTG_HCSPLT_SPLITEN (1 << 31) -/* Bits 30:17 - Reserved */ -#define OTG_HCSPLT_COMPLSPLT (1 << 16) -#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14) -#define OTG_HCSPLT_XACTPOS_BEGIN (0x2 << 14) -#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14) -#define OTG_HCSPLT_XACTPOS_END (0x1 << 14) -#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7) -#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0) - -#endif diff --git a/libopencm3/include/libopencm3/usb/hid.h b/libopencm3/include/libopencm3/usb/hid.h deleted file mode 100644 index 9296673..0000000 --- a/libopencm3/include/libopencm3/usb/hid.h +++ /dev/null @@ -1,91 +0,0 @@ -/** @defgroup usb_hid_defines USB HID Type Definitions - -@brief Defined Constants and Types for the USB HID Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __HID_H -#define __HID_H - -#include - -#define USB_CLASS_HID 3 - -/* USB HID 4.2 */ -#define USB_HID_SUBCLASS_NO 0 -#define USB_HID_SUBCLASS_BOOT_INTERFACE 1 - -/* USB HID 4.3 */ -#define USB_HID_INTERFACE_PROTOCOL_NONE 0 -#define USB_HID_INTERFACE_PROTOCOL_KEYBOARD 1 -#define USB_HID_INTERFACE_PROTOCOL_MOUSE 2 - -/* USB HID 7.1 */ -#define USB_HID_DT_HID 0x21 -#define USB_HID_DT_REPORT 0x22 -#define USB_HID_DT_PHYSICAL 0x23 -/** @deprecated Use @ref USB_HID_DT_HID */ -#define USB_DT_HID USB_HID_DT_HID -/** @deprecated Use @ref USB_HID_DT_REPORT */ -#define USB_DT_REPORT USB_HID_DT_REPORT - -/* USB HID 7.2 */ -#define USB_HID_REQ_TYPE_GET_REPORT 0x01 -#define USB_HID_REQ_TYPE_GET_IDLE 0x02 -#define USB_HID_REQ_TYPE_GET_PROTOCOL 0x03 -#define USB_HID_REQ_TYPE_SET_REPORT 0x09 -#define USB_HID_REQ_TYPE_SET_IDLE 0x0A -#define USB_HID_REQ_TYPE_SET_PROTOCOL 0x0B - -/* USB HID 7.2.1 */ -#define USB_HID_REPORT_TYPE_INPUT 1 -#define USB_HID_REPORT_TYPE_OUTPUT 2 -#define USB_HID_REPORT_TYPE_FEATURE 3 - -/* USB HID 7.2.5 */ -#define USB_HID_PROTOCOL_BOOT 0 -#define USB_HID_PROTOCOL_REPORT 1 - -struct usb_hid_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdHID; - uint8_t bCountryCode; - uint8_t bNumDescriptors; -} __attribute__((packed)); - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/midi.h b/libopencm3/include/libopencm3/usb/midi.h deleted file mode 100644 index 1110141..0000000 --- a/libopencm3/include/libopencm3/usb/midi.h +++ /dev/null @@ -1,190 +0,0 @@ -/** @defgroup usb_audio_defines USB MIDI Type Definitions - -@brief Defined Constants and Types for the USB MIDI Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2014 -Daniel Thompson - -@date 19 April 2014 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Daniel Thompson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef LIBOPENCM3_USB_MIDI_H -#define LIBOPENCM3_USB_MIDI_H - -/* - * Definitions from the USB_MIDI_ or usb_midi_ namespace come from: - * "Universal Serial Bus Class Definitions for MIDI Devices, Revision 1.0" - */ - -/* Appendix A.1: MS Class-Specific Interface Descriptor Subtypes */ -#define USB_MIDI_SUBTYPE_MS_DESCRIPTOR_UNDEFINED 0x00 -#define USB_MIDI_SUBTYPE_MS_HEADER 0x01 -#define USB_MIDI_SUBTYPE_MIDI_IN_JACK 0x02 -#define USB_MIDI_SUBTYPE_MIDI_OUT_JACK 0x03 -#define USB_MIDI_SUBTYPE_MIDI_ELEMENT 0x04 - -/* Appendix A.2: MS Class-Specific Endpoint Descriptor Subtypes */ -#define USB_MIDI_SUBTYPE_DESCRIPTOR_UNDEFINED 0x00 -#define USB_MIDI_SUBTYPE_MS_GENERAL 0x01 - -/* Appendix A.3: MS MIDI IN and OUT Jack types */ -#define USB_MIDI_JACK_TYPE_UNDEFINED 0x00 -#define USB_MIDI_JACK_TYPE_EMBEDDED 0x01 -#define USB_MIDI_JACK_TYPE_EXTERNAL 0x02 - -/* Appendix A.5.1 Endpoint Control Selectors */ -#define USB_MIDI_EP_CONTROL_UNDEFINED 0x00 -#define USB_MIDI_ASSOCIATION_CONTROL 0x01 - - -/* Table 6-2: Class-Specific MS Interface Header Descriptor */ -struct usb_midi_header_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint16_t bcdMSC; - uint16_t wTotalLength; -} __attribute__((packed)); - -/* Table 6-3: MIDI IN Jack Descriptor */ -struct usb_midi_in_jack_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bJackType; - uint8_t bJackID; - uint8_t iJack; -} __attribute__((packed)); - -/* Table 6-4: MIDI OUT Jack Descriptor (head) */ -struct usb_midi_out_jack_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bJackType; - uint8_t bJackID; - uint8_t bNrInputPins; - /* ... */ -} __attribute__((packed)); - -/* Table 6.4: MIDI OUT Jack Descriptor (body) */ -struct usb_midi_out_jack_descriptor_body { - /* ... */ - uint8_t baSourceID; - uint8_t baSourcePin; - /* ... */ -} __attribute__((packed)); - -/* Table 6.4: MIDI OUT Jack Descriptor (tail) */ -struct usb_midi_out_jack_descriptor_tail { - /* ... */ - uint8_t iJack; -} __attribute__((packed)); - -/* Table 6.4: MIDI OUT Jack Descriptor (single) - * - * This structure is a convenience covering the (normal) case where - * there is only one input pin. - */ -struct usb_midi_out_jack_descriptor { - struct usb_midi_out_jack_descriptor_head head; - struct usb_midi_out_jack_descriptor_body source[1]; - struct usb_midi_out_jack_descriptor_tail tail; -} __attribute__((packed)); - -/* Table 6-5: MIDI Element Descriptor (head) */ -struct usb_midi_element_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bElementID; - uint8_t bNrInputPins; - /* ... */ -} __attribute__((packed)); - -/* Table 6-5: MIDI Element Descriptor (body) */ -struct usb_midi_element_descriptor_body { - /* ... */ - uint8_t baSourceID; - uint8_t baSourcePin; - /* ... */ -} __attribute__((packed)); - -/* Table 6-5: MIDI Element Descriptor (tail) */ -struct usb_midi_element_descriptor_tail { - /* ... */ - uint8_t bNrOutputPins; - uint8_t bInTerminalLink; - uint8_t bOutTerminalLink; - uint8_t bElCapsSize; - uint16_t bmElementCaps; /* host cannot assume this is 16-bit but device - can (since highest defined bitmap value in - v1.0 is bit 11) */ - uint8_t iElement; -} __attribute__((packed)); - -/* Table 6-5: MIDI Element Descriptor (single) - * - * This structure is a convenience covering the (common) case where - * there is only one input pin. - */ -struct usb_midi_element_descriptor { - struct usb_midi_element_descriptor_head head; - struct usb_midi_element_descriptor_body source[1]; - struct usb_midi_element_descriptor_tail tail; -} __attribute__((packed)); - -/* Table 6-7: Class-specific MS Bulk Data Endpoint Descriptor (head) */ -struct usb_midi_endpoint_descriptor_head { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubType; - uint8_t bNumEmbMIDIJack; -} __attribute__((packed)); - -/* Table 6-7: Class-specific MS Bulk Data Endpoint Descriptor (body) */ -struct usb_midi_endpoint_descriptor_body { - uint8_t baAssocJackID; -} __attribute__((packed)); - -/* Table 6.7: Class-specific MS Bulk Data Endpoint Descriptor (single) - * - * This structure is a convenience covering the (normal) case where - * there is only one input pin. - */ -struct usb_midi_endpoint_descriptor { - struct usb_midi_endpoint_descriptor_head head; - struct usb_midi_endpoint_descriptor_body jack[1]; -} __attribute__((packed)); - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/msc.h b/libopencm3/include/libopencm3/usb/msc.h deleted file mode 100644 index cf9c54a..0000000 --- a/libopencm3/include/libopencm3/usb/msc.h +++ /dev/null @@ -1,93 +0,0 @@ -/** @defgroup usb_msc_defines USB MSC Type Definitions - -@brief Defined Constants and Types for the USB MSC Type Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2013 -Weston Schmidt -Pavol Rusnak - -@date 27 June 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Weston Schmidt - * Copyright (C) 2013 Pavol Rusnak - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __MSC_H -#define __MSC_H - -typedef struct _usbd_mass_storage usbd_mass_storage; - -/* Definitions of Mass Storage Class from: - * - * (A) "Universal Serial Bus Mass Storage Class Bulk-Only Transport - * Revision 1.0" - * - * (B) "Universal Serial Bus Mass Storage Class Specification Overview - * Revision 1.0" - */ - -/* (A) Table 4.5: Mass Storage Device Class Code */ -#define USB_CLASS_MSC 0x08 - -/* (B) Table 2.1: Class Subclass Code */ -#define USB_MSC_SUBCLASS_RBC 0x01 -#define USB_MSC_SUBCLASS_ATAPI 0x02 -#define USB_MSC_SUBCLASS_UFI 0x04 -#define USB_MSC_SUBCLASS_SCSI 0x06 -#define USB_MSC_SUBCLASS_LOCKABLE 0x07 -#define USB_MSC_SUBCLASS_IEEE1667 0x08 - -/* (B) Table 3.1 Mass Storage Interface Class Control Protocol Codes */ -#define USB_MSC_PROTOCOL_CBI 0x00 -#define USB_MSC_PROTOCOL_CBI_ALT 0x01 -#define USB_MSC_PROTOCOL_BBB 0x50 - -/* (B) Table 4.1 Mass Storage Request Codes */ -#define USB_MSC_REQ_CODES_ADSC 0x00 -#define USB_MSC_REQ_CODES_GET 0xFC -#define USB_MSC_REQ_CODES_PUT 0xFD -#define USB_MSC_REQ_CODES_GML 0xFE -#define USB_MSC_REQ_CODES_BOMSR 0xFF - -/* (A) Table 3.1/3.2 Class-Specific Request Codes */ -#define USB_MSC_REQ_BULK_ONLY_RESET 0xFF -#define USB_MSC_REQ_GET_MAX_LUN 0xFE - -usbd_mass_storage *usb_msc_init(usbd_device *usbd_dev, - uint8_t ep_in, uint8_t ep_in_size, - uint8_t ep_out, uint8_t ep_out_size, - const char *vendor_id, - const char *product_id, - const char *product_revision_level, - const uint32_t block_count, - int (*read_block)(uint32_t lba, uint8_t *copy_to), - int (*write_block)(uint32_t lba, const uint8_t *copy_from)); - -#endif - -/**@}*/ diff --git a/libopencm3/include/libopencm3/usb/usbd.h b/libopencm3/include/libopencm3/usb/usbd.h deleted file mode 100644 index d245101..0000000 --- a/libopencm3/include/libopencm3/usb/usbd.h +++ /dev/null @@ -1,240 +0,0 @@ -/** @defgroup usb_driver_defines USB Drivers - -@brief Defined Constants and Types for the USB Drivers - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 -Gareth McMullin - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __USBD_H -#define __USBD_H - -#include - -BEGIN_DECLS - - -enum usbd_request_return_codes { - USBD_REQ_NOTSUPP = 0, - USBD_REQ_HANDLED = 1, - USBD_REQ_NEXT_CALLBACK = 2, -}; - -typedef struct _usbd_driver usbd_driver; -typedef struct _usbd_device usbd_device; - -extern const usbd_driver st_usbfs_v1_usb_driver; -extern const usbd_driver stm32f107_usb_driver; -extern const usbd_driver stm32f207_usb_driver; -extern const usbd_driver st_usbfs_v2_usb_driver; -#define otgfs_usb_driver stm32f107_usb_driver -#define otghs_usb_driver stm32f207_usb_driver -extern const usbd_driver efm32lg_usb_driver; -extern const usbd_driver efm32hg_usb_driver; -extern const usbd_driver lm4f_usb_driver; - -/* */ -/** - * Main initialization entry point. - * - * Initialize the USB firmware library to implement the USB device described - * by the descriptors provided. - * - * It is required that the 48MHz USB clock is already available. - * - * @param driver TODO - * @param dev Pointer to USB device descriptor. This must not be changed while - * the device is in use. - * @param conf Pointer to array of USB configuration descriptors. These must - * not be changed while the device is in use. The length of this - * array is determined by the bNumConfigurations field in the - * device descriptor. - * @param strings Pointer to an array of strings for USB string descriptors. - * Referenced in @e iSomething fields, e.g. @a iManufacturer. - * Since a zero index means "no string", an iSomething value of - * 1 refers strings[0]. - * @param num_strings Number of items in @a strings array. - * @param control_buffer Pointer to array that would hold the data - * received during control requests with DATA - * stage - * @param control_buffer_size Size of control_buffer - * @return the usb device initialized for use. (currently cannot fail). - * - * To place @a strings entirely into Flash/read-only memory, use - * @code static const * const strings[] = { ... }; @endcode - * (note the double @e const.) The first @e const refers to the strings - * while the second @e const refers to the array. - */ -extern usbd_device * usbd_init(const usbd_driver *driver, - const struct usb_device_descriptor *dev, - const struct usb_config_descriptor *conf, - const char * const *strings, int num_strings, - uint8_t *control_buffer, - uint16_t control_buffer_size); - -/** Registers a reset callback */ -extern void usbd_register_reset_callback(usbd_device *usbd_dev, - void (*callback)(void)); -/** Registers a suspend callback */ -extern void usbd_register_suspend_callback(usbd_device *usbd_dev, - void (*callback)(void)); -/** Registers a resume callback */ -extern void usbd_register_resume_callback(usbd_device *usbd_dev, - void (*callback)(void)); -/** Registers a SOF callback */ -extern void usbd_register_sof_callback(usbd_device *usbd_dev, - void (*callback)(void)); - -typedef void (*usbd_control_complete_callback)(usbd_device *usbd_dev, - struct usb_setup_data *req); - -typedef enum usbd_request_return_codes (*usbd_control_callback)( - usbd_device *usbd_dev, - struct usb_setup_data *req, uint8_t **buf, uint16_t *len, - usbd_control_complete_callback *complete); - -typedef void (*usbd_set_config_callback)(usbd_device *usbd_dev, - uint16_t wValue); - -typedef void (*usbd_set_altsetting_callback)(usbd_device *usbd_dev, - uint16_t wIndex, uint16_t wValue); - -typedef void (*usbd_endpoint_callback)(usbd_device *usbd_dev, uint8_t ep); - -/* */ -/** Registers a control callback. - * - * Since the list of user control callbacks is cleared every time - * device configuration is set (inside usb_standard_set_configuration()), - * control callback registration must happen inside (or after) the - * config callback. The specified callback will be called if - * (type == (bmRequestType & type_mask)). - * @sa usbd_register_set_config_callback - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param type Handled request type - * @param type_mask Mask to apply before matching request type - * @param callback your desired callback function - * @return 0 if successful - */ -extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, - uint8_t type_mask, - usbd_control_callback callback); - -/* */ -/** Registers a "Set Config" callback - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param callback your desired callback function - * @return 0 if successful or already existed. - * @return -1 if no more space was available for callbacks. - */ -extern int usbd_register_set_config_callback(usbd_device *usbd_dev, - usbd_set_config_callback callback); -/** Registers a "Set Interface" (alternate setting) callback - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param callback your desired callback function - */ -extern void usbd_register_set_altsetting_callback(usbd_device *usbd_dev, - usbd_set_altsetting_callback callback); - -/* Functions to be provided by the hardware abstraction layer */ -extern void usbd_poll(usbd_device *usbd_dev); - -/** Disconnect, if supported by the driver - * - * This function is implemented as weak function and can be replaced by an - * application specific version to handle chips that don't have built-in - * handling for this (e.g. STM32F1.) - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param disconnected true to request a disconnect - */ -extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected); - -/** Setup an endpoint - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr Full EP address including direction (e.g. 0x01 or 0x81) - * @param type Value for bmAttributes (USB_ENDPOINT_ATTR_*) - * @param max_size Endpoint max size - * @param callback your desired callback function - * @note The stack only supports 8 endpoints, 0..7, so don't try - * and use arbitrary addresses here, even though USB itself would allow this. - * Not all backends support arbitrary addressing anyway. - */ -extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, - uint16_t max_size, usbd_endpoint_callback callback); - -/** Write a packet - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr EP address (direction is ignored) - * @param buf pointer to user data to write - * @param len # of bytes - * @return 0 if failed, len if successful - */ -extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, - const void *buf, uint16_t len); - -/** Read a packet - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr EP address - * @param buf user buffer that will receive data - * @param len # of bytes - * @return Actual # of bytes read - */ -extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, - void *buf, uint16_t len); -/** Set/clear STALL condition on an endpoint - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr Full EP address (with direction bit) - * @param stall if 0, clear STALL, else set stall. - */ -extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, - uint8_t stall); - -/** Get STALL status of an endpoint - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr Full EP address (with direction bit) - * @return nonzero if endpoint is stalled - */ -extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); - -/** Set an Out endpoint to NAK - * @param usbd_dev the usb device handle returned from @ref usbd_init - * @param addr EP address - * @param nak if nonzero, set NAK - */ -extern void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); - -END_DECLS - -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/usb/usbstd.h b/libopencm3/include/libopencm3/usb/usbstd.h deleted file mode 100644 index 33bdd8b..0000000 --- a/libopencm3/include/libopencm3/usb/usbstd.h +++ /dev/null @@ -1,278 +0,0 @@ -/** @defgroup usb_type_defines USB Standard Structure Definitions - -@brief Defined Constants and Types for the USB Standard Structure -Definitions - -@ingroup USB_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 -Gareth McMullin - -@date 10 March 2013 - -A set of structure definitions for the USB control structures -defined in chapter 9 of the "Universal Serial Bus Specification Revision 2.0" -Available from the USB Implementers Forum - http://www.usb.org/ - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#ifndef __USBSTD_H -#define __USBSTD_H - -#include -#include - -/* - * This file contains structure definitions for the USB control structures - * defined in chapter 9 of the "Universal Serial Bus Specification Revision 2.0" - * Available from the USB Implementers Forum - http://www.usb.org/ - */ - -/* USB Setup Data structure - Table 9-2 */ -struct usb_setup_data { - uint8_t bmRequestType; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} __attribute__((packed)); - -/* Class Definition */ -#define USB_CLASS_VENDOR 0xFF - -/* bmRequestType bit definitions */ -/* bit 7 : direction */ -#define USB_REQ_TYPE_DIRECTION 0x80 -#define USB_REQ_TYPE_IN 0x80 -#define USB_REQ_TYPE_OUT 0x0 -/* bits 6..5 : type */ -#define USB_REQ_TYPE_TYPE 0x60 -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -/* bits 4..0 : recipient */ -#define USB_REQ_TYPE_RECIPIENT 0x1F -#define USB_REQ_TYPE_DEVICE 0x00 -#define USB_REQ_TYPE_INTERFACE 0x01 -#define USB_REQ_TYPE_ENDPOINT 0x02 -#define USB_REQ_TYPE_OTHER 0x03 - -/* USB Standard Request Codes - Table 9-4 */ -#define USB_REQ_GET_STATUS 0 -#define USB_REQ_CLEAR_FEATURE 1 -/* Reserved for future use: 2 */ -#define USB_REQ_SET_FEATURE 3 -/* Reserved for future use: 3 */ -#define USB_REQ_SET_ADDRESS 5 -#define USB_REQ_GET_DESCRIPTOR 6 -#define USB_REQ_SET_DESCRIPTOR 7 -#define USB_REQ_GET_CONFIGURATION 8 -#define USB_REQ_SET_CONFIGURATION 9 -#define USB_REQ_GET_INTERFACE 10 -#define USB_REQ_SET_INTERFACE 11 -#define USB_REQ_SET_SYNCH_FRAME 12 - -/* USB Descriptor Types - Table 9-5 */ -#define USB_DT_DEVICE 1 -#define USB_DT_CONFIGURATION 2 -#define USB_DT_STRING 3 -#define USB_DT_INTERFACE 4 -#define USB_DT_ENDPOINT 5 -#define USB_DT_DEVICE_QUALIFIER 6 -#define USB_DT_OTHER_SPEED_CONFIGURATION 7 -#define USB_DT_INTERFACE_POWER 8 -/* From ECNs */ -#define USB_DT_OTG 9 -#define USB_DT_DEBUG 10 -#define USB_DT_INTERFACE_ASSOCIATION 11 - -/* USB Standard Feature Selectors - Table 9-6 */ -#define USB_FEAT_ENDPOINT_HALT 0 -#define USB_FEAT_DEVICE_REMOTE_WAKEUP 1 -#define USB_FEAT_TEST_MODE 2 - -/* Information Returned by a GetStatus() Request to a Device - Figure 9-4 */ -#define USB_DEV_STATUS_SELF_POWERED 0x01 -#define USB_DEV_STATUS_REMOTE_WAKEUP 0x02 - -/* USB Standard Device Descriptor - Table 9-8 */ -struct usb_device_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint16_t idVendor; - uint16_t idProduct; - uint16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} __attribute__((packed)); - -#define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor) - -/* USB Device_Qualifier Descriptor - Table 9-9 - * Not used in this implementation. - */ -struct usb_device_qualifier_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} __attribute__((packed)); - -/* This is only defined as a top level named struct to improve c++ - * compatibility. You should never need to instance this struct - * in user code! */ -struct usb_interface { - uint8_t *cur_altsetting; - uint8_t num_altsetting; - const struct usb_iface_assoc_descriptor *iface_assoc; - const struct usb_interface_descriptor *altsetting; -}; - -/* USB Standard Configuration Descriptor - Table 9-10 */ -struct usb_config_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; - - /* Descriptor ends here. The following are used internally: */ - const struct usb_interface *interface; -} __attribute__((packed)); -#define USB_DT_CONFIGURATION_SIZE 9 - -/* USB Configuration Descriptor bmAttributes bit definitions */ -#define USB_CONFIG_ATTR_DEFAULT 0x80 /** always required (USB2.0 table 9-10) */ -#define USB_CONFIG_ATTR_SELF_POWERED 0x40 -#define USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20 - -/* Other Speed Configuration is the same as Configuration Descriptor. - * - Table 9-11 - */ - -/* USB Standard Interface Descriptor - Table 9-12 */ -struct usb_interface_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; - - /* Descriptor ends here. The following are used internally: */ - const struct usb_endpoint_descriptor *endpoint; - const void *extra; - int extralen; -} __attribute__((packed)); -#define USB_DT_INTERFACE_SIZE 9 - -/* USB Standard Endpoint Descriptor - Table 9-13 */ -struct usb_endpoint_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; - - /* Descriptor ends here. The following are used internally: */ - const void *extra; - int extralen; -} __attribute__((packed)); -#define USB_DT_ENDPOINT_SIZE 7 - -/* USB bEndpointAddress helper macros */ -#define USB_ENDPOINT_ADDR_OUT(x) (x) -#define USB_ENDPOINT_ADDR_IN(x) (0x80 | (x)) - -/* USB Endpoint Descriptor bmAttributes bit definitions - Table 9-13 */ -/* bits 1..0 : transfer type */ -#define USB_ENDPOINT_ATTR_CONTROL 0x00 -#define USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01 -#define USB_ENDPOINT_ATTR_BULK 0x02 -#define USB_ENDPOINT_ATTR_INTERRUPT 0x03 -#define USB_ENDPOINT_ATTR_TYPE 0x03 -/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ -#define USB_ENDPOINT_ATTR_NOSYNC 0x00 -#define USB_ENDPOINT_ATTR_ASYNC 0x04 -#define USB_ENDPOINT_ATTR_ADAPTIVE 0x08 -#define USB_ENDPOINT_ATTR_SYNC 0x0C -#define USB_ENDPOINT_ATTR_SYNCTYPE 0x0C -/* bits 5..4 : usage type (only if ISOCHRONOUS) */ -#define USB_ENDPOINT_ATTR_DATA 0x00 -#define USB_ENDPOINT_ATTR_FEEDBACK 0x10 -#define USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 -#define USB_ENDPOINT_ATTR_USAGETYPE 0x30 - -/* Table 9-15 specifies String Descriptor Zero. - * Table 9-16 specified UNICODE String Descriptor. - */ -struct usb_string_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wData[]; -} __attribute__((packed)); - -/* From ECN: Interface Association Descriptors, Table 9-Z */ -struct usb_iface_assoc_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bFirstInterface; - uint8_t bInterfaceCount; - uint8_t bFunctionClass; - uint8_t bFunctionSubClass; - uint8_t bFunctionProtocol; - uint8_t iFunction; -} __attribute__((packed)); -#define USB_DT_INTERFACE_ASSOCIATION_SIZE \ - sizeof(struct usb_iface_assoc_descriptor) - -enum usb_language_id { - USB_LANGID_ENGLISH_US = 0x409, -}; -#endif - -/**@}*/ - diff --git a/libopencm3/include/libopencm3/vf6xx/anadig.h b/libopencm3/include/libopencm3/vf6xx/anadig.h deleted file mode 100644 index 594da96..0000000 --- a/libopencm3/include/libopencm3/vf6xx/anadig.h +++ /dev/null @@ -1,224 +0,0 @@ -/** @defgroup anadig_defines ANADIG Defines - * - * @brief Defined Constants and Types for the VF6xx Analog components - * control digital interface - * - * @ingroup VF6xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Stefan Agner - * - * @date 01 July 2014 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_ANADIG_H -#define LIBOPENCM3_ANADIG_H - -#include -#include - -/* --- ANADIG registers ---------------------------------------------------- */ - -#define ANADIG_PLL3_CTRL MMIO32(ANADIG_BASE + 0x010) -#define ANADIG_PLL7_CTRL MMIO32(ANADIG_BASE + 0x020) -#define ANADIG_PLL2_CTRL MMIO32(ANADIG_BASE + 0x030) -#define ANADIG_PLL2_SS MMIO32(ANADIG_BASE + 0x040) -#define ANADIG_PLL2_NUM MMIO32(ANADIG_BASE + 0x050) -#define ANADIG_PLL2_DENOM MMIO32(ANADIG_BASE + 0x060) -#define ANADIG_PLL4_CTRL MMIO32(ANADIG_BASE + 0x070) -#define ANADIG_PLL4_NUM MMIO32(ANADIG_BASE + 0x080) -#define ANADIG_PLL4_DENOM MMIO32(ANADIG_BASE + 0x090) -#define ANADIG_PLL6_CTRL MMIO32(ANADIG_BASE + 0x0A0) -#define ANADIG_PLL6_NUM MMIO32(ANADIG_BASE + 0x0B0) -#define ANADIG_PLL6_DENOM MMIO32(ANADIG_BASE + 0x0C0) -#define ANADIG_PLL5_CTRL MMIO32(ANADIG_BASE + 0x0E0) -#define ANADIG_PLL3_PFD MMIO32(ANADIG_BASE + 0x0F0) -#define ANADIG_PLL2_PFD MMIO32(ANADIG_BASE + 0x100) -#define ANADIG_REG_1P1 MMIO32(ANADIG_BASE + 0x110) -#define ANADIG_REG_3P0 MMIO32(ANADIG_BASE + 0x120) -#define ANADIG_REG_2P5 MMIO32(ANADIG_BASE + 0x130) -#define ANADIG_ANA_MISC0 MMIO32(ANADIG_BASE + 0x150) -#define ANADIG_ANA_MISC1 MMIO32(ANADIG_BASE + 0x160) -#define ANADIG_ANADIG_DIGPROG MMIO32(ANADIG_BASE + 0x260) -#define ANADIG_PLL1_CTRL MMIO32(ANADIG_BASE + 0x270) -#define ANADIG_PLL1_SS MMIO32(ANADIG_BASE + 0x280) -#define ANADIG_PLL1_NUM MMIO32(ANADIG_BASE + 0x290) -#define ANADIG_PLL1_DENOM MMIO32(ANADIG_BASE + 0x2A0) -#define ANADIG_PLL1_PFD MMIO32(ANADIG_BASE + 0x2B0) -#define ANADIG_PLL_LOCK MMIO32(ANADIG_BASE + 0x2C0) - -/* --- ANADIG values -....-------------------------------------------------- */ - -/* ANADIG_PLL3_CTRL: PLL3 Control Register (480MHz PLL of USB0) */ -#define ANADIG_PLL3_CTRL_LOCK (1 << 31) -#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL3_CTRL_POWER (1 << 12) -#define ANADIG_PLL3_CTRL_EN_USB_CLKS (1 << 6) -#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) - -/* ANADIG_PLL7_CTRL: PLL7 Control Register (480MHz PLL of USB1) */ -#define ANADIG_PLL7_CTRL_LOCK (1 << 31) -#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL7_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL7_CTRL_POWER (1 << 12) -#define ANADIG_PLL7_CTRL_EN_USB_CLKS (1 << 6) -#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) - -/* ANADIG_PLL2_CTRL: PLL2 Control Register (528MHz PLL) */ -#define ANADIG_PLL2_CTRL_LOCK (1 << 31) -#define ANADIG_PLL2_CTRL_PFD_OFFSET_EN (1 << 18) -#define ANADIG_PLL2_CTRL_DITHER_ENABLE (1 << 17) -#define ANADIG_PLL2_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL2_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL2_CTRL_DIV_SELECT (1 << 1) - -/* ANADIG_PLL2_SS: PLL2 Spread Spectrum definition register */ -#define ANADIG_PLL2_SS_STOP_MASK (0xffff << 16) -#define ANADIG_PLL2_SS_ENABLE (1 << 15) -#define ANADIG_PLL2_SS_STEP_MASK 0x8fff - -/* ANADIG_PLL2_NUM: PLL2 Numerator definition register */ -#define ANADIG_PLL2_NUM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL2_DENOM: PLL2 Denominator definition register */ -#define ANADIG_PLL2_DENOM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL4_CTRL: PLL4 Control Register (audio PLL) */ -#define ANADIG_PLL4_CTRL_LOCK (1 << 31) -#define ANADIG_PLL4_CTRL_PFD_OFFSET_EN (1 << 18) -#define ANADIG_PLL4_CTRL_DITHER_ENABLE (1 << 17) -#define ANADIG_PLL4_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL4_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL4_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL4_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL4_CTRL_DIV_SELECT_MASK (0x7f) - -/* ANADIG_PLL4_NUM: PLL4 Numerator definition register */ -#define ANADIG_PLL4_NUM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL4_DENOM: PLL4 Denominator definition register */ -#define ANADIG_PLL4_DENOM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL6_CTRL: PLL6 Control Register (video PLL) */ -#define ANADIG_PLL6_CTRL_LOCK (1 << 31) -#define ANADIG_PLL6_CTRL_PFD_OFFSET_EN (1 << 18) -#define ANADIG_PLL6_CTRL_DITHER_ENABLE (1 << 17) -#define ANADIG_PLL6_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL6_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL6_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL6_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL6_CTRL_DIV_SELECT_MASK (0x7f) - -/* ANADIG_PLL6_NUM: PLL6 Numerator definition register */ -#define ANADIG_PLL6_NUM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL6_DENOM: PLL6 Denominator definition register */ -#define ANADIG_PLL6_DENOM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL5_CTRL: PLL5 Control Register (video PLL) */ -#define ANADIG_PLL5_CTRL_LOCK (1 << 31) -#define ANADIG_PLL5_CTRL_PFD_OFFSET_EN (1 << 18) -#define ANADIG_PLL5_CTRL_DITHER_ENABLE (1 << 17) -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL5_CTRL_DIV_SELECT_MASK (0x3) - -/* ANADIG_PLL_PFD: PLL1/PLL2/PLL3 PFD Clocks */ -#define ANADIG_PLL_PFD4_CLKGATE (1 << 31) -#define ANADIG_PLL_PFD4_STABLE (1 << 30) -#define ANADIG_PLL_PFD4_FRAC_SHIFT 24 -#define ANADIG_PLL_PFD4_FRAC_MASK (0x3f << 24) -#define ANADIG_PLL_PFD3_CLKGATE (1 << 23) -#define ANADIG_PLL_PFD3_STABLE (1 << 22) -#define ANADIG_PLL_PFD3_FRAC_SHIFT 16 -#define ANADIG_PLL_PFD3_FRAC_MASK (0x3f << 16) -#define ANADIG_PLL_PFD2_CLKGATE (1 << 15) -#define ANADIG_PLL_PFD2_STABLE (1 << 14) -#define ANADIG_PLL_PFD2_FRAC_SHIFT 8 -#define ANADIG_PLL_PFD2_FRAC_MASK (0x3f << 8) -#define ANADIG_PLL_PFD1_CLKGATE (1 << 7) -#define ANADIG_PLL_PFD1_STABLE (1 << 6) -#define ANADIG_PLL_PFD1_FRAC_SHIFT 0 -#define ANADIG_PLL_PFD1_FRAC_MASK (0x3f << 0) - -/* AANADIG_ANA_MISC0: miscellaneous analog blocks */ -#define ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17) -#define ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) -#define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) -#define ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) -#define ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) -#define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) -#define ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) -#define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) -#define ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0) - -/* AANADIG_ANA_MISC0: miscellaneous analog blocks */ -#define ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30) -#define ANADIG_ANA_MISC1_IRQ_TEMPSENSE (1 << 29) -#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) -#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) - -/* AANADIG_ANA_DIGPROG: Digital Program register */ -#define ANADIG_ANADIG_DIGPROG_MAJOR_MASK (0xffff << 8) -#define ANADIG_ANADIG_DIGPROG_MINOR_MASK (0xff << 0) - -/* ANADIG_PLL1_CTRL: PLL1 Control Register (video PLL) */ -#define ANADIG_PLL1_CTRL_LOCK (1 << 31) -#define ANADIG_PLL1_CTRL_PFD_OFFSET_EN (1 << 18) -#define ANADIG_PLL1_CTRL_DITHER_ENABLE (1 << 17) -#define ANADIG_PLL1_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL1_CTRL_BYPASS_CLK_SRC (1 << 14) -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL1_CTRL_DIV_SELECT (1 << 1) - -/* ANADIG_PLL1_SS: PLL1 Spread Spectrum definition register */ -#define ANADIG_PLL1_SS_STOP_MASK (0xffff << 16) -#define ANADIG_PLL1_SS_ENABLE (1 << 15) -#define ANADIG_PLL1_SS_STEP_MASK 0x8fff - -/* ANADIG_PLL1_NUM: PLL1 Numerator definition register */ -#define ANADIG_PLL1_NUM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL1_DENOM: PLL1 Denominator definition register */ -#define ANADIG_PLL1_DENOM_MFN_MASK 0x3fffffff - -/* ANADIG_PLL_LOCK: PLL Lock Register */ -#define ANADIG_PLL_LOCK_PLL1 (1 << 6) -#define ANADIG_PLL_LOCK_PLL2 (1 << 5) -#define ANADIG_PLL_LOCK_PLL4 (1 << 4) -#define ANADIG_PLL_LOCK_PLL6 (1 << 3) -#define ANADIG_PLL_LOCK_PLL5 (1 << 2) -#define ANADIG_PLL_LOCK_PLL3 (1 << 1) -#define ANADIG_PLL_LOCK_PLL7 (1 << 0) - -#endif diff --git a/libopencm3/include/libopencm3/vf6xx/ccm.h b/libopencm3/include/libopencm3/vf6xx/ccm.h deleted file mode 100644 index b0a2569..0000000 --- a/libopencm3/include/libopencm3/vf6xx/ccm.h +++ /dev/null @@ -1,351 +0,0 @@ -/** @defgroup ccm_defines CCM Defines - * - * @brief Defined Constants and Types for the VF6xx Common Clock Module - * - * @ingroup VF6xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Stefan Agner - * - * @date 30 June 2014 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CCM_H -#define LIBOPENCM3_CCM_H - -#include -#include - -/* --- CCM registers ------------------------------------------------------- */ - -#define CCM_CCR MMIO32(CCM_BASE + 0x00) -#define CCM_CSR MMIO32(CCM_BASE + 0x04) -#define CCM_CCSR MMIO32(CCM_BASE + 0x08) -#define CCM_CACRR MMIO32(CCM_BASE + 0x0C) -#define CCM_CSCMR1 MMIO32(CCM_BASE + 0x10) -#define CCM_CSCDR1 MMIO32(CCM_BASE + 0x14) -#define CCM_CSCDR2 MMIO32(CCM_BASE + 0x18) -#define CCM_CSCDR3 MMIO32(CCM_BASE + 0x1C) -#define CCM_CSCMR2 MMIO32(CCM_BASE + 0x20) - -#define CCM_CTOR MMIO32(CCM_BASE + 0x28) -#define CCM_CLPCR MMIO32(CCM_BASE + 0x2C) -#define CCM_CISR MMIO32(CCM_BASE + 0x30) -#define CCM_CIMR MMIO32(CCM_BASE + 0x34) -#define CCM_CCOSR MMIO32(CCM_BASE + 0x38) -#define CCM_CGPR MMIO32(CCM_BASE + 0x3C) -#define CCM_CCGR(offset) MMIO32(CCM_BASE + 0x40 + (offset)) -#define CCM_CMEOR(ovrr) MMIO32(CCM_BASE + 0x70 + (4 * (ovrr))) -#define CCM_CPPDSR MMIO32(CCM_BASE + 0x88) - -#define CCM_CCOWR MMIO32(CCM_BASE + 0x8C) -#define CCM_CCPGR(pcgr) MMIO32(CCM_BASE + 0x90 + (4 * (pcgr))) - -/* --- CCM values -....----------------------------------------------------- */ - -/* CCR: CCM Control Register */ -#define CCM_CCR_FIRC_EN (1 << 16) -#define CCM_CCR_FXOSC_EN (1 << 12) -#define CCM_CCR_OSCNT_MASK 0xff - -/* CSR: CCM Status Register */ -#define CCM_CSR_FXOSC_RDY (1 << 5) - -/* CCSR: CCM Clock Switcher Register */ -#define CCM_CCSR_PLL3_PFDN4_EN (1 << 31) -#define CCM_CCSR_PLL3_PFDN3_EN (1 << 30) -#define CCM_CCSR_PLL3_PFDN2_EN (1 << 29) -#define CCM_CCSR_PLL3_PFDN1_EN (1 << 28) - -#define CCM_CCSR_DAP_EN (1 << 24) - -/* PLL1/PLL2 PFD SEL definition */ -#define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT 19 -#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) -#define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT 16 -#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) - -#define CCM_CCSR_PLL_PFD_CLK_SEL_MAIN 0x0 -#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD1 0x1 -#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD2 0x2 -#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD3 0x3 -#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD4 0x4 - -#define CCM_CCSR_PLL2_PFDN4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFDN3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFDN2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFDN1_EN (1 << 12) - -#define CCM_CCSR_PLL1_PFDN4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFDN3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFDN2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFDN1_EN (1 << 8) - -#define CCM_CCSR_DDRC_CLK_SEL (1 << 7) -#define CCM_CCSR_FAST_CLK_SEL (1 << 6) -#define CCM_CCSR_SLOW_CLK_SEL (1 << 5) - -#define CCM_CCSR_SYS_CLK_SEL_SHIFT 0 -#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 -#define CCM_CCSR_SYS_CLK_SEL_FAST 0x0 -#define CCM_CCSR_SYS_CLK_SEL_SLOW 0x1 -#define CCM_CCSR_SYS_CLK_SEL_PLL2_PFD 0x2 -#define CCM_CCSR_SYS_CLK_SEL_PLL2 0x3 -#define CCM_CCSR_SYS_CLK_SEL_PLL1_PFD 0x4 -#define CCM_CCSR_SYS_CLK_SEL_PLL3 0x5 - -/* CACRR: ARM Clock Root Register */ -#define CCM_CACRR_FLEX_CLK_DIV_SHIFT 22 -#define CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22) -#define CCM_CACRR_PLL6_CLK_DIV (1 << 21) -#define CCM_CACRR_PLL3_CLK_DIV (1 << 20) -#define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT 16 -#define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK (0x3 << 16) -#define CCM_CACRR_IPG_CLK_DIV_SHIFT 11 -#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) -#define CCM_CACRR_PLL4_CLK_DIV_SHIFT 6 -#define CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6) -#define CCM_CACRR_BUS_CLK_DIV_SHIFT 3 -#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) -#define CCM_CACRR_ARM_CLK_DIV_SHIFT 0 -#define CCM_CACRR_ARM_CLK_DIV_MASK (0x7 << 0) - -/* --- Variable definitions ------------------------------------------------ */ - -extern uint32_t ccm_core_clk; -extern uint32_t ccm_platform_bus_clk; -extern uint32_t ccm_ipg_bus_clk; - -enum ccm_clock_gate { - /* AIPS0 */ - CG0_FLEXCAN0 = 0, - CG1_RESERVED, - CG2_RESERVED, - CG3_RESERVED, - CG4_DMA_MUX0, - CG5_DMA_MUX1, - CG6_RESERVED, - CG7_UART0, - CG8_UART1, - CG9_UART2, - CG10_UART3, - CG11_RESERVED, - CG12_SPI0, - CG13_SPI1, - CG14_RESERVED, - CG15_SAI0, - CG16_SAI1, - CG17_SAI2, - CG18_SAI3, - CG19_CRC, - CG20_USBC0, - CG21_RESERVED, - CG22_PDB, - CG23_PIT, - CG24_FTM0, - CG25_FTM1, - CG26_RESERVED, - CG27_ADC0, - CG28_RESERVED, - CG29_TCON0, - CG30_WDOG_A5, - CG31_WDOG_M4, - CG32_LPTMR, - CG33_RESERVED, - CG34_RLE, - CG35_RESERVED, - CG36_QSPI0, - CG37_RESERVED, - CG38_RESERVED, - CG39_RESERVED, - CG40_IOMUX, - CG41_PORTA, - CG42_PORTB, - CG43_PORTC, - CG44_PORTD, - CG45_PORTE, - CG46_RESERVED, - CG47_RESERVED, - CG48_ANADIG, - CG49_RESERVED, - CG50_SCSCM, - CG51_RESERVED, - CG52_RESERVED, - CG53_RESERVED, - CG54_RESERVED, - CG55_RESERVED, - CG56_DCU0, - CG57_RESERVED, - CG58_RESERVED, - CG59_RESERVED, - CG60_RESERVED, - CG61_RESERVED, - CG62_RESERVED, - CG63_RESERVED, - CG64_ASRC, - CG65_SPDIF, - CG66_ESAI, - CG67_RESERVED, - CG68_RESERVED, - CG69_EWM, - CG70_I2C0, - CG71_I2C1, - CG72_RESERVED, - CG73_RESERVED, - CG74_WKUP, - CG75_CCM, - CG76_GPC, - CG77_VREG_DIG, - CG78_RESERVED, - CG79_CMU, - CG80_NOTUSED, - CG81_NOTUSED, - CG82_NOTUSED, - CG83_NOTUSED, - CG84_NOTUSED, - CG85_NOTUSED, - CG86_NOTUSED, - CG87_NOTUSED, - CG88_NOTUSED, - CG89_NOTUSED, - CG90_NOTUSED, - CG91_NOTUSED, - CG92_NOTUSED, - CG93_NOTUSED, - CG94_NOTUSED, - CG95_NOTUSED, - - /* AIPS1 */ - CG96_RESERVED, - CG97_DMA_MUX2, - CG98_DMA_MUX3, - CG99_RESERVED, - CG100_RESERVED, - CG101_OTP_CTRL, - CG102_RESERVED, - CG103_RESERVED, - CG104_RESERVED, - CG105_UART4, - CG106_UART5, - CG107_RESERVED, - CG108_SPI2, - CG109_SPI3, - CG110_DDRMC, - CG111_RESERVED, - CG112_RESERVED, - CG113_SDHC0, - CG114_SDHC1, - CG115_RESERVED, - CG116_USBC1, - CG117_RESERVED, - CG118_RESERVED, - CG119_RESERVED, - CG120_FTM2, - CG121_FTM3, - CG122_RESERVED, - CG123_ADC1, - CG124_RESERVED, - CG125_TCON1, - CG126_SEG_LCD, - CG127_RESERVED, - CG128_RESERVED, - CG129_RESERVED, - CG130_RESERVED, - CG131_RESERVED, - CG132_QSPI1, - CG133_RESERVED, - CG134_RESERVED, - CG135_VADC, - CG136_VDEC, - CG137_VIU3, - CG138_RESERVED, - CG139_RESERVED, - CG140_DAC0, - CG141_DAC1, - CG142_RESERVED, - CG143_NOTUSED, - CG144_ETH0_1588, - CG145_ETH1_1588, - CG146_RESERVED, - CG147_RESERVED, - CG148_FLEXCAN1, - CG149_RESERVED, - CG150_RESERVED, - CG151_RESERVED, - CG152_DCU1, - CG153_RESERVED, - CG154_RESERVED, - CG155_RESERVED, - CG156_RESERVED, - CG157_RESERVED, - CG158_RESERVED, - CG159_RESERVED, - CG160_NFC, - CG161_RESERVED, - CG162_RESERVED, - CG163_RESERVED, - CG164_RESERVED, - CG165_RESERVED, - CG166_I2C2, - CG167_I2C3, - CG168_ETH_L2, - CG169_RESERVED, - CG170_RESERVED, - CG171_RESERVED, - CG172_RESERVED, - CG173_RESERVED, - CG174_RESERVED, - CG175_RESERVED, - CG176_RESERVED, - CG177_RESERVED, - CG178_RESERVED, - CG179_RESERVED, - CG180_RESERVED, - CG181_RESERVED, - CG182_RESERVED, - CG183_RESERVED, - CG184_RESERVED, - CG185_RESERVED, - CG186_RESERVED, - CG187_RESERVED, - CG188_RESERVED, - CG189_RESERVED, - CG190_RESERVED, - CG191_RESERVED -}; - -/* --- Function prototypes ------------------------------------------------- */ - -#include - -BEGIN_DECLS - -void ccm_clock_gate_enable(enum ccm_clock_gate gr); -void ccm_clock_gate_disable(enum ccm_clock_gate gr); -void ccm_calculate_clocks(void); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/vf6xx/doc-vf6xx.h b/libopencm3/include/libopencm3/vf6xx/doc-vf6xx.h deleted file mode 100644 index 6448297..0000000 --- a/libopencm3/include/libopencm3/vf6xx/doc-vf6xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/** @page libopencm3 VF6xx - * - * @version 1.0.0 - * - * @date 03 July 2014 - * - * API documentation for Freescale VF6xx series Cortex-M4 core. - * - * LGPL License Terms @ref lgpl_license - */ - -/** @defgroup VF6xx VF6xx - * Libraries for Freescale VF6xx series Cortex-M4 core. - * - * @version 1.0.0 - * - * @date 03 July 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/** @defgroup VF6xx_defines VF6xx Defines - * - * @brief Defined Constants and Types for the VF6xx series - * - * @version 1.0.0 - * - * @date 03 July 2014 - * - * LGPL License Terms @ref lgpl_license - */ - diff --git a/libopencm3/include/libopencm3/vf6xx/gpio.h b/libopencm3/include/libopencm3/vf6xx/gpio.h deleted file mode 100644 index 899e4a7..0000000 --- a/libopencm3/include/libopencm3/vf6xx/gpio.h +++ /dev/null @@ -1,80 +0,0 @@ -/** @defgroup VF6xx_gpio_defines GPIO Defines - * - * @brief Defined Constants and Types for the VF6xx GPIO Module - * - * @ingroup VF6xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Stefan Agner - * - * @date 03 July 2014 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_VF6XX_GPIO_H -#define LIBOPENCM3_VF6XX_GPIO_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup gpio_reg_base GPIO register base addresses -@ingroup VF6xx_gpio_defines - -@{*/ -#define GPIO(port) (GPIO_BASE + (0x040 * (port))) -#define GPIO0 (GPIO_BASE + 0x000) -#define GPIO1 (GPIO_BASE + 0x040) -#define GPIO2 (GPIO_BASE + 0x080) -#define GPIO3 (GPIO_BASE + 0x0C0) -#define GPIO4 (GPIO_BASE + 0x100) - -#define GPIO_OFFSET(gpio) (0x1 << ((gpio) % 32)) - -/* --- GPIO registers ------------------------------------------------------ */ - -#define GPIO_PDOR(gpio_base) MMIO32((gpio_base) + 0x00) -#define GPIO_PSOR(gpio_base) MMIO32((gpio_base) + 0x04) -#define GPIO_PCOR(gpio_base) MMIO32((gpio_base) + 0x08) -#define GPIO_PTOR(gpio_base) MMIO32((gpio_base) + 0x0C) -#define GPIO_PDIR(gpio_base) MMIO32((gpio_base) + 0x10) - -/* --- Function prototypes ------------------------------------------------- */ - -#include - -BEGIN_DECLS - -void gpio_set(uint32_t gpio); -void gpio_clear(uint32_t gpio); -bool gpio_get(uint32_t gpio); -void gpio_toggle(uint32_t gpio); -uint32_t gpio_port_read(uint32_t gpioport); -void gpio_port_write(uint32_t gpioport, uint32_t data); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/vf6xx/iomuxc.h b/libopencm3/include/libopencm3/vf6xx/iomuxc.h deleted file mode 100644 index b08a24e..0000000 --- a/libopencm3/include/libopencm3/vf6xx/iomuxc.h +++ /dev/null @@ -1,256 +0,0 @@ -/** @defgroup VF6xx_iomuxc_defines IO MUX Controller Defines - * - * @brief Defined Constants and Types for the VF6xx IO MUX Controller - * - * @ingroup VF6xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Stefan Agner - * - * @date 03 July 2014 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_VF6XX_IOMUXC_H -#define LIBOPENCM3_VF6XX_IOMUXC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup iomuxc_reg IO MUX Controller register -@ingroup VF6xx_iomuxc_defines - -@{*/ -#define IOMUXC(pad) MMIO32(IOMUXC_BASE + (0x4 * (pad))) - -#define IOMUXC_PAD(mode, speed, dse, pus, flags) \ - ((IOMUXC_##mode) << IOMUXC_MUX_MODE_SHIFT | \ - (IOMUXC_##speed) << IOMUXC_SPEED_SHIFT | \ - (IOMUXC_##dse) << IOMUXC_DSE_SHIFT | \ - (IOMUXC_##pus) << IOMUXC_PUS_SHIFT | \ - (flags)) - - -/* --- GPIO registers ------------------------------------------------------ */ - -#define IOMUXC_MUX_MODE_SHIFT 20 -#define IOMUXC_MUX_MODE_MASK (0x7 << 20) -#define IOMUXC_MUX_MODE_ALT0 0x0 -#define IOMUXC_MUX_MODE_ALT1 0x1 -#define IOMUXC_MUX_MODE_ALT2 0x2 -#define IOMUXC_MUX_MODE_ALT3 0x3 -#define IOMUXC_MUX_MODE_ALT4 0x4 -#define IOMUXC_MUX_MODE_ALT5 0x5 -#define IOMUXC_MUX_MODE_ALT6 0x6 -#define IOMUXC_MUX_MODE_ALT7 0x7 -#define IOMUXC_SPEED_SHIFT 12 -#define IOMUXC_SPEED_MASK (0x3 << 12) -#define IOMUXC_SPEED_LOW 0x0 -#define IOMUXC_SPEED_MEDIUM 0x1 -#define IOMUXC_SPEED_HIGH 0x3 -#define IOMUXC_SRE (0x1 << 11) -#define IOMUXC_ODE (0x1 << 10) -#define IOMUXC_HYS (0x1 << 9) -#define IOMUXC_DSE_SHIFT 6 -#define IOMUXC_DSE_MASK (0x7 << 6) -#define IOMUXC_DSE_OFF 0x0 -#define IOMUXC_DSE_150OHM 0x1 -#define IOMUXC_DSE_75OHM 0x2 -#define IOMUXC_DSE_50OHM 0x3 -#define IOMUXC_DSE_37OHM 0x4 -#define IOMUXC_DSE_30OHM 0x5 -#define IOMUXC_DSE_25OHM 0x6 -#define IOMUXC_DSE_20OHM 0x7 -#define IOMUXC_PUS_SHIFT 4 -#define IOMUXC_PUS_MASK (0x3 << 4) -#define IOMUXC_PUS_PD_100KOHM 0x0 -#define IOMUXC_PUS_PU_47KOHM 0x1 -#define IOMUXC_PUS_PU_100KOHM 0x2 -#define IOMUXC_PUS_PU_22KOHM 0x3 -#define IOMUXC_PKE (0x1 << 3) -#define IOMUXC_PUE (0x1 << 2) -#define IOMUXC_OBE (0x1 << 1) -#define IOMUXC_IBE (0x1 << 0) - - -/* --- Type definitions ---------------------------------------------------- */ -/*---------------------------------------------------------------------------*/ -/** @brief IO-MUX Pads - -Pads available by the IO-MUX controller -*/ - -enum vf6xx_pad { - PTA6, - PTA8, - PTA9, - PTA10, - PTA11, - PTA12, - PTA16, - PTA17, - PTA18, - PTA19, - PTA20, - PTA21, - PTA22, - PTA23, - PTA24, - PTA25, - PTA26, - PTA27, - PTA28, - PTA29, - PTA30, - PTA31, - PTB0, - PTB1, - PTB2, - PTB3, - PTB4, - PTB5, - PTB6, - PTB7, - PTB8, - PTB9, - PTB10, - PTB11, - PTB12, - PTB13, - PTB14, - PTB15, - PTB16, - PTB17, - PTB18, - PTB19, - PTB20, - PTB21, - PTB22, - PTC0, - PTC1, - PTC2, - PTC3, - PTC4, - PTC5, - PTC6, - PTC7, - PTC8, - PTC9, - PTC10, - PTC11, - PTC12, - PTC13, - PTC14, - PTC15, - PTC16, - PTC17, - PTD31, - PTD30, - PTD29, - PTD28, - PTD27, - PTD26, - PTD25, - PTD24, - PTD23, - PTD22, - PTD21, - PTD20, - PTD19, - PTD18, - PTD17, - PTD16, - PTD0, - PTD1, - PTD2, - PTD3, - PTD4, - PTD5, - PTD6, - PTD7, - PTD8, - PTD9, - PTD10, - PTD11, - PTD12, - PTD13, - PTB23, - PTB24, - PTB25, - PTB26, - PTB27, - PTB28, - PTC26, - PTC27, - PTC28, - PTC29, - PTC30, - PTC31, - PTE0, - PTE1, - PTE2, - PTE3, - PTE4, - PTE5, - PTE6, - PTE7, - PTE8, - PTE9, - PTE10, - PTE11, - PTE12, - PTE13, - PTE14, - PTE15, - PTE16, - PTE17, - PTE18, - PTE19, - PTE20, - PTE21, - PTE22, - PTE23, - PTE24, - PTE25, - PTE26, - PTE27, - PTE28, - PTA7, -}; - - -/* --- Function prototypes ------------------------------------------------- */ - -#include - -BEGIN_DECLS - -void iomuxc_mux(enum vf6xx_pad pad, uint32_t muxc); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencm3/vf6xx/irq.json b/libopencm3/include/libopencm3/vf6xx/irq.json deleted file mode 100644 index d8d1557..0000000 --- a/libopencm3/include/libopencm3/vf6xx/irq.json +++ /dev/null @@ -1,119 +0,0 @@ -{ - "irqs": [ - "cpu2cpu_int0", - "cpu2cpu_int1", - "cpu2cpu_int2", - "cpu2cpu_int3", - "directed0_sema4", - "directed1_mcm", - "directed2", - "directed3", - "dma0", - "dma0_error", - "dma1", - "dma1_error", - "reserved0", - "reserved1", - "mscm_ecc0", - "mscm_ecc1", - "csu_alarm", - "reserved2", - "mscm_actzs", - "reserved3", - "wdog_a5", - "wdog_m4", - "wdog_snvs", - "cp1_boot_fail", - "qspi0", - "qspi1", - "ddrmc", - "sdhc0", - "sdhc1", - "reserved4", - "dcu0", - "dcu1", - "viu", - "reserved5", - "reserved6", - "rle", - "seg_lcd", - "reserved7", - "reserved8", - "pit", - "lptimer0", - "reserved9", - "flextimer0", - "flextimer1", - "flextimer2", - "flextimer3", - "reserved10", - "reserved11", - "reserved12", - "reserved13", - "usbphy0", - "usbphy1", - "reserved14", - "adc0", - "adc1", - "dac0", - "dac1", - "reserved15", - "flexcan0", - "flexcan1", - "reserved16", - "uart0", - "uart1", - "uart2", - "uart3", - "uart4", - "uart5", - "spi0", - "spi1", - "spi2", - "spi3", - "i2c0", - "i2c1", - "i2c2", - "i2c3", - "usbc0", - "usbc1", - "reserved17", - "enet0", - "enet1", - "enet0_1588", - "enet1_1588", - "enet_switch", - "nfc", - "sai0", - "sai1", - "sai2", - "sai3", - "esai_bififo", - "spdif", - "asrc", - "vreg", - "wkpu0", - "reserved18", - "ccm_fxosc", - "ccm", - "src", - "pdb", - "ewm", - "reserved19", - "reserved20", - "reserved21", - "reserved22", - "reserved23", - "reserved24", - "reserved25", - "reserved26", - "gpio0", - "gpio1", - "gpio2", - "gpio3", - "gpio4" - ], - "partname_humanreadable": "VF6xx series", - "partname_doxygen": "VF6XX", - "includeguard": "LIBOPENCM3_VF6XX_NVIC_H" -} diff --git a/libopencm3/include/libopencm3/vf6xx/memorymap.h b/libopencm3/include/libopencm3/vf6xx/memorymap.h deleted file mode 100644 index efb84f6..0000000 --- a/libopencm3/include/libopencm3/vf6xx/memorymap.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- VF6xx specific peripheral definitions ----------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE (0x40000000U) -#define PERIPH_BASE_AIPS0 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_AIPS1 (PERIPH_BASE + 0x80000) - -/* Pheripheral addresses */ - -/* AIPS0 */ -#define MSCM_BASE (PERIPH_BASE_AIPS0 + 0x01000) - -#define SEMA4_BASE (PERIPH_BASE_AIPS0 + 0x1D000) - -#define UART0_BASE (PERIPH_BASE_AIPS0 + 0x27000) -#define UART1_BASE (PERIPH_BASE_AIPS0 + 0x28000) -#define UART2_BASE (PERIPH_BASE_AIPS0 + 0x29000) -#define UART3_BASE (PERIPH_BASE_AIPS0 + 0x2A000) - -#define SPI0_BASE (PERIPH_BASE_AIPS0 + 0x2C000) -#define SPI1_BASE (PERIPH_BASE_AIPS0 + 0x2D000) - -#define IOMUXC_BASE (PERIPH_BASE_AIPS0 + 0x48000) -#define PORTA_MUX_BASE (PERIPH_BASE_AIPS0 + 0x49000) -#define PORTB_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4A000) -#define PORTC_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4B000) -#define PORTD_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4C000) -#define PORTE_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4D000) - -#define ANADIG_BASE (PERIPH_BASE_AIPS0 + 0x50000) - -#define CCM_BASE (PERIPH_BASE_AIPS0 + 0x6B000) - -/* AIPS1 */ -#define UART4_BASE (PERIPH_BASE_AIPS1 + 0x29000) -#define UART5_BASE (PERIPH_BASE_AIPS1 + 0x2A000) - -/* GPIO module */ -#define GPIO_BASE (PERIPH_BASE + 0xff000) - -#endif diff --git a/libopencm3/include/libopencm3/vf6xx/uart.h b/libopencm3/include/libopencm3/vf6xx/uart.h deleted file mode 100644 index 369918c..0000000 --- a/libopencm3/include/libopencm3/vf6xx/uart.h +++ /dev/null @@ -1,182 +0,0 @@ -/** @defgroup VF6xx_uart_defines UART Defines - * - * @brief Defined Constants and Types for the VF6xx UART Module - * - * @ingroup VF6xx_defines - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Stefan Agner - * - * @date 01 July 2014 - * - * LGPL License Terms @ref lgpl_license - * */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Stefan Agner - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_VF6XX_UART_H -#define LIBOPENCM3_VF6XX_UART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/****************************************************************************/ -/** @defgroup uart_reg_base UART register base addresses -@ingroup VF6xx_uart_defines - -@{*/ -#define UART0 UART0_BASE -#define UART1 UART1_BASE -#define UART2 UART2_BASE -#define UART3 UART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE - -/* --- UART registers ------------------------------------------------------ */ - -#define UART_BDH(uart_base) MMIO8((uart_base) + 0x00) -#define UART_BDL(uart_base) MMIO8((uart_base) + 0x01) -#define UART_C1(uart_base) MMIO8((uart_base) + 0x02) -#define UART_C2(uart_base) MMIO8((uart_base) + 0x03) -#define UART_S1(uart_base) MMIO8((uart_base) + 0x04) -#define UART_S2(uart_base) MMIO8((uart_base) + 0x05) -#define UART_C3(uart_base) MMIO8((uart_base) + 0x06) -#define UART_D(uart_base) MMIO8((uart_base) + 0x07) -#define UART_MA1(uart_base) MMIO8((uart_base) + 0x08) -#define UART_MA2(uart_base) MMIO8((uart_base) + 0x09) -#define UART_C4(uart_base) MMIO8((uart_base) + 0x0A) -#define UART_C5(uart_base) MMIO8((uart_base) + 0x0B) -#define UART_ED(uart_base) MMIO8((uart_base) + 0x0C) -#define UART_MODEM(uart_base) MMIO8((uart_base) + 0x0D) -/* Incomplete */ - -/* --- CCM values -....----------------------------------------------------- */ - -/* BDH: Baud Rate Register High */ -#define UART_BDH_LBKDIE (1 << 7) -#define UART_BDH_RXEDGIE (1 << 6) -#define UART_BDH_SBR_MASK 0x1f - -/* BDL: Baud Rate Register Low */ -#define UART_BDL_SBR_MASK 0xff - -/* C1: Control register 1 */ -#define UART_C1_LOOPS (1 << 7) -#define UART_C1_RSRC (1 << 5) -#define UART_C1_M (1 << 4) -#define UART_C1_WAKE (1 << 3) -#define UART_C1_ILT (1 << 2) -#define UART_C1_PE (1 << 1) -#define UART_C1_PT (1 << 0) - -/* C2: Control register 2 */ -#define UART_C2_TIE (1 << 7) -#define UART_C2_TCIE (1 << 6) -#define UART_C2_RIE (1 << 5) -#define UART_C2_ILIE (1 << 4) -#define UART_C2_TE (1 << 3) -#define UART_C2_RE (1 << 2) -#define UART_C2_RWU (1 << 1) -#define UART_C2_SBK (1 << 0) - -/* S1: Status register 1 */ -#define UART_S1_TDRE (1 << 7) -#define UART_S1_TC (1 << 6) -#define UART_S1_RDRF (1 << 5) -#define UART_S1_IDLE (1 << 4) -#define UART_S1_OR (1 << 3) -#define UART_S1_NF (1 << 2) -#define UART_S1_FE (1 << 1) -#define UART_S1_PF (1 << 0) - -/* S2: Status register 2 */ -#define UART_S2_LBKDIF (1 << 7) -#define UART_S2_RXEDGIF (1 << 6) -#define UART_S2_MSBF (1 << 5) -#define UART_S2_RXINV (1 << 4) -#define UART_S2_RWUID (1 << 3) -#define UART_S2_BRK13 (1 << 2) -#define UART_S2_LBKDE (1 << 1) -#define UART_S2_RAF (1 << 0) - -/* C3: Control register 3 */ -#define UART_C3_R8 (1 << 7) -#define UART_C3_T8 (1 << 6) -#define UART_C3_TXDIR (1 << 5) -#define UART_C3_TXINV (1 << 4) -#define UART_C3_ORIE (1 << 3) -#define UART_C3_NEIE (1 << 2) -#define UART_C3_FEIE (1 << 1) -#define UART_C3_PEIE (1 << 0) - -/* MODEM: Modem configuration register */ -#define UART_MODEM_RXRTSE (1 << 3) -#define UART_MODEM_TXRTSPOL (1 << 2) -#define UART_MODEM_TXRTSE (1 << 1) -#define UART_MODEM_TXCTSE (1 << 0) - -/****************************************************************************/ -/** @defgroup uart_parity UART Parity Selection -@ingroup VF6xx_uart_defines - -@{*/ -#define UART_PARITY_NONE 0x00 -#define UART_PARITY_EVEN UART_C1_PE -#define UART_PARITY_ODD (UART_C1_PE | UART_C1_PT) -/**@}*/ -#define UART_PARITY_MASK 0x3 - -/* CR3_CTSE/CR3_RTSE combined values */ -/****************************************************************************/ -/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection -@ingroup STM32F_usart_defines - -@{*/ -#define UART_FLOWCONTROL_NONE 0x00 -#define UART_FLOWCONTROL_RTS UART_MODEM_RXRTSE -#define UART_FLOWCONTROL_CTS UART_MODEM_TXCTSE -#define UART_FLOWCONTROL_RTS_CTS (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE) -/**@}*/ -#define UART_FLOWCONTROL_MASK (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -#include - -BEGIN_DECLS - -void uart_enable(uint32_t uart); -void uart_disable(uint32_t uart); -void uart_set_baudrate(uint32_t uart, uint32_t baud); -void uart_set_parity(uint32_t uart, uint8_t parity); -void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol); -void uart_send(uint32_t uart, uint8_t data); -void uart_send_blocking(uint32_t usart, uint8_t data); -void uart_wait_send_ready(uint32_t uart); -uint8_t uart_recv(uint32_t uart); -uint8_t uart_recv_blocking(uint32_t uart); -void uart_wait_recv_ready(uint32_t uart); - -END_DECLS - -#endif diff --git a/libopencm3/include/libopencmsis/core_cm3.h b/libopencm3/include/libopencmsis/core_cm3.h deleted file mode 100644 index c54137b..0000000 --- a/libopencm3/include/libopencmsis/core_cm3.h +++ /dev/null @@ -1,183 +0,0 @@ -/* big fat FIXME: this should use a consistent structure, and reference - * functionality from libopencm3 instead of copypasting. - * - * particularly unimplemented features are FIXME'd extra - * */ - -/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant - * of the symbols efm32lib needs of CMSIS. */ - -#ifndef OPENCMSIS_CORECM3_H -#define OPENCMSIS_CORECM3_H - -#include -#include -#include -#include -#include -#include - -/* needed by system_efm32.h:196, guessing */ -#define __INLINE inline -/* new since emlib 3.0 */ -#define __STATIC_INLINE static inline - -/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the - * libopencm3 ones, "volatile" is all that's missing. */ -#define __IO volatile -#define __O volatile -#define __I volatile - -/* -> style access for what is defined in libopencm3/stm32/f1/scb.h / - * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ - -/* from cm3/scb.h */ -#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP - -/* structure as in, for example, - * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from - * libopencm3/cm3/scb.h. FIXME incomplete. */ -typedef struct { - __IO uint32_t CPUID; - __IO uint32_t ICSR; - __IO uint32_t VTOR; - __IO uint32_t AIRCR; - __IO uint32_t SCR; - __IO uint32_t CCR; - __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */ - __IO uint32_t SHCSR; -} SCB_TypeDef; -#define SCB ((SCB_TypeDef *) SCB_BASE) - -/* needed by efm32_emu.h, guessing and taking the implementation used in - * lightswitch-interrupt.c */ -#define __WFI() __asm__("wfi") - -/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ -#define __CLZ(div) __builtin_clz(div) - -/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev - * instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 - */ -#define __REV(x) __builtin_bswap32(x) - -/* stubs for efm32_dbg.h */ -typedef struct { - uint32_t DHCSR; - uint32_t DEMCR; /* needed by efm32tg stk trace.c */ -} CoreDebug_TypeDef; -/* FIXME let's just hope writes to flash are protected */ -#define CoreDebug ((CoreDebug_TypeDef *) 0) -#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 -#define CoreDebug_DEMCR_TRCENA_Msk 0 - -/* stubs for efm32_dma */ - -static inline void NVIC_ClearPendingIRQ(uint8_t irqn) -{ - nvic_clear_pending_irq(irqn); -} -static inline void NVIC_EnableIRQ(uint8_t irqn) -{ - nvic_enable_irq(irqn); -} -static inline void NVIC_DisableIRQ(uint8_t irqn) -{ - nvic_disable_irq(irqn); -} - -/* stubs for efm32_int */ - -static inline void __enable_irq(void) -{ - cm_enable_interrupts(); -} -static inline void __disable_irq(void) -{ - cm_disable_interrupts(); -} - -/* stubs for efm32_mpu FIXME */ - -#define SCB_SHCSR_MEMFAULTENA_Msk 0 - -typedef struct { - uint32_t CTRL; - uint32_t RNR; - uint32_t RBAR; - uint32_t RASR; -} MPU_TypeDef; -/* FIXME struct at NULL */ -#define MPU ((MPU_TypeDef *) 0) -#define MPU_CTRL_ENABLE_Msk 0 -#define MPU_RASR_XN_Pos 0 -#define MPU_RASR_AP_Pos 0 -#define MPU_RASR_TEX_Pos 0 -#define MPU_RASR_S_Pos 0 -#define MPU_RASR_C_Pos 0 -#define MPU_RASR_B_Pos 0 -#define MPU_RASR_SRD_Pos 0 -#define MPU_RASR_SIZE_Pos 0 -#define MPU_RASR_ENABLE_Pos 0 - -/* required for the blink example */ - -/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ; - * configures the sys ticks to 1ms, then the argument to SysTick_Config - * describes how many cycles to wait between two systicks. - * - * the endless loop part looks like an "if it returns an error condition, - * rather loop here than continue"; every other solution would involve things - * that are dark magic to my understanding. - * - * implementation more or less copypasted from lib/stm32/systick.c, FIXME until - * the generic cm3 functionality is moved out from stm32 and can be used here - * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable - * and systick_set_clocksource). - * - * modified for CMSIS style array as the powertest example needs it. - * */ - -/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ -typedef struct { - uint32_t CTRL; - uint32_t LOAD; - uint32_t VAL; - uint32_t CALIB; -} SysTick_TypeDef; -#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE) - -static inline uint32_t SysTick_Config(uint32_t n_ticks) -{ - /* constant from systick_set_reload -- as this returns something that's - * not void, this is the only possible error condition */ - if (n_ticks & ~0x00FFFFFF) { - return 1; - } - - systick_set_reload(n_ticks); - systick_set_clocksource(true); - systick_interrupt_enable(); - systick_counter_enable(); - - return 0; -} - -/* stubs for efm32tg stk trace.c */ -typedef struct { - uint32_t LAR; - uint32_t TCR; -} ITM_TypeDef; -/* FIXME struct at NULL */ -#define ITM ((ITM_TypeDef *) 0) - -/* blink.h expects the isr for systicks to be named SysTick_Handler. with this, - * its Systick_Handler function gets renamed to the weak symbol exported by - * vector.c */ - -#define SysTick_Handler sys_tick_handler -/* FIXME: this needs to be done for all of the 14 hard vectors */ - -#include - -#endif diff --git a/libopencm3/include/libopencmsis/dispatch/irqhandlers.h b/libopencm3/include/libopencmsis/dispatch/irqhandlers.h deleted file mode 100644 index e8ac859..0000000 --- a/libopencm3/include/libopencmsis/dispatch/irqhandlers.h +++ /dev/null @@ -1,67 +0,0 @@ -#if defined(STM32F0) -# include -#elif defined(STM32F1) -# include -#elif defined(STM32F2) -# include -#elif defined(STM32F3) -# include -#elif defined(STM32F4) -# include -#elif defined(STM32F7) -# include -#elif defined(STM32L0) -# include -#elif defined(STM32L1) -# include -#elif defined(STM32L4) -# include -#elif defined(STM32G0) -# include - -#elif defined(GD32F1X0) -# include - -#elif defined(EFM32TG) -# include -#elif defined(EFM32G) -# include -#elif defined(EFM32HG) -# include -#elif defined(EFM32LG) -# include -#elif defined(EFM32GG) -# include - -#elif defined(LPC13XX) -# include -#elif defined(LPC17XX) -# include -#elif defined(LPC43XX_M4) -# include -#elif defined(LPC43XX_M0) -# include - -#elif defined(SAM3A) -# include -#elif defined(SAM3N) -# include -#elif defined(SAM3S) -# include -#elif defined(SAM3U) -# include -#elif defined(SAM3X) -# include -#elif defined(SAMD) -# include - -#elif defined(LM3S) || defined(LM4F) -/* Yes, we use the same interrupt table for both LM3S and LM4F */ -# include - -#elif defined(SWM050) -# include -#else -# warning"no chipset defined; user interrupts are not redirected" - -#endif diff --git a/libopencm3/ld/README b/libopencm3/ld/README deleted file mode 100644 index 5694c6e..0000000 --- a/libopencm3/ld/README +++ /dev/null @@ -1,144 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -LIBOPENCM3 LINKER SCRIPT GENERATOR ----------------------------------- - -This folder contains files needed for the automatic linker script generation -mechanism developed for libopencm3 library. - -File contents -------------- - -* {ROOT}/ld/tests/* - Prepared tests for the testing of the script -* {ROOT}/ld/devices.data - Device database file -* {ROOT}/ld/linker.ld.S - Linker script template -* {ROOT}/scripts/genlink.py - Device database file search script -* {ROOT}/scripts/genlinktest.sh - Device database file search test script - -Principle of operation ----------------------- - -The user specifies in the project Makefile the device part name the project is -using, in the variable DEVICE. Note that full device part name must be -specified, because the device specific features is usually dependent on the -last characters of device name string. Note that the device name string search -is case insensitive. - -DEVICE=stm32f407vgt6 - -Device database contains definitions of common sections and its origins for -the linker preprocessor. Every definition is interpreted in the linker script -template as a macro, and it can be used for conditional insertion of the device -dependent stuff. - -The search in the device database is pattern-based, and using python script -genlink.py. The python script traverses the file as a tree, joining the options -for the preprocessor together by single space. The python script adds -D to -each parameter for you. - -Testing -------- - -The testing of feature is done by executing in the root of libopencm3 library. - -make genlinktests - -The test cases are defined in subdirectory {ROOT}/ld/tests/. Each test contains -two files, the database file *.data and the expected result *.result file. If -the particular test fails, the file *.out containing output of the script is -not deleted to help resolving problem with the script. - -The search pattern for the test is the base filename of particular test. - -The testing stops after all test cases are valid, or at first error found. - -Example of use --------------- - -* Check the documentation for the genlink module in /mk/README. - -Device database file structure ------------------------------- - -Line description: - ( ...) - - : is the pattern for the chip description to be searched for. - The case of the pattern string is ignored. - Pattern match symbols: - ? - matches exactly one character - * - matches none or more characters - + - matches single or more characters - - : is the parent group name, where the search will continue. - There are special parents names that controls traversing: - "END" - Exit traversal. - "+" - Don't change the parent. Use for split long line to two. - - : space-separated list of preprocessor symbols supplied to the linker. - -D option name with single underscore is automatically prepended to each - symbol definition - if the symbol starts with dash "-", it is interpreted as parameter to - linker, and no -D or underscore is generated. - -All lines starting with # symbol are treated as Comments - -Recommended tree hierarchy: - - - +- - +- - +- END - -You can split the long line into two or more by using "+" in the parent field, -and defining same regex with appropriate parent on the next line. Example: - - device + PARAM1=aaa PARAM2=bbbb PARAM3=ccc PARAM4=dddd PARAM5=eeee - device parent PARAM6=ffff PARAM7=gggg PARAM8=hhhh - parent END - -The order of the lines is important. After the regex match, its parent will -be used for match on the next line. If two regexp lines matches input, only -the first will be evaluated, except special group definition "+" - -The regex matches entire sym - -Example: - ---- devices.data file --- -stm32f05[01]?4* stm32f0 ROM=16K RAM=4K -stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -stm32 END - ---- queried chip name --- -stm32f051c4t6 - ---- output of the python script --- --D_ROM=16K -D_RAM=4K -D_ROM_OFF=0x08000000 -D_RAM_OFF=0x20000000 - -The generated linker script file will contain sections rom and ram with -appropriate initialization code, specified in linker file source linker.ld.S - - -Copyright ---------- - -This file is part of the libopencm3 project. - -Copyright (C) 2013 Frantisek Burian -Copyright (C) 2013 Werner Almesberger - -This library is free software: you can redistribute it and/or modify -it under the terms of the GNU Lesser General Public License as published by -the Free Software Foundation, either version 3 of the License, or -(at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public License -along with this library. If not, see . diff --git a/libopencm3/ld/devices.data b/libopencm3/ld/devices.data deleted file mode 100644 index 12c61ff..0000000 --- a/libopencm3/ld/devices.data +++ /dev/null @@ -1,591 +0,0 @@ -################################################################################ -# -# Device chip tree definition file. -# -# Copyright (c) 2013 Frantisek Burian -# Copyright (C) 2013 Werner Almesberger -# -# Line description: -# ( ...) -# -# : is the pattern for the chip description to be searched for. -# The case of the pattern string is ignored. -# Pattern match symbols: -# ? - matches exactly one character -# * - matches none or more characters -# + - matches single or more characters -# -# : is the parent group name, where the search will continue. -# There are special parents names that controls traversing: -# "END" - Exit traversal. -# "+" - Don't change the parent. Use for split long line to two. -# -# : space-separated list of preprocessor symbols supplied to the linker. -# -D option name is automatically prepended to each symbol definition -# -# All lines starting with # symbol are treated as Comments -# -# Recommended tree hierarchy: -# -# -# +- -# +- -# +- END -# -# You can split the long line into two or more by using "+" in the parent field, -# and defining same regex with appropriate parent on the next line. Example: -# -# device + PARAM1=aaa PARAM2=bbbb PARAM3=ccc PARAM4=dddd PARAM5=eeee -# device parent PARAM6=ffff PARAM7=gggg PARAM8=hhhh -# parent END -# -# The order of the lines is important. After the regex match, its parent will -# be used for match on the next line. If two regexp lines matches input, only -# the first will be evaluated, except special group definition "+" -# -# The regex matches entire sym -# -# Example: -# -# --- devices.data file --- -# stm32f05[01]?4* stm32f0 ROM=16K RAM=4K -# stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -# stm32 END -# -# --- queried chip name --- -# stm32f051c8t6 -# -# --- output of the python script --- -# -DROM=16K -DRAM=4K -DROM_OFF=0x08000000 -DRAM_OFF=0x20000000 -# -# The generated linker script file will contain sections rom and ram with -# appropriate initialization code, specified in linker file source linker.ld.S -# - -################################################################################ -# the STM32 chips - -stm32f03[01]?4* stm32f0 ROM=16K RAM=4K -stm32f03[01]?6* stm32f0 ROM=32K RAM=4K -stm32f030?8* stm32f0 ROM=64K RAM=8K -stm32f030?c* stm32f0 ROM=256K RAM=32K -stm32f042?4* stm32f0 ROM=16K RAM=6K -stm32f042?6* stm32f0 ROM=32K RAM=6K -stm32f050?4* stm32f0 ROM=16K RAM=4K -stm32f050?6* stm32f0 ROM=32K RAM=4K -stm32f051?4* stm32f0 ROM=16K RAM=8K -stm32f051?6* stm32f0 ROM=32K RAM=8K -stm32f051?8* stm32f0 ROM=64K RAM=8K -stm32f070?6* stm32f0 ROM=32K RAM=6K -stm32f07[12]?8* stm32f0 ROM=64K RAM=16K -stm32f07[012]?b* stm32f0 ROM=128K RAM=16K -stm32f091?b* stm32f0 ROM=128K RAM=32K -stm32f091?c* stm32f0 ROM=256K RAM=32K - -stm32f10[012]?4* stm32f1 ROM=16K RAM=4K -stm32f103?4* stm32f1 ROM=16K RAM=6K -stm32f100?6* stm32f1 ROM=32K RAM=4K -stm32f103?6* stm32f1 ROM=32K RAM=10K -stm32f10[12]?6* stm32f1 ROM=32K RAM=6K -stm32f100?8* stm32f1 ROM=64K RAM=8K -stm32f10[12]?8* stm32f1 ROM=64K RAM=10K -stm32f103?8* stm32f1 ROM=64K RAM=20K -stm32f105?8* stm32f1 ROM=64K RAM=64K -stm32f100?b* stm32f1 ROM=128K RAM=8K -stm32f10[12]?b* stm32f1 ROM=128K RAM=16K -stm32f103?b* stm32f1 ROM=128K RAM=20K -stm32f10[57]?b* stm32f1 ROM=128K RAM=64K -stm32f100?c* stm32f1 ROM=256K RAM=24K -stm32f101?c* stm32f1 ROM=256K RAM=32K -stm32f103?c* stm32f1 ROM=256K RAM=48K -stm32f10[57]?c* stm32f1 ROM=256K RAM=64K -stm32f100?d* stm32f1 ROM=384K RAM=32K -stm32f101?d* stm32f1 ROM=384K RAM=48K -stm32f103?d* stm32f1 ROM=384K RAM=64K -stm32f100?e* stm32f1 ROM=512K RAM=32K -stm32f101?e* stm32f1 ROM=512K RAM=48K -stm32f103?e* stm32f1 ROM=512K RAM=64K -stm32f100?f* stm32f1 ROM=768K RAM=80K -stm32f103?f* stm32f1 ROM=768K RAM=96K -stm32f100?g* stm32f1 ROM=1024K RAM=80K -stm32f103?g* stm32f1 ROM=1024K RAM=96K - -stm32f205?b* stm32f2 ROM=128K RAM=64K -stm32f205?c* stm32f2 ROM=256K RAM=96K -stm32f207?c* stm32f2 ROM=256K RAM=128K -stm32f2[01][57]?e* stm32f2 ROM=512K RAM=128K -stm32f20[57]?f* stm32f2 ROM=768K RAM=128K -stm32f2[01][57]?g* stm32f2 ROM=1024K RAM=128K - -stm32f30[12]?6* stm32f3 ROM=32K RAM=16K -stm32f30[12]?8* stm32f3 ROM=64K RAM=16K -stm32f302?b* stm32f3 ROM=128K RAM=32K -stm32f302?c* stm32f3 ROM=256K RAM=40K -stm32f302?d* stm32f3 ROM=384K RAM=64K -stm32f302?e* stm32f3 ROM=512K RAM=64K -stm32f303?6* stm32f3ccm ROM=32K RAM=12K CCM=4K -stm32f303?8* stm32f3ccm ROM=64K RAM=12K CCM=4K -stm32f303?b* stm32f3ccm ROM=128K RAM=32K CCM=8K -stm32f3[01]3?c* stm32f3ccm ROM=256K RAM=40K CCM=8K -stm32f3[01]3?d* stm32f3ccm ROM=384K RAM=64K CCM=16K -stm32f3[01]3?e* stm32f3ccm ROM=512K RAM=64K CCM=16K - -stm32f334?3* stm32f3ccm ROM=16K RAM=12K CCM=4K -stm32f334?6* stm32f3ccm ROM=32K RAM=12K CCM=4K -stm32f334?8* stm32f3ccm ROM=64K RAM=12K CCM=4K - -stm32f318?8* stm32f3 ROM=64K RAM=16K -stm32f328?8* stm32f3ccm ROM=64K RAM=12K CCM=4K -stm32f358?c* stm32f3ccm ROM=256K RAM=40K CCM=8K -stm32f378?c* stm32f3 ROM=256K RAM=32K -stm32f398?e* stm32f3ccm ROM=512K RAM=64K CCM=16K - -stm32f373?8* stm32f3 ROM=64K RAM=16K -stm32f373?b* stm32f3 ROM=128K RAM=24K -stm32f373?c* stm32f3 ROM=256K RAM=32K -stm32f3[78]3?8* stm32f3 ROM=64K RAM=16K -stm32f3[78]3?b* stm32f3 ROM=128K RAM=24K -stm32f3[78]3?c* stm32f3 ROM=256K RAM=32K - -stm32f401?b* stm32f4 ROM=128K RAM=64K -stm32f401?c* stm32f4 ROM=256K RAM=64K -stm32f401?d* stm32f4 ROM=384K RAM=96K -stm32f401?e* stm32f4 ROM=512K RAM=96K -stm32f4[01][57]?e* stm32f4ccm ROM=512K RAM=128K CCM=64K -stm32f4[01][57]?g* stm32f4ccm ROM=1024K RAM=128K CCM=64K -stm32f410?8* stm32f4 ROM=64K RAM=32K -stm32f410?b* stm32f4 ROM=128K RAM=32K -stm32f411?c* stm32f4 ROM=256K RAM=128K -stm32f411?e* stm32f4 ROM=512K RAM=128K -stm32f412?e* stm32f4 ROM=512K RAM=256K -stm32f412?g* stm32f4 ROM=1024K RAM=256K -stm32f4[12]3?g* stm32f4ccm ROM=1024K RAM=256K CCM=64K -stm32f4[12]3?h* stm32f4ccm ROM=1536K RAM=256K CCM=64K -stm32f4[23][79]?e* stm32f4ccm ROM=512K RAM=192K CCM=64K -stm32f4[23][79]?g* stm32f4ccm ROM=1024K RAM=192K CCM=64K -stm32f4[23][79]?i* stm32f4ccm ROM=2048K RAM=192K CCM=64K -stm32f446?c* stm32f4 ROM=256K RAM=128K -stm32f446?e* stm32f4 ROM=512K RAM=128K -stm32f4[67]9?e* stm32f4ccm ROM=512K RAM=320K CCM=64K -stm32f4[67]9?g* stm32f4ccm ROM=1024K RAM=320K CCM=64K -stm32f4[67]9?i* stm32f4ccm ROM=2048K RAM=320K CCM=64K - -# on F7 CCM is in some datasheets named as DTCM -stm32f7[23][23]?c* stm32f7ccm ROM=256K RAM=192K CCM=64K -stm32f7[23][23]?e* stm32f7ccm ROM=512K RAM=192K CCM=64K -stm32f745?e* stm32f7ccm ROM=512K RAM=256K CCM=64K -stm32f745?g* stm32f7ccm ROM=1024K RAM=256K CCM=64K -stm32f765?g* stm32f7ccm ROM=512K RAM=384K CCM=128K -stm32f765?i* stm32f7ccm ROM=2048K RAM=384K CCM=128K -stm32f7[45]6?e* stm32f7ccm ROM=512K RAM=256K CCM=64K -stm32f7[45]6?g* stm32f7ccm ROM=1024K RAM=256K CCM=64K -stm32f7[67]7?g* stm32f7ccm ROM=1024K RAM=384K CCM=128K -stm32f7[67]7?i* stm32f7ccm ROM=2048K RAM=384K CCM=128K -stm32f769?g* stm32f7ccm ROM=1024K RAM=384K CCM=128K -stm32f7[67][89]?i* stm32f7ccm ROM=2048K RAM=384K CCM=128K -stm32f750* stm32f7ccm ROM=64K RAM=256K CCM=64K -stm32f730* stm32f7ccm ROM=64K RAM=192K CCM=64K - -stm32l01??3* stm32l0 ROM=8K RAM=2K -stm32l0[12]??4* stm32l0 ROM=16K RAM=2K -stm32l03??4* stm32l0 ROM=16K RAM=8K -stm32l0???6* stm32l0 ROM=32K RAM=8K -stm32l0[78]??8* stm32l0 ROM=64K RAM=20K -stm32l0???8* stm32l0 ROM=64K RAM=8K -stm32l0???b* stm32l0 ROM=128K RAM=20K -stm32l0???z* stm32l0 ROM=192K RAM=20K - -stm32l100?6* stm32l1eep ROM=32K RAM=4K EEP=2K -stm32l100?8* stm32l1eep ROM=64K RAM=8K EEP=2K -stm32l100?b*_a stm32l1eep ROM=128K RAM=16K EEP=2K -stm32l100?b* stm32l1eep ROM=128K RAM=10K EEP=2K -stm32l100?c* stm32l1eep ROM=256K RAM=16K EEP=4K -stm32l15[12]?6*_a stm32l1eep ROM=32K RAM=16K EEP=4K -stm32l15[12]?6* stm32l1eep ROM=32K RAM=10K EEP=4K -stm32l15[12]?8*_a stm32l1eep ROM=64K RAM=32K EEP=4K -stm32l15[12]?8* stm32l1eep ROM=64K RAM=10K EEP=4K -stm32l15[12]?b*_a stm32l1eep ROM=128K RAM=32K EEP=4K -stm32l15[12]?b* stm32l1eep ROM=128K RAM=16K EEP=4K -stm32l15[12]?c* stm32l1eep ROM=256K RAM=32K EEP=8K -stm32l15[12]?d*_x stm32l1eep ROM=384K RAM=80K EEP=16K -stm32l15[12]?d* stm32l1eep ROM=384K RAM=48K EEP=12K -stm32l15[12]?e* stm32l1eep ROM=512K RAM=80K EEP=16K -stm32l162?c* stm32l1eep ROM=256K RAM=32K EEP=8K -stm32l162?d*_x stm32l1eep ROM=384K RAM=80K EEP=16K -stm32l162?d* stm32l1eep ROM=384K RAM=48K EEP=12K - -stm32l43??b* stm32l4 ROM=128K RAM=48K RAM2=16K -stm32l4[34]??c* stm32l4 ROM=256K RAM=48K RAM2=16K -stm32l451?c* stm32l4 ROM=256K RAM=128K RAM2=32K -stm32l451?e* stm32l4 ROM=512K RAM=128K RAM2=32K -stm32l471?e* stm32l4 ROM=512K RAM=96K RAM2=32K -stm32l471?g* stm32l4 ROM=1024K RAM=96K RAM2=32K - -stm32l452?c* stm32l4 ROM=256K RAM=128K RAM2=32K -stm32l4[56]2?e* stm32l4 ROM=512K RAM=128K RAM2=32K - -stm32l47[56]?c* stm32l4 ROM=256K RAM=96K RAM2=32K -stm32l47[56]?e* stm32l4 ROM=512K RAM=96K RAM2=32K -stm32l47[56]?g* stm32l4 ROM=1024K RAM=96K RAM2=32K - -stm32l486?g* stm32l4 ROM=1024K RAM=96K RAM2=32K -stm32l496?e* stm32l4 ROM=512K RAM=256K RAM2=64K -stm32l496?g* stm32l4 ROM=1024K RAM=256K RAM2=64K -stm32l4a6?g* stm32l4 ROM=1024K RAM=256K RAM2=64K - -stm32ts60 stm32t ROM=32K RAM=10K - -stm32w108c8 stm32w ROM=64K RAM=8K -stm32w108?b stm32w ROM=128K RAM=8K -stm32w108cz stm32w ROM=192K RAM=12K -stm32w108cc stm32w ROM=256K RAM=16K - -stm32g0[43]1?4* stm32g0 ROM=16K RAM=8K -stm32g0[43][01]?6* stm32g0 ROM=32K RAM=8K -stm32g0[43][01]?8* stm32g0 ROM=64K RAM=8K -stm32g0[78]1?8* stm32g0 ROM=64K RAM=36K -stm32g0[78][01]?b* stm32g0 ROM=128K RAM=36K -stm32g0[BC]1?c* stm32g0 ROM=256K RAM=128K -stm32g0[BC]1?e* stm32g0 ROM=512K RAM=128K - -stm32g4?1?6* stm32g4ccm ROM=32K RAM=22K CCM=10K -stm32g4?1?8* stm32g4ccm ROM=64K RAM=22K CCM=10K -stm32g4?1?b* stm32g4ccm ROM=128K RAM=22K CCM=10K -stm32g4?1?c* stm32g4ccm ROM=256K RAM=96K CCM=16K -stm32g4?1?e* stm32g4ccm ROM=512K RAM=96K CCM=16K -stm32g4?[34]?b* stm32g4ccm ROM=128K RAM=96K CCM=32K -stm32g4?[34]?c* stm32g4ccm ROM=256K RAM=96K CCM=32K -stm32g4?[34]?e* stm32g4ccm ROM=512K RAM=96K CCM=32K - -################################################################################ -# the SAM3 chips - -sam3a4* sam3a ROM=256K RAM=32K RAM1=32K -sam3a8* sam3a ROM=512K RAM=64K RAM1=32K - -sam3n00* sam3n ROM=16K RAM=4K -sam3n0* sam3n ROM=32K RAM=8K -sam3n1* sam3n ROM=64K RAM=8K -sam3n2* sam3n ROM=128K RAM=16K -sam3n4* sam3n ROM=256K RAM=24K - -sam3s1* sam3s ROM=64K RAM=16K -sam3s2* sam3s ROM=128K RAM=32K -sam3s4* sam3s ROM=256K RAM=48K -sam3s8* sam3s ROM=512K RAM=64K -sam3sd8* sam3s ROM=512K RAM=64K - -sam3u1* sam3u ROM=64K RAM=8K RAM1=8K -sam3u2* sam3u ROM=128K RAM=16K RAM1=16K -sam3u4* sam3u ROM=265K RAM=32K RAM1=16K - -sam3x4c* sam3x ROM=256K RAM=32K RAM1=32K -sam3x4e* sam3xnfc ROM=256K RAM=32K RAM1=32K -sam3x8c* sam3x ROM=512K RAM=64K RAM1=32K -sam3x8e* sam3xnfc ROM=512K RAM=64K RAM1=32K - -samd10?13* samd ROM=8K RAM=4K -samd10?14* samd ROM=16K RAM=4K - -################################################################################ -# the SAM4 chips - -sam4l?8* sam4l ROM=512K RAM=64K RAM1=4K -sam4l?4* sam4l ROM=256K RAM=32K RAM1=4K -sam4l?2* sam4l ROM=128K RAM=32K RAM1=4K - -################################################################################ -# the lpc chips - -lpc1311* lpc13 ROM=8K RAM=4K -lpc1313* lpc13 ROM=32K RAM=8K -lpc1342* lpc13 ROM=16K RAM=4K -lpc1343* lpc13 ROM=32K RAM=8K -lpc1315* lpc13u ROM=32K RAM=8K -lpc1316* lpc13u ROM=48K RAM=8K -lpc1317* lpc13u ROM=64K RAM=8K RAM1=2K -lpc1345* lpc13u ROM=32K RAM=8K USBRAM=2K -lpc1346* lpc13u ROM=48K RAM=8K USBRAM=2K -lpc1346* lpc13u ROM=64K RAM=8K USBRAM=2K RAM1=2K - -lpc1751* lpc175x ROM=32K RAM=8K -lpc1752* lpc175x ROM=64K RAM=16K -lpc1754* lpc175x ROM=128K RAM=16K RAM1=16K -lpc1756* lpc175x ROM=256K RAM=16K RAM1=16K -lpc1758* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K -lpc1759* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K -lpc1763* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K -lpc1764* lpc176x ROM=128K RAM=16K RAM1=16K -lpc1765* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K -lpc1766* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K -lpc1767* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K -lpc1768* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K -lpc1769* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K -lpc1774* lpc177x ROM=128K RAM=32K RAM1=8K -lpc1776* lpc177x ROM=256K RAM=64K RAM1=16K -lpc1777* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K -lpc1778* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K -lpc1785* lpc178x ROM=256K RAM=64K RAM1=16K -lpc1786* lpc178x ROM=256K RAM=64K RAM1=16K -lpc1787* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K -lpc1788* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K - -lpc4370* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc4350* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc4330* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc4320* lpc43xx RAM=96K RAM1=40K RAM2=32K RAM3=16K -lpc4310* lpc43xx RAM=96K RAM1=40K RAM2=16K -lpc43S70* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc43S50* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc43S30* lpc43xx RAM=128K RAM1=72K RAM2=32K RAM3=16K -lpc43S20* lpc43xx RAM=96K RAM1=40K RAM2=32K RAM3=16K -lpc43S10* lpc43xx RAM=96K RAM1=40K RAM2=16K -lpc4367* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4357* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4355* lpc43xx ROM=384K ROM1=384K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4353* lpc43xx ROM=256K ROM1=256K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4352* lpc43xx ROM=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4350* lpc43xx RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4337* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4335* lpc43xx ROM=384K ROM1=384K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4333* lpc43xx ROM=256K ROM1=256K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4332* lpc43xx ROM=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4330* lpc43xx RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4327* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4325* lpc43xx ROM=384K ROM1=384K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4323* lpc43xx ROM=256K ROM1=256K RAM=32K RAM1=40K RAM2=16K -lpc4322* lpc43xx ROM=512K RAM=32K RAM1=40K RAM2=16K -lpc4317* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4315* lpc43xx ROM=384K ROM1=384K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc4313* lpc43xx ROM=256K ROM1=256K RAM=32K RAM1=40K RAM2=16K -lpc4312* lpc43xx ROM=512K RAM=32K RAM1=40K RAM2=16K -lpc43S67* lpc43xx ROM=512K ROM1=512K RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc43S57* lpc43xx RAM=32K RAM1=40K RAM2=32K RAM3=16K -lpc43S37* lpc43xx RAM=32K RAM1=40K RAM2=32K RAM3=16K - -################################################################################ -# the efm32 chips - -# Zero Gecko -efm32zg???f4 efm32zg ROM=4K RAM=2K -efm32zg???f8 efm32zg ROM=8K RAM=2K -efm32zg???f16 efm32zg ROM=16K RAM=4K -efm32zg???f32 efm32zg ROM=32K RAM=4K - -# Happy Gecko -efm32hg[12]??f32 efm32hg ROM=32K RAM=4K -efm32hg3??f32 efm32hg ROM=32K RAM=8K -efm32hg???f64 efm32hg ROM=64K RAM=8K - -# Tiny Gecko -efm32tg108f4 efm32tg ROM=4K RAM=1K -efm32tg110f4 efm32tg ROM=4K RAM=2K -efm32tg???f8 efm32tg ROM=8K RAM=2K -efm32tg???f16 efm32tg ROM=16K RAM=4K -efm32tg???f32 efm32tg ROM=32K RAM=4K - -# Gecko -efm32g200f16 efm32g ROM=16K RAM=8K -efm32g???f32 efm32g ROM=32K RAM=8K -efm32g???f64 efm32g ROM=64K RAM=16K -efm32g???f128 efm32g ROM=128K RAM=16K - -# Large Gecko -efm32lg???f64 efm32lg ROM=64K RAM=32K -efm32lg???f128 efm32lg ROM=128K RAM=32K -efm32lg???f256 efm32lg ROM=256K RAM=32K - -# Giant Gecko -efm32gg???f512 efm32gg ROM=512K RAM=128K -efm32gg???f1024 efm32gg ROM=1024K RAM=128K - -# Wonder Gecko -efm32wg???f64 efm32gg ROM=64K RAM=32K -efm32wg???f128 efm32gg ROM=128K RAM=32K -efm32wg???f256 efm32gg ROM=256K RAM=32K - -################################################################################ -# the TI cortex M3 chips - -lm3s101 lm3sandstorm ROM=8K RAM=2K -lm3s102 lm3sandstorm ROM=8K RAM=2K - -lm3s300 lm3sandstorm ROM=16K RAM=4K -lm3s301 lm3sandstorm ROM=16K RAM=2K -lm3s308 lm3sandstorm ROM=16K RAM=4K -lm3s310 lm3sandstorm ROM=16K RAM=4K -lm3s315 lm3sandstorm ROM=16K RAM=4K -lm3s316 lm3sandstorm ROM=16K RAM=4K -lm3s317 lm3sandstorm ROM=16K RAM=4K -lm3s328 lm3sandstorm ROM=16K RAM=4K -lm3s600 lm3sandstorm ROM=32K RAM=8K -lm3s601 lm3sandstorm ROM=32K RAM=8K -lm3s608 lm3sandstorm ROM=32K RAM=8K -lm3s610 lm3sandstorm ROM=32K RAM=8K -lm3s611 lm3sandstorm ROM=32K RAM=8K -lm3s612 lm3sandstorm ROM=32K RAM=8K -lm3s613 lm3sandstorm ROM=32K RAM=8K -lm3s615 lm3sandstorm ROM=32K RAM=8K -lm3s617 lm3sandstorm ROM=32K RAM=8K -lm3s618 lm3sandstorm ROM=32K RAM=8K -lm3s628 lm3sandstorm ROM=32K RAM=8K -lm3s800 lm3sandstorm ROM=64K RAM=8K -lm3s801 lm3sandstorm ROM=64K RAM=8K -lm3s808 lm3sandstorm ROM=64K RAM=8K -lm3s811 lm3sandstorm ROM=64K RAM=8K -lm3s812 lm3sandstorm ROM=64K RAM=8K -lm3s815 lm3sandstorm ROM=64K RAM=8K -lm3s817 lm3sandstorm ROM=64K RAM=8K -lm3s818 lm3sandstorm ROM=64K RAM=8K -lm3s828 lm3sandstorm ROM=64K RAM=8K - -lm3s1110 lm3fury ROM=64K RAM=16K -lm3s1133 lm3fury ROM=64K RAM=16K -lm3s1138 lm3fury ROM=64K RAM=16K -lm3s1150 lm3fury ROM=64K RAM=16K -lm3s1162 lm3fury ROM=64K RAM=16K -lm3s1165 lm3fury ROM=64K RAM=16K -lm3s1332 lm3fury ROM=96K RAM=16K -lm3s1435 lm3fury ROM=96K RAM=32K -lm3s1439 lm3fury ROM=96K RAM=32K -lm3s1512 lm3fury ROM=96K RAM=64K -lm3s1538 lm3fury ROM=96K RAM=64K -lm3s1601 lm3fury ROM=128K RAM=32K -lm3s1607 lm3fury ROM=128K RAM=32K -lm3s1608 lm3fury ROM=128K RAM=32K -lm3s1620 lm3fury ROM=128K RAM=32K -lm3s3748 lm3fury ROM=128K RAM=64K -lm3s6965 lm3fury ROM=256K RAM=64K -lm3s8962 lm3fury ROM=256K RAM=64K - -lm4f120xl lm4f ROM=128K RAM=32K - - -################################################################################ -# the TI cortex R4F chips - -rm46l852* rm46l ROM=1280K RAM=192K - -################################################################################ -# NXP/Freescale Vybrid VF6xx parts. (Cortex A5+M4 pair) - -vf610 vf6xx RAM=256K RAM1=256K RAM_OFF=0x1f000000 RAM1_OFF=0x3f040000 - -################################################################################ -# SWM050 chips - -swm050* END ROM=8K RAM=1K ROM_OFF=0x00000000 RAM_OFF=0x20000000 CPU=cortex-m0 FPU=soft - -################################################################################ -# Qorvo PAC55xx Cortex-M4 based chips - -pac5523 pac55xx ROM=128K RAM=32K -pac5524 pac55xx ROM=128K RAM=32K -pac5527 pac55xx ROM=128K RAM=32K -pac5532 pac55xx ROM=128K RAM=32K -pac5556 pac55xx ROM=128K RAM=32K - -################################################################################ -################################################################################ -################################################################################ -# the STM32 family groups - -stm32f3ccm stm32f3 CCM_OFF=0x10000000 -stm32f4ccm stm32f4 CCM_OFF=0x10000000 -stm32f7ccm stm32f7 CCM_OFF=0x20000000 -stm32g4ccm stm32g4 CCM_OFF=0x10000000 -stm32l1eep stm32l1 EEP_OFF=0x08080000 - -################################################################################ -# the SAM3 family groups -sam3xnfc sam3x NFCRAM=4K NFCRAM_OFF=0x20100000 - -################################################################################ -# the lpc family groups - -lpc13 lpc13xx -lpc13u lpc13xx USBRAM_OFF=0x20004000 - -lpc17[56]x lpc17xx RAM1_OFF=0x2007C000 RAM2_OFF=0x20080000 -lpc17[78]x lpc17xx RAM1_OFF=0x20000000 RAM2_OFF=0x20004000 - -lpc43xx_m0 lpc43xx CPU=cortex-m0 FPU=soft -lpc43xx_m4 lpc43xx CPU=cortex-m4 FPU=hard-fp4-sp-d16 - -################################################################################ -################################################################################ -################################################################################ -# the STM32 families - -stm32f0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0 FPU=soft -stm32f1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -stm32f2 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -stm32f3 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 -stm32f4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 -#stm32f7 is supported on GCC-arm-embedded 4.8 2014q4 -stm32f7 END ROM_OFF=0x08000000 RAM_OFF=0x20010000 CPU=cortex-m7 FPU=hard-fpv5-sp-d16 -stm32l0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft -stm32l1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -stm32l4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 RAM2_OFF=0x10000000 RAM3_OFF=0x20040000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 -stm32g0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft -stm32g4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 -stm32w END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -stm32t END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft - -################################################################################ -# the SAM3 families - -sam3a END ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000 CPU=cortex-m3 FPU=soft -sam3n END ROM_OFF=0x00400000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -sam3s END ROM_OFF=0x00400000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -sam3u END ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000 NFCRAM=4K NFCRAM_OFF=0x20100000 CPU=cortex-m3 FPU=soft -sam3x END ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000 CPU=cortex-m3 FPU=soft -samd END ROM_OFF=0x00000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft - -################################################################################ -# the SAM4 families -sam4l END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x21000000 - -################################################################################ -# the lpc families - -lpc13xx END ROM_OFF=0x00000000 RAM_OFF=0x10000000 RAM1_OFF=0x20000000 CPU=cortex-m3 FPU=soft -lpc17xx END ROM_OFF=0x00000000 RAM_OFF=0x10000000 CPU=cortex-m3 FPU=soft -lpc43xx + ROM_OFF=0x1A000000 ROM1_OFF=0x1B000000 RAM_OFF=0x10000000 RAM1_OFF=0x10080000 -lpc43xx + RAM2_OFF=0x20000000 RAM3_OFF=0x20008000 -lpc43xx END CPU=cortex-m4 FPU=hard-fpv4-sp-d16 - -################################################################################ -# the efm32 Gecko families - -efm32zg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m0plus FPU=soft -efm32hg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m0plus FPU=soft -efm32tg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m3 FPU=soft -efm32g END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m3 FPU=soft -efm32lg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m3 FPU=soft -efm32gg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m3 FPU=soft -efm32wg END ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 - -################################################################################ -# Cortex LM3 and LM4 families - -lm3fury lm3s -lm3sandstorm lm3s -lm3s END ROM_OFF=0x00000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft -lm4f END ROM_OFF=0x00000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 - - -################################################################################ -# Cortex R4F families - -rm46l END ROM_OFF=0x00000000 RAM_OFF=0x08000000 RAM1_OFF=0x08400000 - -################################################################################ -# VF6xx families - -vf6xx END CPU=cortex-m4 FPU=hard-fpv4-sp-d16 - -################################################################################ -# PAC55xx families - -pac55xx END ROM_OFF=0x00000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 diff --git a/libopencm3/ld/linker.ld.S b/libopencm3/ld/linker.ld.S deleted file mode 100644 index 908ad9e..0000000 --- a/libopencm3/ld/linker.ld.S +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* Generic linker script for all targets using libopencm3. */ - -/* Enforce emmition of the vector table. */ -EXTERN(vector_table) - -/* Define the entry point of the output file. */ -ENTRY(reset_handler) - -/* Define memory regions. */ -MEMORY -{ - /* RAM is always used */ - ram (rwx) : ORIGIN = _RAM_OFF, LENGTH = _RAM - -#if defined(_ROM) - rom (rx) : ORIGIN = _ROM_OFF, LENGTH = _ROM -#endif -#if defined(_ROM1) - rom1 (rx) : ORIGIN = _ROM1_OFF, LENGTH = _ROM1 -#endif -#if defined(_ROM2) - rom2 (rx) : ORIGIN = _ROM2_OFF, LENGTH = _ROM2 -#endif -#if defined(_RAM1) - ram1 (rwx) : ORIGIN = _RAM1_OFF, LENGTH = _RAM1 -#endif -#if defined(_RAM2) - ram2 (rwx) : ORIGIN = _RAM2_OFF, LENGTH = _RAM2 -#endif -#if defined(_RAM3) - ram3 (rwx) : ORIGIN = _RAM3_OFF, LENGTH = _RAM3 -#endif -#if defined(_CCM) - ccm (rwx) : ORIGIN = _CCM_OFF, LENGTH = _CCM -#endif -#if defined(_EEP) - eep (r) : ORIGIN = _EEP_OFF, LENGTH = _EEP -#endif -#if defined(_XSRAM) - xsram (rw) : ORIGIN = _XSRAM_OFF, LENGTH = _XSRAM -#endif -#if defined(_XDRAM) - xdram (rw) : ORIGIN = _XDRAM_OFF, LENGTH = _XDRAM -#endif -#if defined(_NFCRAM) - nfcram (rw) : ORIGIN _NFCRAM_OFF, LENGTH = _NFCRAM -#endif -} - -/* Define sections. */ -SECTIONS -{ - .text : { - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - } >rom - - /* C++ Static constructors/destructors, also used for - * __attribute__((constructor)) and the likes. - */ - .preinit_array : { - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - } >rom - .init_array : { - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - } >rom - .fini_array : { - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - } >rom - - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ - .ARM.extab : { - *(.ARM.extab*) - } >rom - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >rom - - . = ALIGN(4); - _etext = .; - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram AT >rom - _data_loadaddr = LOADADDR(.data); - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram - -#if defined(_CCM) - .ccm : { - *(.ccmram*) - . = ALIGN(4); - } >ccm -#endif - -#if defined(_RAM1) - .ram1 : { - *(.ram1*) - . = ALIGN(4); - } >ram1 -#endif - -#if defined(_RAM2) - .ram2 : { - *(.ram2*) - . = ALIGN(4); - } >ram2 -#endif - -#if defined(_RAM3) - .ram3 : { - *(.ram3*) - . = ALIGN(4); - } >ram3 -#endif - -#if defined(_XSRAM) - .xsram : { - *(.xsram*) - . = ALIGN(4); - } >xsram -#endif - -#if defined(_XDRAM) - .xdram : { - *(.xdram*) - . = ALIGN(4); - } >xdram -#endif - -#if defined(_NFCRAM) - .nfcram : { - *(.nfcram*) - . = ALIGN(4); - } >nfcram -#endif - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - . = ALIGN(4); - end = .; -} - -PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); - diff --git a/libopencm3/ld/tests/device.data b/libopencm3/ld/tests/device.data deleted file mode 100644 index 82b5426..0000000 --- a/libopencm3/ld/tests/device.data +++ /dev/null @@ -1,2 +0,0 @@ -device family A=val B=val -family END CPU=cpu FPU=fpu diff --git a/libopencm3/ld/tests/device.result b/libopencm3/ld/tests/device.result deleted file mode 100644 index 0844140..0000000 --- a/libopencm3/ld/tests/device.result +++ /dev/null @@ -1,6 +0,0 @@ --DFAMILY -DDEVICE --DFAMILY -DDEVICE -D_A=val -D_B=val -family -device -cpu -fpu diff --git a/libopencm3/ld/tests/ignore.data b/libopencm3/ld/tests/ignore.data deleted file mode 100644 index 0ed2087..0000000 --- a/libopencm3/ld/tests/ignore.data +++ /dev/null @@ -1 +0,0 @@ -ignore END A B C D -E=val f=val diff --git a/libopencm3/ld/tests/ignore.result b/libopencm3/ld/tests/ignore.result deleted file mode 100644 index ce5436b..0000000 --- a/libopencm3/ld/tests/ignore.result +++ /dev/null @@ -1,6 +0,0 @@ --DIGNORE --DIGNORE -ignore - - - diff --git a/libopencm3/ld/tests/multiline.data b/libopencm3/ld/tests/multiline.data deleted file mode 100644 index 1b13590..0000000 --- a/libopencm3/ld/tests/multiline.data +++ /dev/null @@ -1,2 +0,0 @@ -multiline + A=val B=val -multiline END C=val D=val diff --git a/libopencm3/ld/tests/multiline.result b/libopencm3/ld/tests/multiline.result deleted file mode 100644 index a359707..0000000 --- a/libopencm3/ld/tests/multiline.result +++ /dev/null @@ -1,6 +0,0 @@ --DMULTILINE --DMULTILINE -D_A=val -D_B=val -D_C=val -D_D=val -multiline - - - diff --git a/libopencm3/ld/tests/pattern.data b/libopencm3/ld/tests/pattern.data deleted file mode 100644 index c915ebc..0000000 --- a/libopencm3/ld/tests/pattern.data +++ /dev/null @@ -1,2 +0,0 @@ -p?tte* parent A=val B=val -parent END C=val D=val diff --git a/libopencm3/ld/tests/pattern.result b/libopencm3/ld/tests/pattern.result deleted file mode 100644 index d999c45..0000000 --- a/libopencm3/ld/tests/pattern.result +++ /dev/null @@ -1,6 +0,0 @@ --DPARENT -DPATTERN --DPARENT -DPATTERN -D_A=val -D_B=val -D_C=val -D_D=val -parent -pattern - - diff --git a/libopencm3/ld/tests/single.data b/libopencm3/ld/tests/single.data deleted file mode 100644 index eb4e1ab..0000000 --- a/libopencm3/ld/tests/single.data +++ /dev/null @@ -1 +0,0 @@ -single END A=val B=val diff --git a/libopencm3/ld/tests/single.result b/libopencm3/ld/tests/single.result deleted file mode 100644 index b9cb568..0000000 --- a/libopencm3/ld/tests/single.result +++ /dev/null @@ -1,6 +0,0 @@ --DSINGLE --DSINGLE -D_A=val -D_B=val -single - - - diff --git a/libopencm3/ld/tests/tree1.data b/libopencm3/ld/tests/tree1.data deleted file mode 100644 index e4f3ad7..0000000 --- a/libopencm3/ld/tests/tree1.data +++ /dev/null @@ -1,2 +0,0 @@ -tree1 parent A=val B=val -parent END C=val D=val diff --git a/libopencm3/ld/tests/tree1.result b/libopencm3/ld/tests/tree1.result deleted file mode 100644 index dab933e..0000000 --- a/libopencm3/ld/tests/tree1.result +++ /dev/null @@ -1,6 +0,0 @@ --DPARENT -DTREE1 --DPARENT -DTREE1 -D_A=val -D_B=val -D_C=val -D_D=val -parent -tree1 - - diff --git a/libopencm3/ld/tests/tree5.data b/libopencm3/ld/tests/tree5.data deleted file mode 100644 index b960395..0000000 --- a/libopencm3/ld/tests/tree5.data +++ /dev/null @@ -1,5 +0,0 @@ -tree5 tree4 A=val -tree4 tree3 B=val -tree3 tree2 C=val -tree2 tree1 D=val -tree1 END E=VAL F=val diff --git a/libopencm3/ld/tests/tree5.result b/libopencm3/ld/tests/tree5.result deleted file mode 100644 index a55d694..0000000 --- a/libopencm3/ld/tests/tree5.result +++ /dev/null @@ -1,6 +0,0 @@ --DTREE1 -DTREE2 -DTREE3 -DTREE4 -DTREE5 --DTREE1 -DTREE2 -DTREE3 -DTREE4 -DTREE5 -D_A=val -D_B=val -D_C=val -D_D=val -D_E=VAL -D_F=val -tree1 -tree2 - - diff --git a/libopencm3/ld/tests/twomatch.data b/libopencm3/ld/tests/twomatch.data deleted file mode 100644 index ab69daa..0000000 --- a/libopencm3/ld/tests/twomatch.data +++ /dev/null @@ -1,4 +0,0 @@ -twomatch treeparent A=val B=val C=val D=val -# the next line will be ignored because previous matches before and no + there -twomatch treeparent P=val Q=val R=val S=val -treeparent END E F diff --git a/libopencm3/ld/tests/twomatch.result b/libopencm3/ld/tests/twomatch.result deleted file mode 100644 index a98a4f2..0000000 --- a/libopencm3/ld/tests/twomatch.result +++ /dev/null @@ -1,6 +0,0 @@ --DTREEPARENT -DTWOMATCH --DTREEPARENT -DTWOMATCH -D_A=val -D_B=val -D_C=val -D_D=val -treeparent -twomatch - - diff --git a/libopencm3/lib/Makefile.include b/libopencm3/lib/Makefile.include deleted file mode 100644 index 9caf3ee..0000000 --- a/libopencm3/lib/Makefile.include +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2012 Piotr Esden-Tempski -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -# common objects -OBJS += vector.o systick.o scb.o nvic.o assert.o sync.o dwt.o - -# Slightly bigger .elf files but gains the ability to decode macros -DEBUG_FLAGS ?= -ggdb3 -STANDARD_FLAGS ?= -std=c99 - -all: $(SRCLIBDIR)/$(LIBNAME).a - -$(SRCLIBDIR)/$(LIBNAME).a: $(OBJS) - @printf " AR $(LIBNAME).a\n" - $(Q)$(AR) $(ARFLAGS) "$@" $(OBJS) - -%.o: %.c - @printf " CC $( - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This is a generic linker script for Cortex-M targets using libopencm3. - * - * Memory regions MUST be defined in the ld script which includes this one! - * Example: - -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -INCLUDE cortex-m-generic.ld - -*/ - -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) - -/* Define the entry point of the output file. */ -ENTRY(reset_handler) - -/* Define sections. */ -SECTIONS -{ - .text : { - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - } >rom - - /* C++ Static constructors/destructors, also used for __attribute__ - * ((constructor)) and the likes */ - .preinit_array : { - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - } >rom - .init_array : { - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - } >rom - .fini_array : { - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - } >rom - - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ - .ARM.extab : { - *(.ARM.extab*) - } >rom - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >rom - - . = ALIGN(4); - _etext = .; - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram AT >rom - _data_loadaddr = LOADADDR(.data); - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - . = ALIGN(4); - end = .; -} - -PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); - diff --git a/libopencm3/locm3.sublime-project b/libopencm3/locm3.sublime-project deleted file mode 100644 index 19e6127..0000000 --- a/libopencm3/locm3.sublime-project +++ /dev/null @@ -1,35 +0,0 @@ -{ - "folders": - [ - { - "path": ".", - "file_exclude_patterns": - [ - "*.o", - "*.a", - "*.d", - "*.sublime-project", - "*.sublime-workspace", - "*.swp" - ], - "folder_exclude_patterns": - [ - ] - } - ], - "settings": - { - "tab_size": 8, - "translate_tabs_to_spaces": false, - "rulers": [80] - }, - "build_systems": - [ - { - "name": "libopencm3", - "working_dir": "${project_path}", - "file_regex": "^(..[^:]*):([0-9]+):?([0-9]+)?:? (.*)$", - "cmd": ["make"] - } - ] -} diff --git a/libopencm3/mk/README b/libopencm3/mk/README deleted file mode 100644 index 87e37e0..0000000 --- a/libopencm3/mk/README +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------------- -README -------------------------------------------------------------------------------- - - This directory contains makefile modular support files, that can be used in -your project. - - Each module is packaged with two inclusion makefiles, -config.mk and --rules.mk. The first one defines some new variables for the make, or -appends values to the existing variables for the make. The second defines rules -for support building. - - So in your project, the -config.mk should be included at some place, -where you are defining variables (near the beginning of the file), and file --rules.mk should be included in the rules part of makefile (somewhere -near to the end of file). - -Example makefile using the gcc compiler module together with the linker script -generator module: - ->>>>>> -DEVICE = -OPENCM3_DIR = -OBJS += foo.o - -CFLAGS += -Os -ggdb3 -CPPFLAGS += -MD -LDFLAGS += -static -nostartfiles -LDLIBS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group - -include $(OPENCM3_DIR)/mk/genlink-config.mk -include $(OPENCM3_DIR)/mk/gcc-config.mk - -.PHONY: clean all - -all: binary.elf binary.hex - -clean: - $(Q)$(RM) -rf binary.* *.o - -include $(OPENCM3_DIR)/mk/genlink-rules.mk -include $(OPENCM3_DIR)/mk/gcc-rules.mk -<<<<<< - - -MODULES -======= - -------------------------------------------------------------------------------- -gcc -------------------------------------------------------------------------------- - - This module adds an extended support for GCC toolchain. This adds rules, -necessary for compiling C and C++ files into elf binary, and rules for -generation of bin, hex, or srec output files for flashing. - -Variables to control the build process (should be set in your makefile): ------------------------------------------------------------------------- - -CFLAGS C compiler flags -CXXFLAGS C++ compiler flags -CPPFLAGS C preprocessor flags (used for C and for C++ compiler) -LDFLAGS Linker flags -ARCH_FLAGS Architecture specification flags (-mcpu, -march etc ) - -Variables to tell gcc about project dependencies and input files ----------------------------------------------------------------- - -LDSCRIPT Linker script file name (can be generated or fixed) -LIBDEPS Array of library filenames that shoud be rebuilt if needed -LDLIBS Array of libraries to be linked with (array of -l) -OBJS Array of object files to be built - - -------------------------------------------------------------------------------- -genlink -------------------------------------------------------------------------------- - - This module adds an support for the user to the linker script generator. The -linker script will be generated as the file $(DEVICE).ld in the project folder, -and automatically be used for the linking process. -Additionally the matching library is added to the LDLIBS variable. - -Variables to control the build process (should be set in your makefile): ------------------------------------------------------------------------- - -DEVICE The full device part name used for the compilation process. -OPENCM3_DIR The root path of libopencm3 library. - -Output variables from this module: ----------------------------------- - -CPPFLAGS (appended) - - Appends the chip family to the CPPFLAGS. For example -DSTM32F1 - - Appends the include path for libopencm3 - -ARCH_FLAGS (replaced) - - Architecture build flags for specified chip. - * No needed to handle this variable if you use module too. - -LDSCRIPT (replaced) - - Linker script generated file. - * No needed to handle this variable if you use module too. - -LDLIBS (appended) - - LDLIBS += -lopencm3_$(family) is appended to link against the - matching library. - -LDFLAGS (appended) - - LDFLAGS += -L$(OPENCM3_DIR)/lib is appended to make sure the - matching library can be found. - -family,cpu,fpu (replaced) - - these are used internally to create the above variables - -Temporary variables that you should not use in your makefile: -------------------------------------------------------------- - -GENLINK_DEFS -GENLINK_ARCH -GENLINK_LIB diff --git a/libopencm3/mk/gcc-config.mk b/libopencm3/mk/gcc-config.mk deleted file mode 100644 index 8c92424..0000000 --- a/libopencm3/mk/gcc-config.mk +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2014 Frantisek Burian -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -############################################################################### -# The support makefile for GCC compiler toolchain, the rules part. -# -# please read mk/README for specification how to use this file in your project - - -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf - -CC := $(PREFIX)-gcc -CXX := $(PREFIX)-g++ -LD := $(PREFIX)-gcc -AR := $(PREFIX)-ar -AS := $(PREFIX)-as -OBJCOPY := $(PREFIX)-objcopy -OBJDUMP := $(PREFIX)-objdump -GDB := $(PREFIX)-gdb -SIZE := $(PREFIX)-size diff --git a/libopencm3/mk/gcc-rules.mk b/libopencm3/mk/gcc-rules.mk deleted file mode 100644 index 821912b..0000000 --- a/libopencm3/mk/gcc-rules.mk +++ /dev/null @@ -1,56 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2014 Frantisek Burian -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -############################################################################### -# The support makefile for GCC compiler toolchain, the rules part. -# -# please read mk/README for specification how to use this file in your project -# - -%.bin: %.elf - @printf " OBJCOPY $@\n" - $(Q)$(OBJCOPY) -Obinary $< $@ - -%.hex: %.elf - @printf " OBJCOPY $@\n" - $(Q)$(OBJCOPY) -Oihex $< $@ - -%.srec: %.elf - @printf " OBJCOPY $@\n" - $(Q)$(OBJCOPY) -Osrec $< $@ - -%.list: %.elf - @printf " OBJDUMP $@\n" - $(Q)$(OBJDUMP) -S $< > $@ - -%.elf: $(OBJS) $(LDSCRIPT) $(LIBDEPS) - @printf " LD $(*).elf\n" - $(Q)$(LD) $(OBJS) $(LDLIBS) $(LDFLAGS) -T$(LDSCRIPT) $(ARCH_FLAGS) -o $@ - -%.o: %.c - @printf " CC $<\n" - $(Q)$(CC) $(CFLAGS) $(CPPFLAGS) $(ARCH_FLAGS) -o $@ -c $< - -%.o: %.cxx - @printf " CXX $<\n" - $(Q)$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(ARCH_FLAGS) -o $@ -c $< - -%.o: %.cpp - @printf " CXX $(*).cpp\n" - $(Q)$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(ARCH_FLAGS) -o $@ -c $< diff --git a/libopencm3/mk/genlink-config.mk b/libopencm3/mk/genlink-config.mk deleted file mode 100644 index 4686fe6..0000000 --- a/libopencm3/mk/genlink-config.mk +++ /dev/null @@ -1,82 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2014 Frantisek Burian -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -ifeq ($(DEVICE),) -$(warning no DEVICE specified for linker script generator) -endif - -LDSCRIPT = generated.$(DEVICE).ld -DEVICES_DATA = $(OPENCM3_DIR)/ld/devices.data - -genlink_family :=$(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) FAMILY) -genlink_subfamily :=$(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) SUBFAMILY) -genlink_cpu :=$(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) CPU) -genlink_fpu :=$(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) FPU) -genlink_cppflags :=$(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) CPPFLAGS) - -CPPFLAGS += $(genlink_cppflags) - -ARCH_FLAGS :=-mcpu=$(genlink_cpu) -ifeq ($(genlink_cpu),$(filter $(genlink_cpu),cortex-m0 cortex-m0plus cortex-m3 cortex-m4 cortex-m7)) -ARCH_FLAGS +=-mthumb -endif - -ifeq ($(genlink_fpu),soft) -ARCH_FLAGS += -msoft-float -else ifeq ($(genlink_fpu),hard-fpv4-sp-d16) -ARCH_FLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -else ifeq ($(genlink_fpu),hard-fpv5-sp-d16) -ARCH_FLAGS += -mfloat-abi=hard -mfpu=fpv5-sp-d16 -else -$(warning No match for the FPU flags) -endif - - -ifeq ($(genlink_family),) -$(warning $(DEVICE) not found in $(DEVICES_DATA)) -endif - -# only append to LDFLAGS if the library file exists to not break builds -# where those are provided by different means -ifneq (,$(wildcard $(OPENCM3_DIR)/lib/libopencm3_$(genlink_family).a)) -LIBNAME = opencm3_$(genlink_family) -else -ifneq (,$(wildcard $(OPENCM3_DIR)/lib/libopencm3_$(genlink_subfamily).a)) -LIBNAME = opencm3_$(genlink_subfamily) -else -$(warning $(OPENCM3_DIR)/lib/libopencm3_$(genlink_family).a library variant for the selected device does not exist.) -endif -endif - -LDLIBS += -l$(LIBNAME) -LIBDEPS += $(OPENCM3_DIR)/lib/lib$(LIBNAME).a - -# only append to LDLIBS if the directory exists -ifneq (,$(wildcard $(OPENCM3_DIR)/lib)) -LDFLAGS += -L$(OPENCM3_DIR)/lib -else -$(warning $(OPENCM3_DIR)/lib as given be OPENCM3_DIR does not exist.) -endif - -# only append include path to CPPFLAGS if the directory exists -ifneq (,$(wildcard $(OPENCM3_DIR)/include)) -CPPFLAGS += -I$(OPENCM3_DIR)/include -else -$(warning $(OPENCM3_DIR)/include as given be OPENCM3_DIR does not exist.) -endif diff --git a/libopencm3/mk/genlink-rules.mk b/libopencm3/mk/genlink-rules.mk deleted file mode 100644 index ebbcd74..0000000 --- a/libopencm3/mk/genlink-rules.mk +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2014 Frantisek Burian -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -$(LDSCRIPT): $(OPENCM3_DIR)/ld/linker.ld.S $(OPENCM3_DIR)/ld/devices.data - @printf " GENLNK $(DEVICE)\n" - $(Q)$(CPP) $(ARCH_FLAGS) $(shell $(OPENCM3_DIR)/scripts/genlink.py $(DEVICES_DATA) $(DEVICE) DEFS) -P -E $< -o $@ diff --git a/libopencm3/scripts/checkpatch.pl b/libopencm3/scripts/checkpatch.pl deleted file mode 100755 index 54026fb..0000000 --- a/libopencm3/scripts/checkpatch.pl +++ /dev/null @@ -1,3731 +0,0 @@ -#!/usr/bin/perl -w -# (c) 2001, Dave Jones. (the file handling bit) -# (c) 2005, Joel Schopp (the ugly bit) -# (c) 2007,2008, Andy Whitcroft (new conditions, test suite) -# (c) 2008-2010 Andy Whitcroft -# Licensed under the terms of the GNU GPL License version 2 - -use strict; - -my $P = $0; -$P =~ s@.*/@@g; - -my $V = '0.32'; - -use Getopt::Long qw(:config no_auto_abbrev); - -my $quiet = 0; -my $tree = 1; -my $chk_signoff = 1; -my $chk_patch = 1; -my $tst_only; -my $emacs = 0; -my $terse = 0; -my $file = 0; -my $check = 0; -my $summary = 1; -my $mailback = 0; -my $summary_file = 0; -my $show_types = 0; -my $root; -my %debug; -my %ignore_type = (); -my @ignore = (); -my $help = 0; -my $configuration_file = ".checkpatch.conf"; -my $max_line_length = 80; - -sub help { - my ($exitcode) = @_; - - print << "EOM"; -Usage: $P [OPTION]... [FILE]... -Version: $V - -Options: - -q, --quiet quiet - --no-tree run without a kernel tree - --no-signoff do not check for 'Signed-off-by' line - --patch treat FILE as patchfile (default) - --emacs emacs compile window format - --terse one line per report - -f, --file treat FILE as regular source file - --subjective, --strict enable more subjective tests - --ignore TYPE(,TYPE2...) ignore various comma separated message types - --max-line-length=n set the maximum line length, if exceeded, warn - --show-types show the message "types" in the output - --root=PATH PATH to the kernel tree root - --no-summary suppress the per-file summary - --mailback only produce a report in case of warnings/errors - --summary-file include the filename in summary - --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of - 'values', 'possible', 'type', and 'attr' (default - is all off) - --test-only=WORD report only warnings/errors containing WORD - literally - -h, --help, --version display this help and exit - -When FILE is - read standard input. -EOM - - exit($exitcode); -} - -my $conf = which_conf($configuration_file); -if (-f $conf) { - my @conf_args; - open(my $conffile, '<', "$conf") - or warn "$P: Can't find a readable $configuration_file file $!\n"; - - while (<$conffile>) { - my $line = $_; - - $line =~ s/\s*\n?$//g; - $line =~ s/^\s*//g; - $line =~ s/\s+/ /g; - - next if ($line =~ m/^\s*#/); - next if ($line =~ m/^\s*$/); - - my @words = split(" ", $line); - foreach my $word (@words) { - last if ($word =~ m/^#/); - push (@conf_args, $word); - } - } - close($conffile); - unshift(@ARGV, @conf_args) if @conf_args; -} - -GetOptions( - 'q|quiet+' => \$quiet, - 'tree!' => \$tree, - 'signoff!' => \$chk_signoff, - 'patch!' => \$chk_patch, - 'emacs!' => \$emacs, - 'terse!' => \$terse, - 'f|file!' => \$file, - 'subjective!' => \$check, - 'strict!' => \$check, - 'ignore=s' => \@ignore, - 'show-types!' => \$show_types, - 'max-line-length=i' => \$max_line_length, - 'root=s' => \$root, - 'summary!' => \$summary, - 'mailback!' => \$mailback, - 'summary-file!' => \$summary_file, - - 'debug=s' => \%debug, - 'test-only=s' => \$tst_only, - 'h|help' => \$help, - 'version' => \$help -) or help(1); - -help(0) if ($help); - -my $exit = 0; - -if ($#ARGV < 0) { - print "$P: no input files\n"; - exit(1); -} - -@ignore = split(/,/, join(',',@ignore)); -foreach my $word (@ignore) { - $word =~ s/\s*\n?$//g; - $word =~ s/^\s*//g; - $word =~ s/\s+/ /g; - $word =~ tr/[a-z]/[A-Z]/; - - next if ($word =~ m/^\s*#/); - next if ($word =~ m/^\s*$/); - - $ignore_type{$word}++; -} - -my $dbg_values = 0; -my $dbg_possible = 0; -my $dbg_type = 0; -my $dbg_attr = 0; -for my $key (keys %debug) { - ## no critic - eval "\${dbg_$key} = '$debug{$key}';"; - die "$@" if ($@); -} - -my $rpt_cleaners = 0; - -if ($terse) { - $emacs = 1; - $quiet++; -} - -if ($tree) { - if (defined $root) { - if (!top_of_kernel_tree($root)) { - die "$P: $root: --root does not point at a valid tree\n"; - } - } else { - if (top_of_kernel_tree('.')) { - $root = '.'; - } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && - top_of_kernel_tree($1)) { - $root = $1; - } - } - - if (!defined $root) { - print "Must be run from the top-level dir. of a kernel tree\n"; - exit(2); - } -} - -my $emitted_corrupt = 0; - -our $Ident = qr{ - [A-Za-z_][A-Za-z\d_]* - (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* - }x; -our $Storage = qr{extern|static|asmlinkage}; -our $Sparse = qr{ - __user| - __kernel| - __force| - __iomem| - __must_check| - __init_refok| - __kprobes| - __ref| - __rcu - }x; - -# Notes to $Attribute: -# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check -our $Attribute = qr{ - const| - __percpu| - __nocast| - __safe| - __bitwise__| - __packed__| - __packed2__| - __naked| - __maybe_unused| - __always_unused| - __noreturn| - __used| - __cold| - __noclone| - __deprecated| - __read_mostly| - __kprobes| - __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| - ____cacheline_aligned| - ____cacheline_aligned_in_smp| - ____cacheline_internodealigned_in_smp| - __weak - }x; -our $Modifier; -our $Inline = qr{inline|__always_inline|noinline}; -our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; -our $Lval = qr{$Ident(?:$Member)*}; - -our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; -our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; -our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; -our $Float = qr{$Float_hex|$Float_dec|$Float_int}; -our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; -our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; -our $Compare = qr{<=|>=|==|!=|<|>}; -our $Operators = qr{ - <=|>=|==|!=| - =>|->|<<|>>|<|>|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% - }x; - -our $NonptrType; -our $Type; -our $Declare; - -our $NON_ASCII_UTF8 = qr{ - [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte - | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs - | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte - | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates - | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 - | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 - | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 -}x; - -our $UTF8 = qr{ - [\x09\x0A\x0D\x20-\x7E] # ASCII - | $NON_ASCII_UTF8 -}x; - -our $typeTypedefs = qr{(?x: - (?:__)?(?:u|s|be|le)(?:8|16|32|64)| - atomic_t -)}; - -our $logFunctions = qr{(?x: - printk(?:_ratelimited|_once|)| - [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| - WARN(?:_RATELIMIT|_ONCE|)| - panic| - MODULE_[A-Z_]+ -)}; - -our $signature_tags = qr{(?xi: - Signed-off-by:| - Acked-by:| - Tested-by:| - Reviewed-by:| - Reported-by:| - Suggested-by:| - To:| - Cc: -)}; - -our @typeList = ( - qr{void}, - qr{(?:unsigned\s+)?char}, - qr{(?:unsigned\s+)?short}, - qr{(?:unsigned\s+)?int}, - qr{(?:unsigned\s+)?long}, - qr{(?:unsigned\s+)?long\s+int}, - qr{(?:unsigned\s+)?long\s+long}, - qr{(?:unsigned\s+)?long\s+long\s+int}, - qr{unsigned}, - qr{float}, - qr{double}, - qr{bool}, - qr{struct\s+$Ident}, - qr{union\s+$Ident}, - qr{enum\s+$Ident}, - qr{${Ident}_t}, - qr{${Ident}_handler}, - qr{${Ident}_handler_fn}, -); -our @modifierList = ( - qr{fastcall}, -); - -our $allowed_asm_includes = qr{(?x: - irq| - memory -)}; -# memory.h: ARM has a custom one - -sub build_types { - my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; - my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; - $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; - $NonptrType = qr{ - (?:$Modifier\s+|const\s+)* - (?: - (?:typeof|__typeof__)\s*\([^\)]*\)| - (?:$typeTypedefs\b)| - (?:${all}\b) - ) - (?:\s+$Modifier|\s+const)* - }x; - $Type = qr{ - $NonptrType - (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? - (?:\s+$Inline|\s+$Modifier)* - }x; - $Declare = qr{(?:$Storage\s+)?$Type}; -} -build_types(); - - -our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; - -# Using $balanced_parens, $LvalOrFunc, or $FuncArg -# requires at least perl version v5.10.0 -# Any use must be runtime checked with $^V - -our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; -our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; -our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; - -sub deparenthesize { - my ($string) = @_; - return "" if (!defined($string)); - $string =~ s@^\s*\(\s*@@g; - $string =~ s@\s*\)\s*$@@g; - $string =~ s@\s+@ @g; - return $string; -} - -$chk_signoff = 0 if ($file); - -my @rawlines = (); -my @lines = (); -my $vname; -for my $filename (@ARGV) { - my $FILE; - if ($file) { - open($FILE, '-|', "diff -u /dev/null $filename") || - die "$P: $filename: diff failed - $!\n"; - } elsif ($filename eq '-') { - open($FILE, '<&STDIN'); - } else { - open($FILE, '<', "$filename") || - die "$P: $filename: open failed - $!\n"; - } - if ($filename eq '-') { - $vname = 'Your patch'; - } else { - $vname = $filename; - } - while (<$FILE>) { - chomp; - push(@rawlines, $_); - } - close($FILE); - if (!process($filename)) { - $exit = 1; - } - @rawlines = (); - @lines = (); -} - -exit($exit); - -sub top_of_kernel_tree { - my ($root) = @_; - - my @tree_check = ( - "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", - "README", "Documentation", "arch", "include", "drivers", - "fs", "init", "ipc", "kernel", "lib", "scripts", - ); - - foreach my $check (@tree_check) { - if (! -e $root . '/' . $check) { - return 0; - } - } - return 1; -} - -sub parse_email { - my ($formatted_email) = @_; - - my $name = ""; - my $address = ""; - my $comment = ""; - - if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { - $name = $1; - $address = $2; - $comment = $3 if defined $3; - } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { - $address = $1; - $comment = $2 if defined $2; - } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { - $address = $1; - $comment = $2 if defined $2; - $formatted_email =~ s/$address.*$//; - $name = $formatted_email; - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - # If there's a name left after stripping spaces and - # leading quotes, and the address doesn't have both - # leading and trailing angle brackets, the address - # is invalid. ie: - # "joe smith joe@smith.com" bad - # "joe smith ]+>$/) { - $name = ""; - $address = ""; - $comment = ""; - } - } - - $name =~ s/^\s+|\s+$//g; - $name =~ s/^\"|\"$//g; - $address =~ s/^\s+|\s+$//g; - $address =~ s/^\<|\>$//g; - - if ($name =~ /[^\w \-]/i) { ##has "must quote" chars - $name =~ s/(?"; - } - - return $formatted_email; -} - -sub which_conf { - my ($conf) = @_; - - foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { - if (-e "$path/$conf") { - return "$path/$conf"; - } - } - - return ""; -} - -sub expand_tabs { - my ($str) = @_; - - my $res = ''; - my $n = 0; - for my $c (split(//, $str)) { - if ($c eq "\t") { - $res .= ' '; - $n++; - for (; ($n % 8) != 0; $n++) { - $res .= ' '; - } - next; - } - $res .= $c; - $n++; - } - - return $res; -} -sub copy_spacing { - (my $res = shift) =~ tr/\t/ /c; - return $res; -} - -sub line_stats { - my ($line) = @_; - - # Drop the diff line leader and expand tabs - $line =~ s/^.//; - $line = expand_tabs($line); - - # Pick the indent from the front of the line. - my ($white) = ($line =~ /^(\s*)/); - - return (length($line), length($white)); -} - -my $sanitise_quote = ''; - -sub sanitise_line_reset { - my ($in_comment) = @_; - - if ($in_comment) { - $sanitise_quote = '*/'; - } else { - $sanitise_quote = ''; - } -} -sub sanitise_line { - my ($line) = @_; - - my $res = ''; - my $l = ''; - - my $qlen = 0; - my $off = 0; - my $c; - - # Always copy over the diff marker. - $res = substr($line, 0, 1); - - for ($off = 1; $off < length($line); $off++) { - $c = substr($line, $off, 1); - - # Comments we are wacking completly including the begin - # and end, all to $;. - if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { - $sanitise_quote = '*/'; - - substr($res, $off, 2, "$;$;"); - $off++; - next; - } - if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { - $sanitise_quote = ''; - substr($res, $off, 2, "$;$;"); - $off++; - next; - } - if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { - $sanitise_quote = '//'; - - substr($res, $off, 2, $sanitise_quote); - $off++; - next; - } - - # A \ in a string means ignore the next character. - if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && - $c eq "\\") { - substr($res, $off, 2, 'XX'); - $off++; - next; - } - # Regular quotes. - if ($c eq "'" || $c eq '"') { - if ($sanitise_quote eq '') { - $sanitise_quote = $c; - - substr($res, $off, 1, $c); - next; - } elsif ($sanitise_quote eq $c) { - $sanitise_quote = ''; - } - } - - #print "c<$c> SQ<$sanitise_quote>\n"; - if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { - substr($res, $off, 1, $;); - } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { - substr($res, $off, 1, $;); - } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { - substr($res, $off, 1, 'X'); - } else { - substr($res, $off, 1, $c); - } - } - - if ($sanitise_quote eq '//') { - $sanitise_quote = ''; - } - - # The pathname on a #include may be surrounded by '<' and '>'. - if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { - my $clean = 'X' x length($1); - $res =~ s@\<.*\>@<$clean>@; - - # The whole of a #error is a string. - } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { - my $clean = 'X' x length($1); - $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; - } - - return $res; -} - -sub get_quoted_string { - my ($line, $rawline) = @_; - - return "" if ($line !~ m/(\"[X]+\")/g); - return substr($rawline, $-[0], $+[0] - $-[0]); -} - -sub ctx_statement_block { - my ($linenr, $remain, $off) = @_; - my $line = $linenr - 1; - my $blk = ''; - my $soff = $off; - my $coff = $off - 1; - my $coff_set = 0; - - my $loff = 0; - - my $type = ''; - my $level = 0; - my @stack = (); - my $p; - my $c; - my $len = 0; - - my $remainder; - while (1) { - @stack = (['', 0]) if ($#stack == -1); - - #warn "CSB: blk<$blk> remain<$remain>\n"; - # If we are about to drop off the end, pull in more - # context. - if ($off >= $len) { - for (; $remain > 0; $line++) { - last if (!defined $lines[$line]); - next if ($lines[$line] =~ /^-/); - $remain--; - $loff = $len; - $blk .= $lines[$line] . "\n"; - $len = length($blk); - $line++; - last; - } - # Bail if there is no further context. - #warn "CSB: blk<$blk> off<$off> len<$len>\n"; - if ($off >= $len) { - last; - } - if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { - $level++; - $type = '#'; - } - } - $p = $c; - $c = substr($blk, $off, 1); - $remainder = substr($blk, $off); - - #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; - - # Handle nested #if/#else. - if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { - push(@stack, [ $type, $level ]); - } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { - ($type, $level) = @{$stack[$#stack - 1]}; - } elsif ($remainder =~ /^#\s*endif\b/) { - ($type, $level) = @{pop(@stack)}; - } - - # Statement ends at the ';' or a close '}' at the - # outermost level. - if ($level == 0 && $c eq ';') { - last; - } - - # An else is really a conditional as long as its not else if - if ($level == 0 && $coff_set == 0 && - (!defined($p) || $p =~ /(?:\s|\}|\+)/) && - $remainder =~ /^(else)(?:\s|{)/ && - $remainder !~ /^else\s+if\b/) { - $coff = $off + length($1) - 1; - $coff_set = 1; - #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; - #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; - } - - if (($type eq '' || $type eq '(') && $c eq '(') { - $level++; - $type = '('; - } - if ($type eq '(' && $c eq ')') { - $level--; - $type = ($level != 0)? '(' : ''; - - if ($level == 0 && $coff < $soff) { - $coff = $off; - $coff_set = 1; - #warn "CSB: mark coff<$coff>\n"; - } - } - if (($type eq '' || $type eq '{') && $c eq '{') { - $level++; - $type = '{'; - } - if ($type eq '{' && $c eq '}') { - $level--; - $type = ($level != 0)? '{' : ''; - - if ($level == 0) { - if (substr($blk, $off + 1, 1) eq ';') { - $off++; - } - last; - } - } - # Preprocessor commands end at the newline unless escaped. - if ($type eq '#' && $c eq "\n" && $p ne "\\") { - $level--; - $type = ''; - $off++; - last; - } - $off++; - } - # We are truly at the end, so shuffle to the next line. - if ($off == $len) { - $loff = $len + 1; - $line++; - $remain--; - } - - my $statement = substr($blk, $soff, $off - $soff + 1); - my $condition = substr($blk, $soff, $coff - $soff + 1); - - #warn "STATEMENT<$statement>\n"; - #warn "CONDITION<$condition>\n"; - - #print "coff<$coff> soff<$off> loff<$loff>\n"; - - return ($statement, $condition, - $line, $remain + 1, $off - $loff + 1, $level); -} - -sub statement_lines { - my ($stmt) = @_; - - # Strip the diff line prefixes and rip blank lines at start and end. - $stmt =~ s/(^|\n)./$1/g; - $stmt =~ s/^\s*//; - $stmt =~ s/\s*$//; - - my @stmt_lines = ($stmt =~ /\n/g); - - return $#stmt_lines + 2; -} - -sub statement_rawlines { - my ($stmt) = @_; - - my @stmt_lines = ($stmt =~ /\n/g); - - return $#stmt_lines + 2; -} - -sub statement_block_size { - my ($stmt) = @_; - - $stmt =~ s/(^|\n)./$1/g; - $stmt =~ s/^\s*{//; - $stmt =~ s/}\s*$//; - $stmt =~ s/^\s*//; - $stmt =~ s/\s*$//; - - my @stmt_lines = ($stmt =~ /\n/g); - my @stmt_statements = ($stmt =~ /;/g); - - my $stmt_lines = $#stmt_lines + 2; - my $stmt_statements = $#stmt_statements + 1; - - if ($stmt_lines > $stmt_statements) { - return $stmt_lines; - } else { - return $stmt_statements; - } -} - -sub ctx_statement_full { - my ($linenr, $remain, $off) = @_; - my ($statement, $condition, $level); - - my (@chunks); - - # Grab the first conditional/block pair. - ($statement, $condition, $linenr, $remain, $off, $level) = - ctx_statement_block($linenr, $remain, $off); - #print "F: c<$condition> s<$statement> remain<$remain>\n"; - push(@chunks, [ $condition, $statement ]); - if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { - return ($level, $linenr, @chunks); - } - - # Pull in the following conditional/block pairs and see if they - # could continue the statement. - for (;;) { - ($statement, $condition, $linenr, $remain, $off, $level) = - ctx_statement_block($linenr, $remain, $off); - #print "C: c<$condition> s<$statement> remain<$remain>\n"; - last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); - #print "C: push\n"; - push(@chunks, [ $condition, $statement ]); - } - - return ($level, $linenr, @chunks); -} - -sub ctx_block_get { - my ($linenr, $remain, $outer, $open, $close, $off) = @_; - my $line; - my $start = $linenr - 1; - my $blk = ''; - my @o; - my @c; - my @res = (); - - my $level = 0; - my @stack = ($level); - for ($line = $start; $remain > 0; $line++) { - next if ($rawlines[$line] =~ /^-/); - $remain--; - - $blk .= $rawlines[$line]; - - # Handle nested #if/#else. - if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { - push(@stack, $level); - } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { - $level = $stack[$#stack - 1]; - } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { - $level = pop(@stack); - } - - foreach my $c (split(//, $lines[$line])) { - ##print "C<$c>L<$level><$open$close>O<$off>\n"; - if ($off > 0) { - $off--; - next; - } - - if ($c eq $close && $level > 0) { - $level--; - last if ($level == 0); - } elsif ($c eq $open) { - $level++; - } - } - - if (!$outer || $level <= 1) { - push(@res, $rawlines[$line]); - } - - last if ($level == 0); - } - - return ($level, @res); -} -sub ctx_block_outer { - my ($linenr, $remain) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); - return @r; -} -sub ctx_block { - my ($linenr, $remain) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); - return @r; -} -sub ctx_statement { - my ($linenr, $remain, $off) = @_; - - my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); - return @r; -} -sub ctx_block_level { - my ($linenr, $remain) = @_; - - return ctx_block_get($linenr, $remain, 0, '{', '}', 0); -} -sub ctx_statement_level { - my ($linenr, $remain, $off) = @_; - - return ctx_block_get($linenr, $remain, 0, '(', ')', $off); -} - -sub ctx_locate_comment { - my ($first_line, $end_line) = @_; - - # Catch a comment on the end of the line itself. - my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); - return $current_comment if (defined $current_comment); - - # Look through the context and try and figure out if there is a - # comment. - my $in_comment = 0; - $current_comment = ''; - for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { - my $line = $rawlines[$linenr - 1]; - #warn " $line\n"; - if ($linenr == $first_line and $line =~ m@^.\s*\*@) { - $in_comment = 1; - } - if ($line =~ m@/\*@) { - $in_comment = 1; - } - if (!$in_comment && $current_comment ne '') { - $current_comment = ''; - } - $current_comment .= $line . "\n" if ($in_comment); - if ($line =~ m@\*/@) { - $in_comment = 0; - } - } - - chomp($current_comment); - return($current_comment); -} -sub ctx_has_comment { - my ($first_line, $end_line) = @_; - my $cmt = ctx_locate_comment($first_line, $end_line); - - ##print "LINE: $rawlines[$end_line - 1 ]\n"; - ##print "CMMT: $cmt\n"; - - return ($cmt ne ''); -} - -sub raw_line { - my ($linenr, $cnt) = @_; - - my $offset = $linenr - 1; - $cnt++; - - my $line; - while ($cnt) { - $line = $rawlines[$offset++]; - next if (defined($line) && $line =~ /^-/); - $cnt--; - } - - return $line; -} - -sub cat_vet { - my ($vet) = @_; - my ($res, $coded); - - $res = ''; - while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { - $res .= $1; - if ($2 ne '') { - $coded = sprintf("^%c", unpack('C', $2) + 64); - $res .= $coded; - } - } - $res =~ s/$/\$/; - - return $res; -} - -my $av_preprocessor = 0; -my $av_pending; -my @av_paren_type; -my $av_pend_colon; - -sub annotate_reset { - $av_preprocessor = 0; - $av_pending = '_'; - @av_paren_type = ('E'); - $av_pend_colon = 'O'; -} - -sub annotate_values { - my ($stream, $type) = @_; - - my $res; - my $var = '_' x length($stream); - my $cur = $stream; - - print "$stream\n" if ($dbg_values > 1); - - while (length($cur)) { - @av_paren_type = ('E') if ($#av_paren_type < 0); - print " <" . join('', @av_paren_type) . - "> <$type> <$av_pending>" if ($dbg_values > 1); - if ($cur =~ /^(\s+)/o) { - print "WS($1)\n" if ($dbg_values > 1); - if ($1 =~ /\n/ && $av_preprocessor) { - $type = pop(@av_paren_type); - $av_preprocessor = 0; - } - - } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { - print "CAST($1)\n" if ($dbg_values > 1); - push(@av_paren_type, $type); - $type = 'c'; - - } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { - print "DECLARE($1)\n" if ($dbg_values > 1); - $type = 'T'; - - } elsif ($cur =~ /^($Modifier)\s*/) { - print "MODIFIER($1)\n" if ($dbg_values > 1); - $type = 'T'; - - } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { - print "DEFINE($1,$2)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - push(@av_paren_type, $type); - if ($2 ne '') { - $av_pending = 'N'; - } - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { - print "UNDEF($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - push(@av_paren_type, $type); - - } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { - print "PRE_START($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - - push(@av_paren_type, $type); - push(@av_paren_type, $type); - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { - print "PRE_RESTART($1)\n" if ($dbg_values > 1); - $av_preprocessor = 1; - - push(@av_paren_type, $av_paren_type[$#av_paren_type]); - - $type = 'E'; - - } elsif ($cur =~ /^(\#\s*(?:endif))/o) { - print "PRE_END($1)\n" if ($dbg_values > 1); - - $av_preprocessor = 1; - - # Assume all arms of the conditional end as this - # one does, and continue as if the #endif was not here. - pop(@av_paren_type); - push(@av_paren_type, $type); - $type = 'E'; - - } elsif ($cur =~ /^(\\\n)/o) { - print "PRECONT($1)\n" if ($dbg_values > 1); - - } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { - print "ATTR($1)\n" if ($dbg_values > 1); - $av_pending = $type; - $type = 'N'; - - } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { - print "SIZEOF($1)\n" if ($dbg_values > 1); - if (defined $2) { - $av_pending = 'V'; - } - $type = 'N'; - - } elsif ($cur =~ /^(if|while|for)\b/o) { - print "COND($1)\n" if ($dbg_values > 1); - $av_pending = 'E'; - $type = 'N'; - - } elsif ($cur =~/^(case)/o) { - print "CASE($1)\n" if ($dbg_values > 1); - $av_pend_colon = 'C'; - $type = 'N'; - - } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { - print "KEYWORD($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(\()/o) { - print "PAREN('$1')\n" if ($dbg_values > 1); - push(@av_paren_type, $av_pending); - $av_pending = '_'; - $type = 'N'; - - } elsif ($cur =~ /^(\))/o) { - my $new_type = pop(@av_paren_type); - if ($new_type ne '_') { - $type = $new_type; - print "PAREN('$1') -> $type\n" - if ($dbg_values > 1); - } else { - print "PAREN('$1')\n" if ($dbg_values > 1); - } - - } elsif ($cur =~ /^($Ident)\s*\(/o) { - print "FUNC($1)\n" if ($dbg_values > 1); - $type = 'V'; - $av_pending = 'V'; - - } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { - if (defined $2 && $type eq 'C' || $type eq 'T') { - $av_pend_colon = 'B'; - } elsif ($type eq 'E') { - $av_pend_colon = 'L'; - } - print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); - $type = 'V'; - - } elsif ($cur =~ /^($Ident|$Constant)/o) { - print "IDENT($1)\n" if ($dbg_values > 1); - $type = 'V'; - - } elsif ($cur =~ /^($Assignment)/o) { - print "ASSIGN($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~/^(;|{|})/) { - print "END($1)\n" if ($dbg_values > 1); - $type = 'E'; - $av_pend_colon = 'O'; - - } elsif ($cur =~/^(,)/) { - print "COMMA($1)\n" if ($dbg_values > 1); - $type = 'C'; - - } elsif ($cur =~ /^(\?)/o) { - print "QUESTION($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(:)/o) { - print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); - - substr($var, length($res), 1, $av_pend_colon); - if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { - $type = 'E'; - } else { - $type = 'N'; - } - $av_pend_colon = 'O'; - - } elsif ($cur =~ /^(\[)/o) { - print "CLOSE($1)\n" if ($dbg_values > 1); - $type = 'N'; - - } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { - my $variant; - - print "OPV($1)\n" if ($dbg_values > 1); - if ($type eq 'V') { - $variant = 'B'; - } else { - $variant = 'U'; - } - - substr($var, length($res), 1, $variant); - $type = 'N'; - - } elsif ($cur =~ /^($Operators)/o) { - print "OP($1)\n" if ($dbg_values > 1); - if ($1 ne '++' && $1 ne '--') { - $type = 'N'; - } - - } elsif ($cur =~ /(^.)/o) { - print "C($1)\n" if ($dbg_values > 1); - } - if (defined $1) { - $cur = substr($cur, length($1)); - $res .= $type x length($1); - } - } - - return ($res, $var); -} - -sub possible { - my ($possible, $line) = @_; - my $notPermitted = qr{(?: - ^(?: - $Modifier| - $Storage| - $Type| - DEFINE_\S+ - )$| - ^(?: - goto| - return| - case| - else| - asm|__asm__| - do| - \#| - \#\#| - )(?:\s|$)| - ^(?:typedef|struct|enum)\b - )}x; - warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); - if ($possible !~ $notPermitted) { - # Check for modifiers. - $possible =~ s/\s*$Storage\s*//g; - $possible =~ s/\s*$Sparse\s*//g; - if ($possible =~ /^\s*$/) { - - } elsif ($possible =~ /\s/) { - $possible =~ s/\s*$Type\s*//g; - for my $modifier (split(' ', $possible)) { - if ($modifier !~ $notPermitted) { - warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); - push(@modifierList, $modifier); - } - } - - } else { - warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); - push(@typeList, $possible); - } - build_types(); - } else { - warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); - } -} - -my $prefix = ''; - -sub show_type { - return !defined $ignore_type{$_[0]}; -} - -sub report { - if (!show_type($_[1]) || - (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { - return 0; - } - my $line; - if ($show_types) { - $line = "$prefix$_[0]:$_[1]: $_[2]\n"; - } else { - $line = "$prefix$_[0]: $_[2]\n"; - } - $line = (split('\n', $line))[0] . "\n" if ($terse); - - push(our @report, $line); - - return 1; -} -sub report_dump { - our @report; -} - -sub ERROR { - if (report("ERROR", $_[0], $_[1])) { - our $clean = 0; - our $cnt_error++; - } -} -sub WARN { - if (report("WARNING", $_[0], $_[1])) { - our $clean = 0; - our $cnt_warn++; - } -} -sub CHK { - if ($check && report("CHECK", $_[0], $_[1])) { - our $clean = 0; - our $cnt_chk++; - } -} - -sub check_absolute_file { - my ($absolute, $herecurr) = @_; - my $file = $absolute; - - ##print "absolute<$absolute>\n"; - - # See if any suffix of this path is a path within the tree. - while ($file =~ s@^[^/]*/@@) { - if (-f "$root/$file") { - ##print "file<$file>\n"; - last; - } - } - if (! -f _) { - return 0; - } - - # It is, so see if the prefix is acceptable. - my $prefix = $absolute; - substr($prefix, -length($file)) = ''; - - ##print "prefix<$prefix>\n"; - if ($prefix ne ".../") { - WARN("USE_RELATIVE_PATH", - "use relative pathname instead of absolute in changelog text\n" . $herecurr); - } -} - -sub pos_last_openparen { - my ($line) = @_; - - my $pos = 0; - - my $opens = $line =~ tr/\(/\(/; - my $closes = $line =~ tr/\)/\)/; - - my $last_openparen = 0; - - if (($opens == 0) || ($closes >= $opens)) { - return -1; - } - - my $len = length($line); - - for ($pos = 0; $pos < $len; $pos++) { - my $string = substr($line, $pos); - if ($string =~ /^($FuncArg|$balanced_parens)/) { - $pos += length($1) - 1; - } elsif (substr($line, $pos, 1) eq '(') { - $last_openparen = $pos; - } elsif (index($string, '(') == -1) { - last; - } - } - - return $last_openparen + 1; -} - -sub process { - my $filename = shift; - - my $linenr=0; - my $prevline=""; - my $prevrawline=""; - my $stashline=""; - my $stashrawline=""; - - my $length; - my $indent; - my $previndent=0; - my $stashindent=0; - - our $clean = 1; - my $signoff = 0; - my $is_patch = 0; - - my $in_header_lines = 1; - my $in_commit_log = 0; #Scanning lines before patch - - my $non_utf8_charset = 0; - - our @report = (); - our $cnt_lines = 0; - our $cnt_error = 0; - our $cnt_warn = 0; - our $cnt_chk = 0; - - # Trace the real file/line as we go. - my $realfile = ''; - my $realline = 0; - my $realcnt = 0; - my $here = ''; - my $in_comment = 0; - my $comment_edge = 0; - my $first_line = 0; - my $p1_prefix = ''; - - my $prev_values = 'E'; - - # suppression flags - my %suppress_ifbraces; - my %suppress_whiletrailers; - my %suppress_export; - my $suppress_statement = 0; - - my %camelcase = (); - - # Pre-scan the patch sanitizing the lines. - # Pre-scan the patch looking for any __setup documentation. - # - my @setup_docs = (); - my $setup_docs = 0; - - sanitise_line_reset(); - my $line; - foreach my $rawline (@rawlines) { - $linenr++; - $line = $rawline; - - if ($rawline=~/^\+\+\+\s+(\S+)/) { - $setup_docs = 0; - if ($1 =~ m@Documentation/kernel-parameters.txt$@) { - $setup_docs = 1; - } - #next; - } - if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { - $realline=$1-1; - if (defined $2) { - $realcnt=$3+1; - } else { - $realcnt=1+1; - } - $in_comment = 0; - - # Guestimate if this is a continuing comment. Run - # the context looking for a comment "edge". If this - # edge is a close comment then we must be in a comment - # at context start. - my $edge; - my $cnt = $realcnt; - for (my $ln = $linenr + 1; $cnt > 0; $ln++) { - next if (defined $rawlines[$ln - 1] && - $rawlines[$ln - 1] =~ /^-/); - $cnt--; - #print "RAW<$rawlines[$ln - 1]>\n"; - last if (!defined $rawlines[$ln - 1]); - if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && - $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { - ($edge) = $1; - last; - } - } - if (defined $edge && $edge eq '*/') { - $in_comment = 1; - } - - # Guestimate if this is a continuing comment. If this - # is the start of a diff block and this line starts - # ' *' then it is very likely a comment. - if (!defined $edge && - $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) - { - $in_comment = 1; - } - - ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; - sanitise_line_reset($in_comment); - - } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { - # Standardise the strings and chars within the input to - # simplify matching -- only bother with positive lines. - $line = sanitise_line($rawline); - } - push(@lines, $line); - - if ($realcnt > 1) { - $realcnt-- if ($line =~ /^(?:\+| |$)/); - } else { - $realcnt = 0; - } - - #print "==>$rawline\n"; - #print "-->$line\n"; - - if ($setup_docs && $line =~ /^\+/) { - push(@setup_docs, $line); - } - } - - $prefix = ''; - - $realcnt = 0; - $linenr = 0; - foreach my $line (@lines) { - $linenr++; - - my $rawline = $rawlines[$linenr - 1]; - -#extract the line range in the file after the patch is applied - if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { - $is_patch = 1; - $first_line = $linenr + 1; - $realline=$1-1; - if (defined $2) { - $realcnt=$3+1; - } else { - $realcnt=1+1; - } - annotate_reset(); - $prev_values = 'E'; - - %suppress_ifbraces = (); - %suppress_whiletrailers = (); - %suppress_export = (); - $suppress_statement = 0; - next; - -# track the line number as we move through the hunk, note that -# new versions of GNU diff omit the leading space on completely -# blank context lines so we need to count that too. - } elsif ($line =~ /^( |\+|$)/) { - $realline++; - $realcnt-- if ($realcnt != 0); - - # Measure the line length and indent. - ($length, $indent) = line_stats($rawline); - - # Track the previous line. - ($prevline, $stashline) = ($stashline, $line); - ($previndent, $stashindent) = ($stashindent, $indent); - ($prevrawline, $stashrawline) = ($stashrawline, $rawline); - - #warn "line<$line>\n"; - - } elsif ($realcnt == 1) { - $realcnt--; - } - - my $hunk_line = ($realcnt != 0); - -#make up the handle for any error we report on this line - $prefix = "$filename:$realline: " if ($emacs && $file); - $prefix = "$filename:$linenr: " if ($emacs && !$file); - - $here = "#$linenr: " if (!$file); - $here = "#$realline: " if ($file); - - # extract the filename as it passes - if ($line =~ /^diff --git.*?(\S+)$/) { - $realfile = $1; - $realfile =~ s@^([^/]*)/@@; - $in_commit_log = 0; - } elsif ($line =~ /^\+\+\+\s+(\S+)/) { - $realfile = $1; - $realfile =~ s@^([^/]*)/@@; - $in_commit_log = 0; - - $p1_prefix = $1; - if (!$file && $tree && $p1_prefix ne '' && - -e "$root/$p1_prefix") { - WARN("PATCH_PREFIX", - "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); - } - - if ($realfile =~ m@^include/asm/@) { - ERROR("MODIFIED_INCLUDE_ASM", - "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); - } - next; - } - - $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); - - my $hereline = "$here\n$rawline\n"; - my $herecurr = "$here\n$rawline\n"; - my $hereprev = "$here\n$prevrawline\n$rawline\n"; - - $cnt_lines++ if ($realcnt != 0); - -# Check for incorrect file permissions - if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { - my $permhere = $here . "FILE: $realfile\n"; - if ($realfile !~ m@scripts/@ && - $realfile !~ /\.(py|pl|awk|sh)$/) { - ERROR("EXECUTE_PERMISSIONS", - "do not set execute permissions for source files\n" . $permhere); - } - } - -# Check the patch for a signoff: - if ($line =~ /^\s*signed-off-by:/i) { - $signoff++; - $in_commit_log = 0; - } - -# Check signature styles - if (!$in_header_lines && - $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { - my $space_before = $1; - my $sign_off = $2; - my $space_after = $3; - my $email = $4; - my $ucfirst_sign_off = ucfirst(lc($sign_off)); - - if ($sign_off !~ /$signature_tags/) { - WARN("BAD_SIGN_OFF", - "Non-standard signature: $sign_off\n" . $herecurr); - } - if (defined $space_before && $space_before ne "") { - WARN("BAD_SIGN_OFF", - "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); - } - if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { - WARN("BAD_SIGN_OFF", - "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); - } - if (!defined $space_after || $space_after ne " ") { - WARN("BAD_SIGN_OFF", - "Use a single space after $ucfirst_sign_off\n" . $herecurr); - } - - my ($email_name, $email_address, $comment) = parse_email($email); - my $suggested_email = format_email(($email_name, $email_address)); - if ($suggested_email eq "") { - ERROR("BAD_SIGN_OFF", - "Unrecognized email address: '$email'\n" . $herecurr); - } else { - my $dequoted = $suggested_email; - $dequoted =~ s/^"//; - $dequoted =~ s/" $comment" ne $email && - "$suggested_email$comment" ne $email) { - WARN("BAD_SIGN_OFF", - "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); - } - } - } - -# Check for wrappage within a valid hunk of the file - if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { - ERROR("CORRUPTED_PATCH", - "patch seems to be corrupt (line wrapped?)\n" . - $herecurr) if (!$emitted_corrupt++); - } - -# Check for absolute kernel paths. - if ($tree) { - while ($line =~ m{(?:^|\s)(/\S*)}g) { - my $file = $1; - - if ($file =~ m{^(.*?)(?::\d+)+:?$} && - check_absolute_file($1, $herecurr)) { - # - } else { - check_absolute_file($file, $herecurr); - } - } - } - -# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php - if (($realfile =~ /^$/ || $line =~ /^\+/) && - $rawline !~ m/^$UTF8*$/) { - my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); - - my $blank = copy_spacing($rawline); - my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; - my $hereptr = "$hereline$ptr\n"; - - CHK("INVALID_UTF8", - "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); - } - -# Check if it's the start of a commit log -# (not a header line and we haven't seen the patch filename) - if ($in_header_lines && $realfile =~ /^$/ && - $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { - $in_header_lines = 0; - $in_commit_log = 1; - } - -# Check if there is UTF-8 in a commit log when a mail header has explicitly -# declined it, i.e defined some charset where it is missing. - if ($in_header_lines && - $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && - $1 !~ /utf-8/i) { - $non_utf8_charset = 1; - } - - if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && - $rawline =~ /$NON_ASCII_UTF8/) { - WARN("UTF8_BEFORE_PATCH", - "8-bit UTF-8 used in possible commit log\n" . $herecurr); - } - -# ignore non-hunk lines and lines being removed - next if (!$hunk_line || $line =~ /^-/); - -#trailing whitespace - if ($line =~ /^\+.*\015/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("DOS_LINE_ENDINGS", - "DOS line endings\n" . $herevet); - - } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("TRAILING_WHITESPACE", - "trailing whitespace\n" . $herevet); - $rpt_cleaners = 1; - } - -# check for Kconfig help text having a real description -# Only applies when adding the entry originally, after that we do not have -# sufficient context to determine whether it is indeed long enough. - if ($realfile =~ /Kconfig/ && - $line =~ /.\s*config\s+/) { - my $length = 0; - my $cnt = $realcnt; - my $ln = $linenr + 1; - my $f; - my $is_start = 0; - my $is_end = 0; - for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { - $f = $lines[$ln - 1]; - $cnt-- if ($lines[$ln - 1] !~ /^-/); - $is_end = $lines[$ln - 1] =~ /^\+/; - - next if ($f =~ /^-/); - - if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { - $is_start = 1; - } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { - $length = -1; - } - - $f =~ s/^.//; - $f =~ s/#.*//; - $f =~ s/^\s+//; - next if ($f =~ /^$/); - if ($f =~ /^\s*config\s/) { - $is_end = 1; - last; - } - $length++; - } - WARN("CONFIG_DESCRIPTION", - "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); - #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; - } - -# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. - if ($realfile =~ /Kconfig/ && - $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { - WARN("CONFIG_EXPERIMENTAL", - "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); - } - - if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && - ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { - my $flag = $1; - my $replacement = { - 'EXTRA_AFLAGS' => 'asflags-y', - 'EXTRA_CFLAGS' => 'ccflags-y', - 'EXTRA_CPPFLAGS' => 'cppflags-y', - 'EXTRA_LDFLAGS' => 'ldflags-y', - }; - - WARN("DEPRECATED_VARIABLE", - "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); - } - -# check we are in a valid source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); - -#line length limit - if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && - $rawline !~ /^.\s*\*\s*\@$Ident\s/ && - !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || - $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && - $length > $max_line_length) - { - WARN("LONG_LINE", - "line over $max_line_length characters\n" . $herecurr); - } - -# Check for user-visible strings broken across lines, which breaks the ability -# to grep for the string. Limited to strings used as parameters (those -# following an open parenthesis), which almost completely eliminates false -# positives, as well as warning only once per parameter rather than once per -# line of the string. Make an exception when the previous string ends in a -# newline (multiple lines in one string constant) or \n\t (common in inline -# assembly to indent the instruction on the following line). - if ($line =~ /^\+\s*"/ && - $prevline =~ /"\s*$/ && - $prevline =~ /\(/ && - $prevrawline !~ /\\n(?:\\t)*"\s*$/) { - WARN("SPLIT_STRING", - "quoted string split across lines\n" . $hereprev); - } - -# check for spaces before a quoted newline - if ($rawline =~ /^.*\".*\s\\n/) { - WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", - "unnecessary whitespace before a quoted newline\n" . $herecurr); - } - -# check for adding lines without a newline. - if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { - WARN("MISSING_EOF_NEWLINE", - "adding a line without newline at end of file\n" . $herecurr); - } - -# Blackfin: use hi/lo macros - if ($realfile =~ m@arch/blackfin/.*\.S$@) { - if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("LO_MACRO", - "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); - } - if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("HI_MACRO", - "use the HI() macro, not (... >> 16)\n" . $herevet); - } - } - -# check we are in a valid source file C or perl if not then ignore this hunk - next if ($realfile !~ /\.(h|c|pl)$/); - -# at the beginning of a line any tabs must come first and anything -# more than 8 must use tabs. - if ($rawline =~ /^\+\s* \t\s*\S/ || - $rawline =~ /^\+\s* \s*/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - ERROR("CODE_INDENT", - "code indent should use tabs where possible\n" . $herevet); - $rpt_cleaners = 1; - } - -# check for space before tabs. - if ($rawline =~ /^\+/ && $rawline =~ / \t/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("SPACE_BEFORE_TAB", - "please, no space before tabs\n" . $herevet); - } - -# check for && or || at the start of a line - if ($rawline =~ /^\+\s*(&&|\|\|)/) { - CHK("LOGICAL_CONTINUATIONS", - "Logical continuations should be on the previous line\n" . $hereprev); - } - -# check multi-line statement indentation matches previous line - if ($^V && $^V ge 5.10.0 && - $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { - $prevline =~ /^\+(\t*)(.*)$/; - my $oldindent = $1; - my $rest = $2; - - my $pos = pos_last_openparen($rest); - if ($pos >= 0) { - $line =~ /^(\+| )([ \t]*)/; - my $newindent = $2; - - my $goodtabindent = $oldindent . - "\t" x ($pos / 8) . - " " x ($pos % 8); - my $goodspaceindent = $oldindent . " " x $pos; - - if ($newindent ne $goodtabindent && - $newindent ne $goodspaceindent) { - CHK("PARENTHESIS_ALIGNMENT", - "Alignment should match open parenthesis\n" . $hereprev); - } - } - } - - if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { - CHK("SPACING", - "No space is necessary after a cast\n" . $hereprev); - } - - if ($realfile =~ m@^(drivers/net/|net/)@ && - $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && - $prevrawline =~ /^\+[ \t]*$/) { - WARN("NETWORKING_BLOCK_COMMENT_STYLE", - "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); - } - - if ($realfile =~ m@^(drivers/net/|net/)@ && - $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ - $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ - $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ - $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ - WARN("NETWORKING_BLOCK_COMMENT_STYLE", - "networking block comments put the trailing */ on a separate line\n" . $herecurr); - } - -# check for spaces at the beginning of a line. -# Exceptions: -# 1) within comments -# 2) indented preprocessor commands -# 3) hanging labels - if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { - my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - WARN("LEADING_SPACE", - "please, no spaces at the start of a line\n" . $herevet); - } - -# check we are in a valid C source file if not then ignore this hunk - next if ($realfile !~ /\.(h|c)$/); - -# discourage the addition of CONFIG_EXPERIMENTAL in #if(def). - if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { - WARN("CONFIG_EXPERIMENTAL", - "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); - } - -# check for RCS/CVS revision markers - if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { - WARN("CVS_KEYWORD", - "CVS style keyword markers, these will _not_ be updated\n". $herecurr); - } - -# Blackfin: don't use __builtin_bfin_[cs]sync - if ($line =~ /__builtin_bfin_csync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("CSYNC", - "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); - } - if ($line =~ /__builtin_bfin_ssync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("SSYNC", - "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); - } - -# check for old HOTPLUG __dev section markings - if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { - WARN("HOTPLUG_SECTION", - "Using $1 is unnecessary\n" . $herecurr); - } - -# Check for potential 'bare' types - my ($stat, $cond, $line_nr_next, $remain_next, $off_next, - $realline_next); -#print "LINE<$line>\n"; - if ($linenr >= $suppress_statement && - $realcnt && $line =~ /.\s*\S/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0); - $stat =~ s/\n./\n /g; - $cond =~ s/\n./\n /g; - -#print "linenr<$linenr> <$stat>\n"; - # If this statement has no statement boundaries within - # it there is no point in retrying a statement scan - # until we hit end of it. - my $frag = $stat; $frag =~ s/;+\s*$//; - if ($frag !~ /(?:{|;)/) { -#print "skip<$line_nr_next>\n"; - $suppress_statement = $line_nr_next; - } - - # Find the real next line. - $realline_next = $line_nr_next; - if (defined $realline_next && - (!defined $lines[$realline_next - 1] || - substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { - $realline_next++; - } - - my $s = $stat; - $s =~ s/{.*$//s; - - # Ignore goto labels. - if ($s =~ /$Ident:\*$/s) { - - # Ignore functions being called - } elsif ($s =~ /^.\s*$Ident\s*\(/s) { - - } elsif ($s =~ /^.\s*else\b/s) { - - # declarations always start with types - } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { - my $type = $1; - $type =~ s/\s+/ /g; - possible($type, "A:" . $s); - - # definitions in global scope can only start with types - } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { - possible($1, "B:" . $s); - } - - # any (foo ... *) is a pointer cast, and foo is a type - while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { - possible($1, "C:" . $s); - } - - # Check for any sort of function declaration. - # int foo(something bar, other baz); - # void (*store_gdt)(x86_descr_ptr *); - if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { - my ($name_len) = length($1); - - my $ctx = $s; - substr($ctx, 0, $name_len + 1, ''); - $ctx =~ s/\)[^\)]*$//; - - for my $arg (split(/\s*,\s*/, $ctx)) { - if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { - - possible($1, "D:" . $s); - } - } - } - - } - -# -# Checks which may be anchored in the context. -# - -# Check for switch () and associated case and default -# statements should be at the same indent. - if ($line=~/\bswitch\s*\(.*\)/) { - my $err = ''; - my $sep = ''; - my @ctx = ctx_block_outer($linenr, $realcnt); - shift(@ctx); - for my $ctx (@ctx) { - my ($clen, $cindent) = line_stats($ctx); - if ($ctx =~ /^\+\s*(case\s+|default:)/ && - $indent != $cindent) { - $err .= "$sep$ctx\n"; - $sep = ''; - } else { - $sep = "[...]\n"; - } - } - if ($err ne '') { - ERROR("SWITCH_CASE_INDENT_LEVEL", - "switch and case should be at the same indent\n$hereline$err"); - } - } - -# if/while/etc brace do not go on next line, unless defining a do while loop, -# or if that brace on the next line is for something else - if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { - my $pre_ctx = "$1$2"; - - my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); - - if ($line =~ /^\+\t{6,}/) { - WARN("DEEP_INDENTATION", - "Too many leading tabs - consider code refactoring\n" . $herecurr); - } - - my $ctx_cnt = $realcnt - $#ctx - 1; - my $ctx = join("\n", @ctx); - - my $ctx_ln = $linenr; - my $ctx_skip = $realcnt; - - while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && - defined $lines[$ctx_ln - 1] && - $lines[$ctx_ln - 1] =~ /^-/)) { - ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; - $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); - $ctx_ln++; - } - - #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; - #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; - - if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { - ERROR("OPEN_BRACE", - "that open brace { should be on the previous line\n" . - "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); - } - if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && - $ctx =~ /\)\s*\;\s*$/ && - defined $lines[$ctx_ln - 1]) - { - my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); - if ($nindent > $indent) { - WARN("TRAILING_SEMICOLON", - "trailing semicolon indicates no statements, indent implies otherwise\n" . - "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); - } - } - } - -# Check relative indent for conditionals and blocks. - if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0) - if (!defined $stat); - my ($s, $c) = ($stat, $cond); - - substr($s, 0, length($c), ''); - - # Make sure we remove the line prefixes as we have - # none on the first line, and are going to readd them - # where necessary. - $s =~ s/\n./\n/gs; - - # Find out how long the conditional actually is. - my @newlines = ($c =~ /\n/gs); - my $cond_lines = 1 + $#newlines; - - # We want to check the first line inside the block - # starting at the end of the conditional, so remove: - # 1) any blank line termination - # 2) any opening brace { on end of the line - # 3) any do (...) { - my $continuation = 0; - my $check = 0; - $s =~ s/^.*\bdo\b//; - $s =~ s/^\s*{//; - if ($s =~ s/^\s*\\//) { - $continuation = 1; - } - if ($s =~ s/^\s*?\n//) { - $check = 1; - $cond_lines++; - } - - # Also ignore a loop construct at the end of a - # preprocessor statement. - if (($prevline =~ /^.\s*#\s*define\s/ || - $prevline =~ /\\\s*$/) && $continuation == 0) { - $check = 0; - } - - my $cond_ptr = -1; - $continuation = 0; - while ($cond_ptr != $cond_lines) { - $cond_ptr = $cond_lines; - - # If we see an #else/#elif then the code - # is not linear. - if ($s =~ /^\s*\#\s*(?:else|elif)/) { - $check = 0; - } - - # Ignore: - # 1) blank lines, they should be at 0, - # 2) preprocessor lines, and - # 3) labels. - if ($continuation || - $s =~ /^\s*?\n/ || - $s =~ /^\s*#\s*?/ || - $s =~ /^\s*$Ident\s*:/) { - $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; - if ($s =~ s/^.*?\n//) { - $cond_lines++; - } - } - } - - my (undef, $sindent) = line_stats("+" . $s); - my $stat_real = raw_line($linenr, $cond_lines); - - # Check if either of these lines are modified, else - # this is not this patch's fault. - if (!defined($stat_real) || - $stat !~ /^\+/ && $stat_real !~ /^\+/) { - $check = 0; - } - if (defined($stat_real) && $cond_lines > 1) { - $stat_real = "[...]\n$stat_real"; - } - - #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; - - if ($check && (($sindent % 8) != 0 || - ($sindent <= $indent && $s ne ''))) { - WARN("SUSPECT_CODE_INDENT", - "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); - } - } - - # Track the 'values' across context and added lines. - my $opline = $line; $opline =~ s/^./ /; - my ($curr_values, $curr_vars) = - annotate_values($opline . "\n", $prev_values); - $curr_values = $prev_values . $curr_values; - if ($dbg_values) { - my $outline = $opline; $outline =~ s/\t/ /g; - print "$linenr > .$outline\n"; - print "$linenr > $curr_values\n"; - print "$linenr > $curr_vars\n"; - } - $prev_values = substr($curr_values, -1); - -#ignore lines not being added - if ($line=~/^[^\+]/) {next;} - -# TEST: allow direct testing of the type matcher. - if ($dbg_type) { - if ($line =~ /^.\s*$Declare\s*$/) { - ERROR("TEST_TYPE", - "TEST: is type\n" . $herecurr); - } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { - ERROR("TEST_NOT_TYPE", - "TEST: is not type ($1 is)\n". $herecurr); - } - next; - } -# TEST: allow direct testing of the attribute matcher. - if ($dbg_attr) { - if ($line =~ /^.\s*$Modifier\s*$/) { - ERROR("TEST_ATTR", - "TEST: is attr\n" . $herecurr); - } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { - ERROR("TEST_NOT_ATTR", - "TEST: is not attr ($1 is)\n". $herecurr); - } - next; - } - -# check for initialisation to aggregates open brace on the next line - if ($line =~ /^.\s*{/ && - $prevline =~ /(?:^|[^=])=\s*$/) { - ERROR("OPEN_BRACE", - "that open brace { should be on the previous line\n" . $hereprev); - } - -# -# Checks which are anchored on the added line. -# - -# check for malformed paths in #include statements (uses RAW line) - if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { - my $path = $1; - if ($path =~ m{//}) { - ERROR("MALFORMED_INCLUDE", - "malformed #include filename\n" . $herecurr); - } - if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { - ERROR("UAPI_INCLUDE", - "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); - } - } - -# no C99 // comments - if ($line =~ m{//}) { - ERROR("C99_COMMENTS", - "do not use C99 // comments\n" . $herecurr); - } - # Remove C99 comments. - $line =~ s@//.*@@; - $opline =~ s@//.*@@; - -# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider -# the whole statement. -#print "APW <$lines[$realline_next - 1]>\n"; - if (defined $realline_next && - exists $lines[$realline_next - 1] && - !defined $suppress_export{$realline_next} && - ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { - # Handle definitions which produce identifiers with - # a prefix: - # XXX(foo); - # EXPORT_SYMBOL(something_foo); - my $name = $1; - if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && - $name =~ /^${Ident}_$2/) { -#print "FOO C name<$name>\n"; - $suppress_export{$realline_next} = 1; - - } elsif ($stat !~ /(?: - \n.}\s*$| - ^.DEFINE_$Ident\(\Q$name\E\)| - ^.DECLARE_$Ident\(\Q$name\E\)| - ^.LIST_HEAD\(\Q$name\E\)| - ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| - \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() - )/x) { -#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; - $suppress_export{$realline_next} = 2; - } else { - $suppress_export{$realline_next} = 1; - } - } - if (!defined $suppress_export{$linenr} && - $prevline =~ /^.\s*$/ && - ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || - $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { -#print "FOO B <$lines[$linenr - 1]>\n"; - $suppress_export{$linenr} = 2; - } - if (defined $suppress_export{$linenr} && - $suppress_export{$linenr} == 2) { - WARN("EXPORT_SYMBOL", - "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); - } - -# check for global initialisers. - if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { - ERROR("GLOBAL_INITIALISERS", - "do not initialise globals to 0 or NULL\n" . - $herecurr); - } -# check for static initialisers. - if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { - ERROR("INITIALISED_STATIC", - "do not initialise statics to 0 or NULL\n" . - $herecurr); - } - -# check for static const char * arrays. - if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { - WARN("STATIC_CONST_CHAR_ARRAY", - "static const char * array should probably be static const char * const\n" . - $herecurr); - } - -# check for static char foo[] = "bar" declarations. - if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { - WARN("STATIC_CONST_CHAR_ARRAY", - "static char array declaration should probably be static const char\n" . - $herecurr); - } - -# check for declarations of struct pci_device_id - if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { - WARN("DEFINE_PCI_DEVICE_TABLE", - "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); - } - -# check for new typedefs, only function parameters and sparse annotations -# make sense. - if ($line =~ /\btypedef\s/ && - $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && - $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && - $line !~ /\b$typeTypedefs\b/ && - $line !~ /\b__bitwise(?:__|)\b/) { - WARN("NEW_TYPEDEFS", - "do not add new typedefs\n" . $herecurr); - } - -# * goes on variable not on type - # (char*[ const]) - while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { - #print "AA<$1>\n"; - my ($from, $to) = ($2, $2); - - # Should start with a space. - $to =~ s/^(\S)/ $1/; - # Should not end with a space. - $to =~ s/\s+$//; - # '*'s should not have spaces between. - while ($to =~ s/\*\s+\*/\*\*/) { - } - - #print "from<$from> to<$to>\n"; - if ($from ne $to) { - ERROR("POINTER_LOCATION", - "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); - } - } - while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { - #print "BB<$1>\n"; - my ($from, $to, $ident) = ($2, $2, $3); - - # Should start with a space. - $to =~ s/^(\S)/ $1/; - # Should not end with a space. - $to =~ s/\s+$//; - # '*'s should not have spaces between. - while ($to =~ s/\*\s+\*/\*\*/) { - } - # Modifiers should have spaces. - $to =~ s/(\b$Modifier$)/$1 /; - - #print "from<$from> to<$to> ident<$ident>\n"; - if ($from ne $to && $ident !~ /^$Modifier$/) { - ERROR("POINTER_LOCATION", - "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); - } - } - -# # no BUG() or BUG_ON() -# if ($line =~ /\b(BUG|BUG_ON)\b/) { -# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; -# print "$herecurr"; -# $clean = 0; -# } - - if ($line =~ /\bLINUX_VERSION_CODE\b/) { - WARN("LINUX_VERSION_CODE", - "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); - } - -# check for uses of printk_ratelimit - if ($line =~ /\bprintk_ratelimit\s*\(/) { - WARN("PRINTK_RATELIMITED", -"Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); - } - -# printk should use KERN_* levels. Note that follow on printk's on the -# same line do not need a level, so we use the current block context -# to try and find and validate the current printk. In summary the current -# printk includes all preceding printk's which have no newline on the end. -# we assume the first bad printk is the one to report. - if ($line =~ /\bprintk\((?!KERN_)\s*"/) { - my $ok = 0; - for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { - #print "CHECK<$lines[$ln - 1]\n"; - # we have a preceding printk if it ends - # with "\n" ignore it, else it is to blame - if ($lines[$ln - 1] =~ m{\bprintk\(}) { - if ($rawlines[$ln - 1] !~ m{\\n"}) { - $ok = 1; - } - last; - } - } - if ($ok == 0) { - WARN("PRINTK_WITHOUT_KERN_LEVEL", - "printk() should include KERN_ facility level\n" . $herecurr); - } - } - - if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { - my $orig = $1; - my $level = lc($orig); - $level = "warn" if ($level eq "warning"); - my $level2 = $level; - $level2 = "dbg" if ($level eq "debug"); - WARN("PREFER_PR_LEVEL", - "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); - } - - if ($line =~ /\bpr_warning\s*\(/) { - WARN("PREFER_PR_LEVEL", - "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); - } - - if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { - my $orig = $1; - my $level = lc($orig); - $level = "warn" if ($level eq "warning"); - $level = "dbg" if ($level eq "debug"); - WARN("PREFER_DEV_LEVEL", - "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); - } - -# function brace can't be on same line, except for #defines of do while, -# or if closed on same line - if (($line=~/$Type\s*$Ident\(.*\).*\s\{/) and - !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) { - ERROR("OPEN_BRACE", - "open brace '{' following function declarations go on the next line\n" . $herecurr); - } - -# open braces for enum, union and struct go on the same line. - if ($line =~ /^.\s*{/ && - $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { - ERROR("OPEN_BRACE", - "open brace '{' following $1 go on the same line\n" . $hereprev); - } - -# missing space after union, struct or enum definition - if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { - WARN("SPACING", - "missing space after $1 definition\n" . $herecurr); - } - -# check for spacing round square brackets; allowed: -# 1. with a type on the left -- int [] a; -# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, -# 3. inside a curly brace -- = { [0...10] = 5 } - while ($line =~ /(.*?\s)\[/g) { - my ($where, $prefix) = ($-[1], $1); - if ($prefix !~ /$Type\s+$/ && - ($where != 0 || $prefix !~ /^.\s+$/) && - $prefix !~ /[{,]\s+$/) { - ERROR("BRACKET_SPACE", - "space prohibited before open square bracket '['\n" . $herecurr); - } - } - -# check for spaces between functions and their parentheses. - while ($line =~ /($Ident)\s+\(/g) { - my $name = $1; - my $ctx_before = substr($line, 0, $-[1]); - my $ctx = "$ctx_before$name"; - - # Ignore those directives where spaces _are_ permitted. - if ($name =~ /^(?: - if|for|while|switch|return|case| - volatile|__volatile__| - __attribute__|format|__extension__| - asm|__asm__)$/x) - { - - # cpp #define statements have non-optional spaces, ie - # if there is a space between the name and the open - # parenthesis it is simply not a parameter group. - } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { - - # cpp #elif statement condition may start with a ( - } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { - - # If this whole things ends with a type its most - # likely a typedef for a function. - } elsif ($ctx =~ /$Type$/) { - - } else { - WARN("SPACING", - "space prohibited between function name and open parenthesis '('\n" . $herecurr); - } - } - -# check for whitespace before a non-naked semicolon - if ($line =~ /^\+.*\S\s+;/) { - WARN("SPACING", - "space prohibited before semicolon\n" . $herecurr); - } - -# Check operator spacing. - if (!($line=~/\#\s*include/)) { - my $ops = qr{ - <<=|>>=|<=|>=|==|!=| - \+=|-=|\*=|\/=|%=|\^=|\|=|&=| - =>|->|<<|>>|<|>|=|!|~| - &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| - \?|: - }x; - my @elements = split(/($ops|;)/, $opline); - my $off = 0; - - my $blank = copy_spacing($opline); - - for (my $n = 0; $n < $#elements; $n += 2) { - $off += length($elements[$n]); - - # Pick up the preceding and succeeding characters. - my $ca = substr($opline, 0, $off); - my $cc = ''; - if (length($opline) >= ($off + length($elements[$n + 1]))) { - $cc = substr($opline, $off + length($elements[$n + 1])); - } - my $cb = "$ca$;$cc"; - - my $a = ''; - $a = 'V' if ($elements[$n] ne ''); - $a = 'W' if ($elements[$n] =~ /\s$/); - $a = 'C' if ($elements[$n] =~ /$;$/); - $a = 'B' if ($elements[$n] =~ /(\[|\()$/); - $a = 'O' if ($elements[$n] eq ''); - $a = 'E' if ($ca =~ /^\s*$/); - - my $op = $elements[$n + 1]; - - my $c = ''; - if (defined $elements[$n + 2]) { - $c = 'V' if ($elements[$n + 2] ne ''); - $c = 'W' if ($elements[$n + 2] =~ /^\s/); - $c = 'C' if ($elements[$n + 2] =~ /^$;/); - $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); - $c = 'O' if ($elements[$n + 2] eq ''); - $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); - } else { - $c = 'E'; - } - - my $ctx = "${a}x${c}"; - - my $at = "(ctx:$ctx)"; - - my $ptr = substr($blank, 0, $off) . "^"; - my $hereptr = "$hereline$ptr\n"; - - # Pull out the value of this operator. - my $op_type = substr($curr_values, $off + 1, 1); - - # Get the full operator variant. - my $opv = $op . substr($curr_vars, $off, 1); - - # Ignore operators passed as parameters. - if ($op_type ne 'V' && - $ca =~ /\s$/ && $cc =~ /^\s*,/) { - -# # Ignore comments -# } elsif ($op =~ /^$;+$/) { - - # ; should have either the end of line or a space or \ after it - } elsif ($op eq ';') { - if ($ctx !~ /.x[WEBC]/ && - $cc !~ /^\\/ && $cc !~ /^;/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); - } - - # // is a comment - } elsif ($op eq '//') { - - # No spaces for: - # -> - # : when part of a bitfield - } elsif ($op eq '->' || $opv eq ':B') { - if ($ctx =~ /Wx.|.xW/) { - ERROR("SPACING", - "spaces prohibited around that '$op' $at\n" . $hereptr); - } - - # , must have a space on the right. - } elsif ($op eq ',') { - if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { - ERROR("SPACING", - "space required after that '$op' $at\n" . $hereptr); - } - - # '*' as part of a type definition -- reported already. - } elsif ($opv eq '*_') { - #warn "'*' is part of type\n"; - - # unary operators should have a space before and - # none after. May be left adjacent to another - # unary operator, or a cast - } elsif ($op eq '!' || $op eq '~' || - $opv eq '*U' || $opv eq '-U' || - $opv eq '&U' || $opv eq '&&U') { - if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { - ERROR("SPACING", - "space required before that '$op' $at\n" . $hereptr); - } - if ($op eq '*' && $cc =~/\s*$Modifier\b/) { - # A unary '*' may be const - - } elsif ($ctx =~ /.xW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); - } - - # unary ++ and unary -- are allowed no space on one side. - } elsif ($op eq '++' or $op eq '--') { - if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { - ERROR("SPACING", - "space required one side of that '$op' $at\n" . $hereptr); - } - if ($ctx =~ /Wx[BE]/ || - ($ctx =~ /Wx./ && $cc =~ /^;/)) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); - } - if ($ctx =~ /ExW/) { - ERROR("SPACING", - "space prohibited after that '$op' $at\n" . $hereptr); - } - - - # << and >> may either have or not have spaces both sides - } elsif ($op eq '<<' or $op eq '>>' or - $op eq '&' or $op eq '^' or $op eq '|' or - $op eq '+' or $op eq '-' or - $op eq '*' or $op eq '/' or - $op eq '%') - { - if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { - ERROR("SPACING", - "need consistent spacing around '$op' $at\n" . - $hereptr); - } - - # A colon needs no spaces before when it is - # terminating a case value or a label. - } elsif ($opv eq ':C' || $opv eq ':L') { - if ($ctx =~ /Wx./) { - ERROR("SPACING", - "space prohibited before that '$op' $at\n" . $hereptr); - } - - # All the others need spaces both sides. - } elsif ($ctx !~ /[EWC]x[CWE]/) { - my $ok = 0; - - # Ignore email addresses - if (($op eq '<' && - $cc =~ /^\S+\@\S+>/) || - ($op eq '>' && - $ca =~ /<\S+\@\S+$/)) - { - $ok = 1; - } - - # Ignore ?: - if (($opv eq ':O' && $ca =~ /\?$/) || - ($op eq '?' && $cc =~ /^:/)) { - $ok = 1; - } - - if ($ok == 0) { - ERROR("SPACING", - "spaces required around that '$op' $at\n" . $hereptr); - } - } - $off += length($elements[$n + 1]); - } - } - -# check for multiple assignments - if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { - CHK("MULTIPLE_ASSIGNMENTS", - "multiple assignments should be avoided\n" . $herecurr); - } - -## # check for multiple declarations, allowing for a function declaration -## # continuation. -## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && -## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { -## -## # Remove any bracketed sections to ensure we do not -## # falsly report the parameters of functions. -## my $ln = $line; -## while ($ln =~ s/\([^\(\)]*\)//g) { -## } -## if ($ln =~ /,/) { -## WARN("MULTIPLE_DECLARATION", -## "declaring multiple variables together should be avoided\n" . $herecurr); -## } -## } - -#need space before brace following if, while, etc - if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\)\{/) || - $line =~ /do\{/) { - ERROR("SPACING", - "space required before the open brace '{'\n" . $herecurr); - } - -# closing brace should have a space following it when it has anything -# on the line - if ($line =~ /\}(?!(?:,|;|\)))\S/) { - ERROR("SPACING", - "space required after that close brace '}'\n" . $herecurr); - } - -# check spacing on square brackets - if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { - ERROR("SPACING", - "space prohibited after that open square bracket '['\n" . $herecurr); - } - if ($line =~ /\s\]/) { - ERROR("SPACING", - "space prohibited before that close square bracket ']'\n" . $herecurr); - } - -# check spacing on parentheses - if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && - $line !~ /for\s*\(\s+;/) { - ERROR("SPACING", - "space prohibited after that open parenthesis '('\n" . $herecurr); - } - if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && - $line !~ /for\s*\(.*;\s+\)/ && - $line !~ /:\s+\)/) { - ERROR("SPACING", - "space prohibited before that close parenthesis ')'\n" . $herecurr); - } - -#goto labels aren't indented, allow a single space however - if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and - !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { - WARN("INDENTED_LABEL", - "labels should not be indented\n" . $herecurr); - } - -# Return is not a function. - if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { - my $spacing = $1; - my $value = $2; - - # Flatten any parentheses - $value =~ s/\(/ \(/g; - $value =~ s/\)/\) /g; - while ($value =~ s/\[[^\[\]]*\]/1/ || - $value !~ /(?:$Ident|-?$Constant)\s* - $Compare\s* - (?:$Ident|-?$Constant)/x && - $value =~ s/\([^\(\)]*\)/1/) { - } -#print "value<$value>\n"; - if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { - ERROR("RETURN_PARENTHESES", - "return is not a function, parentheses are not required\n" . $herecurr); - - } elsif ($spacing !~ /\s+/) { - ERROR("SPACING", - "space required before the open parenthesis '('\n" . $herecurr); - } - } -# Return of what appears to be an errno should normally be -'ve - if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { - my $name = $1; - if ($name ne 'EOF' && $name ne 'ERROR') { - WARN("USE_NEGATIVE_ERRNO", - "return of an errno should typically be -ve (return -$1)\n" . $herecurr); - } - } - -# Need a space before open parenthesis after if, while etc - if ($line=~/\b(if|while|for|switch)\(/) { - ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); - } - -# Check for illegal assignment in if conditional -- and check for trailing -# statements after the conditional. - if ($line =~ /do\s*(?!{)/) { - ($stat, $cond, $line_nr_next, $remain_next, $off_next) = - ctx_statement_block($linenr, $realcnt, 0) - if (!defined $stat); - my ($stat_next) = ctx_statement_block($line_nr_next, - $remain_next, $off_next); - $stat_next =~ s/\n./\n /g; - ##print "stat<$stat> stat_next<$stat_next>\n"; - - if ($stat_next =~ /^\s*while\b/) { - # If the statement carries leading newlines, - # then count those as offsets. - my ($whitespace) = - ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); - my $offset = - statement_rawlines($whitespace) - 1; - - $suppress_whiletrailers{$line_nr_next + - $offset} = 1; - } - } - if (!defined $suppress_whiletrailers{$linenr} && - $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { - my ($s, $c) = ($stat, $cond); - - if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { - ERROR("ASSIGN_IN_IF", - "do not use assignment in if condition\n" . $herecurr); - } - - # Find out what is on the end of the line after the - # conditional. - substr($s, 0, length($c), ''); - $s =~ s/\n.*//g; - $s =~ s/$;//g; # Remove any comments - if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && - $c !~ /}\s*while\s*/ && !($c =~ /while/ && $s eq ";")) - { - # Find out how long the conditional actually is. - my @newlines = ($c =~ /\n/gs); - my $cond_lines = 1 + $#newlines; - my $stat_real = ''; - - $stat_real = raw_line($linenr, $cond_lines) - . "\n" if ($cond_lines); - if (defined($stat_real) && $cond_lines > 1) { - $stat_real = "[...]\n$stat_real"; - } - - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr . $stat_real); - } - } - -# Check for bitwise tests written as boolean - if ($line =~ / - (?: - (?:\[|\(|\&\&|\|\|) - \s*0[xX][0-9]+\s* - (?:\&\&|\|\|) - | - (?:\&\&|\|\|) - \s*0[xX][0-9]+\s* - (?:\&\&|\|\||\)|\]) - )/x) - { - WARN("HEXADECIMAL_BOOLEAN_TEST", - "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); - } - -# if and else should not have general statements after it - if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { - my $s = $1; - $s =~ s/$;//g; # Remove any comments - if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr); - } - } -# if should not continue a brace - if ($line =~ /}\s*if\b/) { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . - $herecurr); - } -# case and default should not have general statements after them - if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && - $line !~ /\G(?: - (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| - \s*return\s+ - )/xg) - { - ERROR("TRAILING_STATEMENTS", - "trailing statements should be on next line\n" . $herecurr); - } - - # Check for }else {, these must be at the same - # indent level to be relevant to each other. - if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and - $previndent == $indent) { - ERROR("ELSE_AFTER_BRACE", - "else should follow close brace '}'\n" . $hereprev); - } - - #if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and - # $previndent == $indent) { - # my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); - - # # Find out what is on the end of the line after the - # # conditional. - # substr($s, 0, length($c), ''); - # $s =~ s/\n.*//g; - - # if ($s =~ /^\s*;/) { - # ERROR("WHILE_AFTER_BRACE", - # "while should follow close brace '}'\n" . $hereprev); - # } - #} - -#CamelCase - while ($line =~ m{($Constant|$Lval)}g) { - my $var = $1; - if ($var !~ /$Constant/ && - $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && - $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && - !defined $camelcase{$var} && - $var !~ /[A-Z][A-Z0-9_]*x[A-Z0-9_]*\b/) { - $camelcase{$var} = 1; - #print "Camelcase line <<$line>> <<$var>>\n"; - WARN("CAMELCASE", - "Avoid CamelCase: <$var>\n" . $herecurr); - } - } - -#no spaces allowed after \ in define - if ($line=~/\#\s*define.*\\\s$/) { - WARN("WHITESPACE_AFTER_LINE_CONTINUATION", - "Whitepspace after \\ makes next lines useless\n" . $herecurr); - } - -#warn if is #included and is available (uses RAW line) - if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { - my $file = "$1.h"; - my $checkfile = "include/linux/$file"; - if (-f "$root/$checkfile" && - $realfile ne $checkfile && - $1 !~ /$allowed_asm_includes/) - { - if ($realfile =~ m{^arch/}) { - CHK("ARCH_INCLUDE_LINUX", - "Consider using #include instead of \n" . $herecurr); - } else { - WARN("INCLUDE_LINUX", - "Use #include instead of \n" . $herecurr); - } - } - } - -# multi-statement macros should be enclosed in a do while loop, grab the -# first statement and ensure its the whole macro if its not enclosed -# in a known good container - if ($realfile !~ m@/vmlinux.lds.h$@ && - $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { - my $ln = $linenr; - my $cnt = $realcnt; - my ($off, $dstat, $dcond, $rest); - my $ctx = ''; - ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $realcnt, 0); - $ctx = $dstat; - #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; - #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; - - $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; - $dstat =~ s/$;//g; - $dstat =~ s/\\\n.//g; - $dstat =~ s/^\s*//s; - $dstat =~ s/\s*$//s; - - # Flatten any parentheses and braces - while ($dstat =~ s/\([^\(\)]*\)/1/ || - $dstat =~ s/\{[^\{\}]*\}/1/ || - $dstat =~ s/\[[^\[\]]*\]/1/) - { - } - - # Flatten any obvious string concatentation. - while ($dstat =~ s/("X*")\s*$Ident/$1/ || - $dstat =~ s/$Ident\s*("X*")/$1/) - { - } - - my $exceptions = qr{ - $Declare| - module_param_named| - MODULE_PARM_DESC| - DECLARE_PER_CPU| - DEFINE_PER_CPU| - __typeof__\(| - union| - struct| - \.$Ident\s*=\s*| - ^\"|\"$ - }x; - #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; - if ($dstat ne '' && - $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), - $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); - $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo - $dstat !~ /^'X'$/ && # character constants - $dstat !~ /$exceptions/ && - $dstat !~ /^\.$Ident\s*=/ && # .foo = - $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo - $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) - $dstat !~ /^for\s*$Constant$/ && # for (...) - $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() - $dstat !~ /^do\s*\{/ && # do {... - $dstat !~ /^\(\{/) # ({... - { - $ctx =~ s/\n*$//; - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($ctx); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - if ($dstat =~ /;/) { - ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", - "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); - } else { - ERROR("COMPLEX_MACRO", - "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); - } - } - -# check for line continuations outside of #defines, preprocessor #, and asm - - } else { - if ($prevline !~ /^..*\\$/ && - $line !~ /^\+\s*\#.*\\$/ && # preprocessor - $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm - $line =~ /^\+.*\\$/) { - WARN("LINE_CONTINUATIONS", - "Avoid unnecessary line continuations\n" . $herecurr); - } - } - -# do {} while (0) macro tests: -# single-statement macros do not need to be enclosed in do while (0) loop, -# macro should not end with a semicolon - if ($^V && $^V ge 5.10.0 && - $realfile !~ m@/vmlinux.lds.h$@ && - $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { - my $ln = $linenr; - my $cnt = $realcnt; - my ($off, $dstat, $dcond, $rest); - my $ctx = ''; - ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $realcnt, 0); - $ctx = $dstat; - - $dstat =~ s/\\\n.//g; - - if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { - my $stmts = $2; - my $semis = $3; - - $ctx =~ s/\n*$//; - my $cnt = statement_rawlines($ctx); - my $herectx = $here . "\n"; - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - if (($stmts =~ tr/;/;/) == 1 && - $stmts !~ /^\s*(if|while|for|switch)\b/) { - WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", - "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); - } - if (defined $semis && $semis ne "") { - WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", - "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); - } - } - } - -# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... -# all assignments may have only one of the following with an assignment: -# . -# ALIGN(...) -# VMLINUX_SYMBOL(...) - if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { - WARN("MISSING_VMLINUX_SYMBOL", - "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); - } - -# check for redundant bracing round if etc - if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { - my ($level, $endln, @chunks) = - ctx_statement_full($linenr, $realcnt, 1); - #if ($#chunks > 0) { - # print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; - # my $count = 0; - # for my $chunk (@chunks) { - # my ($cond, $block) = @{$chunk}; - # print "APW: count<$count> <<$cond>><<$block>>\n"; - # $count++; - # } - #} - if ($#chunks > 0 && $level == 0) { - my @allowed = (); - my $allow = 0; - my $seen = 0; - my $herectx = $here . "\n"; - my $ln = $linenr - 1; - for my $chunk (@chunks) { - my ($cond, $block) = @{$chunk}; - - # If the condition carries leading newlines, then count those as offsets. - my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); - my $offset = statement_rawlines($whitespace) - 1; - - $allowed[$allow] = 0; - #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; - - # We have looked at and allowed this specific line. - $suppress_ifbraces{$ln + $offset} = 1; - - $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; - $ln += statement_rawlines($block) - 1; - - substr($block, 0, length($cond), ''); - - $seen++ if ($block =~ /^\s*{/); - - #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; - #if (statement_lines($cond) > 1) { - # #print "APW: ALLOWED: cond<$cond>\n"; - # $allowed[$allow] = 1; - #} - #if ($block =~/\b(?:if|for|while)\b/) { - # #print "APW: ALLOWED: block<$block>\n"; - # $allowed[$allow] = 1; - #} - #if (statement_block_size($block) > 1) { - # #print "APW: ALLOWED: lines block<$block>\n"; - # $allowed[$allow] = 1; - #} - #$allow++; - } - if (!$seen) { - ERROR("BRACES", - "braces {} are necessary for all arms of this statement\n" . $herectx); - } - #if ($seen) { - # my $sum_allowed = 0; - # foreach (@allowed) { - # $sum_allowed += $_; - # } - # if ($sum_allowed == 0) { - # WARN("BRACES", - # "braces {} are not necessary for any arm of this statement\n" . $herectx); - # } elsif ($sum_allowed != $allow && - # $seen != $allow) { - # CHK("BRACES", - # "braces {} should be used on all arms of this statement\n" . $herectx); - # } - #} - } - } - if (!defined $suppress_ifbraces{$linenr - 1} && - $line =~ /\b(if|while|for|else)\b/) { - my $allowed = 0; - - # Check the pre-context. - if (substr($line, 0, $-[0]) =~ /(#\s*)$/) { - #print "APW: ALLOWED: pre<$1>\n"; - $allowed = 1; - } - - my ($level, $endln, @chunks) = - ctx_statement_full($linenr, $realcnt, $-[0]); - - # Check the condition. - my ($cond, $block) = @{$chunks[0]}; - #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; - if (defined $cond) { - substr($block, 0, length($cond), ''); - } - if ($cond =~ /\bwhile/ && $block =~ /^;/) { - #print "APW: ALLOWED: block<$block>"; - $allowed = 1; - } - #if ($block =~/\b(?:if|for|while)\b/) { - # print "APW: ALLOWED: block<$block>\n"; - # $allowed = 1; - #} - - # Check the post-context. - if (defined $chunks[1]) { - my ($cond, $block) = @{$chunks[1]}; - if (defined $cond) { - substr($block, 0, length($cond), ''); - } - if ($block =~ /^\s*\{/) { - #print "APW: ALLOWED: chunk-1 block<$block>\n"; - #$allowed = 1; - } - } - if ($level == 0 && !($block =~ /^\s*\{/) && !$allowed) { - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($block); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - - WARN("BRACES", - "braces {} are needed for every statement block\n" . $herectx); - } - } - -# check for unnecessary blank lines around braces - if (($line =~ /^.\s*}\s*$/ && $prevline =~ /^.\s*$/)) { - CHK("BRACES", - "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); - } - if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { - CHK("BRACES", - "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); - } - -# no volatiles please - my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; - if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { - WARN("VOLATILE", - "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); - } - -# warn about #if 0 - if ($line =~ /^.\s*\#\s*if\s+0\b/) { - CHK("REDUNDANT_CODE", - "if this code is redundant consider removing it\n" . - $herecurr); - } - -# check for needless "if () fn()" uses - if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { - my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; - if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { - WARN('NEEDLESS_IF', - "$1(NULL) is safe this check is probably not required\n" . $hereprev); - } - } - -# prefer usleep_range over udelay - if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { - # ignore udelay's < 10, however - if (! ($1 < 10) ) { - CHK("USLEEP_RANGE", - "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); - } - } - -# warn about unexpectedly long msleep's - if ($line =~ /\bmsleep\s*\((\d+)\);/) { - if ($1 < 20) { - WARN("MSLEEP", - "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); - } - } - -# warn about #ifdefs in C files -# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { -# print "#ifdef in C files should be avoided\n"; -# print "$herecurr"; -# $clean = 0; -# } - -# warn about spacing in #ifdefs - if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { - ERROR("SPACING", - "exactly one space required after that #$1\n" . $herecurr); - } - -# check for spinlock_t definitions without a comment. - if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || - $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { - my $which = $1; - if (!ctx_has_comment($first_line, $linenr)) { - CHK("UNCOMMENTED_DEFINITION", - "$1 definition without comment\n" . $herecurr); - } - } -# check for memory barriers without a comment. - if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { - if (!ctx_has_comment($first_line, $linenr)) { - CHK("MEMORY_BARRIER", - "memory barrier without comment\n" . $herecurr); - } - } -# check of hardware specific defines - if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { - CHK("ARCH_DEFINES", - "architecture specific defines should be avoided\n" . $herecurr); - } - -# Check that the storage class is at the beginning of a declaration - if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { - WARN("STORAGE_CLASS", - "storage class should be at the beginning of the declaration\n" . $herecurr) - } - -# check the location of the inline attribute, that it is between -# storage class and type. - if ($line =~ /\b$Type\s+$Inline\b/ || - $line =~ /\b$Inline\s+$Storage\b/) { - ERROR("INLINE_LOCATION", - "inline keyword should sit between storage class and type\n" . $herecurr); - } - -# Check for __inline__ and __inline, prefer inline - if ($line =~ /\b(__inline__|__inline)\b/) { - WARN("INLINE", - "plain inline is preferred over $1\n" . $herecurr); - } - -# Check for __attribute__ format(printf, prefer __printf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { - WARN("PREFER_PRINTF", - "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); - } - -# Check for __attribute__ format(scanf, prefer __scanf - if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { - WARN("PREFER_SCANF", - "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); - } - -# check for sizeof(&) - if ($line =~ /\bsizeof\s*\(\s*\&/) { - WARN("SIZEOF_ADDRESS", - "sizeof(& should be avoided\n" . $herecurr); - } - -# check for sizeof without parenthesis - if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { - WARN("SIZEOF_PARENTHESIS", - "sizeof $1 should be sizeof($1)\n" . $herecurr); - } - -# check for line continuations in quoted strings with odd counts of " - if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { - WARN("LINE_CONTINUATIONS", - "Avoid line continuations in quoted strings\n" . $herecurr); - } - -# check for struct spinlock declarations - if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { - WARN("USE_SPINLOCK_T", - "struct spinlock should be spinlock_t\n" . $herecurr); - } - -# check for seq_printf uses that could be seq_puts - if ($line =~ /\bseq_printf\s*\(/) { - my $fmt = get_quoted_string($line, $rawline); - if ($fmt !~ /[^\\]\%/) { - WARN("PREFER_SEQ_PUTS", - "Prefer seq_puts to seq_printf\n" . $herecurr); - } - } - -# Check for misused memsets - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { - - my $ms_addr = $2; - my $ms_val = $7; - my $ms_size = $12; - - if ($ms_size =~ /^(0x|)0$/i) { - ERROR("MEMSET", - "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); - } elsif ($ms_size =~ /^(0x|)1$/i) { - WARN("MEMSET", - "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); - } - } - -# typecasts on min/max could be min_t/max_t - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { - if (defined $2 || defined $7) { - my $call = $1; - my $cast1 = deparenthesize($2); - my $arg1 = $3; - my $cast2 = deparenthesize($7); - my $arg2 = $8; - my $cast; - - if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { - $cast = "$cast1 or $cast2"; - } elsif ($cast1 ne "") { - $cast = $cast1; - } else { - $cast = $cast2; - } - WARN("MINMAX", - "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); - } - } - -# check usleep_range arguments - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { - my $min = $1; - my $max = $7; - if ($min eq $max) { - WARN("USLEEP_RANGE", - "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); - } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && - $min > $max) { - WARN("USLEEP_RANGE", - "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); - } - } - -# check for new externs in .c files. - if ($realfile =~ /\.c$/ && defined $stat && - $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) - { - my $function_name = $1; - my $paren_space = $2; - - my $s = $stat; - if (defined $cond) { - substr($s, 0, length($cond), ''); - } - if ($s =~ /^\s*;/ && - $function_name ne 'uninitialized_var') - { - WARN("AVOID_EXTERNS", - "externs should be avoided in .c files\n" . $herecurr); - } - - if ($paren_space =~ /\n/) { - WARN("FUNCTION_ARGUMENTS", - "arguments for function declarations should follow identifier\n" . $herecurr); - } - - } elsif ($realfile =~ /\.c$/ && defined $stat && - $stat =~ /^.\s*extern\s+/) - { - WARN("AVOID_EXTERNS", - "externs should be avoided in .c files\n" . $herecurr); - } - -# checks for new __setup's - if ($rawline =~ /\b__setup\("([^"]*)"/) { - my $name = $1; - - if (!grep(/$name/, @setup_docs)) { - CHK("UNDOCUMENTED_SETUP", - "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); - } - } - -# check for pointless casting of kmalloc return - if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { - WARN("UNNECESSARY_CASTS", - "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); - } - -# check for krealloc arg reuse - if ($^V && $^V ge 5.10.0 && - $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { - WARN("KREALLOC_ARG_REUSE", - "Reusing the krealloc arg is almost always a bug\n" . $herecurr); - } - -# check for alloc argument mismatch - if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { - WARN("ALLOC_ARRAY_ARGS", - "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); - } - -# check for multiple semicolons - if ($line =~ /;\s*;\s*$/) { - WARN("ONE_SEMICOLON", - "Statements terminations use 1 semicolon\n" . $herecurr); - } - -# check for switch/default statements without a break; - if ($^V && $^V ge 5.10.0 && - defined $stat && - $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { - my $ctx = ''; - my $herectx = $here . "\n"; - my $cnt = statement_rawlines($stat); - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } - WARN("DEFAULT_NO_BREAK", - "switch default: should use break\n" . $herectx); - } - -# check for gcc specific __FUNCTION__ - if ($line =~ /__FUNCTION__/) { - WARN("USE_FUNC", - "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); - } - -# check for use of yield() - if ($line =~ /\byield\s*\(\s*\)/) { - WARN("YIELD", - "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); - } - -# check for semaphores initialized locked - if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { - WARN("CONSIDER_COMPLETION", - "consider using a completion\n" . $herecurr); - } - -# recommend kstrto* over simple_strto* and strict_strto* - if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { - WARN("CONSIDER_KSTRTO", - "$1 is obsolete, use k$3 instead\n" . $herecurr); - } - -# check for __initcall(), use device_initcall() explicitly please - if ($line =~ /^.\s*__initcall\s*\(/) { - WARN("USE_DEVICE_INITCALL", - "please use device_initcall() instead of __initcall()\n" . $herecurr); - } - -# check for various ops structs, ensure they are const. - my $struct_ops = qr{acpi_dock_ops| - address_space_operations| - backlight_ops| - block_device_operations| - dentry_operations| - dev_pm_ops| - dma_map_ops| - extent_io_ops| - file_lock_operations| - file_operations| - hv_ops| - ide_dma_ops| - intel_dvo_dev_ops| - item_operations| - iwl_ops| - kgdb_arch| - kgdb_io| - kset_uevent_ops| - lock_manager_operations| - microcode_ops| - mtrr_ops| - neigh_ops| - nlmsvc_binding| - pci_raw_ops| - pipe_buf_operations| - platform_hibernation_ops| - platform_suspend_ops| - proto_ops| - rpc_pipe_ops| - seq_operations| - snd_ac97_build_ops| - soc_pcmcia_socket_ops| - stacktrace_ops| - sysfs_ops| - tty_operations| - usb_mon_operations| - wd_ops}x; - if ($line !~ /\bconst\b/ && - $line =~ /\bstruct\s+($struct_ops)\b/) { - WARN("CONST_STRUCT", - "struct $1 should normally be const\n" . - $herecurr); - } - -# use of NR_CPUS is usually wrong -# ignore definitions of NR_CPUS and usage to define arrays as likely right - if ($line =~ /\bNR_CPUS\b/ && - $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && - $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && - $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && - $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) - { - WARN("NR_CPUS", - "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); - } - -# check for %L{u,d,i} in strings - my $string; - while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { - $string = substr($rawline, $-[1], $+[1] - $-[1]); - $string =~ s/%%/__/g; - if ($string =~ /(?mutex.\n" . $herecurr); - } - } - - if ($line =~ /debugfs_create_file.*S_IWUGO/ || - $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { - WARN("EXPORTED_WORLD_WRITABLE", - "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); - } - } - - # If we have no input at all, then there is nothing to report on - # so just keep quiet. - if ($#rawlines == -1) { - exit(0); - } - - # In mailback mode only produce a report in the negative, for - # things that appear to be patches. - if ($mailback && ($clean == 1 || !$is_patch)) { - exit(0); - } - - # This is not a patch, and we are are in 'no-patch' mode so - # just keep quiet. - if (!$chk_patch && !$is_patch) { - exit(0); - } - - if (!$is_patch) { - ERROR("NOT_UNIFIED_DIFF", - "Does not appear to be a unified-diff format patch\n"); - } - if ($is_patch && $chk_signoff && $signoff == 0) { - ERROR("MISSING_SIGN_OFF", - "Missing Signed-off-by: line(s)\n"); - } - - print report_dump(); - if ($summary && !($clean == 1 && $quiet == 1)) { - print "$filename " if ($summary_file); - print "total: $cnt_error errors, $cnt_warn warnings, " . - (($check)? "$cnt_chk checks, " : "") . - "$cnt_lines lines checked\n"; - print "\n" if ($quiet == 0); - } - - if ($quiet == 0) { - - if ($^V lt 5.10.0) { - print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); - print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); - } - - # If there were whitespace errors which cleanpatch can fix - # then suggest that. - if ($rpt_cleaners) { - print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; - print " scripts/cleanfile\n\n"; - $rpt_cleaners = 0; - } - } - - if ($quiet == 0 && keys %ignore_type) { - print "NOTE: Ignored message types:"; - foreach my $ignore (sort keys %ignore_type) { - print " $ignore"; - } - print "\n\n"; - } - - if ($clean == 1 && $quiet == 0) { - print "$vname has no obvious style problems and is ready for submission.\n" - } - if ($clean == 0 && $quiet == 0) { - print << "EOM"; -$vname has style problems, please review. - -If any of these errors are false positives, please report -them to the maintainer, see CHECKPATCH in MAINTAINERS. -EOM - } - - return $clean; -} diff --git a/libopencm3/scripts/data/lpc43xx/README b/libopencm3/scripts/data/lpc43xx/README deleted file mode 100644 index b768936..0000000 --- a/libopencm3/scripts/data/lpc43xx/README +++ /dev/null @@ -1,23 +0,0 @@ -These files contain information derived from the LPC43xx user manual (UM10503). -They are intended to be used by scripts for the generation of header files and -functions. - -Each line describes a field within a register. The comma separated values are: - register name (as found in include/lpc43xx/*.h), - bit position, - length in bits, - field name, - description/comment (may be empty if not specified in data sheet), - reset value (may be empty if not specified in data sheet), - access (may be empty if not specified in data sheet) - -The access field may consist of any of the following codes: - r: read only - rw: read/write - rwc: read/write one to clear - rwo: read/write once - rws: read/write one to set - w: write only - ws: write one to set - -Descriptions containing commas are quoted. diff --git a/libopencm3/scripts/data/lpc43xx/adc.yaml b/libopencm3/scripts/data/lpc43xx/adc.yaml deleted file mode 100644 index 9256e2a..0000000 --- a/libopencm3/scripts/data/lpc43xx/adc.yaml +++ /dev/null @@ -1,607 +0,0 @@ -!!omap -- ADC0_CR: - fields: !!omap - - SEL: - access: rw - description: Selects which of the ADCn_[7:0] inputs are to be sampled and - converted - lsb: 0 - reset_value: '0' - width: 8 - - CLKDIV: - access: rw - description: The ADC clock is divided by the CLKDIV value plus one to produce - the clock for the A/D converter - lsb: 8 - reset_value: '0' - width: 8 - - BURST: - access: rw - description: Controls Burst mode - lsb: 16 - reset_value: '0' - width: 1 - - CLKS: - access: rw - description: This field selects the number of clocks used for each conversion - in Burst mode and the number of bits of accuracy of the result in the LS - bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). - lsb: 17 - reset_value: '0' - width: 3 - - PDN: - access: rw - description: Power mode - lsb: 21 - reset_value: '0' - width: 1 - - START: - access: rw - description: Controls the start of an A/D conversion when the BURST bit is - 0 - lsb: 24 - reset_value: '0' - width: 3 - - EDGE: - access: rw - description: Controls rising or falling edge on the selected signal for the - start of a conversion - lsb: 27 - reset_value: '0' - width: 1 -- ADC1_CR: - fields: !!omap - - SEL: - access: rw - description: Selects which of the ADCn_[7:0] inputs are to be sampled and - converted - lsb: 0 - reset_value: '0' - width: 8 - - CLKDIV: - access: rw - description: The ADC clock is divided by the CLKDIV value plus one to produce - the clock for the A/D converter - lsb: 8 - reset_value: '0' - width: 8 - - BURST: - access: rw - description: Controls Burst mode - lsb: 16 - reset_value: '0' - width: 1 - - CLKS: - access: rw - description: This field selects the number of clocks used for each conversion - in Burst mode and the number of bits of accuracy of the result in the LS - bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). - lsb: 17 - reset_value: '0' - width: 3 - - PDN: - access: rw - description: Power mode - lsb: 21 - reset_value: '0' - width: 1 - - START: - access: rw - description: Controls the start of an A/D conversion when the BURST bit is - 0 - lsb: 24 - reset_value: '0' - width: 3 - - EDGE: - access: rw - description: Controls rising or falling edge on the selected signal for the - start of a conversion - lsb: 27 - reset_value: '0' - width: 1 -- ADC0_GDR: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADCn pin selected by the SEL field, divided by the reference - voltage on the VDDA pin - lsb: 6 - reset_value: '0' - width: 10 - - CHN: - access: r - description: These bits contain the channel from which the LS bits were converted - lsb: 24 - reset_value: '0' - width: 3 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an analog-to-digital conversion completes. - It is cleared when this register is read and when the AD0/1CR register is - written - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_GDR: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADCn pin selected by the SEL field, divided by the reference - voltage on the VDDA pin - lsb: 6 - reset_value: '0' - width: 10 - - CHN: - access: r - description: These bits contain the channel from which the LS bits were converted - lsb: 24 - reset_value: '0' - width: 3 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an analog-to-digital conversion completes. - It is cleared when this register is read and when the AD0/1CR register is - written - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_INTEN: - fields: !!omap - - ADINTEN: - access: rw - description: These bits allow control over which A/D channels generate interrupts - for conversion completion - lsb: 0 - reset_value: '0' - width: 8 - - ADGINTEN: - access: rw - description: When 1, enables the global DONE flag in ADDR to generate an interrupt. - When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate - interrupts. - lsb: 8 - reset_value: '1' - width: 1 -- ADC1_INTEN: - fields: !!omap - - ADINTEN: - access: rw - description: These bits allow control over which A/D channels generate interrupts - for conversion completion - lsb: 0 - reset_value: '0' - width: 8 - - ADGINTEN: - access: rw - description: When 1, enables the global DONE flag in ADDR to generate an interrupt. - When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate - interrupts. - lsb: 8 - reset_value: '1' - width: 1 -- ADC0_DR0: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC0 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR0: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC0 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR1: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC1 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR1: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC1 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR2: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC2 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR2: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC2 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR3: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC3 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR3: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC3 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR4: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC4 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR4: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC4 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR5: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC5 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR5: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC5 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR6: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC6 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR6: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC6 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_DR7: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC7 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC1_DR7: - fields: !!omap - - V_VREF: - access: r - description: When DONE is 1, this field contains a binary fraction representing - the voltage on the ADC7 pin divided by the reference voltage on the VDDA - pin - lsb: 6 - reset_value: '0' - width: 10 - - OVERRUN: - access: r - description: This bit is 1 in burst mode if the results of one or more conversions - was (were) lost and overwritten before the conversion that produced the - result in the V_VREF bits in this register. - lsb: 30 - reset_value: '0' - width: 1 - - DONE: - access: r - description: This bit is set to 1 when an A/D conversion completes. - lsb: 31 - reset_value: '0' - width: 1 -- ADC0_STAT: - fields: !!omap - - DONE: - access: r - description: These bits mirror the DONE status flags that appear in the result - register for each A/D channel. - lsb: 0 - reset_value: '0' - width: 8 - - OVERRUN: - access: r - description: These bits mirror the OVERRRUN status flags that appear in the - result register for each A/D channel. - lsb: 8 - reset_value: '0' - width: 8 - - ADINT: - access: r - description: This bit is the A/D interrupt flag. It is one when any of the - individual A/D channel Done flags is asserted and enabled to contribute - to the A/D interrupt via the ADINTEN register. - lsb: 16 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/atimer.yaml b/libopencm3/scripts/data/lpc43xx/atimer.yaml deleted file mode 100644 index 010a25d..0000000 --- a/libopencm3/scripts/data/lpc43xx/atimer.yaml +++ /dev/null @@ -1,71 +0,0 @@ -!!omap -- ATIMER_DOWNCOUNTER: - fields: !!omap - - CVAL: - access: rw - description: When equal to zero an interrupt is raised - lsb: 0 - reset_value: '0' - width: 16 -- ATIMER_PRESET: - fields: !!omap - - PRESETVAL: - access: rw - description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero - lsb: 0 - reset_value: '0' - width: 16 -- ATIMER_CLR_EN: - fields: !!omap - - CLR_EN: - access: w - description: Writing a 1 to this bit clears the interrupt enable bit in the - ENABLE register - lsb: 0 - reset_value: '0' - width: 1 -- ATIMER_SET_EN: - fields: !!omap - - SET_EN: - access: w - description: Writing a 1 to this bit sets the interrupt enable bit in the - ENABLE register - lsb: 0 - reset_value: '0' - width: 1 -- ATIMER_STATUS: - fields: !!omap - - STAT: - access: r - description: A 1 in this bit shows that the STATUS interrupt has been raised - lsb: 0 - reset_value: '0' - width: 1 -- ATIMER_ENABLE: - fields: !!omap - - ENA: - access: r - description: A 1 in this bit shows that the STATUS interrupt has been enabled - and that the STATUS interrupt request signal is asserted when STAT = 1 in - the STATUS register - lsb: 0 - reset_value: '0' - width: 1 -- ATIMER_CLR_STAT: - fields: !!omap - - CSTAT: - access: w - description: Writing a 1 to this bit clears the STATUS interrupt bit in the - STATUS register - lsb: 0 - reset_value: '0' - width: 1 -- ATIMER_SET_STAT: - fields: !!omap - - SSTAT: - access: w - description: Writing a 1 to this bit sets the STATUS interrupt bit in the - STATUS register - lsb: 0 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/ccu.yaml b/libopencm3/scripts/data/lpc43xx/ccu.yaml deleted file mode 100644 index b2d225f..0000000 --- a/libopencm3/scripts/data/lpc43xx/ccu.yaml +++ /dev/null @@ -1,2391 +0,0 @@ -!!omap -- CCU1_PM: - fields: !!omap - - PD: - access: rw - description: Initiate power-down mode - lsb: 0 - reset_value: '0' - width: 1 -- CCU1_BASE_STAT: - fields: !!omap - - BASE_APB3_CLK_IND: - access: r - description: Base clock indicator for BASE_APB3_CLK - lsb: 0 - reset_value: '1' - width: 1 - - BASE_APB1_CLK_IND: - access: r - description: Base clock indicator for BASE_APB1_CLK - lsb: 1 - reset_value: '1' - width: 1 - - BASE_SPIFI_CLK_IND: - access: r - description: Base clock indicator for BASE_SPIFI_CLK - lsb: 2 - reset_value: '1' - width: 1 - - BASE_M4_CLK_IND: - access: r - description: Base clock indicator for BASE_M4_CLK - lsb: 3 - reset_value: '1' - width: 1 - - BASE_PERIPH_CLK_IND: - access: r - description: Base clock indicator for BASE_PERIPH_CLK - lsb: 6 - reset_value: '1' - width: 1 - - BASE_USB0_CLK_IND: - access: r - description: Base clock indicator for BASE_USB0_CLK - lsb: 7 - reset_value: '1' - width: 1 - - BASE_USB1_CLK_IND: - access: r - description: Base clock indicator for BASE_USB1_CLK - lsb: 8 - reset_value: '1' - width: 1 - - BASE_SPI_CLK_IND: - access: r - description: Base clock indicator for BASE_SPI_CLK - lsb: 9 - reset_value: '1' - width: 1 -- CCU1_CLK_APB3_BUS_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_BUS_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_I2C1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_I2C1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_DAC_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_DAC_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_ADC0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_ADC0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_ADC1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_ADC1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_CAN0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB3_CAN0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_BUS_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_BUS_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_MOTOCONPWM_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_MOTOCONPWM_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_I2C0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_I2C0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_I2S_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_I2S_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_CAN1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_APB1_CAN1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_SPIFI_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_SPIFI_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_BUS_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_BUS_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SPIFI_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SPIFI_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_GPIO_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_GPIO_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_LCD_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_LCD_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_ETHERNET_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_ETHERNET_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USB0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USB0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_EMC_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_EMC_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SDIO_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SDIO_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_DMA_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_DMA_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_M4CORE_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_M4CORE_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SCT_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SCT_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USB1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USB1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_EMCDIV_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 - - DIV: - access: rw - description: Clock divider value - lsb: 5 - reset_value: '0' - width: 3 -- CCU1_CLK_M4_EMCDIV_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_M0APP_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_M0APP_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_VADC_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_VADC_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_WWDT_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_WWDT_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_UART1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_UART1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SSP0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SSP0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SCU_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SCU_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_CREG_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_CREG_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_RITIMER_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_RITIMER_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART2_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART2_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART3_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_USART3_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER2_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER2_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER3_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_TIMER3_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SSP1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_SSP1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_QEI_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_M4_QEI_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_BUS_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_BUS_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_CORE_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_CORE_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_SGPIO_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_PERIPH_SGPIO_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_USB0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_USB0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_USB1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_USB1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_SPI_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_SPI_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_VADC_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU1_CLK_VADC_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_PM: - fields: !!omap - - PD: - access: rw - description: Initiate power-down mode - lsb: 0 - reset_value: '0' - width: 1 -- CCU2_BASE_STAT: - fields: !!omap - - BASE_UART3_CLK_IND: - access: r - description: Base clock indicator for BASE_UART3_CLK - lsb: 1 - reset_value: '1' - width: 1 - - BASE_UART2_CLK_IND: - access: r - description: Base clock indicator for BASE_UART2_CLK - lsb: 2 - reset_value: '1' - width: 1 - - BASE_UART1_CLK_IND: - access: r - description: Base clock indicator for BASE_UART1_CLK - lsb: 3 - reset_value: '1' - width: 1 - - BASE_UART0_CLK_IND: - access: r - description: Base clock indicator for BASE_UART0_CLK - lsb: 4 - reset_value: '1' - width: 1 - - BASE_SSP1_CLK_IND: - access: r - description: Base clock indicator for BASE_SSP1_CLK - lsb: 5 - reset_value: '1' - width: 1 - - BASE_SSP0_CLK_IND: - access: r - description: Base clock indicator for BASE_SSP0_CLK - lsb: 6 - reset_value: '1' - width: 1 -- CCU2_CLK_APLL_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APLL_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_USART3_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_USART3_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_USART2_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_USART2_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_UART1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_UART1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_USART0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_USART0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_SSP1_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB2_SSP1_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_SSP0_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_APB0_SSP0_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_SDIO_CFG: - fields: !!omap - - RUN: - access: rw - description: Run enable - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: rw - description: Auto (AHB disable mechanism) enable - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: rw - description: Wake-up mechanism enable - lsb: 2 - reset_value: '0' - width: 1 -- CCU2_CLK_SDIO_STAT: - fields: !!omap - - RUN: - access: r - description: Run enable status - lsb: 0 - reset_value: '1' - width: 1 - - AUTO: - access: r - description: Auto (AHB disable mechanism) enable status - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP: - access: r - description: Wake-up mechanism enable status - lsb: 2 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/cgu.yaml b/libopencm3/scripts/data/lpc43xx/cgu.yaml deleted file mode 100644 index f55b8d0..0000000 --- a/libopencm3/scripts/data/lpc43xx/cgu.yaml +++ /dev/null @@ -1,937 +0,0 @@ -!!omap -- CGU_FREQ_MON: - fields: !!omap - - RCNT: - access: rw - description: 9-bit reference clock-counter value - lsb: 0 - reset_value: '0' - width: 9 - - FCNT: - access: r - description: 14-bit selected clock-counter value - lsb: 9 - reset_value: '0' - width: 14 - - MEAS: - access: rw - description: Measure frequency - lsb: 23 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock-source selection for the clock to be measured - lsb: 24 - reset_value: '0' - width: 5 -- CGU_XTAL_OSC_CTRL: - fields: !!omap - - ENABLE: - access: rw - description: Oscillator-pad enable - lsb: 0 - reset_value: '1' - width: 1 - - BYPASS: - access: rw - description: Configure crystal operation or external-clock input pin XTAL1 - lsb: 1 - reset_value: '0' - width: 1 - - HF: - access: rw - description: Select frequency range - lsb: 2 - reset_value: '1' - width: 1 -- CGU_PLL0USB_STAT: - fields: !!omap - - LOCK: - access: r - description: PLL0 lock indicator - lsb: 0 - reset_value: '0' - width: 1 - - FR: - access: r - description: PLL0 free running indicator - lsb: 1 - reset_value: '0' - width: 1 -- CGU_PLL0USB_CTRL: - fields: !!omap - - PD: - access: rw - description: PLL0 power down - lsb: 0 - reset_value: '1' - width: 1 - - BYPASS: - access: rw - description: Input clock bypass control - lsb: 1 - reset_value: '1' - width: 1 - - DIRECTI: - access: rw - description: PLL0 direct input - lsb: 2 - reset_value: '0' - width: 1 - - DIRECTO: - access: rw - description: PLL0 direct output - lsb: 3 - reset_value: '0' - width: 1 - - CLKEN: - access: rw - description: PLL0 clock enable - lsb: 4 - reset_value: '0' - width: 1 - - FRM: - access: rw - description: Free running mode - lsb: 6 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_PLL0USB_MDIV: - fields: !!omap - - MDEC: - access: rw - description: Decoded M-divider coefficient value - lsb: 0 - reset_value: '0x5B6A' - width: 17 - - SELP: - access: rw - description: Bandwidth select P value - lsb: 17 - reset_value: '0x1C' - width: 5 - - SELI: - access: rw - description: Bandwidth select I value - lsb: 22 - reset_value: '0x17' - width: 6 - - SELR: - access: rw - description: Bandwidth select R value - lsb: 28 - reset_value: '0x0' - width: 4 -- CGU_PLL0USB_NP_DIV: - fields: !!omap - - PDEC: - access: rw - description: Decoded P-divider coefficient value - lsb: 0 - reset_value: '0x02' - width: 7 - - NDEC: - access: rw - description: Decoded N-divider coefficient value - lsb: 12 - reset_value: '0xB1' - width: 10 -- CGU_PLL0AUDIO_STAT: - fields: !!omap - - LOCK: - access: r - description: PLL0 lock indicator - lsb: 0 - reset_value: '0' - width: 1 - - FR: - access: r - description: PLL0 free running indicator - lsb: 1 - reset_value: '0' - width: 1 -- CGU_PLL0AUDIO_CTRL: - fields: !!omap - - PD: - access: rw - description: PLL0 power down - lsb: 0 - reset_value: '1' - width: 1 - - BYPASS: - access: rw - description: Input clock bypass control - lsb: 1 - reset_value: '1' - width: 1 - - DIRECTI: - access: rw - description: PLL0 direct input - lsb: 2 - reset_value: '0' - width: 1 - - DIRECTO: - access: rw - description: PLL0 direct output - lsb: 3 - reset_value: '0' - width: 1 - - CLKEN: - access: rw - description: PLL0 clock enable - lsb: 4 - reset_value: '0' - width: 1 - - FRM: - access: rw - description: Free running mode - lsb: 6 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - PLLFRACT_REQ: - access: rw - description: Fractional PLL word write request - lsb: 12 - reset_value: '0' - width: 1 - - SEL_EXT: - access: rw - description: Select fractional divider - lsb: 13 - reset_value: '0' - width: 1 - - MOD_PD: - access: rw - description: Sigma-Delta modulator power-down - lsb: 14 - reset_value: '1' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_PLL0AUDIO_MDIV: - fields: !!omap - - MDEC: - access: rw - description: Decoded M-divider coefficient value - lsb: 0 - reset_value: '0x5B6A' - width: 17 -- CGU_PLL0AUDIO_NP_DIV: - fields: !!omap - - PDEC: - access: rw - description: Decoded P-divider coefficient value - lsb: 0 - reset_value: '0x02' - width: 7 - - NDEC: - access: rw - description: Decoded N-divider coefficient value - lsb: 12 - reset_value: '0xB1' - width: 10 -- CGU_PLLAUDIO_FRAC: - fields: !!omap - - PLLFRACT_CTRL: - access: rw - description: PLL fractional divider control word - lsb: 0 - reset_value: '0x00' - width: 22 -- CGU_PLL1_STAT: - fields: !!omap - - LOCK: - access: r - description: PLL1 lock indicator - lsb: 0 - reset_value: '0' - width: 1 -- CGU_PLL1_CTRL: - fields: !!omap - - PD: - access: rw - description: PLL1 power down - lsb: 0 - reset_value: '1' - width: 1 - - BYPASS: - access: rw - description: Input clock bypass control - lsb: 1 - reset_value: '1' - width: 1 - - FBSEL: - access: rw - description: PLL feedback select - lsb: 6 - reset_value: '0' - width: 1 - - DIRECT: - access: rw - description: PLL direct CCO output - lsb: 7 - reset_value: '0' - width: 1 - - PSEL: - access: rw - description: Post-divider division ratio P - lsb: 8 - reset_value: '0x1' - width: 2 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - NSEL: - access: rw - description: Pre-divider division ratio N - lsb: 12 - reset_value: '0x2' - width: 2 - - MSEL: - access: rw - description: Feedback-divider division ratio (M) - lsb: 16 - reset_value: '0x18' - width: 8 - - CLK_SEL: - access: rw - description: Clock-source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_IDIVA_CTRL: - fields: !!omap - - PD: - access: rw - description: Integer divider power down - lsb: 0 - reset_value: '0' - width: 1 - - IDIV: - access: rw - description: Integer divider A divider value (1/(IDIV + 1)) - lsb: 2 - reset_value: '0x0' - width: 2 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_IDIVB_CTRL: - fields: !!omap - - PD: - access: rw - description: Integer divider power down - lsb: 0 - reset_value: '0' - width: 1 - - IDIV: - access: rw - description: Integer divider B divider value (1/(IDIV + 1)) - lsb: 2 - reset_value: '0x0' - width: 4 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_IDIVC_CTRL: - fields: !!omap - - PD: - access: rw - description: Integer divider power down - lsb: 0 - reset_value: '0' - width: 1 - - IDIV: - access: rw - description: Integer divider C divider value (1/(IDIV + 1)) - lsb: 2 - reset_value: '0x0' - width: 4 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_IDIVD_CTRL: - fields: !!omap - - PD: - access: rw - description: Integer divider power down - lsb: 0 - reset_value: '0' - width: 1 - - IDIV: - access: rw - description: Integer divider D divider value (1/(IDIV + 1)) - lsb: 2 - reset_value: '0x0' - width: 4 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_IDIVE_CTRL: - fields: !!omap - - PD: - access: rw - description: Integer divider power down - lsb: 0 - reset_value: '0' - width: 1 - - IDIV: - access: rw - description: Integer divider E divider value (1/(IDIV + 1)) - lsb: 2 - reset_value: '0x00' - width: 8 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SAFE_CLK: - fields: !!omap - - PD: - access: r - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: r - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: r - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_USB0_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x07' - width: 5 -- CGU_BASE_PERIPH_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_USB1_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_M4_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SPIFI_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SPI_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_PHY_RX_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_PHY_TX_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_APB1_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_APB3_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_LCD_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_VADC_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SDIO_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SSP0_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_SSP1_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_UART0_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_UART1_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_UART2_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_UART3_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_OUT_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_APLL_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_CGU_OUT0_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 -- CGU_BASE_CGU_OUT1_CLK: - fields: !!omap - - PD: - access: rw - description: Output stage power down - lsb: 0 - reset_value: '0' - width: 1 - - AUTOBLOCK: - access: rw - description: Block clock automatically during frequency change - lsb: 11 - reset_value: '0' - width: 1 - - CLK_SEL: - access: rw - description: Clock source selection - lsb: 24 - reset_value: '0x01' - width: 5 diff --git a/libopencm3/scripts/data/lpc43xx/creg.yaml b/libopencm3/scripts/data/lpc43xx/creg.yaml deleted file mode 100644 index 3fb8ab7..0000000 --- a/libopencm3/scripts/data/lpc43xx/creg.yaml +++ /dev/null @@ -1,312 +0,0 @@ -!!omap -- CREG_CREG0: - fields: !!omap - - EN1KHZ: - access: rw - description: Enable 1 kHz output - lsb: 0 - reset_value: '0' - width: 1 - - EN32KHZ: - access: rw - description: Enable 32 kHz output - lsb: 1 - reset_value: '0' - width: 1 - - RESET32KHZ: - access: rw - description: 32 kHz oscillator reset - lsb: 2 - reset_value: '1' - width: 1 - - PD32KHZ: - access: rw - description: 32 kHz power control - lsb: 3 - reset_value: '1' - width: 1 - - USB0PHY: - access: rw - description: USB0 PHY power control - lsb: 5 - reset_value: '1' - width: 1 - - ALARMCTRL: - access: rw - description: RTC_ALARM pin output control - lsb: 6 - reset_value: '0' - width: 2 - - BODLVL1: - access: rw - description: BOD trip level to generate an interrupt - lsb: 8 - reset_value: '0x3' - width: 2 - - BODLVL2: - access: rw - description: BOD trip level to generate a reset - lsb: 10 - reset_value: '0x3' - width: 2 - - SAMPLECTRL: - access: rw - description: SAMPLE pin input/output control - lsb: 12 - reset_value: '0' - width: 2 - - WAKEUP0CTRL: - access: rw - description: WAKEUP0 pin input/output control - lsb: 14 - reset_value: '0' - width: 2 - - WAKEUP1CTRL: - access: rw - description: WAKEUP1 pin input/output control - lsb: 16 - reset_value: '0' - width: 2 -- CREG_M4MEMMAP: - fields: !!omap - - M4MAP: - access: rw - description: Shadow address when accessing memory at address 0x00000000 - lsb: 12 - reset_value: '0x10400000' - width: 20 -- CREG_CREG5: - fields: !!omap - - M4TAPSEL: - access: rw - description: JTAG debug select for M4 core - lsb: 6 - reset_value: '1' - width: 1 - - M0APPTAPSEL: - access: rw - description: JTAG debug select for M0 co-processor - lsb: 9 - reset_value: '1' - width: 1 -- CREG_DMAMUX: - fields: !!omap - - DMAMUXPER0: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 0 - lsb: 0 - reset_value: '0' - width: 2 - - DMAMUXPER1: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 1 - lsb: 2 - reset_value: '0' - width: 2 - - DMAMUXPER2: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 2 - lsb: 4 - reset_value: '0' - width: 2 - - DMAMUXPER3: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 3 - lsb: 6 - reset_value: '0' - width: 2 - - DMAMUXPER4: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 4 - lsb: 8 - reset_value: '0' - width: 2 - - DMAMUXPER5: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 5 - lsb: 10 - reset_value: '0' - width: 2 - - DMAMUXPER6: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 6 - lsb: 12 - reset_value: '0' - width: 2 - - DMAMUXPER7: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 7 - lsb: 14 - reset_value: '0' - width: 2 - - DMAMUXPER8: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 8 - lsb: 16 - reset_value: '0' - width: 2 - - DMAMUXPER9: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 9 - lsb: 18 - reset_value: '0' - width: 2 - - DMAMUXPER10: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 10 - lsb: 20 - reset_value: '0' - width: 2 - - DMAMUXPER11: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 11 - lsb: 22 - reset_value: '0' - width: 2 - - DMAMUXPER12: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 12 - lsb: 24 - reset_value: '0' - width: 2 - - DMAMUXPER13: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 13 - lsb: 26 - reset_value: '0' - width: 2 - - DMAMUXPER14: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 14 - lsb: 28 - reset_value: '0' - width: 2 - - DMAMUXPER15: - access: rw - description: Select DMA to peripheral connection for DMA peripheral 15 - lsb: 30 - reset_value: '0' - width: 2 -- CREG_FLASHCFGA: - fields: !!omap - - FLASHTIM: - access: rw - description: Flash access time. The value of this field plus 1 gives the number - of BASE_M4_CLK clocks used for a flash access - lsb: 12 - reset_value: '' - width: 4 - - POW: - access: rw - description: Flash bank A power control - lsb: 31 - reset_value: '1' - width: 1 -- CREG_FLASHCFGB: - fields: !!omap - - FLASHTIM: - access: rw - description: Flash access time. The value of this field plus 1 gives the number - of BASE_M4_CLK clocks used for a flash access - lsb: 12 - reset_value: '' - width: 4 - - POW: - access: rw - description: Flash bank B power control - lsb: 31 - reset_value: '1' - width: 1 -- CREG_ETBCFG: - fields: !!omap - - ETB: - access: rw - description: Select SRAM interface - lsb: 0 - reset_value: '1' - width: 1 -- CREG_CREG6: - fields: !!omap - - ETHMODE: - access: rw - description: Selects the Ethernet mode. Reset the ethernet after changing - the PHY interface - lsb: 0 - reset_value: '' - width: 3 - - CTOUTCTRL: - access: rw - description: Selects the functionality of the SCT outputs - lsb: 4 - reset_value: '0' - width: 1 - - I2S0_TX_SCK_IN_SEL: - access: rw - description: I2S0_TX_SCK input select - lsb: 12 - reset_value: '0' - width: 1 - - I2S0_RX_SCK_IN_SEL: - access: rw - description: I2S0_RX_SCK input select - lsb: 13 - reset_value: '0' - width: 1 - - I2S1_TX_SCK_IN_SEL: - access: rw - description: I2S1_TX_SCK input select - lsb: 14 - reset_value: '0' - width: 1 - - I2S1_RX_SCK_IN_SEL: - access: rw - description: I2S1_RX_SCK input select - lsb: 15 - reset_value: '0' - width: 1 - - EMC_CLK_SEL: - access: rw - description: EMC_CLK divided clock select - lsb: 16 - reset_value: '0' - width: 1 -- CREG_M4TXEVENT: - fields: !!omap - - TXEVCLR: - access: rw - description: Cortex-M4 TXEV event - lsb: 0 - reset_value: '0' - width: 1 -- CREG_M0TXEVENT: - fields: !!omap - - TXEVCLR: - access: rw - description: Cortex-M0 TXEV event - lsb: 0 - reset_value: '0' - width: 1 -- CREG_M0APPMEMMAP: - fields: !!omap - - M0APPMAP: - access: rw - description: Shadow address when accessing memory at address 0x00000000 - lsb: 12 - reset_value: '0x20000000' - width: 20 -- CREG_USB0FLADJ: - fields: !!omap - - FLTV: - access: rw - description: Frame length timing value - lsb: 0 - reset_value: '0x20' - width: 6 -- CREG_USB1FLADJ: - fields: !!omap - - FLTV: - access: rw - description: Frame length timing value - lsb: 0 - reset_value: '0x20' - width: 6 diff --git a/libopencm3/scripts/data/lpc43xx/csv2yaml.py b/libopencm3/scripts/data/lpc43xx/csv2yaml.py deleted file mode 100755 index 7b2f8c6..0000000 --- a/libopencm3/scripts/data/lpc43xx/csv2yaml.py +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env python - -import sys -import yaml -import csv -from collections import OrderedDict - -def convert_file(fname): - reader = csv.reader(open(fname, 'r')) - - registers = OrderedDict() - for register_name, lsb, width, field_name, description, reset_value, access in reader: - if register_name not in registers: - registers[register_name] = { - 'fields': OrderedDict(), - } - - register = registers[register_name] - fields = register['fields'] - if field_name in fields: - raise RuntimeError('Duplicate field name "%s" in register "%s"' % - field_name, register_name) - else: - fields[field_name] = { - 'lsb': int(lsb), - 'width': int(width), - 'description': description, - 'reset_value': reset_value, - 'access': access, - } - - with open(fname.replace('.csv', '.yaml'), 'w') as out_file: - yaml.dump(registers, out_file, default_flow_style=False) - -for fname in sys.argv[1:]: - convert_file(fname) diff --git a/libopencm3/scripts/data/lpc43xx/eventrouter.yaml b/libopencm3/scripts/data/lpc43xx/eventrouter.yaml deleted file mode 100644 index 677b0d9..0000000 --- a/libopencm3/scripts/data/lpc43xx/eventrouter.yaml +++ /dev/null @@ -1,959 +0,0 @@ -!!omap -- EVENTROUTER_HILO: - fields: !!omap - - WAKEUP0_L: - access: rw - description: Level detect mode for WAKEUP0 event - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_L: - access: rw - description: Level detect mode for WAKEUP1 event - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_L: - access: rw - description: Level detect mode for WAKEUP2 event - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_L: - access: rw - description: Level detect mode for WAKEUP3 event - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_L: - access: rw - description: Level detect mode for alarm timer event - lsb: 4 - reset_value: '0' - width: 1 - - RTC_L: - access: rw - description: Level detect mode for RTC event - lsb: 5 - reset_value: '0' - width: 1 - - BOD_L: - access: rw - description: Level detect mode for BOD event - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_L: - access: rw - description: Level detect mode for WWDT event - lsb: 7 - reset_value: '0' - width: 1 - - ETH_L: - access: rw - description: Level detect mode for Ethernet event - lsb: 8 - reset_value: '0' - width: 1 - - USB0_L: - access: rw - description: Level detect mode for USB0 event - lsb: 9 - reset_value: '0' - width: 1 - - USB1_L: - access: rw - description: Level detect mode for USB1 event - lsb: 10 - reset_value: '0' - width: 1 - - SDMMC_L: - access: rw - description: Level detect mode for SD/MMC event - lsb: 11 - reset_value: '0' - width: 1 - - CAN_L: - access: rw - description: Level detect mode for C_CAN event - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_L: - access: rw - description: Level detect mode for combined timer output 2 event - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_L: - access: rw - description: Level detect mode for combined timer output 6 event - lsb: 14 - reset_value: '0' - width: 1 - - QEI_L: - access: rw - description: Level detect mode for QEI event - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_L: - access: rw - description: Level detect mode for combined timer output 14 event - lsb: 16 - reset_value: '0' - width: 1 - - RESET_L: - access: rw - description: Level detect mode for Reset - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_EDGE: - fields: !!omap - - WAKEUP0_E: - access: rw - description: Edge/Level detect mode for WAKEUP0 event - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_E: - access: rw - description: Edge/Level detect mode for WAKEUP1 event - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_E: - access: rw - description: Edge/Level detect mode for WAKEUP2 event - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_E: - access: rw - description: Edge/Level detect mode for WAKEUP3 event - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_E: - access: rw - description: Edge/Level detect mode for alarm timer event - lsb: 4 - reset_value: '0' - width: 1 - - RTC_E: - access: rw - description: Edge/Level detect mode for RTC event - lsb: 5 - reset_value: '0' - width: 1 - - BOD_E: - access: rw - description: Edge/Level detect mode for BOD event - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_E: - access: rw - description: Edge/Level detect mode for WWDT event - lsb: 7 - reset_value: '0' - width: 1 - - ETH_E: - access: rw - description: Edge/Level detect mode for Ethernet event - lsb: 8 - reset_value: '0' - width: 1 - - USB0_E: - access: rw - description: Edge/Level detect mode for USB0 event - lsb: 9 - reset_value: '0' - width: 1 - - USB1_E: - access: rw - description: Edge/Level detect mode for USB1 event - lsb: 10 - reset_value: '0' - width: 1 - - SDMMC_E: - access: rw - description: Edge/Level detect mode for SD/MMC event - lsb: 11 - reset_value: '0' - width: 1 - - CAN_E: - access: rw - description: Edge/Level detect mode for C_CAN event - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_E: - access: rw - description: Edge/Level detect mode for combined timer output 2 event - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_E: - access: rw - description: Edge/Level detect mode for combined timer output 6 event - lsb: 14 - reset_value: '0' - width: 1 - - QEI_E: - access: rw - description: Edge/Level detect mode for QEI event - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_E: - access: rw - description: Edge/Level detect mode for combined timer output 14 event - lsb: 16 - reset_value: '0' - width: 1 - - RESET_E: - access: rw - description: Edge/Level detect mode for Reset - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_CLR_EN: - fields: !!omap - - WAKEUP0_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 0 in the - ENABLE register - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 1 in the - ENABLE register - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 2 in the - ENABLE register - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 3 in the - ENABLE register - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 4 in the - ENABLE register - lsb: 4 - reset_value: '0' - width: 1 - - RTC_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 5 in the - ENABLE register - lsb: 5 - reset_value: '0' - width: 1 - - BOD_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 6 in the - ENABLE register - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 7 in the - ENABLE register - lsb: 7 - reset_value: '0' - width: 1 - - ETH_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 8 in the - ENABLE register - lsb: 8 - reset_value: '0' - width: 1 - - USB0_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 9 in the - ENABLE register - lsb: 9 - reset_value: '0' - width: 1 - - USB1_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 10 in the - ENABLE register - lsb: 10 - reset_value: '0' - width: 1 - - SDMCC_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 11 in the - ENABLE register - lsb: 11 - reset_value: '0' - width: 1 - - CAN_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 12 in the - ENABLE register - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 13 in the - ENABLE register - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 14 in the - ENABLE register - lsb: 14 - reset_value: '0' - width: 1 - - QEI_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 15 in the - ENABLE register - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 16 in the - ENABLE register - lsb: 16 - reset_value: '0' - width: 1 - - RESET_CLREN: - access: w - description: Writing a 1 to this bit clears the event enable bit 19 in the - ENABLE register - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_SET_EN: - fields: !!omap - - WAKEUP0_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE - register - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE - register - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE - register - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE - register - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE - register - lsb: 4 - reset_value: '0' - width: 1 - - RTC_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE - register - lsb: 5 - reset_value: '0' - width: 1 - - BOD_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE - register - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE - register - lsb: 7 - reset_value: '0' - width: 1 - - ETH_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE - register - lsb: 8 - reset_value: '0' - width: 1 - - USB0_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE - register - lsb: 9 - reset_value: '0' - width: 1 - - USB1_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE - register - lsb: 10 - reset_value: '0' - width: 1 - - SDMCC_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE - register - lsb: 11 - reset_value: '0' - width: 1 - - CAN_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE - register - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE - register - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE - register - lsb: 14 - reset_value: '0' - width: 1 - - QEI_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE - register - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE - register - lsb: 16 - reset_value: '0' - width: 1 - - RESET_SETEN: - access: w - description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE - register - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_STATUS: - fields: !!omap - - WAKEUP0_ST: - access: r - description: A 1 in this bit shows that the WAKEUP0 event has been raised - lsb: 0 - reset_value: '1' - width: 1 - - WAKEUP1_ST: - access: r - description: A 1 in this bit shows that the WAKEUP1 event has been raised - lsb: 1 - reset_value: '1' - width: 1 - - WAKEUP2_ST: - access: r - description: A 1 in this bit shows that the WAKEUP2 event has been raised - lsb: 2 - reset_value: '1' - width: 1 - - WAKEUP3_ST: - access: r - description: A 1 in this bit shows that the WAKEUP3 event has been raised - lsb: 3 - reset_value: '1' - width: 1 - - ATIMER_ST: - access: r - description: A 1 in this bit shows that the ATIMER event has been raised - lsb: 4 - reset_value: '1' - width: 1 - - RTC_ST: - access: r - description: A 1 in this bit shows that the RTC event has been raised - lsb: 5 - reset_value: '1' - width: 1 - - BOD_ST: - access: r - description: A 1 in this bit shows that the BOD event has been raised - lsb: 6 - reset_value: '1' - width: 1 - - WWDT_ST: - access: r - description: A 1 in this bit shows that the WWDT event has been raised - lsb: 7 - reset_value: '1' - width: 1 - - ETH_ST: - access: r - description: A 1 in this bit shows that the ETH event has been raised - lsb: 8 - reset_value: '1' - width: 1 - - USB0_ST: - access: r - description: A 1 in this bit shows that the USB0 event has been raised - lsb: 9 - reset_value: '1' - width: 1 - - USB1_ST: - access: r - description: A 1 in this bit shows that the USB1 event has been raised - lsb: 10 - reset_value: '1' - width: 1 - - SDMMC_ST: - access: r - description: A 1 in this bit shows that the SDMMC event has been raised - lsb: 11 - reset_value: '1' - width: 1 - - CAN_ST: - access: r - description: A 1 in this bit shows that the CAN event has been raised - lsb: 12 - reset_value: '1' - width: 1 - - TIM2_ST: - access: r - description: A 1 in this bit shows that the combined timer 2 output event - has been raised - lsb: 13 - reset_value: '1' - width: 1 - - TIM6_ST: - access: r - description: A 1 in this bit shows that the combined timer 6 output event - has been raised - lsb: 14 - reset_value: '1' - width: 1 - - QEI_ST: - access: r - description: A 1 in this bit shows that the QEI event has been raised - lsb: 15 - reset_value: '1' - width: 1 - - TIM14_ST: - access: r - description: A 1 in this bit shows that the combined timer 14 output event - has been raised - lsb: 16 - reset_value: '1' - width: 1 - - RESET_ST: - access: r - description: A 1 in this bit shows that the reset event has been raised - lsb: 19 - reset_value: '1' - width: 1 -- EVENTROUTER_ENABLE: - fields: !!omap - - WAKEUP0_EN: - access: r - description: A 1 in this bit shows that the WAKEUP0 event has been enabled - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_EN: - access: r - description: A 1 in this bit shows that the WAKEUP1 event has been enabled - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_EN: - access: r - description: A 1 in this bit shows that the WAKEUP2 event has been enabled - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_EN: - access: r - description: A 1 in this bit shows that the WAKEUP3 event has been enabled - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_EN: - access: r - description: A 1 in this bit shows that the ATIMER event has been enabled - lsb: 4 - reset_value: '0' - width: 1 - - RTC_EN: - access: r - description: A 1 in this bit shows that the RTC event has been enabled - lsb: 5 - reset_value: '0' - width: 1 - - BOD_EN: - access: r - description: A 1 in this bit shows that the BOD event has been enabled - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_EN: - access: r - description: A 1 in this bit shows that the WWDT event has been enabled - lsb: 7 - reset_value: '0' - width: 1 - - ETH_EN: - access: r - description: A 1 in this bit shows that the ETH event has been enabled - lsb: 8 - reset_value: '0' - width: 1 - - USB0_EN: - access: r - description: A 1 in this bit shows that the USB0 event has been enabled - lsb: 9 - reset_value: '0' - width: 1 - - USB1_EN: - access: r - description: A 1 in this bit shows that the USB1 event has been enabled - lsb: 10 - reset_value: '0' - width: 1 - - SDMMC_EN: - access: r - description: A 1 in this bit shows that the SDMMC event has been enabled - lsb: 11 - reset_value: '0' - width: 1 - - CAN_EN: - access: r - description: A 1 in this bit shows that the CAN event has been enabled - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_EN: - access: r - description: A 1 in this bit shows that the combined timer 2 output event - has been enabled - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_EN: - access: r - description: A 1 in this bit shows that the combined timer 6 output event - has been enabled - lsb: 14 - reset_value: '0' - width: 1 - - QEI_EN: - access: r - description: A 1 in this bit shows that the QEI event has been enabled - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_EN: - access: r - description: A 1 in this bit shows that the combined timer 14 output event - has been enabled - lsb: 16 - reset_value: '0' - width: 1 - - RESET_EN: - access: r - description: A 1 in this bit shows that the reset event has been enabled - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_CLR_STAT: - fields: !!omap - - WAKEUP0_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 0 in the - STATUS register - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 1 in the - STATUS register - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 2 in the - STATUS register - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 3 in the - STATUS register - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 4 in the - STATUS register - lsb: 4 - reset_value: '0' - width: 1 - - RTC_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 5 in the - STATUS register - lsb: 5 - reset_value: '0' - width: 1 - - BOD_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 6 in the - STATUS register - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 7 in the - STATUS register - lsb: 7 - reset_value: '0' - width: 1 - - ETH_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 8 in the - STATUS register - lsb: 8 - reset_value: '0' - width: 1 - - USB0_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 9 in the - STATUS register - lsb: 9 - reset_value: '0' - width: 1 - - USB1_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 10 in the - STATUS register - lsb: 10 - reset_value: '0' - width: 1 - - SDMCC_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 11 in the - STATUS register - lsb: 11 - reset_value: '0' - width: 1 - - CAN_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 12 in the - STATUS register - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 13 in the - STATUS register - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 14 in the - STATUS register - lsb: 14 - reset_value: '0' - width: 1 - - QEI_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 15 in the - STATUS register - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 16 in the - STATUS register - lsb: 16 - reset_value: '0' - width: 1 - - RESET_CLRST: - access: w - description: Writing a 1 to this bit clears the STATUS event bit 19 in the - STATUS register - lsb: 19 - reset_value: '0' - width: 1 -- EVENTROUTER_SET_STAT: - fields: !!omap - - WAKEUP0_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS - register - lsb: 0 - reset_value: '0' - width: 1 - - WAKEUP1_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS - register - lsb: 1 - reset_value: '0' - width: 1 - - WAKEUP2_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS - register - lsb: 2 - reset_value: '0' - width: 1 - - WAKEUP3_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS - register - lsb: 3 - reset_value: '0' - width: 1 - - ATIMER_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS - register - lsb: 4 - reset_value: '0' - width: 1 - - RTC_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS - register - lsb: 5 - reset_value: '0' - width: 1 - - BOD_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS - register - lsb: 6 - reset_value: '0' - width: 1 - - WWDT_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS - register - lsb: 7 - reset_value: '0' - width: 1 - - ETH_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS - register - lsb: 8 - reset_value: '0' - width: 1 - - USB0_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS - register - lsb: 9 - reset_value: '0' - width: 1 - - USB1_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS - register - lsb: 10 - reset_value: '0' - width: 1 - - SDMCC_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS - register - lsb: 11 - reset_value: '0' - width: 1 - - CAN_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS - register - lsb: 12 - reset_value: '0' - width: 1 - - TIM2_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS - register - lsb: 13 - reset_value: '0' - width: 1 - - TIM6_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS - register - lsb: 14 - reset_value: '0' - width: 1 - - QEI_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS - register - lsb: 15 - reset_value: '0' - width: 1 - - TIM14_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS - register - lsb: 16 - reset_value: '0' - width: 1 - - RESET_SETST: - access: w - description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS - register - lsb: 19 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/gen.py b/libopencm3/scripts/data/lpc43xx/gen.py deleted file mode 100755 index af253dd..0000000 --- a/libopencm3/scripts/data/lpc43xx/gen.py +++ /dev/null @@ -1,25 +0,0 @@ -#!/usr/bin/env python - -import sys -import yaml - -registers = yaml.load(open(sys.argv[1], 'r')) - -for register_name, register in registers.iteritems(): - print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name)))) - print - fields = register['fields'] - #for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])): - for field_name, field in fields.items(): - mask_bits = (1 << field['width']) - 1 - print('/* %s: %s */' % (field_name, field['description'])) - print('#define %s_%s_SHIFT (%d)' % ( - register_name, field_name, field['lsb'], - )) - print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % ( - register_name, field_name, mask_bits, register_name, field_name, - )) - print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % ( - register_name, field_name, register_name, field_name, - )) - print diff --git a/libopencm3/scripts/data/lpc43xx/gima.yaml b/libopencm3/scripts/data/lpc43xx/gima.yaml deleted file mode 100644 index d34086d..0000000 --- a/libopencm3/scripts/data/lpc43xx/gima.yaml +++ /dev/null @@ -1,961 +0,0 @@ -!!omap -- GIMA_CAP0_0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP0_1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP0_2_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP0_3_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP1_0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP1_1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP1_2_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP1_3_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP2_0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP2_1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP2_2_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP2_3_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP3_0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP3_1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP3_2_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CAP3_3_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_2_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_3_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_4_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_5_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_6_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_CTIN_7_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_VADC_TRIGGER_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_EVENTROUTER_13_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_EVENTROUTER_14_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_EVENTROUTER_16_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_ADCSTART0_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 -- GIMA_ADCSTART1_IN: - fields: !!omap - - INV: - access: rw - description: Invert input - lsb: 0 - reset_value: '0' - width: 1 - - EDGE: - access: rw - description: Enable rising edge detection - lsb: 1 - reset_value: '0' - width: 1 - - SYNCH: - access: rw - description: Enable synchronization - lsb: 2 - reset_value: '0' - width: 1 - - PULSE: - access: rw - description: Enable single pulse generation - lsb: 3 - reset_value: '0' - width: 1 - - SELECT: - access: rw - description: Select input - lsb: 4 - reset_value: '0' - width: 4 diff --git a/libopencm3/scripts/data/lpc43xx/gpdma.yaml b/libopencm3/scripts/data/lpc43xx/gpdma.yaml deleted file mode 100644 index b53ea85..0000000 --- a/libopencm3/scripts/data/lpc43xx/gpdma.yaml +++ /dev/null @@ -1,1498 +0,0 @@ -!!omap -- GPDMA_INTSTAT: - fields: !!omap - - INTSTAT: - access: r - description: Status of DMA channel interrupts after masking - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_INTTCSTAT: - fields: !!omap - - INTTCSTAT: - access: r - description: Terminal count interrupt request status for DMA channels - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_INTTCCLEAR: - fields: !!omap - - INTTCCLEAR: - access: w - description: Allows clearing the Terminal count interrupt request (IntTCStat) - for DMA channels - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_INTERRSTAT: - fields: !!omap - - INTERRSTAT: - access: r - description: Interrupt error status for DMA channels - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_INTERRCLR: - fields: !!omap - - INTERRCLR: - access: w - description: Writing a 1 clears the error interrupt request (IntErrStat) for - DMA channels - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_RAWINTTCSTAT: - fields: !!omap - - RAWINTTCSTAT: - access: r - description: Status of the terminal count interrupt for DMA channels prior - to masking - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_RAWINTERRSTAT: - fields: !!omap - - RAWINTERRSTAT: - access: r - description: Status of the error interrupt for DMA channels prior to masking - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_ENBLDCHNS: - fields: !!omap - - ENABLEDCHANNELS: - access: r - description: Enable status for DMA channels - lsb: 0 - reset_value: '0x00' - width: 8 -- GPDMA_SOFTBREQ: - fields: !!omap - - SOFTBREQ: - access: rw - description: Software burst request flags for each of 16 possible sources - lsb: 0 - reset_value: '0x00' - width: 16 -- GPDMA_SOFTSREQ: - fields: !!omap - - SOFTSREQ: - access: rw - description: Software single transfer request flags for each of 16 possible - sources - lsb: 0 - reset_value: '0x00' - width: 16 -- GPDMA_SOFTLBREQ: - fields: !!omap - - SOFTLBREQ: - access: rw - description: Software last burst request flags for each of 16 possible sources - lsb: 0 - reset_value: '0x00' - width: 16 -- GPDMA_SOFTLSREQ: - fields: !!omap - - SOFTLSREQ: - access: rw - description: Software last single transfer request flags for each of 16 possible - sources - lsb: 0 - reset_value: '0x00' - width: 16 -- GPDMA_CONFIG: - fields: !!omap - - E: - access: rw - description: DMA Controller enable - lsb: 0 - reset_value: '0' - width: 1 - - M0: - access: rw - description: AHB Master 0 endianness configuration - lsb: 1 - reset_value: '0' - width: 1 - - M1: - access: rw - description: AHB Master 1 endianness configuration - lsb: 2 - reset_value: '0' - width: 1 -- GPDMA_SYNC: - fields: !!omap - - DMACSYNC: - access: rw - description: Controls the synchronization logic for DMA request signals - lsb: 0 - reset_value: '0x00' - width: 16 -- GPDMA_C0SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C1SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C2SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C3SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C4SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C5SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C6SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C7SRCADDR: - fields: !!omap - - SRCADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C0DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C1DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C2DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C3DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C4DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C5DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C6DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C7DESTADDR: - fields: !!omap - - DESTADDR: - access: rw - description: DMA source address - lsb: 0 - reset_value: '0x00000000' - width: 32 -- GPDMA_C0LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C1LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C2LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C3LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C4LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C5LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C6LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C7LLI: - fields: !!omap - - LM: - access: rw - description: AHB master select for loading the next LLI - lsb: 0 - reset_value: '0' - width: 1 - - LLI: - access: rw - description: Linked list item - lsb: 2 - reset_value: '0x00000000' - width: 30 -- GPDMA_C0CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C1CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C2CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C3CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C4CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C5CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C6CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C7CONTROL: - fields: !!omap - - TRANSFERSIZE: - access: rw - description: Transfer size in number of transfers - lsb: 0 - reset_value: '0x00' - width: 12 - - SBSIZE: - access: rw - description: Source burst size - lsb: 12 - reset_value: '0x0' - width: 3 - - DBSIZE: - access: rw - description: Destination burst size - lsb: 15 - reset_value: '0x0' - width: 3 - - SWIDTH: - access: rw - description: Source transfer width - lsb: 18 - reset_value: '0x0' - width: 3 - - DWIDTH: - access: rw - description: Destination transfer width - lsb: 21 - reset_value: '0x0' - width: 3 - - S: - access: rw - description: Source AHB master select - lsb: 24 - reset_value: '0' - width: 1 - - D: - access: rw - description: Destination AHB master select - lsb: 25 - reset_value: '0' - width: 1 - - SI: - access: rw - description: Source increment - lsb: 26 - reset_value: '0' - width: 1 - - DI: - access: rw - description: Destination increment - lsb: 27 - reset_value: '0' - width: 1 - - PROT1: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode - lsb: 28 - reset_value: '0' - width: 1 - - PROT2: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable - lsb: 29 - reset_value: '0' - width: 1 - - PROT3: - access: rw - description: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable - lsb: 30 - reset_value: '0' - width: 1 - - I: - access: rw - description: Terminal count interrupt enable bit - lsb: 31 - reset_value: '0' - width: 1 -- GPDMA_C0CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C1CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C2CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C3CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C4CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C5CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C6CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 -- GPDMA_C7CONFIG: - fields: !!omap - - E: - access: rw - description: Channel enable - lsb: 0 - reset_value: '0' - width: 1 - - SRCPERIPHERAL: - access: rw - description: Source peripheral - lsb: 1 - reset_value: '' - width: 5 - - DESTPERIPHERAL: - access: rw - description: Destination peripheral - lsb: 6 - reset_value: '' - width: 5 - - FLOWCNTRL: - access: rw - description: Flow control and transfer type - lsb: 11 - reset_value: '' - width: 3 - - IE: - access: rw - description: Interrupt error mask - lsb: 14 - reset_value: '' - width: 1 - - ITC: - access: rw - description: Terminal count interrupt mask - lsb: 15 - reset_value: '' - width: 1 - - L: - access: rw - description: Lock - lsb: 16 - reset_value: '' - width: 1 - - A: - access: r - description: Active - lsb: 17 - reset_value: '' - width: 1 - - H: - access: rw - description: Halt - lsb: 18 - reset_value: '' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/gpio.yaml b/libopencm3/scripts/data/lpc43xx/gpio.yaml deleted file mode 100644 index b76e37f..0000000 --- a/libopencm3/scripts/data/lpc43xx/gpio.yaml +++ /dev/null @@ -1,4926 +0,0 @@ -!!omap -- GPIO_PIN_INTERRUPT_ISEL: - fields: !!omap - - PMODE: - access: rw - description: Selects the interrupt mode for each pin interrupt - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_PIN_INTERRUPT_IENR: - fields: !!omap - - ENRL: - access: rw - description: Enables the rising edge or level interrupt for each pin interrupt - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_PIN_INTERRUPT_SIENR: - fields: !!omap - - SETENRL: - access: w - description: Ones written to this address set bits in the IENR, thus enabling - interrupts - lsb: 0 - reset_value: '' - width: 8 -- GPIO_PIN_INTERRUPT_CIENR: - fields: !!omap - - CENRL: - access: w - description: Ones written to this address clear bits in the IENR, thus disabling - the interrupts - lsb: 0 - reset_value: '' - width: 8 -- GPIO_PIN_INTERRUPT_IENF: - fields: !!omap - - ENAF: - access: rw - description: Enables the falling edge or configures the active level interrupt - for each pin interrupt - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_PIN_INTERRUPT_SIENF: - fields: !!omap - - SETENAF: - access: w - description: Ones written to this address set bits in the IENF, thus enabling - interrupts - lsb: 0 - reset_value: '' - width: 8 -- GPIO_PIN_INTERRUPT_CIENF: - fields: !!omap - - CENAF: - access: w - description: Ones written to this address clears bits in the IENF, thus disabling - interrupts - lsb: 0 - reset_value: '' - width: 8 -- GPIO_PIN_INTERRUPT_RISE: - fields: !!omap - - RDET: - access: rw - description: Rising edge detect - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_PIN_INTERRUPT_FALL: - fields: !!omap - - FDET: - access: rw - description: Falling edge detect - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_PIN_INTERRUPT_IST: - fields: !!omap - - PSTAT: - access: rw - description: Pin interrupt status - lsb: 0 - reset_value: '0' - width: 8 -- GPIO_GROUP0_INTERRUPT_CTRL: - fields: !!omap - - INT: - access: rw - description: Group interrupt status - lsb: 0 - reset_value: '0' - width: 1 - - COMB: - access: rw - description: Combine enabled inputs for group interrupt - lsb: 1 - reset_value: '0' - width: 1 - - TRIG: - access: rw - description: Group interrupt trigger - lsb: 2 - reset_value: '0' - width: 1 -- GPIO_GROUP0_INTERRUPT_PORT_POL0: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 0 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL1: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 1 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL2: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 2 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL3: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 3 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL4: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 4 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL5: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 5 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL6: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 6 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_POL7: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 7 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA0: - fields: !!omap - - ENA: - access: rw - description: Enable port 0 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA1: - fields: !!omap - - ENA: - access: rw - description: Enable port 1 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA2: - fields: !!omap - - ENA: - access: rw - description: Enable port 2 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA3: - fields: !!omap - - ENA: - access: rw - description: Enable port 3 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA4: - fields: !!omap - - ENA: - access: rw - description: Enable port 4 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA5: - fields: !!omap - - ENA: - access: rw - description: Enable port 5 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA6: - fields: !!omap - - ENA: - access: rw - description: Enable port 6 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP0_INTERRUPT_PORT_ENA7: - fields: !!omap - - ENA: - access: rw - description: Enable port 7 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_CTRL: - fields: !!omap - - INT: - access: rw - description: Group interrupt status - lsb: 0 - reset_value: '0' - width: 1 - - COMB: - access: rw - description: Combine enabled inputs for group interrupt - lsb: 1 - reset_value: '0' - width: 1 - - TRIG: - access: rw - description: Group interrupt trigger - lsb: 2 - reset_value: '0' - width: 1 -- GPIO_GROUP1_INTERRUPT_PORT_POL0: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 0 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL1: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 1 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL2: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 2 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL3: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 3 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL4: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 4 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL5: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 5 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL6: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 6 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_POL7: - fields: !!omap - - POL: - access: rw - description: Configure pin polarity of port 7 pins for group interrupt - lsb: 0 - reset_value: '1' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA0: - fields: !!omap - - ENA: - access: rw - description: Enable port 0 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA1: - fields: !!omap - - ENA: - access: rw - description: Enable port 1 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA2: - fields: !!omap - - ENA: - access: rw - description: Enable port 2 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA3: - fields: !!omap - - ENA: - access: rw - description: Enable port 3 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA4: - fields: !!omap - - ENA: - access: rw - description: Enable port 4 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA5: - fields: !!omap - - ENA: - access: rw - description: Enable port 5 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA6: - fields: !!omap - - ENA: - access: rw - description: Enable port 6 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_GROUP1_INTERRUPT_PORT_ENA7: - fields: !!omap - - ENA: - access: rw - description: Enable port 7 pin for group interrupt - lsb: 0 - reset_value: '0' - width: 32 -- GPIO_B0: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B1: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B2: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B3: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B4: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B5: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B6: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B7: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B8: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B9: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B10: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B11: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B12: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B13: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B14: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B15: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B16: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B17: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B18: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B19: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B20: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B21: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B22: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B23: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B24: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B25: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B26: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B27: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B28: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B29: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B30: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B31: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B32: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B33: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B34: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B35: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B36: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B37: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B38: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B39: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B40: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B41: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B42: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B43: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B44: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B45: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B46: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B47: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B48: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B49: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B50: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B51: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B52: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B53: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B54: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B55: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B56: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B57: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B58: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B59: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B60: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B61: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B62: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B63: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B64: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B65: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B66: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B67: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B68: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B69: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B70: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B71: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B72: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B73: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B74: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B75: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B76: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B77: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B78: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B79: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B80: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B81: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B82: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B83: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B84: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B85: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B86: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B87: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B88: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B89: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B90: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B91: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B92: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B93: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B94: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B95: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B96: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B97: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B98: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B99: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B100: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B101: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B102: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B103: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B104: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B105: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B106: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B107: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B108: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B109: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B110: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B111: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B112: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B113: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B114: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B115: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B116: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B117: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B118: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B119: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B120: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B121: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B122: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B123: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B124: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B125: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B126: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B127: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B128: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B129: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B130: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B131: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B132: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B133: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B134: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B135: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B136: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B137: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B138: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B139: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B140: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B141: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B142: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B143: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B144: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B145: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B146: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B147: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B148: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B149: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B150: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B151: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B152: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B153: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B154: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B155: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B156: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B157: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B158: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B159: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B160: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B161: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B162: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B163: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B164: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B165: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B166: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B167: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B168: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B169: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B170: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B171: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B172: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B173: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B174: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B175: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B176: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B177: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B178: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B179: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B180: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B181: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B182: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B183: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B184: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B185: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B186: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B187: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B188: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B189: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B190: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B191: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B192: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B193: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B194: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B195: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B196: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B197: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B198: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B199: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B200: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B201: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B202: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B203: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B204: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B205: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B206: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B207: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B208: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B209: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B210: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B211: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B212: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B213: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B214: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B215: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B216: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B217: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B218: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B219: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B220: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B221: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B222: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B223: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B224: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B225: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B226: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B227: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B228: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B229: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B230: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B231: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B232: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B233: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B234: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B235: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B236: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B237: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B238: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B239: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B240: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B241: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B242: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B243: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B244: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B245: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B246: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B247: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B248: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B249: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B250: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B251: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B252: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B253: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B254: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_B255: - fields: !!omap - - PBYTE: - access: rw - description: GPIO port byte pin register - lsb: 0 - reset_value: '' - width: 1 -- GPIO_W0: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W1: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W2: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W3: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W4: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W5: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W6: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W7: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W8: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W9: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W10: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W11: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W12: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W13: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W14: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W15: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W16: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W17: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W18: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W19: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W20: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W21: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W22: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W23: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W24: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W25: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W26: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W27: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W28: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W29: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W30: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W31: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W32: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W33: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W34: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W35: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W36: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W37: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W38: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W39: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W40: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W41: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W42: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W43: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W44: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W45: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W46: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W47: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W48: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W49: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W50: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W51: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W52: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W53: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W54: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W55: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W56: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W57: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W58: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W59: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W60: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W61: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W62: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W63: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W64: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W65: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W66: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W67: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W68: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W69: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W70: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W71: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W72: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W73: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W74: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W75: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W76: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W77: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W78: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W79: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W80: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W81: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W82: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W83: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W84: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W85: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W86: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W87: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W88: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W89: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W90: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W91: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W92: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W93: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W94: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W95: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W96: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W97: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W98: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W99: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W100: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W101: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W102: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W103: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W104: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W105: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W106: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W107: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W108: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W109: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W110: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W111: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W112: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W113: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W114: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W115: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W116: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W117: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W118: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W119: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W120: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W121: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W122: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W123: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W124: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W125: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W126: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W127: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W128: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W129: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W130: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W131: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W132: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W133: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W134: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W135: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W136: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W137: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W138: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W139: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W140: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W141: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W142: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W143: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W144: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W145: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W146: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W147: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W148: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W149: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W150: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W151: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W152: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W153: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W154: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W155: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W156: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W157: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W158: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W159: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W160: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W161: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W162: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W163: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W164: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W165: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W166: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W167: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W168: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W169: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W170: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W171: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W172: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W173: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W174: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W175: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W176: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W177: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W178: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W179: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W180: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W181: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W182: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W183: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W184: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W185: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W186: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W187: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W188: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W189: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W190: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W191: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W192: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W193: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W194: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W195: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W196: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W197: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W198: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W199: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W200: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W201: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W202: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W203: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W204: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W205: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W206: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W207: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W208: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W209: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W210: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W211: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W212: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W213: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W214: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W215: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W216: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W217: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W218: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W219: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W220: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W221: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W222: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W223: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W224: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W225: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W226: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W227: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W228: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W229: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W230: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W231: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W232: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W233: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W234: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W235: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W236: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W237: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W238: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W239: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W240: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W241: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W242: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W243: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W244: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W245: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W246: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W247: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W248: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W249: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W250: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W251: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W252: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W253: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W254: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO_W255: - fields: !!omap - - PWORD: - access: rw - description: GPIO port word pin register - lsb: 0 - reset_value: '' - width: 32 -- GPIO0_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO0 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO1_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO1 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO2_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO2 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO3_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO3 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO4_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO4 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO5_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO5 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO6_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO6 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO7_DIR: - fields: !!omap - - DIR: - access: rw - description: Selects pin direction for GPIO7 - lsb: 0 - reset_value: '0' - width: 32 -- GPIO0_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO1_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO2_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO3_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO4_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO5_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO6_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO7_MASK: - fields: !!omap - - MASK: - access: rw - description: Controls which pins are active in the MPORT register - lsb: 0 - reset_value: '0' - width: 32 -- GPIO0_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO1_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO2_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO3_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO4_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO5_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO6_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO7_PIN: - fields: !!omap - - PORT: - access: rw - description: Reads pin states or loads output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO0_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO1_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO2_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO3_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO4_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO5_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO6_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO7_MPIN: - fields: !!omap - - MPORT: - access: rw - description: Masked port register - lsb: 0 - reset_value: '' - width: 32 -- GPIO0_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO1_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO2_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO3_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO4_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO5_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO6_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO7_SET: - fields: !!omap - - SET: - access: rw - description: Read or set output bits - lsb: 0 - reset_value: '0' - width: 32 -- GPIO0_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO1_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO2_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO3_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO4_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO5_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO6_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO7_CLR: - fields: !!omap - - CLR: - access: w - description: Clear output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO0_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO1_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO2_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO3_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO4_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO5_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO6_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 -- GPIO7_NOT: - fields: !!omap - - NOT: - access: w - description: Toggle output bits - lsb: 0 - reset_value: '' - width: 32 diff --git a/libopencm3/scripts/data/lpc43xx/i2c.yaml b/libopencm3/scripts/data/lpc43xx/i2c.yaml deleted file mode 100644 index 0e59a6a..0000000 --- a/libopencm3/scripts/data/lpc43xx/i2c.yaml +++ /dev/null @@ -1,415 +0,0 @@ -!!omap -- I2C0_CONSET: - fields: !!omap - - AA: - access: rw - description: Assert acknowledge flag - lsb: 2 - reset_value: '0' - width: 1 - - SI: - access: rw - description: I2C interrupt flag - lsb: 3 - reset_value: '0' - width: 1 - - STO: - access: rw - description: STOP flag - lsb: 4 - reset_value: '0' - width: 1 - - STA: - access: rw - description: START flag - lsb: 5 - reset_value: '0' - width: 1 - - I2EN: - access: rw - description: I2C interface enable - lsb: 6 - reset_value: '0' - width: 1 -- I2C1_CONSET: - fields: !!omap - - AA: - access: rw - description: Assert acknowledge flag - lsb: 2 - reset_value: '0' - width: 1 - - SI: - access: rw - description: I2C interrupt flag - lsb: 3 - reset_value: '0' - width: 1 - - STO: - access: rw - description: STOP flag - lsb: 4 - reset_value: '0' - width: 1 - - STA: - access: rw - description: START flag - lsb: 5 - reset_value: '0' - width: 1 - - I2EN: - access: rw - description: I2C interface enable - lsb: 6 - reset_value: '0' - width: 1 -- I2C0_STAT: - fields: !!omap - - STATUS: - access: r - description: These bits give the actual status information about the I2C interface - lsb: 3 - reset_value: '0x1f' - width: 5 -- I2C1_STAT: - fields: !!omap - - STATUS: - access: r - description: These bits give the actual status information about the I2C interface - lsb: 3 - reset_value: '0x1f' - width: 5 -- I2C0_DAT: - fields: !!omap - - DATA: - access: rw - description: This register holds data values that have been received or are - to be transmitted - lsb: 0 - reset_value: '0' - width: 8 -- I2C1_DAT: - fields: !!omap - - DATA: - access: rw - description: This register holds data values that have been received or are - to be transmitted - lsb: 0 - reset_value: '0' - width: 8 -- I2C0_ADR0: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_ADR0: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_SCLH: - fields: !!omap - - SCLH: - access: rw - description: Count for SCL HIGH time period selection - lsb: 0 - reset_value: '0x0004' - width: 16 -- I2C1_SCLH: - fields: !!omap - - SCLH: - access: rw - description: Count for SCL HIGH time period selection - lsb: 0 - reset_value: '0x0004' - width: 16 -- I2C0_SCLL: - fields: !!omap - - SCLL: - access: rw - description: Count for SCL LOW time period selection - lsb: 0 - reset_value: '0x0004' - width: 16 -- I2C1_SCLL: - fields: !!omap - - SCLL: - access: rw - description: Count for SCL LOW time period selection - lsb: 0 - reset_value: '0x0004' - width: 16 -- I2C0_CONCLR: - fields: !!omap - - AAC: - access: w - description: Assert acknowledge Clear bit - lsb: 2 - reset_value: '0' - width: 1 - - SIC: - access: w - description: I2C interrupt Clear bit - lsb: 3 - reset_value: '0' - width: 1 - - STAC: - access: w - description: START flag Clear bit - lsb: 5 - reset_value: '0' - width: 1 - - I2ENC: - access: w - description: I2C interface Disable bit - lsb: 6 - reset_value: '0' - width: 1 -- I2C1_CONCLR: - fields: !!omap - - AAC: - access: w - description: Assert acknowledge Clear bit - lsb: 2 - reset_value: '0' - width: 1 - - SIC: - access: w - description: I2C interrupt Clear bit - lsb: 3 - reset_value: '0' - width: 1 - - STAC: - access: w - description: START flag Clear bit - lsb: 5 - reset_value: '0' - width: 1 - - I2ENC: - access: w - description: I2C interface Disable bit - lsb: 6 - reset_value: '0' - width: 1 -- I2C0_MMCTRL: - fields: !!omap - - MM_ENA: - access: rw - description: Monitor mode enable - lsb: 0 - reset_value: '0' - width: 1 - - ENA_SCL: - access: rw - description: SCL output enable - lsb: 1 - reset_value: '0' - width: 1 - - MATCH_ALL: - access: rw - description: Select interrupt register match - lsb: 2 - reset_value: '0' - width: 1 -- I2C1_MMCTRL: - fields: !!omap - - MM_ENA: - access: rw - description: Monitor mode enable - lsb: 0 - reset_value: '0' - width: 1 - - ENA_SCL: - access: rw - description: SCL output enable - lsb: 1 - reset_value: '0' - width: 1 - - MATCH_ALL: - access: rw - description: Select interrupt register match - lsb: 2 - reset_value: '0' - width: 1 -- I2C0_ADR1: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_ADR1: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_ADR2: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_ADR2: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_ADR3: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_ADR3: - fields: !!omap - - GC: - access: rw - description: General Call enable bit - lsb: 0 - reset_value: '0' - width: 1 - - ADDRESS: - access: rw - description: The I2C device address for slave mode - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_DATA_BUFFER: - fields: !!omap - - DATA: - access: r - description: This register holds contents of the 8 MSBs of the DAT shift register - lsb: 0 - reset_value: '0' - width: 8 -- I2C1_DATA_BUFFER: - fields: !!omap - - DATA: - access: r - description: This register holds contents of the 8 MSBs of the DAT shift register - lsb: 0 - reset_value: '0' - width: 8 -- I2C0_MASK0: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_MASK0: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_MASK1: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_MASK1: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_MASK2: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_MASK2: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C0_MASK3: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 -- I2C1_MASK3: - fields: !!omap - - MASK: - access: rw - description: Mask bits - lsb: 1 - reset_value: '0' - width: 7 diff --git a/libopencm3/scripts/data/lpc43xx/i2s.yaml b/libopencm3/scripts/data/lpc43xx/i2s.yaml deleted file mode 100644 index 833e5b5..0000000 --- a/libopencm3/scripts/data/lpc43xx/i2s.yaml +++ /dev/null @@ -1,619 +0,0 @@ -!!omap -- I2S0_DAO: - fields: !!omap - - WORDWIDTH: - access: rw - description: Selects the number of bytes in data - lsb: 0 - reset_value: '1' - width: 2 - - MONO: - access: rw - description: When 1, data is of monaural format. When 0, the data is in stereo - format - lsb: 2 - reset_value: '0' - width: 1 - - STOP: - access: rw - description: When 1, disables accesses on FIFOs, places the transmit channel - in mute mode - lsb: 3 - reset_value: '0' - width: 1 - - RESET: - access: rw - description: When 1, asynchronously resets the transmit channel and FIFO - lsb: 4 - reset_value: '0' - width: 1 - - WS_SEL: - access: rw - description: When 0, the interface is in master mode. When 1, the interface - is in slave mode - lsb: 5 - reset_value: '1' - width: 1 - - WS_HALFPERIOD: - access: rw - description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod - = 31. - lsb: 6 - reset_value: '0x1f' - width: 9 - - MUTE: - access: rw - description: When 1, the transmit channel sends only zeroes - lsb: 15 - reset_value: '1' - width: 1 -- I2S1_DAO: - fields: !!omap - - WORDWIDTH: - access: rw - description: Selects the number of bytes in data - lsb: 0 - reset_value: '1' - width: 2 - - MONO: - access: rw - description: When 1, data is of monaural format. When 0, the data is in stereo - format - lsb: 2 - reset_value: '0' - width: 1 - - STOP: - access: rw - description: When 1, disables accesses on FIFOs, places the transmit channel - in mute mode - lsb: 3 - reset_value: '0' - width: 1 - - RESET: - access: rw - description: When 1, asynchronously resets the transmit channel and FIFO - lsb: 4 - reset_value: '0' - width: 1 - - WS_SEL: - access: rw - description: When 0, the interface is in master mode. When 1, the interface - is in slave mode - lsb: 5 - reset_value: '1' - width: 1 - - WS_HALFPERIOD: - access: rw - description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod - = 31. - lsb: 6 - reset_value: '0x1f' - width: 9 - - MUTE: - access: rw - description: When 1, the transmit channel sends only zeroes - lsb: 15 - reset_value: '1' - width: 1 -- I2S0_DAI: - fields: !!omap - - WORDWIDTH: - access: rw - description: Selects the number of bytes in data - lsb: 0 - reset_value: '1' - width: 2 - - MONO: - access: rw - description: When 1, data is of monaural format. When 0, the data is in stereo - format - lsb: 2 - reset_value: '0' - width: 1 - - STOP: - access: rw - description: When 1, disables accesses on FIFOs, places the transmit channel - in mute mode - lsb: 3 - reset_value: '0' - width: 1 - - RESET: - access: rw - description: When 1, asynchronously resets the transmit channel and FIFO - lsb: 4 - reset_value: '0' - width: 1 - - WS_SEL: - access: rw - description: When 0, the interface is in master mode. When 1, the interface - is in slave mode - lsb: 5 - reset_value: '1' - width: 1 - - WS_HALFPERIOD: - access: rw - description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod - = 31. - lsb: 6 - reset_value: '0x1f' - width: 9 - - MUTE: - access: rw - description: When 1, the transmit channel sends only zeroes - lsb: 15 - reset_value: '1' - width: 1 -- I2S1_DAI: - fields: !!omap - - WORDWIDTH: - access: rw - description: Selects the number of bytes in data - lsb: 0 - reset_value: '1' - width: 2 - - MONO: - access: rw - description: When 1, data is of monaural format. When 0, the data is in stereo - format - lsb: 2 - reset_value: '0' - width: 1 - - STOP: - access: rw - description: When 1, disables accesses on FIFOs, places the transmit channel - in mute mode - lsb: 3 - reset_value: '0' - width: 1 - - RESET: - access: rw - description: When 1, asynchronously resets the transmit channel and FIFO - lsb: 4 - reset_value: '0' - width: 1 - - WS_SEL: - access: rw - description: When 0, the interface is in master mode. When 1, the interface - is in slave mode - lsb: 5 - reset_value: '1' - width: 1 - - WS_HALFPERIOD: - access: rw - description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod - = 31. - lsb: 6 - reset_value: '0x1f' - width: 9 - - MUTE: - access: rw - description: When 1, the transmit channel sends only zeroes - lsb: 15 - reset_value: '1' - width: 1 -- I2S0_TXFIFO: - fields: !!omap - - I2STXFIFO: - access: w - description: 8 x 32-bit transmit FIFO - lsb: 0 - reset_value: '0' - width: 32 -- I2S1_TXFIFO: - fields: !!omap - - I2STXFIFO: - access: w - description: 8 x 32-bit transmit FIFO - lsb: 0 - reset_value: '0' - width: 32 -- I2S0_RXFIFO: - fields: !!omap - - I2SRXFIFO: - access: r - description: 8 x 32-bit receive FIFO - lsb: 0 - reset_value: '0' - width: 32 -- I2S1_RXFIFO: - fields: !!omap - - I2SRXFIFO: - access: r - description: 8 x 32-bit receive FIFO - lsb: 0 - reset_value: '0' - width: 32 -- I2S0_STATE: - fields: !!omap - - IRQ: - access: r - description: This bit reflects the presence of Receive Interrupt or Transmit - Interrupt - lsb: 0 - reset_value: '1' - width: 1 - - DMAREQ1: - access: r - description: This bit reflects the presence of Receive or Transmit DMA Request - 1 - lsb: 1 - reset_value: '1' - width: 1 - - DMAREQ2: - access: r - description: This bit reflects the presence of Receive or Transmit DMA Request - 2 - lsb: 2 - reset_value: '1' - width: 1 - - RX_LEVEL: - access: r - description: Reflects the current level of the Receive FIFO - lsb: 8 - reset_value: '0' - width: 4 - - TX_LEVEL: - access: r - description: Reflects the current level of the Transmit FIFO - lsb: 16 - reset_value: '0' - width: 4 -- I2S1_STATE: - fields: !!omap - - IRQ: - access: r - description: This bit reflects the presence of Receive Interrupt or Transmit - Interrupt - lsb: 0 - reset_value: '1' - width: 1 - - DMAREQ1: - access: r - description: This bit reflects the presence of Receive or Transmit DMA Request - 1 - lsb: 1 - reset_value: '1' - width: 1 - - DMAREQ2: - access: r - description: This bit reflects the presence of Receive or Transmit DMA Request - 2 - lsb: 2 - reset_value: '1' - width: 1 - - RX_LEVEL: - access: r - description: Reflects the current level of the Receive FIFO - lsb: 8 - reset_value: '0' - width: 4 - - TX_LEVEL: - access: r - description: Reflects the current level of the Transmit FIFO - lsb: 16 - reset_value: '0' - width: 4 -- I2S0_DMA1: - fields: !!omap - - RX_DMA1_ENABLE: - access: rw - description: When 1, enables DMA1 for I2S receive - lsb: 0 - reset_value: '0' - width: 1 - - TX_DMA1_ENABLE: - access: rw - description: When 1, enables DMA1 for I2S transmit - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_DMA1: - access: rw - description: Set the FIFO level that triggers a receive DMA request on DMA1 - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_DMA1: - access: rw - description: Set the FIFO level that triggers a transmit DMA request on DMA1 - lsb: 16 - reset_value: '0' - width: 4 -- I2S1_DMA1: - fields: !!omap - - RX_DMA1_ENABLE: - access: rw - description: When 1, enables DMA1 for I2S receive - lsb: 0 - reset_value: '0' - width: 1 - - TX_DMA1_ENABLE: - access: rw - description: When 1, enables DMA1 for I2S transmit - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_DMA1: - access: rw - description: Set the FIFO level that triggers a receive DMA request on DMA1 - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_DMA1: - access: rw - description: Set the FIFO level that triggers a transmit DMA request on DMA1 - lsb: 16 - reset_value: '0' - width: 4 -- I2S0_DMA2: - fields: !!omap - - RX_DMA2_ENABLE: - access: rw - description: When 1, enables DMA2 for I2S receive - lsb: 0 - reset_value: '0' - width: 1 - - TX_DMA2_ENABLE: - access: rw - description: When 1, enables DMA2 for I2S transmit - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_DMA2: - access: rw - description: Set the FIFO level that triggers a receive DMA request on DMA2 - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_DMA2: - access: rw - description: Set the FIFO level that triggers a transmit DMA request on DMA2 - lsb: 16 - reset_value: '0' - width: 4 -- I2S1_DMA2: - fields: !!omap - - RX_DMA2_ENABLE: - access: rw - description: When 1, enables DMA2 for I2S receive - lsb: 0 - reset_value: '0' - width: 1 - - TX_DMA2_ENABLE: - access: rw - description: When 1, enables DMA2 for I2S transmit - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_DMA2: - access: rw - description: Set the FIFO level that triggers a receive DMA request on DMA2 - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_DMA2: - access: rw - description: Set the FIFO level that triggers a transmit DMA request on DMA2 - lsb: 16 - reset_value: '0' - width: 4 -- I2S0_IRQ: - fields: !!omap - - RX_IRQ_ENABLE: - access: rw - description: When 1, enables I2S receive interrupt - lsb: 0 - reset_value: '0' - width: 1 - - TX_IRQ_ENABLE: - access: rw - description: When 1, enables I2S transmit interrupt - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_IRQ: - access: rw - description: Set the FIFO level on which to create an irq request. - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_IRQ: - access: rw - description: Set the FIFO level on which to create an irq request. - lsb: 16 - reset_value: '0' - width: 4 -- I2S1_IRQ: - fields: !!omap - - RX_IRQ_ENABLE: - access: rw - description: When 1, enables I2S receive interrupt - lsb: 0 - reset_value: '0' - width: 1 - - TX_IRQ_ENABLE: - access: rw - description: When 1, enables I2S transmit interrupt - lsb: 1 - reset_value: '0' - width: 1 - - RX_DEPTH_IRQ: - access: rw - description: Set the FIFO level on which to create an irq request. - lsb: 8 - reset_value: '0' - width: 4 - - TX_DEPTH_IRQ: - access: rw - description: Set the FIFO level on which to create an irq request. - lsb: 16 - reset_value: '0' - width: 4 -- I2S0_TXRATE: - fields: !!omap - - Y_DIVIDER: - access: rw - description: I2S transmit MCLK rate denominator - lsb: 0 - reset_value: '0' - width: 8 - - X_DIVIDER: - access: rw - description: I2S transmit MCLK rate numerator - lsb: 8 - reset_value: '0' - width: 8 -- I2S1_TXRATE: - fields: !!omap - - Y_DIVIDER: - access: rw - description: I2S transmit MCLK rate denominator - lsb: 0 - reset_value: '0' - width: 8 - - X_DIVIDER: - access: rw - description: I2S transmit MCLK rate numerator - lsb: 8 - reset_value: '0' - width: 8 -- I2S0_RXRATE: - fields: !!omap - - Y_DIVIDER: - access: rw - description: I2S receive MCLK rate denominator - lsb: 0 - reset_value: '0' - width: 8 - - X_DIVIDER: - access: rw - description: I2S receive MCLK rate numerator - lsb: 8 - reset_value: '0' - width: 8 -- I2S1_RXRATE: - fields: !!omap - - Y_DIVIDER: - access: rw - description: I2S receive MCLK rate denominator - lsb: 0 - reset_value: '0' - width: 8 - - X_DIVIDER: - access: rw - description: I2S receive MCLK rate numerator - lsb: 8 - reset_value: '0' - width: 8 -- I2S0_TXBITRATE: - fields: !!omap - - TX_BITRATE: - access: rw - description: I2S transmit bit rate - lsb: 0 - reset_value: '0' - width: 6 -- I2S1_TXBITRATE: - fields: !!omap - - TX_BITRATE: - access: rw - description: I2S transmit bit rate - lsb: 0 - reset_value: '0' - width: 6 -- I2S0_RXBITRATE: - fields: !!omap - - RX_BITRATE: - access: rw - description: I2S receive bit rate - lsb: 0 - reset_value: '0' - width: 6 -- I2S1_RXBITRATE: - fields: !!omap - - RX_BITRATE: - access: rw - description: I2S receive bit rate - lsb: 0 - reset_value: '0' - width: 6 -- I2S0_TXMODE: - fields: !!omap - - TXCLKSEL: - access: rw - description: Clock source selection for the transmit bit clock divider - lsb: 0 - reset_value: '0' - width: 2 - - TX4PIN: - access: rw - description: Transmit 4-pin mode selection - lsb: 2 - reset_value: '0' - width: 1 - - TXMCENA: - access: rw - description: Enable for the TX_MCLK output - lsb: 3 - reset_value: '0' - width: 1 -- I2S1_TXMODE: - fields: !!omap - - TXCLKSEL: - access: rw - description: Clock source selection for the transmit bit clock divider - lsb: 0 - reset_value: '0' - width: 2 - - TX4PIN: - access: rw - description: Transmit 4-pin mode selection - lsb: 2 - reset_value: '0' - width: 1 - - TXMCENA: - access: rw - description: Enable for the TX_MCLK output - lsb: 3 - reset_value: '0' - width: 1 -- I2S0_RXMODE: - fields: !!omap - - RXCLKSEL: - access: rw - description: Clock source selection for the receive bit clock divider - lsb: 0 - reset_value: '0' - width: 2 - - RX4PIN: - access: rw - description: Receive 4-pin mode selection - lsb: 2 - reset_value: '0' - width: 1 - - RXMCENA: - access: rw - description: Enable for the RX_MCLK output - lsb: 3 - reset_value: '0' - width: 1 -- I2S1_RXMODE: - fields: !!omap - - RXCLKSEL: - access: rw - description: Clock source selection for the receive bit clock divider - lsb: 0 - reset_value: '0' - width: 2 - - RX4PIN: - access: rw - description: Receive 4-pin mode selection - lsb: 2 - reset_value: '0' - width: 1 - - RXMCENA: - access: rw - description: Enable for the RX_MCLK output - lsb: 3 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/rgu.yaml b/libopencm3/scripts/data/lpc43xx/rgu.yaml deleted file mode 100644 index 6561d32..0000000 --- a/libopencm3/scripts/data/lpc43xx/rgu.yaml +++ /dev/null @@ -1,1199 +0,0 @@ -!!omap -- RESET_CTRL0: - fields: !!omap - - CORE_RST: - access: w - description: Writing a one activates the reset - lsb: 0 - reset_value: '0' - width: 1 - - PERIPH_RST: - access: w - description: Writing a one activates the reset - lsb: 1 - reset_value: '0' - width: 1 - - MASTER_RST: - access: w - description: Writing a one activates the reset - lsb: 2 - reset_value: '0' - width: 1 - - WWDT_RST: - access: '' - description: Writing a one to this bit has no effect - lsb: 4 - reset_value: '0' - width: 1 - - CREG_RST: - access: '' - description: Writing a one to this bit has no effect - lsb: 5 - reset_value: '0' - width: 1 - - BUS_RST: - access: w - description: Writing a one activates the reset - lsb: 8 - reset_value: '0' - width: 1 - - SCU_RST: - access: w - description: Writing a one activates the reset - lsb: 9 - reset_value: '0' - width: 1 - - M4_RST: - access: w - description: Writing a one activates the reset - lsb: 13 - reset_value: '0' - width: 1 - - LCD_RST: - access: w - description: Writing a one activates the reset - lsb: 16 - reset_value: '0' - width: 1 - - USB0_RST: - access: w - description: Writing a one activates the reset - lsb: 17 - reset_value: '0' - width: 1 - - USB1_RST: - access: w - description: Writing a one activates the reset - lsb: 18 - reset_value: '0' - width: 1 - - DMA_RST: - access: w - description: Writing a one activates the reset - lsb: 19 - reset_value: '0' - width: 1 - - SDIO_RST: - access: w - description: Writing a one activates the reset - lsb: 20 - reset_value: '0' - width: 1 - - EMC_RST: - access: w - description: Writing a one activates the reset - lsb: 21 - reset_value: '0' - width: 1 - - ETHERNET_RST: - access: w - description: Writing a one activates the reset - lsb: 22 - reset_value: '0' - width: 1 - - FLASHA_RST: - access: w - description: Writing a one activates the reset - lsb: 25 - reset_value: '0' - width: 1 - - EEPROM_RST: - access: w - description: Writing a one activates the reset - lsb: 27 - reset_value: '0' - width: 1 - - GPIO_RST: - access: w - description: Writing a one activates the reset - lsb: 28 - reset_value: '0' - width: 1 - - FLASHB_RST: - access: w - description: Writing a one activates the reset - lsb: 29 - reset_value: '0' - width: 1 -- RESET_CTRL1: - fields: !!omap - - TIMER0_RST: - access: w - description: Writing a one activates the reset - lsb: 0 - reset_value: '0' - width: 1 - - TIMER1_RST: - access: w - description: Writing a one activates the reset - lsb: 1 - reset_value: '0' - width: 1 - - TIMER2_RST: - access: w - description: Writing a one activates the reset - lsb: 2 - reset_value: '0' - width: 1 - - TIMER3_RST: - access: w - description: Writing a one activates the reset - lsb: 3 - reset_value: '0' - width: 1 - - RTIMER_RST: - access: w - description: Writing a one activates the reset - lsb: 4 - reset_value: '0' - width: 1 - - SCT_RST: - access: w - description: Writing a one activates the reset - lsb: 5 - reset_value: '0' - width: 1 - - MOTOCONPWM_RST: - access: w - description: Writing a one activates the reset - lsb: 6 - reset_value: '0' - width: 1 - - QEI_RST: - access: w - description: Writing a one activates the reset - lsb: 7 - reset_value: '0' - width: 1 - - ADC0_RST: - access: w - description: Writing a one activates the reset - lsb: 8 - reset_value: '0' - width: 1 - - ADC1_RST: - access: w - description: Writing a one activates the reset - lsb: 9 - reset_value: '0' - width: 1 - - DAC_RST: - access: w - description: Writing a one activates the reset - lsb: 10 - reset_value: '0' - width: 1 - - UART0_RST: - access: w - description: Writing a one activates the reset - lsb: 12 - reset_value: '0' - width: 1 - - UART1_RST: - access: w - description: Writing a one activates the reset - lsb: 13 - reset_value: '0' - width: 1 - - UART2_RST: - access: w - description: Writing a one activates the reset - lsb: 14 - reset_value: '0' - width: 1 - - UART3_RST: - access: w - description: Writing a one activates the reset - lsb: 15 - reset_value: '0' - width: 1 - - I2C0_RST: - access: w - description: Writing a one activates the reset - lsb: 16 - reset_value: '0' - width: 1 - - I2C1_RST: - access: w - description: Writing a one activates the reset - lsb: 17 - reset_value: '0' - width: 1 - - SSP0_RST: - access: w - description: Writing a one activates the reset - lsb: 18 - reset_value: '0' - width: 1 - - SSP1_RST: - access: w - description: Writing a one activates the reset - lsb: 19 - reset_value: '0' - width: 1 - - I2S_RST: - access: w - description: Writing a one activates the reset - lsb: 20 - reset_value: '0' - width: 1 - - SPIFI_RST: - access: w - description: Writing a one activates the reset - lsb: 21 - reset_value: '0' - width: 1 - - CAN1_RST: - access: w - description: Writing a one activates the reset - lsb: 22 - reset_value: '0' - width: 1 - - CAN0_RST: - access: w - description: Writing a one activates the reset - lsb: 23 - reset_value: '0' - width: 1 - - M0APP_RST: - access: w - description: Writing a one activates the reset - lsb: 24 - reset_value: '1' - width: 1 - - SGPIO_RST: - access: w - description: Writing a one activates the reset - lsb: 25 - reset_value: '0' - width: 1 - - SPI_RST: - access: w - description: Writing a one activates the reset - lsb: 26 - reset_value: '0' - width: 1 -- RESET_STATUS0: - fields: !!omap - - CORE_RST: - access: rw - description: Status of the CORE_RST reset generator output - lsb: 0 - reset_value: '0x0' - width: 2 - - PERIPH_RST: - access: rw - description: Status of the PERIPH_RST reset generator output - lsb: 2 - reset_value: '0x0' - width: 2 - - MASTER_RST: - access: rw - description: Status of the MASTER_RST reset generator output - lsb: 4 - reset_value: '0x1' - width: 2 - - WWDT_RST: - access: rw - description: Status of the WWDT_RST reset generator output - lsb: 8 - reset_value: '0x0' - width: 2 - - CREG_RST: - access: rw - description: Status of the CREG_RST reset generator output - lsb: 10 - reset_value: '0x0' - width: 2 - - BUS_RST: - access: rw - description: Status of the BUS_RST reset generator output - lsb: 16 - reset_value: '0x1' - width: 2 - - SCU_RST: - access: rw - description: Status of the SCU_RST reset generator output - lsb: 18 - reset_value: '0x1' - width: 2 - - M4_RST: - access: rw - description: Status of the M4_RST reset generator output - lsb: 26 - reset_value: '0x1' - width: 2 -- RESET_STATUS1: - fields: !!omap - - LCD_RST: - access: rw - description: Status of the LCD_RST reset generator output - lsb: 0 - reset_value: '0x1' - width: 2 - - USB0_RST: - access: rw - description: Status of the USB0_RST reset generator output - lsb: 2 - reset_value: '0x1' - width: 2 - - USB1_RST: - access: rw - description: Status of the USB1_RST reset generator output - lsb: 4 - reset_value: '0x1' - width: 2 - - DMA_RST: - access: rw - description: Status of the DMA_RST reset generator output - lsb: 6 - reset_value: '0x1' - width: 2 - - SDIO_RST: - access: rw - description: Status of the SDIO_RST reset generator output - lsb: 8 - reset_value: '0x1' - width: 2 - - EMC_RST: - access: rw - description: Status of the EMC_RST reset generator output - lsb: 10 - reset_value: '0x1' - width: 2 - - ETHERNET_RST: - access: rw - description: Status of the ETHERNET_RST reset generator output - lsb: 12 - reset_value: '0x1' - width: 2 - - FLASHA_RST: - access: '' - description: Status of the FLASHA_RST reset generator output - lsb: 18 - reset_value: '0x1' - width: 2 - - EEPROM_RST: - access: '' - description: Status of the EEPROM_RST reset generator output - lsb: 22 - reset_value: '0x1' - width: 2 - - GPIO_RST: - access: rw - description: Status of the GPIO_RST reset generator output - lsb: 24 - reset_value: '0x1' - width: 2 - - FLASHB_RST: - access: rw - description: Status of the FLASHB_RST reset generator output - lsb: 26 - reset_value: '0x1' - width: 2 -- RESET_STATUS2: - fields: !!omap - - TIMER0_RST: - access: rw - description: Status of the TIMER0_RST reset generator output - lsb: 0 - reset_value: '0x1' - width: 2 - - TIMER1_RST: - access: rw - description: Status of the TIMER1_RST reset generator output - lsb: 2 - reset_value: '0x1' - width: 2 - - TIMER2_RST: - access: rw - description: Status of the TIMER2_RST reset generator output - lsb: 4 - reset_value: '0x1' - width: 2 - - TIMER3_RST: - access: rw - description: Status of the TIMER3_RST reset generator output - lsb: 6 - reset_value: '0x1' - width: 2 - - RITIMER_RST: - access: rw - description: Status of the RITIMER_RST reset generator output - lsb: 8 - reset_value: '0x1' - width: 2 - - SCT_RST: - access: rw - description: Status of the SCT_RST reset generator output - lsb: 10 - reset_value: '0x1' - width: 2 - - MOTOCONPWM_RST: - access: rw - description: Status of the MOTOCONPWM_RST reset generator output - lsb: 12 - reset_value: '0x1' - width: 2 - - QEI_RST: - access: rw - description: Status of the QEI_RST reset generator output - lsb: 14 - reset_value: '0x1' - width: 2 - - ADC0_RST: - access: rw - description: Status of the ADC0_RST reset generator output - lsb: 16 - reset_value: '0x1' - width: 2 - - ADC1_RST: - access: rw - description: Status of the ADC1_RST reset generator output - lsb: 18 - reset_value: '0x1' - width: 2 - - DAC_RST: - access: rw - description: Status of the DAC_RST reset generator output - lsb: 20 - reset_value: '0x1' - width: 2 - - UART0_RST: - access: rw - description: Status of the UART0_RST reset generator output - lsb: 24 - reset_value: '0x1' - width: 2 - - UART1_RST: - access: rw - description: Status of the UART1_RST reset generator output - lsb: 26 - reset_value: '0x1' - width: 2 - - UART2_RST: - access: rw - description: Status of the UART2_RST reset generator output - lsb: 28 - reset_value: '0x1' - width: 2 - - UART3_RST: - access: rw - description: Status of the UART3_RST reset generator output - lsb: 30 - reset_value: '0x1' - width: 2 -- RESET_STATUS3: - fields: !!omap - - I2C0_RST: - access: rw - description: Status of the I2C0_RST reset generator output - lsb: 0 - reset_value: '0x1' - width: 2 - - I2C1_RST: - access: rw - description: Status of the I2C1_RST reset generator output - lsb: 2 - reset_value: '0x1' - width: 2 - - SSP0_RST: - access: rw - description: Status of the SSP0_RST reset generator output - lsb: 4 - reset_value: '0x1' - width: 2 - - SSP1_RST: - access: rw - description: Status of the SSP1_RST reset generator output - lsb: 6 - reset_value: '0x1' - width: 2 - - I2S_RST: - access: rw - description: Status of the I2S_RST reset generator output - lsb: 8 - reset_value: '0x1' - width: 2 - - SPIFI_RST: - access: rw - description: Status of the SPIFI_RST reset generator output - lsb: 10 - reset_value: '0x1' - width: 2 - - CAN1_RST: - access: rw - description: Status of the CAN1_RST reset generator output - lsb: 12 - reset_value: '0x1' - width: 2 - - CAN0_RST: - access: rw - description: Status of the CAN0_RST reset generator output - lsb: 14 - reset_value: '0x1' - width: 2 - - M0APP_RST: - access: rw - description: Status of the M0APP_RST reset generator output - lsb: 16 - reset_value: '0x3' - width: 2 - - SGPIO_RST: - access: rw - description: Status of the SGPIO_RST reset generator output - lsb: 18 - reset_value: '0x1' - width: 2 - - SPI_RST: - access: rw - description: Status of the SPI_RST reset generator output - lsb: 20 - reset_value: '0x1' - width: 2 -- RESET_ACTIVE_STATUS0: - fields: !!omap - - CORE_RST: - access: r - description: Current status of the CORE_RST - lsb: 0 - reset_value: '0' - width: 1 - - PERIPH_RST: - access: r - description: Current status of the PERIPH_RST - lsb: 1 - reset_value: '0' - width: 1 - - MASTER_RST: - access: r - description: Current status of the MASTER_RST - lsb: 2 - reset_value: '0' - width: 1 - - WWDT_RST: - access: r - description: Current status of the WWDT_RST - lsb: 4 - reset_value: '0' - width: 1 - - CREG_RST: - access: r - description: Current status of the CREG_RST - lsb: 5 - reset_value: '0' - width: 1 - - BUS_RST: - access: r - description: Current status of the BUS_RST - lsb: 8 - reset_value: '0' - width: 1 - - SCU_RST: - access: r - description: Current status of the SCU_RST - lsb: 9 - reset_value: '0' - width: 1 - - M4_RST: - access: r - description: Current status of the M4_RST - lsb: 13 - reset_value: '0' - width: 1 - - LCD_RST: - access: r - description: Current status of the LCD_RST - lsb: 16 - reset_value: '0' - width: 1 - - USB0_RST: - access: r - description: Current status of the USB0_RST - lsb: 17 - reset_value: '0' - width: 1 - - USB1_RST: - access: r - description: Current status of the USB1_RST - lsb: 18 - reset_value: '0' - width: 1 - - DMA_RST: - access: r - description: Current status of the DMA_RST - lsb: 19 - reset_value: '0' - width: 1 - - SDIO_RST: - access: r - description: Current status of the SDIO_RST - lsb: 20 - reset_value: '0' - width: 1 - - EMC_RST: - access: r - description: Current status of the EMC_RST - lsb: 21 - reset_value: '0' - width: 1 - - ETHERNET_RST: - access: r - description: Current status of the ETHERNET_RST - lsb: 22 - reset_value: '0' - width: 1 - - FLASHA_RST: - access: r - description: Current status of the FLASHA_RST - lsb: 25 - reset_value: '0' - width: 1 - - EEPROM_RST: - access: r - description: Current status of the EEPROM_RST - lsb: 27 - reset_value: '0' - width: 1 - - GPIO_RST: - access: r - description: Current status of the GPIO_RST - lsb: 28 - reset_value: '0' - width: 1 - - FLASHB_RST: - access: r - description: Current status of the FLASHB_RST - lsb: 29 - reset_value: '0' - width: 1 -- RESET_ACTIVE_STATUS1: - fields: !!omap - - TIMER0_RST: - access: r - description: Current status of the TIMER0_RST - lsb: 0 - reset_value: '0' - width: 1 - - TIMER1_RST: - access: r - description: Current status of the TIMER1_RST - lsb: 1 - reset_value: '0' - width: 1 - - TIMER2_RST: - access: r - description: Current status of the TIMER2_RST - lsb: 2 - reset_value: '0' - width: 1 - - TIMER3_RST: - access: r - description: Current status of the TIMER3_RST - lsb: 3 - reset_value: '0' - width: 1 - - RITIMER_RST: - access: r - description: Current status of the RITIMER_RST - lsb: 4 - reset_value: '0' - width: 1 - - SCT_RST: - access: r - description: Current status of the SCT_RST - lsb: 5 - reset_value: '0' - width: 1 - - MOTOCONPWM_RST: - access: r - description: Current status of the MOTOCONPWM_RST - lsb: 6 - reset_value: '0' - width: 1 - - QEI_RST: - access: r - description: Current status of the QEI_RST - lsb: 7 - reset_value: '0' - width: 1 - - ADC0_RST: - access: r - description: Current status of the ADC0_RST - lsb: 8 - reset_value: '0' - width: 1 - - ADC1_RST: - access: r - description: Current status of the ADC1_RST - lsb: 9 - reset_value: '0' - width: 1 - - DAC_RST: - access: r - description: Current status of the DAC_RST - lsb: 10 - reset_value: '0' - width: 1 - - UART0_RST: - access: r - description: Current status of the UART0_RST - lsb: 12 - reset_value: '0' - width: 1 - - UART1_RST: - access: r - description: Current status of the UART1_RST - lsb: 13 - reset_value: '0' - width: 1 - - UART2_RST: - access: r - description: Current status of the UART2_RST - lsb: 14 - reset_value: '0' - width: 1 - - UART3_RST: - access: r - description: Current status of the UART3_RST - lsb: 15 - reset_value: '0' - width: 1 - - I2C0_RST: - access: r - description: Current status of the I2C0_RST - lsb: 16 - reset_value: '0' - width: 1 - - I2C1_RST: - access: r - description: Current status of the I2C1_RST - lsb: 17 - reset_value: '0' - width: 1 - - SSP0_RST: - access: r - description: Current status of the SSP0_RST - lsb: 18 - reset_value: '0' - width: 1 - - SSP1_RST: - access: r - description: Current status of the SSP1_RST - lsb: 19 - reset_value: '0' - width: 1 - - I2S_RST: - access: r - description: Current status of the I2S_RST - lsb: 20 - reset_value: '0' - width: 1 - - SPIFI_RST: - access: r - description: Current status of the SPIFI_RST - lsb: 21 - reset_value: '0' - width: 1 - - CAN1_RST: - access: r - description: Current status of the CAN1_RST - lsb: 22 - reset_value: '0' - width: 1 - - CAN0_RST: - access: r - description: Current status of the CAN0_RST - lsb: 23 - reset_value: '0' - width: 1 - - M0APP_RST: - access: r - description: Current status of the M0APP_RST - lsb: 24 - reset_value: '0' - width: 1 - - SGPIO_RST: - access: r - description: Current status of the SGPIO_RST - lsb: 25 - reset_value: '0' - width: 1 - - SPI_RST: - access: r - description: Current status of the SPI_RST - lsb: 26 - reset_value: '0' - width: 1 -- RESET_EXT_STAT0: - fields: !!omap - - EXT_RESET: - access: rw - description: Reset activated by external reset from reset pin - lsb: 0 - reset_value: '0' - width: 1 - - BOD_RESET: - access: rw - description: Reset activated by BOD reset - lsb: 4 - reset_value: '0' - width: 1 - - WWDT_RESET: - access: rw - description: Reset activated by WWDT time-out - lsb: 5 - reset_value: '0' - width: 1 -- RESET_EXT_STAT1: - fields: !!omap - - CORE_RESET: - access: rw - description: Reset activated by CORE_RST output - lsb: 1 - reset_value: '0' - width: 1 -- RESET_EXT_STAT2: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT4: - fields: !!omap - - CORE_RESET: - access: rw - description: Reset activated by CORE_RST output - lsb: 1 - reset_value: '0' - width: 1 -- RESET_EXT_STAT5: - fields: !!omap - - CORE_RESET: - access: rw - description: Reset activated by CORE_RST output - lsb: 1 - reset_value: '0' - width: 1 -- RESET_EXT_STAT8: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT9: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT13: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT16: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT17: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT18: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT19: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT20: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT21: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT22: - fields: !!omap - - MASTER_RESET: - access: rw - description: Reset activated by MASTER_RST output - lsb: 3 - reset_value: '0' - width: 1 -- RESET_EXT_STAT25: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT27: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT28: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT29: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT32: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT33: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT34: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT35: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT36: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT37: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT38: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT39: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT40: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT41: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT42: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT44: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT45: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT46: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT47: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT48: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT49: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT50: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT51: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT52: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT53: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT54: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT55: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT56: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '' - width: 1 -- RESET_EXT_STAT57: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 -- RESET_EXT_STAT58: - fields: !!omap - - PERIPHERAL_RESET: - access: rw - description: Reset activated by PERIPHERAL_RST output - lsb: 2 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/ritimer.yaml b/libopencm3/scripts/data/lpc43xx/ritimer.yaml deleted file mode 100644 index 9c4da5c..0000000 --- a/libopencm3/scripts/data/lpc43xx/ritimer.yaml +++ /dev/null @@ -1,51 +0,0 @@ -!!omap -- RITIMER_COMPVAL: - fields: !!omap - - RICOMP: - access: rw - description: Compare register - lsb: 0 - reset_value: '0xFFFFFFFF' - width: 32 -- RITIMER_MASK: - fields: !!omap - - RIMASK: - access: rw - description: Mask register - lsb: 0 - reset_value: '0' - width: 32 -- RITIMER_CTRL: - fields: !!omap - - RITINT: - access: rw - description: Interrupt flag - lsb: 0 - reset_value: '0' - width: 1 - - RITENCLR: - access: rw - description: Timer enable clear - lsb: 1 - reset_value: '0' - width: 1 - - RITENBR: - access: rw - description: Timer enable for debug - lsb: 2 - reset_value: '1' - width: 1 - - RITEN: - access: rw - description: Timer enable - lsb: 3 - reset_value: '1' - width: 1 -- RITIMER_COUNTER: - fields: !!omap - - RICOUNTER: - access: rw - description: 32-bit up counter - lsb: 0 - reset_value: '0' - width: 32 diff --git a/libopencm3/scripts/data/lpc43xx/scu.yaml b/libopencm3/scripts/data/lpc43xx/scu.yaml deleted file mode 100644 index 447ce24..0000000 --- a/libopencm3/scripts/data/lpc43xx/scu.yaml +++ /dev/null @@ -1,7063 +0,0 @@ -!!omap -- SCU_SFSP0_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP0_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_13: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_14: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_15: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_16: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_18: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_19: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_20: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP2_13: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP3_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP4_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP5_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP6_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP7_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP8_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP9_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPA_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPA_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPB_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_13: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPC_14: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_13: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_14: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_15: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPD_16: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_12: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_13: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_14: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPE_15: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_6: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_7: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_8: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_9: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_10: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSPF_11: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSP1_17: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP2_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP2_4: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP2_5: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP8_0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP8_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP8_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSPA_1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSPA_2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSPA_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 - - EHD: - access: rw - description: Select drive strength - lsb: 8 - reset_value: '0' - width: 2 -- SCU_SFSP3_3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSCLK0: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSCLK1: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSCLK2: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSCLK3: - fields: !!omap - - MODE: - access: rw - description: Select pin function - lsb: 0 - reset_value: '0' - width: 3 - - EPD: - access: rw - description: Enable pull-down resistor at pad - lsb: 3 - reset_value: '0' - width: 1 - - EPUN: - access: rw - description: Disable pull-up resistor at pad - lsb: 4 - reset_value: '0' - width: 1 - - EHS: - access: rw - description: Select Slew rate - lsb: 5 - reset_value: '0' - width: 1 - - EZI: - access: rw - description: Input buffer enable - lsb: 6 - reset_value: '0' - width: 1 - - ZIF: - access: rw - description: Input glitch filter - lsb: 7 - reset_value: '0' - width: 1 -- SCU_SFSUSB: - fields: !!omap - - USB_AIM: - access: rw - description: Differential data input AIP/AIM - lsb: 0 - reset_value: '0' - width: 1 - - USB_ESEA: - access: rw - description: Control signal for differential input or single input - lsb: 1 - reset_value: '1' - width: 1 - - USB_EPD: - access: rw - description: Enable pull-down connect - lsb: 2 - reset_value: '0' - width: 1 - - USB_EPWR: - access: rw - description: Power mode - lsb: 4 - reset_value: '0' - width: 1 - - USB_VBUS: - access: rw - description: Enable the vbus_valid signal - lsb: 5 - reset_value: '0' - width: 1 -- SCU_SFSI2C0: - fields: !!omap - - SCL_EFP: - access: rw - description: Select input glitch filter time constant for the SCL pin - lsb: 0 - reset_value: '0' - width: 1 - - SCL_EHD: - access: rw - description: Select I2C mode for the SCL pin - lsb: 2 - reset_value: '0' - width: 1 - - SCL_EZI: - access: rw - description: Enable the input receiver for the SCL pin - lsb: 3 - reset_value: '0' - width: 1 - - SCL_ZIF: - access: rw - description: Enable or disable input glitch filter for the SCL pin - lsb: 7 - reset_value: '0' - width: 1 - - SDA_EFP: - access: rw - description: Select input glitch filter time constant for the SDA pin - lsb: 8 - reset_value: '0' - width: 1 - - SDA_EHD: - access: rw - description: Select I2C mode for the SDA pin - lsb: 10 - reset_value: '0' - width: 1 - - SDA_EZI: - access: rw - description: Enable the input receiver for the SDA pin - lsb: 11 - reset_value: '0' - width: 1 - - SDA_ZIF: - access: rw - description: Enable or disable input glitch filter for the SDA pin - lsb: 15 - reset_value: '0' - width: 1 -- SCU_ENAIO0: - fields: !!omap - - ADC0_0: - access: rw - description: Select ADC0_0 - lsb: 0 - reset_value: '0' - width: 1 - - ADC0_1: - access: rw - description: Select ADC0_1 - lsb: 1 - reset_value: '0' - width: 1 - - ADC0_2: - access: rw - description: Select ADC0_2 - lsb: 2 - reset_value: '0' - width: 1 - - ADC0_3: - access: rw - description: Select ADC0_3 - lsb: 3 - reset_value: '0' - width: 1 - - ADC0_4: - access: rw - description: Select ADC0_4 - lsb: 4 - reset_value: '0' - width: 1 - - ADC0_5: - access: rw - description: Select ADC0_5 - lsb: 5 - reset_value: '0' - width: 1 - - ADC0_6: - access: rw - description: Select ADC0_6 - lsb: 6 - reset_value: '0' - width: 1 -- SCU_ENAIO1: - fields: !!omap - - ADC1_0: - access: rw - description: Select ADC1_0 - lsb: 0 - reset_value: '0' - width: 1 - - ADC1_1: - access: rw - description: Select ADC1_1 - lsb: 1 - reset_value: '0' - width: 1 - - ADC1_2: - access: rw - description: Select ADC1_2 - lsb: 2 - reset_value: '0' - width: 1 - - ADC1_3: - access: rw - description: Select ADC1_3 - lsb: 3 - reset_value: '0' - width: 1 - - ADC1_4: - access: rw - description: Select ADC1_4 - lsb: 4 - reset_value: '0' - width: 1 - - ADC1_5: - access: rw - description: Select ADC1_5 - lsb: 5 - reset_value: '0' - width: 1 - - ADC1_6: - access: rw - description: Select ADC1_6 - lsb: 6 - reset_value: '0' - width: 1 - - ADC1_7: - access: rw - description: Select ADC1_7 - lsb: 7 - reset_value: '0' - width: 1 -- SCU_ENAIO2: - fields: !!omap - - DAC: - access: rw - description: Select DAC - lsb: 0 - reset_value: '0' - width: 1 - - BG: - access: rw - description: Select band gap output - lsb: 4 - reset_value: '0' - width: 1 -- SCU_EMCDELAYCLK: - fields: !!omap - - CLK_DELAY: - access: rw - description: EMC_CLKn SDRAM clock output delay - lsb: 0 - reset_value: '0' - width: 16 -- SCU_PINTSEL0: - fields: !!omap - - INTPIN0: - access: '' - description: pin number for interrupt 0 source - lsb: 0 - reset_value: '0' - width: 5 - - PORTSEL0: - access: '' - description: port for interrupt 0 source - lsb: 5 - reset_value: '0' - width: 3 - - INTPIN1: - access: '' - description: pin number for interrupt 1 source - lsb: 8 - reset_value: '0' - width: 5 - - PORTSEL1: - access: '' - description: port for interrupt 1 source - lsb: 13 - reset_value: '0' - width: 3 - - INTPIN2: - access: '' - description: pin number for interrupt 2 source - lsb: 16 - reset_value: '0' - width: 5 - - PORTSEL2: - access: '' - description: port for interrupt 2 source - lsb: 21 - reset_value: '0' - width: 3 - - INTPIN3: - access: '' - description: pin number for interrupt 3 source - lsb: 24 - reset_value: '0' - width: 5 - - PORTSEL3: - access: '' - description: port for interrupt 3 source - lsb: 29 - reset_value: '0' - width: 3 -- SCU_PINTSEL1: - fields: !!omap - - INTPIN4: - access: '' - description: pin number for interrupt 4 source - lsb: 0 - reset_value: '0' - width: 5 - - PORTSEL4: - access: '' - description: port for interrupt 4 source - lsb: 5 - reset_value: '0' - width: 3 - - INTPIN5: - access: '' - description: pin number for interrupt 5 source - lsb: 8 - reset_value: '0' - width: 5 - - PORTSEL5: - access: '' - description: port for interrupt 5 source - lsb: 13 - reset_value: '0' - width: 3 - - INTPIN6: - access: '' - description: pin number for interrupt 6 source - lsb: 16 - reset_value: '0' - width: 5 - - PORTSEL6: - access: '' - description: port for interrupt 6 source - lsb: 21 - reset_value: '0' - width: 3 - - INTPIN7: - access: '' - description: pin number for interrupt 7 source - lsb: 24 - reset_value: '0' - width: 5 - - PORTSEL7: - access: '' - description: port for interrupt 7 source - lsb: 29 - reset_value: '0' - width: 3 diff --git a/libopencm3/scripts/data/lpc43xx/sgpio.yaml b/libopencm3/scripts/data/lpc43xx/sgpio.yaml deleted file mode 100644 index fab91b6..0000000 --- a/libopencm3/scripts/data/lpc43xx/sgpio.yaml +++ /dev/null @@ -1,1953 +0,0 @@ -!!omap -- SGPIO_OUT_MUX_CFG0: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG1: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG2: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG3: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG4: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG5: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG6: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG7: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG8: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG9: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG10: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG11: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG12: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG13: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG14: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_OUT_MUX_CFG15: - fields: !!omap - - P_OUT_CFG: - access: rw - description: Output control of output SGPIOn - lsb: 0 - reset_value: '0' - width: 4 - - P_OE_CFG: - access: rw - description: Output enable source - lsb: 4 - reset_value: '0' - width: 3 -- SGPIO_MUX_CFG0: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG1: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG2: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG3: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG4: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG5: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG6: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG7: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG8: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG9: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG10: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG11: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG12: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG13: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG14: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_MUX_CFG15: - fields: !!omap - - EXT_CLK_ENABLE: - access: rw - description: Select clock signal - lsb: 0 - reset_value: '0' - width: 1 - - CLK_SOURCE_PIN_MODE: - access: rw - description: Select source clock pin - lsb: 1 - reset_value: '0' - width: 2 - - CLK_SOURCE_SLICE_MODE: - access: rw - description: Select clock source slice - lsb: 3 - reset_value: '0' - width: 2 - - QUALIFIER_MODE: - access: rw - description: Select qualifier mode - lsb: 5 - reset_value: '0' - width: 2 - - QUALIFIER_PIN_MODE: - access: rw - description: Select qualifier pin - lsb: 7 - reset_value: '0' - width: 2 - - QUALIFIER_SLICE_MODE: - access: rw - description: Select qualifier slice - lsb: 9 - reset_value: '0' - width: 2 - - CONCAT_ENABLE: - access: rw - description: Enable concatenation - lsb: 11 - reset_value: '0' - width: 1 - - CONCAT_ORDER: - access: rw - description: Select concatenation order - lsb: 12 - reset_value: '0' - width: 2 -- SGPIO_SLICE_MUX_CFG0: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG1: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG2: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG3: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG4: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG5: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG6: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG7: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG8: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG9: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG10: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG11: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG12: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG13: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG14: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_SLICE_MUX_CFG15: - fields: !!omap - - MATCH_MODE: - access: rw - description: Match mode - lsb: 0 - reset_value: '0' - width: 1 - - CLK_CAPTURE_MODE: - access: rw - description: Capture clock mode - lsb: 1 - reset_value: '0' - width: 1 - - CLKGEN_MODE: - access: rw - description: Clock generation mode - lsb: 2 - reset_value: '0' - width: 1 - - INV_OUT_CLK: - access: rw - description: Invert output clock - lsb: 3 - reset_value: '0' - width: 1 - - DATA_CAPTURE_MODE: - access: rw - description: Condition for input bit match interrupt - lsb: 4 - reset_value: '0' - width: 2 - - PARALLEL_MODE: - access: rw - description: Parallel mode - lsb: 6 - reset_value: '0' - width: 2 - - INV_QUALIFIER: - access: rw - description: Inversion qualifier - lsb: 8 - reset_value: '0' - width: 1 -- SGPIO_POS0: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS1: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS2: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS3: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS4: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS5: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS6: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS7: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS8: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS9: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS10: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS11: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS12: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS13: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS14: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 -- SGPIO_POS15: - fields: !!omap - - POS: - access: rw - description: Each time COUNT reaches 0x0 POS counts down - lsb: 0 - reset_value: '0' - width: 8 - - POS_RESET: - access: rw - description: Reload value for POS after POS reaches 0x0 - lsb: 8 - reset_value: '0' - width: 8 diff --git a/libopencm3/scripts/data/lpc43xx/ssp.yaml b/libopencm3/scripts/data/lpc43xx/ssp.yaml deleted file mode 100644 index 54b440b..0000000 --- a/libopencm3/scripts/data/lpc43xx/ssp.yaml +++ /dev/null @@ -1,445 +0,0 @@ -!!omap -- SSP0_CR0: - fields: !!omap - - DSS: - access: rw - description: Data Size Select - lsb: 0 - reset_value: '0' - width: 4 - - FRF: - access: rw - description: Frame Format - lsb: 4 - reset_value: '0' - width: 2 - - CPOL: - access: rw - description: Clock Out Polarity - lsb: 6 - reset_value: '0' - width: 1 - - CPHA: - access: rw - description: Clock Out Phase - lsb: 7 - reset_value: '0' - width: 1 - - SCR: - access: rw - description: Serial Clock Rate - lsb: 8 - reset_value: '0' - width: 8 -- SSP1_CR0: - fields: !!omap - - DSS: - access: rw - description: Data Size Select - lsb: 0 - reset_value: '0' - width: 4 - - FRF: - access: rw - description: Frame Format - lsb: 4 - reset_value: '0' - width: 2 - - CPOL: - access: rw - description: Clock Out Polarity - lsb: 6 - reset_value: '0' - width: 1 - - CPHA: - access: rw - description: Clock Out Phase - lsb: 7 - reset_value: '0' - width: 1 - - SCR: - access: rw - description: Serial Clock Rate - lsb: 8 - reset_value: '0' - width: 8 -- SSP0_CR1: - fields: !!omap - - LBM: - access: rw - description: Loop Back Mode - lsb: 0 - reset_value: '0' - width: 1 - - SSE: - access: rw - description: SSP Enable - lsb: 1 - reset_value: '0' - width: 1 - - MS: - access: rw - description: Master/Slave Mode - lsb: 2 - reset_value: '0' - width: 1 - - SOD: - access: rw - description: Slave Output Disable - lsb: 3 - reset_value: '0' - width: 1 -- SSP1_CR1: - fields: !!omap - - SSE: - access: rw - description: SSP Enable - lsb: 1 - reset_value: '0' - width: 1 - - MS: - access: rw - description: Master/Slave Mode - lsb: 2 - reset_value: '0' - width: 1 - - SOD: - access: rw - description: Slave Output Disable - lsb: 3 - reset_value: '0' - width: 1 -- SSP0_DR: - fields: !!omap - - DATA: - access: rw - description: Software can write data to be transmitted to this register, and - read data that has been - lsb: 0 - reset_value: '0' - width: 16 -- SSP1_DR: - fields: !!omap - - DATA: - access: rw - description: Software can write data to be transmitted to this register, and - read data that has been - lsb: 0 - reset_value: '0' - width: 16 -- SSP0_SR: - fields: !!omap - - TFE: - access: r - description: Transmit FIFO Empty - lsb: 0 - reset_value: '1' - width: 1 - - TNF: - access: r - description: Transmit FIFO Not Full - lsb: 1 - reset_value: '1' - width: 1 - - RNE: - access: r - description: Receive FIFO Not Empty - lsb: 2 - reset_value: '0' - width: 1 - - RFF: - access: r - description: Receive FIFO Full - lsb: 3 - reset_value: '0' - width: 1 - - BSY: - access: r - description: Busy. - lsb: 4 - reset_value: '0' - width: 1 -- SSP1_SR: - fields: !!omap - - TFE: - access: r - description: Transmit FIFO Empty - lsb: 0 - reset_value: '1' - width: 1 - - TNF: - access: r - description: Transmit FIFO Not Full - lsb: 1 - reset_value: '1' - width: 1 - - RNE: - access: r - description: Receive FIFO Not Empty - lsb: 2 - reset_value: '0' - width: 1 - - RFF: - access: r - description: Receive FIFO Full - lsb: 3 - reset_value: '0' - width: 1 - - BSY: - access: r - description: Busy. - lsb: 4 - reset_value: '0' - width: 1 -- SSP0_CPSR: - fields: !!omap - - CPSDVSR: - access: rw - description: SSP Clock Prescale Register - lsb: 0 - reset_value: '0' - width: 8 -- SSP1_CPSR: - fields: !!omap - - CPSDVSR: - access: rw - description: SSP Clock Prescale Register - lsb: 0 - reset_value: '0' - width: 8 -- SSP0_IMSC: - fields: !!omap - - RORIM: - access: rw - description: Software should set this bit to enable interrupt when a Receive - Overrun occurs - lsb: 0 - reset_value: '0' - width: 1 - - RTIM: - access: rw - description: Software should set this bit to enable interrupt when a Receive - Time-out condition occurs - lsb: 1 - reset_value: '0' - width: 1 - - RXIM: - access: rw - description: Software should set this bit to enable interrupt when the Rx - FIFO is at least half full - lsb: 2 - reset_value: '0' - width: 1 - - TXIM: - access: rw - description: Software should set this bit to enable interrupt when the Tx - FIFO is at least half empty - lsb: 3 - reset_value: '0' - width: 1 -- SSP1_IMSC: - fields: !!omap - - RORIM: - access: rw - description: Software should set this bit to enable interrupt when a Receive - Overrun occurs - lsb: 0 - reset_value: '0' - width: 1 - - RTIM: - access: rw - description: Software should set this bit to enable interrupt when a Receive - Time-out condition occurs - lsb: 1 - reset_value: '0' - width: 1 - - RXIM: - access: rw - description: Software should set this bit to enable interrupt when the Rx - FIFO is at least half full - lsb: 2 - reset_value: '0' - width: 1 - - TXIM: - access: rw - description: Software should set this bit to enable interrupt when the Tx - FIFO is at least half empty - lsb: 3 - reset_value: '0' - width: 1 -- SSP0_RIS: - fields: !!omap - - RORRIS: - access: r - description: This bit is 1 if another frame was completely received while - the RxFIFO was full - lsb: 0 - reset_value: '0' - width: 1 - - RTRIS: - access: r - description: This bit is 1 if the Rx FIFO is not empty, and has not been read - for a time-out period - lsb: 1 - reset_value: '0' - width: 1 - - RXRIS: - access: r - description: This bit is 1 if the Rx FIFO is at least half full - lsb: 2 - reset_value: '0' - width: 1 - - TXRIS: - access: r - description: This bit is 1 if the Tx FIFO is at least half empty - lsb: 3 - reset_value: '1' - width: 1 -- SSP1_RIS: - fields: !!omap - - RORRIS: - access: r - description: This bit is 1 if another frame was completely received while - the RxFIFO was full - lsb: 0 - reset_value: '0' - width: 1 - - RTRIS: - access: r - description: This bit is 1 if the Rx FIFO is not empty, and has not been read - for a time-out period - lsb: 1 - reset_value: '0' - width: 1 - - RXRIS: - access: r - description: This bit is 1 if the Rx FIFO is at least half full - lsb: 2 - reset_value: '0' - width: 1 - - TXRIS: - access: r - description: This bit is 1 if the Tx FIFO is at least half empty - lsb: 3 - reset_value: '1' - width: 1 -- SSP0_MIS: - fields: !!omap - - RORMIS: - access: r - description: This bit is 1 if another frame was completely received while - the RxFIFO was full, and this interrupt is enabled - lsb: 0 - reset_value: '0' - width: 1 - - RTMIS: - access: r - description: This bit is 1 if the Rx FIFO is not empty, has not been read - for a time-out period, and this interrupt is enabled - lsb: 1 - reset_value: '0' - width: 1 - - RXMIS: - access: r - description: This bit is 1 if the Rx FIFO is at least half full, and this - interrupt is enabled - lsb: 2 - reset_value: '0' - width: 1 - - TXMIS: - access: r - description: This bit is 1 if the Tx FIFO is at least half empty, and this - interrupt is enabled - lsb: 3 - reset_value: '0' - width: 1 -- SSP1_MIS: - fields: !!omap - - RORMIS: - access: r - description: This bit is 1 if another frame was completely received while - the RxFIFO was full, and this interrupt is enabled - lsb: 0 - reset_value: '0' - width: 1 - - RTMIS: - access: r - description: This bit is 1 if the Rx FIFO is not empty, has not been read - for a time-out period, and this interrupt is enabled - lsb: 1 - reset_value: '0' - width: 1 - - RXMIS: - access: r - description: This bit is 1 if the Rx FIFO is at least half full, and this - interrupt is enabled - lsb: 2 - reset_value: '0' - width: 1 - - TXMIS: - access: r - description: This bit is 1 if the Tx FIFO is at least half empty, and this - interrupt is enabled - lsb: 3 - reset_value: '0' - width: 1 -- SSP0_ICR: - fields: !!omap - - RORIC: - access: w - description: Writing a 1 to this bit clears the 'frame was received when RxFIFO - was full' interrupt - lsb: 0 - reset_value: '' - width: 1 - - RTIC: - access: w - description: Writing a 1 to this bit clears the Rx FIFO was not empty and - has not been read for a time-out period interrupt - lsb: 1 - reset_value: '' - width: 1 -- SSP1_ICR: - fields: !!omap - - RORIC: - access: w - description: Writing a 1 to this bit clears the 'frame was received when RxFIFO - was full' interrupt - lsb: 0 - reset_value: '' - width: 1 - - RTIC: - access: w - description: Writing a 1 to this bit clears the Rx FIFO was not empty and - has not been read for a time-out period interrupt - lsb: 1 - reset_value: '' - width: 1 -- SSP0_DMACR: - fields: !!omap - - RXDMAE: - access: rw - description: Receive DMA Enable - lsb: 0 - reset_value: '0' - width: 1 - - TXDMAE: - access: rw - description: Transmit DMA Enable - lsb: 1 - reset_value: '0' - width: 1 -- SSP1_DMACR: - fields: !!omap - - RXDMAE: - access: rw - description: Receive DMA Enable - lsb: 0 - reset_value: '0' - width: 1 - - TXDMAE: - access: rw - description: Transmit DMA Enable - lsb: 1 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/usb.yaml b/libopencm3/scripts/data/lpc43xx/usb.yaml deleted file mode 100644 index 658a806..0000000 --- a/libopencm3/scripts/data/lpc43xx/usb.yaml +++ /dev/null @@ -1,1416 +0,0 @@ -!!omap -- USB0_CAPLENGTH: - fields: !!omap - - CAPLENGTH: - access: r - description: Indicates offset to add to the register base address at the beginning - of the Operational Register - lsb: 0 - reset_value: '0x40' - width: 8 - - HCIVERSION: - access: r - description: BCD encoding of the EHCI revision number supported by this host - controller - lsb: 8 - reset_value: '0x100' - width: 16 -- USB0_HCSPARAMS: - fields: !!omap - - N_PORTS: - access: r - description: Number of downstream ports - lsb: 0 - reset_value: '0x1' - width: 4 - - PPC: - access: r - description: Port Power Control - lsb: 4 - reset_value: '0x1' - width: 1 - - N_PCC: - access: r - description: Number of Ports per Companion Controller - lsb: 8 - reset_value: '0x0' - width: 4 - - N_CC: - access: r - description: Number of Companion Controller - lsb: 12 - reset_value: '0x0' - width: 4 - - PI: - access: r - description: Port indicators - lsb: 16 - reset_value: '0x1' - width: 1 - - N_PTT: - access: r - description: Number of Ports per Transaction Translator - lsb: 20 - reset_value: '0x0' - width: 4 - - N_TT: - access: r - description: Number of Transaction Translators - lsb: 24 - reset_value: '0x0' - width: 4 -- USB0_HCCPARAMS: - fields: !!omap - - ADC: - access: r - description: 64-bit Addressing Capability - lsb: 0 - reset_value: '0' - width: 1 - - PFL: - access: r - description: Programmable Frame List Flag - lsb: 1 - reset_value: '1' - width: 1 - - ASP: - access: r - description: Asynchronous Schedule Park Capability - lsb: 2 - reset_value: '1' - width: 1 - - IST: - access: r - description: Isochronous Scheduling Threshold - lsb: 4 - reset_value: '0' - width: 4 - - EECP: - access: r - description: EHCI Extended Capabilities Pointer - lsb: 8 - reset_value: '0' - width: 4 -- USB0_DCCPARAMS: - fields: !!omap - - DEN: - access: r - description: Device Endpoint Number - lsb: 0 - reset_value: '0x4' - width: 5 - - DC: - access: r - description: Device Capable - lsb: 7 - reset_value: '0x1' - width: 1 - - HC: - access: r - description: Host Capable - lsb: 8 - reset_value: '0x1' - width: 1 -- USB0_USBCMD_D: - fields: !!omap - - RS: - access: rw - description: Run/Stop - lsb: 0 - reset_value: '0' - width: 1 - - RST: - access: rw - description: Controller reset - lsb: 1 - reset_value: '0' - width: 1 - - SUTW: - access: rw - description: Setup trip wire - lsb: 13 - reset_value: '0' - width: 1 - - ATDTW: - access: rw - description: Add dTD trip wire - lsb: 14 - reset_value: '0' - width: 1 - - ITC: - access: rw - description: Interrupt threshold control - lsb: 16 - reset_value: '0x8' - width: 8 -- USB0_USBCMD_H: - fields: !!omap - - RS: - access: rw - description: Run/Stop - lsb: 0 - reset_value: '0' - width: 1 - - RST: - access: rw - description: Controller reset - lsb: 1 - reset_value: '0' - width: 1 - - FS0: - access: '' - description: Bit 0 of the Frame List Size bits - lsb: 2 - reset_value: '0' - width: 1 - - FS1: - access: '' - description: Bit 1 of the Frame List Size bits - lsb: 3 - reset_value: '0' - width: 1 - - PSE: - access: rw - description: This bit controls whether the host controller skips processing - the periodic schedule - lsb: 4 - reset_value: '0' - width: 1 - - ASE: - access: rw - description: This bit controls whether the host controller skips processing - the asynchronous schedule - lsb: 5 - reset_value: '0' - width: 1 - - IAA: - access: rw - description: This bit is used as a doorbell by software to tell the host controller - to issue an interrupt the next time it advances asynchronous schedule - lsb: 6 - reset_value: '0' - width: 1 - - ASP1_0: - access: rw - description: Asynchronous schedule park mode - lsb: 8 - reset_value: '0x3' - width: 2 - - ASPE: - access: rw - description: Asynchronous Schedule Park Mode Enable - lsb: 11 - reset_value: '1' - width: 1 - - FS2: - access: '' - description: Bit 2 of the Frame List Size bits - lsb: 15 - reset_value: '0' - width: 1 - - ITC: - access: rw - description: Interrupt threshold control - lsb: 16 - reset_value: '0x8' - width: 8 -- USB0_USBSTS_D: - fields: !!omap - - UI: - access: rwc - description: USB interrupt - lsb: 0 - reset_value: '0' - width: 1 - - UEI: - access: rwc - description: USB error interrupt - lsb: 1 - reset_value: '0' - width: 1 - - PCI: - access: rwc - description: Port change detect - lsb: 2 - reset_value: '0' - width: 1 - - URI: - access: rwc - description: USB reset received - lsb: 6 - reset_value: '0' - width: 1 - - SRI: - access: rwc - description: SOF received - lsb: 7 - reset_value: '0' - width: 1 - - SLI: - access: rwc - description: DCSuspend - lsb: 8 - reset_value: '0' - width: 1 - - NAKI: - access: r - description: NAK interrupt bit - lsb: 16 - reset_value: '0' - width: 1 -- USB0_USBSTS_H: - fields: !!omap - - UI: - access: rwc - description: USB interrupt - lsb: 0 - reset_value: '0' - width: 1 - - UEI: - access: rwc - description: USB error interrupt - lsb: 1 - reset_value: '0' - width: 1 - - PCI: - access: rwc - description: Port change detect - lsb: 2 - reset_value: '0' - width: 1 - - FRI: - access: rwc - description: Frame list roll-over - lsb: 3 - reset_value: '0' - width: 1 - - AAI: - access: rwc - description: Interrupt on async advance - lsb: 5 - reset_value: '0' - width: 1 - - SRI: - access: rwc - description: SOF received - lsb: 7 - reset_value: '0' - width: 1 - - HCH: - access: r - description: HCHalted - lsb: 12 - reset_value: '1' - width: 1 - - RCL: - access: r - description: Reclamation - lsb: 13 - reset_value: '0' - width: 1 - - PS: - access: r - description: Periodic schedule status - lsb: 14 - reset_value: '0' - width: 1 - - AS: - access: '' - description: Asynchronous schedule status - lsb: 15 - reset_value: '0' - width: 1 - - UAI: - access: rwc - description: USB host asynchronous interrupt (USBHSTASYNCINT) - lsb: 18 - reset_value: '0' - width: 1 - - UPI: - access: rwc - description: USB host periodic interrupt (USBHSTPERINT) - lsb: 19 - reset_value: '0' - width: 1 -- USB0_USBINTR_D: - fields: !!omap - - UE: - access: rw - description: USB interrupt enable - lsb: 0 - reset_value: '0' - width: 1 - - UEE: - access: rw - description: USB error interrupt enable - lsb: 1 - reset_value: '0' - width: 1 - - PCE: - access: rw - description: Port change detect enable - lsb: 2 - reset_value: '0' - width: 1 - - URE: - access: rw - description: USB reset enable - lsb: 6 - reset_value: '0' - width: 1 - - SRE: - access: rw - description: SOF received enable - lsb: 7 - reset_value: '0' - width: 1 - - SLE: - access: rw - description: Sleep enable - lsb: 8 - reset_value: '0' - width: 1 - - NAKE: - access: rw - description: NAK interrupt enable - lsb: 16 - reset_value: '0' - width: 1 -- USB0_USBINTR_H: - fields: !!omap - - UE: - access: rw - description: USB interrupt enable - lsb: 0 - reset_value: '0' - width: 1 - - UEE: - access: rw - description: USB error interrupt enable - lsb: 1 - reset_value: '0' - width: 1 - - PCE: - access: rw - description: Port change detect enable - lsb: 2 - reset_value: '0' - width: 1 - - FRE: - access: rw - description: Frame list rollover enable - lsb: 3 - reset_value: '0' - width: 1 - - AAE: - access: rw - description: Interrupt on asynchronous advance enable - lsb: 5 - reset_value: '0' - width: 1 - - SRE: - access: '' - description: SOF received enable - lsb: 7 - reset_value: '0' - width: 1 - - UAIE: - access: rw - description: USB host asynchronous interrupt enable - lsb: 18 - reset_value: '0' - width: 1 - - UPIA: - access: rw - description: USB host periodic interrupt enable - lsb: 19 - reset_value: '0' - width: 1 -- USB0_FRINDEX_D: - fields: !!omap - - FRINDEX2_0: - access: r - description: Current micro frame number - lsb: 0 - reset_value: '' - width: 3 - - FRINDEX13_3: - access: r - description: Current frame number of the last frame transmitted - lsb: 3 - reset_value: '' - width: 11 -- USB0_FRINDEX_H: - fields: !!omap - - FRINDEX2_0: - access: rw - description: Current micro frame number - lsb: 0 - reset_value: '' - width: 3 - - FRINDEX12_3: - access: rw - description: Frame list current index - lsb: 3 - reset_value: '' - width: 10 -- USB0_DEVICEADDR: - fields: !!omap - - USBADRA: - access: '' - description: Device address advance - lsb: 24 - reset_value: '0' - width: 1 - - USBADR: - access: rw - description: USB device address - lsb: 25 - reset_value: '0' - width: 7 -- USB0_PERIODICLISTBASE: - fields: !!omap - - PERBASE31_12: - access: rw - description: Base Address (Low) - lsb: 12 - reset_value: '' - width: 20 -- USB0_ENDPOINTLISTADDR: - fields: !!omap - - EPBASE31_11: - access: rw - description: Endpoint list pointer (low) - lsb: 11 - reset_value: '' - width: 21 -- USB0_ASYNCLISTADDR: - fields: !!omap - - ASYBASE31_5: - access: rw - description: Link pointer (Low) LPL - lsb: 5 - reset_value: '' - width: 27 -- USB0_TTCTRL: - fields: !!omap - - TTHA: - access: rw - description: Hub address when FS or LS device are connected directly - lsb: 24 - reset_value: '' - width: 7 -- USB0_BURSTSIZE: - fields: !!omap - - RXPBURST: - access: rw - description: Programmable RX burst length - lsb: 0 - reset_value: '0x10' - width: 8 - - TXPBURST: - access: rw - description: Programmable TX burst length - lsb: 8 - reset_value: '0x10' - width: 8 -- USB0_TXFILLTUNING: - fields: !!omap - - TXSCHOH: - access: rw - description: FIFO burst threshold - lsb: 0 - reset_value: '0x2' - width: 8 - - TXSCHEATLTH: - access: rw - description: Scheduler health counter - lsb: 8 - reset_value: '0x0' - width: 5 - - TXFIFOTHRES: - access: rw - description: Scheduler overhead - lsb: 16 - reset_value: '0x0' - width: 6 -- USB0_BINTERVAL: - fields: !!omap - - BINT: - access: rw - description: bInterval value - lsb: 0 - reset_value: '0x00' - width: 4 -- USB0_ENDPTNAK: - fields: !!omap - - EPRN: - access: rwc - description: Rx endpoint NAK - lsb: 0 - reset_value: '0x00' - width: 6 - - EPTN: - access: rwc - description: Tx endpoint NAK - lsb: 16 - reset_value: '0x00' - width: 6 -- USB0_ENDPTNAKEN: - fields: !!omap - - EPRNE: - access: rw - description: Rx endpoint NAK enable - lsb: 0 - reset_value: '0x00' - width: 6 - - EPTNE: - access: rw - description: Tx endpoint NAK - lsb: 16 - reset_value: '0x00' - width: 6 -- USB0_PORTSC1_D: - fields: !!omap - - CCS: - access: r - description: Current connect status - lsb: 0 - reset_value: '0' - width: 1 - - PE: - access: r - description: Port enable - lsb: 2 - reset_value: '1' - width: 1 - - PEC: - access: r - description: Port enable/disable change - lsb: 3 - reset_value: '0' - width: 1 - - FPR: - access: rw - description: Force port resume - lsb: 6 - reset_value: '0' - width: 1 - - SUSP: - access: r - description: Suspend - lsb: 7 - reset_value: '0' - width: 1 - - PR: - access: r - description: Port reset - lsb: 8 - reset_value: '0' - width: 1 - - HSP: - access: r - description: High-speed status - lsb: 9 - reset_value: '0' - width: 1 - - PIC1_0: - access: rw - description: Port indicator control - lsb: 14 - reset_value: '0' - width: 2 - - PTC3_0: - access: rw - description: Port test control - lsb: 16 - reset_value: '0' - width: 4 - - PHCD: - access: rw - description: PHY low power suspend - clock disable (PLPSCD) - lsb: 23 - reset_value: '0' - width: 1 - - PFSC: - access: rw - description: Port force full speed connect - lsb: 24 - reset_value: '0' - width: 1 - - PSPD: - access: r - description: Port speed - lsb: 26 - reset_value: '0' - width: 2 -- USB0_PORTSC1_H: - fields: !!omap - - CCS: - access: rwc - description: Current connect status - lsb: 0 - reset_value: '0' - width: 1 - - CSC: - access: rwc - description: Connect status change - lsb: 1 - reset_value: '0' - width: 1 - - PE: - access: rw - description: Port enable - lsb: 2 - reset_value: '0' - width: 1 - - PEC: - access: rwc - description: Port disable/enable change - lsb: 3 - reset_value: '0' - width: 1 - - OCA: - access: r - description: Over-current active - lsb: 4 - reset_value: '0' - width: 1 - - OCC: - access: rwc - description: Over-current change - lsb: 5 - reset_value: '0' - width: 1 - - FPR: - access: rw - description: Force port resume - lsb: 6 - reset_value: '0' - width: 1 - - SUSP: - access: rw - description: Suspend - lsb: 7 - reset_value: '0' - width: 1 - - PR: - access: rw - description: Port reset - lsb: 8 - reset_value: '0' - width: 1 - - HSP: - access: r - description: High-speed status - lsb: 9 - reset_value: '0' - width: 1 - - LS: - access: r - description: Line status - lsb: 10 - reset_value: '0x3' - width: 2 - - PP: - access: rw - description: Port power control - lsb: 12 - reset_value: '0' - width: 1 - - PIC1_0: - access: rw - description: Port indicator control - lsb: 14 - reset_value: '0' - width: 2 - - PTC3_0: - access: rw - description: Port test control - lsb: 16 - reset_value: '0' - width: 4 - - WKCN: - access: rw - description: Wake on connect enable (WKCNNT_E) - lsb: 20 - reset_value: '0' - width: 1 - - WKDC: - access: rw - description: Wake on disconnect enable (WKDSCNNT_E) - lsb: 21 - reset_value: '0' - width: 1 - - WKOC: - access: rw - description: Wake on over-current enable (WKOC_E) - lsb: 22 - reset_value: '0' - width: 1 - - PHCD: - access: rw - description: PHY low power suspend - clock disable (PLPSCD) - lsb: 23 - reset_value: '0' - width: 1 - - PFSC: - access: rw - description: Port force full speed connect - lsb: 24 - reset_value: '0' - width: 1 - - PSPD: - access: r - description: Port speed - lsb: 26 - reset_value: '0' - width: 2 -- USB0_OTGSC: - fields: !!omap - - VD: - access: rw - description: VBUS_Discharge - lsb: 0 - reset_value: '0' - width: 1 - - VC: - access: rw - description: VBUS_Charge - lsb: 1 - reset_value: '0' - width: 1 - - HAAR: - access: rw - description: Hardware assist auto_reset - lsb: 2 - reset_value: '0' - width: 1 - - OT: - access: rw - description: OTG termination - lsb: 3 - reset_value: '0' - width: 1 - - DP: - access: rw - description: Data pulsing - lsb: 4 - reset_value: '0' - width: 1 - - IDPU: - access: rw - description: ID pull-up - lsb: 5 - reset_value: '1' - width: 1 - - HADP: - access: rw - description: Hardware assist data pulse - lsb: 6 - reset_value: '0' - width: 1 - - HABA: - access: rw - description: Hardware assist B-disconnect to A-connect - lsb: 7 - reset_value: '0' - width: 1 - - ID: - access: r - description: USB ID - lsb: 8 - reset_value: '0' - width: 1 - - AVV: - access: r - description: A-VBUS valid - lsb: 9 - reset_value: '0' - width: 1 - - ASV: - access: r - description: A-session valid - lsb: 10 - reset_value: '0' - width: 1 - - BSV: - access: r - description: B-session valid - lsb: 11 - reset_value: '0' - width: 1 - - BSE: - access: r - description: B-session end - lsb: 12 - reset_value: '0' - width: 1 - - MS1T: - access: r - description: 1 millisecond timer toggle - lsb: 13 - reset_value: '0' - width: 1 - - DPS: - access: r - description: Data bus pulsing status - lsb: 14 - reset_value: '0' - width: 1 - - IDIS: - access: rwc - description: USB ID interrupt status - lsb: 16 - reset_value: '0' - width: 1 - - AVVIS: - access: rwc - description: A-VBUS valid interrupt status - lsb: 17 - reset_value: '0' - width: 1 - - ASVIS: - access: rwc - description: A-Session valid interrupt status - lsb: 18 - reset_value: '0' - width: 1 - - BSVIS: - access: rwc - description: B-Session valid interrupt status - lsb: 19 - reset_value: '0' - width: 1 - - BSEIS: - access: rwc - description: B-Session end interrupt status - lsb: 20 - reset_value: '0' - width: 1 - - MS1S: - access: rwc - description: 1 millisecond timer interrupt status - lsb: 21 - reset_value: '0' - width: 1 - - DPIS: - access: rwc - description: Data pulse interrupt status - lsb: 22 - reset_value: '0' - width: 1 - - IDIE: - access: rw - description: USB ID interrupt enable - lsb: 24 - reset_value: '0' - width: 1 - - AVVIE: - access: rw - description: A-VBUS valid interrupt enable - lsb: 25 - reset_value: '0' - width: 1 - - ASVIE: - access: rw - description: A-session valid interrupt enable - lsb: 26 - reset_value: '0' - width: 1 - - BSVIE: - access: rw - description: B-session valid interrupt enable - lsb: 27 - reset_value: '0' - width: 1 - - BSEIE: - access: rw - description: B-session end interrupt enable - lsb: 28 - reset_value: '0' - width: 1 - - MS1E: - access: rw - description: 1 millisecond timer interrupt enable - lsb: 29 - reset_value: '0' - width: 1 - - DPIE: - access: rw - description: Data pulse interrupt enable - lsb: 30 - reset_value: '0' - width: 1 -- USB0_USBMODE_D: - fields: !!omap - - CM1_0: - access: rwo - description: Controller mode - lsb: 0 - reset_value: '0' - width: 2 - - ES: - access: rw - description: Endian select - lsb: 2 - reset_value: '0' - width: 1 - - SLOM: - access: rw - description: Setup Lockout mode - lsb: 3 - reset_value: '0' - width: 1 - - SDIS: - access: rw - description: Setup Lockout mode - lsb: 4 - reset_value: '0' - width: 1 -- USB0_USBMODE_H: - fields: !!omap - - CM: - access: rwo - description: Controller mode - lsb: 0 - reset_value: '0' - width: 2 - - ES: - access: rw - description: Endian select - lsb: 2 - reset_value: '0' - width: 1 - - SDIS: - access: rw - description: Stream disable mode - lsb: 4 - reset_value: '0' - width: 1 - - VBPS: - access: rwo - description: VBUS power select - lsb: 5 - reset_value: '0' - width: 1 -- USB0_ENDPTSETUPSTAT: - fields: !!omap - - ENDPTSETUPSTAT: - access: rwc - description: Setup endpoint status for logical endpoints 0 to 5 - lsb: 0 - reset_value: '0' - width: 6 -- USB0_ENDPTPRIME: - fields: !!omap - - PERB: - access: rws - description: Prime endpoint receive buffer for physical OUT endpoints 5 to - 0 - lsb: 0 - reset_value: '0' - width: 6 - - PETB: - access: rws - description: Prime endpoint transmit buffer for physical IN endpoints 5 to - 0 - lsb: 16 - reset_value: '0' - width: 6 -- USB0_ENDPTFLUSH: - fields: !!omap - - FERB: - access: rwc - description: Flush endpoint receive buffer for physical OUT endpoints 5 to - 0 - lsb: 0 - reset_value: '0' - width: 6 - - FETB: - access: rwc - description: Flush endpoint transmit buffer for physical IN endpoints 5 to - 0 - lsb: 16 - reset_value: '0' - width: 6 -- USB0_ENDPTSTAT: - fields: !!omap - - ERBR: - access: r - description: Endpoint receive buffer ready for physical OUT endpoints 5 to - 0 - lsb: 0 - reset_value: '0' - width: 6 - - ETBR: - access: r - description: Endpoint transmit buffer ready for physical IN endpoints 3 to - 0 - lsb: 16 - reset_value: '0' - width: 6 -- USB0_ENDPTCOMPLETE: - fields: !!omap - - ERCE: - access: rwc - description: Endpoint receive complete event for physical OUT endpoints 5 - to 0 - lsb: 0 - reset_value: '0' - width: 6 - - ETCE: - access: rwc - description: Endpoint transmit complete event for physical IN endpoints 5 - to 0 - lsb: 16 - reset_value: '0' - width: 6 -- USB0_ENDPTCTRL0: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT1_0: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXE: - access: r - description: Rx endpoint enable - lsb: 7 - reset_value: '1' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '' - width: 1 - - TXT1_0: - access: r - description: Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '1' - width: 1 -- USB0_ENDPTCTRL1: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXI: - access: rw - description: Rx data toggle inhibit - lsb: 5 - reset_value: '0' - width: 1 - - RXR: - access: ws - description: Rx data toggle reset - lsb: 6 - reset_value: '0' - width: 1 - - RXE: - access: rw - description: Rx endpoint enable - lsb: 7 - reset_value: '0' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '0' - width: 1 - - TXT1_0: - access: r - description: Tx Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXI: - access: rw - description: Tx data toggle inhibit - lsb: 21 - reset_value: '0' - width: 1 - - TXR: - access: ws - description: Tx data toggle reset - lsb: 22 - reset_value: '1' - width: 1 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '0' - width: 1 -- USB0_ENDPTCTRL2: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXI: - access: rw - description: Rx data toggle inhibit - lsb: 5 - reset_value: '0' - width: 1 - - RXR: - access: ws - description: Rx data toggle reset - lsb: 6 - reset_value: '0' - width: 1 - - RXE: - access: rw - description: Rx endpoint enable - lsb: 7 - reset_value: '0' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '0' - width: 1 - - TXT1_0: - access: r - description: Tx Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXI: - access: rw - description: Tx data toggle inhibit - lsb: 21 - reset_value: '0' - width: 1 - - TXR: - access: ws - description: Tx data toggle reset - lsb: 22 - reset_value: '1' - width: 1 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '0' - width: 1 -- USB0_ENDPTCTRL3: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXI: - access: rw - description: Rx data toggle inhibit - lsb: 5 - reset_value: '0' - width: 1 - - RXR: - access: ws - description: Rx data toggle reset - lsb: 6 - reset_value: '0' - width: 1 - - RXE: - access: rw - description: Rx endpoint enable - lsb: 7 - reset_value: '0' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '0' - width: 1 - - TXT1_0: - access: r - description: Tx Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXI: - access: rw - description: Tx data toggle inhibit - lsb: 21 - reset_value: '0' - width: 1 - - TXR: - access: ws - description: Tx data toggle reset - lsb: 22 - reset_value: '1' - width: 1 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '0' - width: 1 -- USB0_ENDPTCTRL4: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXI: - access: rw - description: Rx data toggle inhibit - lsb: 5 - reset_value: '0' - width: 1 - - RXR: - access: ws - description: Rx data toggle reset - lsb: 6 - reset_value: '0' - width: 1 - - RXE: - access: rw - description: Rx endpoint enable - lsb: 7 - reset_value: '0' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '0' - width: 1 - - TXT1_0: - access: r - description: Tx Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXI: - access: rw - description: Tx data toggle inhibit - lsb: 21 - reset_value: '0' - width: 1 - - TXR: - access: ws - description: Tx data toggle reset - lsb: 22 - reset_value: '1' - width: 1 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '0' - width: 1 -- USB0_ENDPTCTRL5: - fields: !!omap - - RXS: - access: rw - description: Rx endpoint stall - lsb: 0 - reset_value: '0' - width: 1 - - RXT: - access: rw - description: Endpoint type - lsb: 2 - reset_value: '0' - width: 2 - - RXI: - access: rw - description: Rx data toggle inhibit - lsb: 5 - reset_value: '0' - width: 1 - - RXR: - access: ws - description: Rx data toggle reset - lsb: 6 - reset_value: '0' - width: 1 - - RXE: - access: rw - description: Rx endpoint enable - lsb: 7 - reset_value: '0' - width: 1 - - TXS: - access: rw - description: Tx endpoint stall - lsb: 16 - reset_value: '0' - width: 1 - - TXT1_0: - access: r - description: Tx Endpoint type - lsb: 18 - reset_value: '0' - width: 2 - - TXI: - access: rw - description: Tx data toggle inhibit - lsb: 21 - reset_value: '0' - width: 1 - - TXR: - access: ws - description: Tx data toggle reset - lsb: 22 - reset_value: '1' - width: 1 - - TXE: - access: r - description: Tx endpoint enable - lsb: 23 - reset_value: '0' - width: 1 diff --git a/libopencm3/scripts/data/lpc43xx/yaml_odict.py b/libopencm3/scripts/data/lpc43xx/yaml_odict.py deleted file mode 100644 index 05aa269..0000000 --- a/libopencm3/scripts/data/lpc43xx/yaml_odict.py +++ /dev/null @@ -1,81 +0,0 @@ -import yaml -from collections import OrderedDict -def construct_odict(load, node): - """This is the same as SafeConstructor.construct_yaml_omap(), - except the data type is changed to OrderedDict() and setitem is - used instead of append in the loop. - - >>> yaml.load(''' - ... !!omap - ... - foo: bar - ... - mumble: quux - ... - baz: gorp - ... ''') - OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) - - >>> yaml.load('''!!omap [ foo: bar, mumble: quux, baz : gorp ]''') - OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) - """ - - omap = OrderedDict() - yield omap - if not isinstance(node, yaml.SequenceNode): - raise yaml.constructor.ConstructorError( - "while constructing an ordered map", - node.start_mark, - "expected a sequence, but found %s" % node.id, node.start_mark - ) - for subnode in node.value: - if not isinstance(subnode, yaml.MappingNode): - raise yaml.constructor.ConstructorError( - "while constructing an ordered map", node.start_mark, - "expected a mapping of length 1, but found %s" % subnode.id, - subnode.start_mark - ) - if len(subnode.value) != 1: - raise yaml.constructor.ConstructorError( - "while constructing an ordered map", node.start_mark, - "expected a single mapping item, but found %d items" % len(subnode.value), - subnode.start_mark - ) - key_node, value_node = subnode.value[0] - key = load.construct_object(key_node) - value = load.construct_object(value_node) - omap[key] = value - -yaml.add_constructor(u'tag:yaml.org,2002:omap', construct_odict) - -def repr_pairs(dump, tag, sequence, flow_style=None): - """This is the same code as BaseRepresenter.represent_sequence(), - but the value passed to dump.represent_data() in the loop is a - dictionary instead of a tuple.""" - - value = [] - node = yaml.SequenceNode(tag, value, flow_style=flow_style) - if dump.alias_key is not None: - dump.represented_objects[dump.alias_key] = node - best_style = True - for (key, val) in sequence: - item = dump.represent_data({key: val}) - if not (isinstance(item, yaml.ScalarNode) and not item.style): - best_style = False - value.append(item) - if flow_style is None: - if dump.default_flow_style is not None: - node.flow_style = dump.default_flow_style - else: - node.flow_style = best_style - return node - -def repr_odict(dumper, data): - """ - >>> data = OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) - >>> yaml.dump(data, default_flow_style=False) - '!!omap\\n- foo: bar\\n- mumble: quux\\n- baz: gorp\\n' - >>> yaml.dump(data, default_flow_style=True) - '!!omap [foo: bar, mumble: quux, baz: gorp]\\n' - """ - return repr_pairs(dumper, u'tag:yaml.org,2002:omap', data.iteritems()) - -yaml.add_representer(OrderedDict, repr_odict) - diff --git a/libopencm3/scripts/gendoxylayout.py b/libopencm3/scripts/gendoxylayout.py deleted file mode 100755 index 2415495..0000000 --- a/libopencm3/scripts/gendoxylayout.py +++ /dev/null @@ -1,68 +0,0 @@ -#!/usr/bin/env python -# This python program generates parameters for the linker script generator feature. - -# This file is part of the libopencm3 project. -# -# 2019 Guillaume Revaillot -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -from xml.etree import ElementTree - -import argparse - - -parser = argparse.ArgumentParser(prog='gendoxylayout') -parser.add_argument("--template", required=True) -parser.add_argument("--out", required=True) -parser.add_argument("--target") -parser.add_argument("devices", nargs='*') -args = parser.parse_args() - -class CommentedTreeBuilder(ElementTree.TreeBuilder): - def __init__(self, *args, **kwargs): - super(CommentedTreeBuilder, self).__init__(*args, **kwargs) - - def comment(self, data): - self.start(ElementTree.Comment, {}) - self.data(data) - self.end(ElementTree.Comment) - -tree = ElementTree.parse(args.template, ElementTree.XMLParser(target=CommentedTreeBuilder())) -parent_map = {c:p for p in tree.iter() for c in p} -for element in tree.iter(tag=ElementTree.Comment): - if ("#devices#" in element.text): - idx = (list(parent_map[element]).index(element)) - for device in args.devices: - tab = ElementTree.Element('tab') - - tab.set("visible", "yes") - tab.set("title", str(device).upper()) - tab.set("intro", "") - - if (args.target != None): - if (device == args.target): - tab.set("type", "modules") - else: - tab.set("type", "user") - tab.set("url", "../../" + device + "/html/modules.html") - else: - tab.set("type", "user") - tab.set("url", "../" + device + "/html/modules.html") - - parent_map[element].insert(idx, tab) - idx = idx+1; - parent_map[element].remove(element) - -tree.write(args.out) diff --git a/libopencm3/scripts/gendoxylist b/libopencm3/scripts/gendoxylist deleted file mode 100755 index 108e2a9..0000000 --- a/libopencm3/scripts/gendoxylist +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh -# Karl Palsson Sept 2017 -# Parse .d files for a given target, and generate a doxygen config file -# stub that is to be "@INCLUDE = " into a doxygen template file. - -DDIR=$1 -ODIR=$2 -ONAME=doxy.sourcelist -IPATH=$(echo ${DDIR} | sed -e 's#../lib/##') - -PATH_DELTA=$(realpath --relative-to=${ODIR} ${DDIR}) - -printf "# This file is autogenerated by scripts/gendoxylist\n" > ${ODIR}/${ONAME} -printf "# All headers for core/platform, not always caught by .d file tracking\n" >> ${ODIR}/${ONAME} -UNTRACKED_DIRS="../include/libopencm3/cm3 ../include/libopencm3/${IPATH}" -for FN in $(find ${UNTRACKED_DIRS} -name '*.h' | sort); do - printf "INPUT += ../%s\n" "$FN" >> ${ODIR}/${ONAME} -done - -# There will be duplicates here, but doxygen doesn't mind. -printf "# Headers first\n" >> ${ODIR}/${ONAME} -grep -o '[^ ]*.h' ${DDIR}/*.d | grep 'include/libopencm3' | cut -d ':' -f2 | sort | uniq | sed "s#^#INPUT += ${PATH_DELTA}/#" >> ${ODIR}/${ONAME} - -printf "# Now sources\n" >> ${ODIR}/${ONAME} -grep -o '[^ ]*\.c' ${DDIR}/*.d | cut -d ':' -f 2 | sort | uniq | sed "s#^#INPUT += $PATH_DELTA/#" >> ${ODIR}/${ONAME} diff --git a/libopencm3/scripts/genlink.py b/libopencm3/scripts/genlink.py deleted file mode 100755 index 96c27e0..0000000 --- a/libopencm3/scripts/genlink.py +++ /dev/null @@ -1,125 +0,0 @@ -#!/usr/bin/env python -# This python program generates parameters for the linker script generator feature. - -# This file is part of the libopencm3 project. -# -# 2017 George-Cristian Jiglau -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . -from __future__ import print_function -import fnmatch -import sys -import re -import os - -if len(sys.argv) != 4: - print("usage: %s " % sys.argv[0], file=sys.stderr) - sys.exit(1) - -data_file_path = sys.argv[1] -find = sys.argv[2].lower() -mode = sys.argv[3].upper() - -device = { - 'info': {}, - 'defs': [], - 'family': [], -} - -# open device data file -with open(data_file_path, 'r') as data_file: - # iterate lines - for line in data_file: - # strip whitespace from the beginning and end of line - line = line.strip() - - # skip empty lines and comments - if line == '' or line.startswith('#'): - continue - - # split line into it's parts: - parts = line.split() - pattern, parent, data = parts[0], parts[1], parts[2:] - - # skip line if pattern did not match first element - if not fnmatch.fnmatch(find, pattern): - continue - - # extract data - for d in data: - # split into K=V - try: - (k, v) = d.split('=') - except: - continue - - # skip invalid datas - if not re.match('^[A-Z0-9_]+$', k): - continue - - # add FPU and CPU to info, not defs - if k in ('FPU', 'CPU'): - device['info'][k.lower()] = v - continue - - device['defs'].append((k, v)) - - # if parent is +, there's more data for this pattern - if parent == '+': - continue - - # device family - device['family'].append(find) - - # break if this was the last line in this chain - if parent == 'END': - break - - # look for the parent - find = parent - -# reverse device list -device['family'] = device['family'][::-1] - -# device was not found -if len(device['family']) == 0: - sys.exit(1) - -# for CPPFLAGS and DEFS, define device family -if mode in ('CPPFLAGS', 'DEFS'): - sys.stdout.write(' '.join('-D%s' % d.upper() for d in device['family'])) - -# defines -if mode == 'DEFS': - if len(device['defs']) > 0: - defs = ' '.join('-D_%s=%s' % d for d in device['defs']) - sys.stdout.write(' ' + defs) - -# device family -elif mode == 'FAMILY': - if len(device['family']) > 0: - sys.stdout.write(device['family'][0]) - -# device subfamily -elif mode == 'SUBFAMILY': - if len(device['family']) > 1: - sys.stdout.write(device['family'][1]) - -# device info -else: - info = mode.lower() - if info in device['info']: - sys.stdout.write(device['info'][info]) - -sys.stdout.flush() diff --git a/libopencm3/scripts/genlinktest.sh b/libopencm3/scripts/genlinktest.sh deleted file mode 100755 index 2c8d4a8..0000000 --- a/libopencm3/scripts/genlinktest.sh +++ /dev/null @@ -1,44 +0,0 @@ -#!/bin/sh - -# This script is intended to test the python program genlink.py for the linker -# script generator feature. -# -# See ld/README file for more info. -# - -# This file is part of the libopencm3 project. -# -# Copyright (C) 2013 Frantisek Burian -# Copyright (C) 2013 Werner Almesberger -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -# run test -DEVICE=`basename $1`; -(scripts/genlink.py $1.data $DEVICE CPPFLAGS; echo) > $1.out -(scripts/genlink.py $1.data $DEVICE DEFS; echo) >> $1.out -(scripts/genlink.py $1.data $DEVICE FAMILY; echo) >> $1.out -(scripts/genlink.py $1.data $DEVICE SUBFAMILY; echo) >> $1.out -(scripts/genlink.py $1.data $DEVICE CPU; echo) >> $1.out -(scripts/genlink.py $1.data $DEVICE FPU; echo) >> $1.out - -#check test -if ! diff -q $1.out $1.result >/dev/null; then - exit 1; -fi - -#remove workout only if it is OK -rm -f $1.out - -exit 0 diff --git a/libopencm3/scripts/irq2nvic_h b/libopencm3/scripts/irq2nvic_h deleted file mode 100755 index 8a1c355..0000000 --- a/libopencm3/scripts/irq2nvic_h +++ /dev/null @@ -1,177 +0,0 @@ -#!/usr/bin/env python - -# This file is part of the libopencm3 project. -# -# Copyright (C) 2012 chrysn -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -"""Generate an nvic.h header from a small JSON file describing the interrupt -numbers. - -Code generation is chosen here because the resulting C code needs to be very -repetetive (definition of the IRQ numbers, function prototypes, weak fallback -definition and vector table definition), all being very repetitive. No portable -method to achieve the same thing with C preprocessor is known to the author. -(Neither is any non-portable method, for that matter.)""" - -import sys -import os -import os.path -import json - -template_nvic_h = '''\ -/* This file is part of the libopencm3 project. - * - * It was generated by the irq2nvic_h script from {sourcefile} - */ - -#ifndef {includeguard} -#define {includeguard} - -#include - -/** @defgroup CM3_nvic_defines_irqs User interrupts for {partname_humanreadable} - @ingroup CM3_nvic_defines - - @{{*/ - -{irqdefinitions} - -#define NVIC_IRQ_COUNT {irqcount} - -/**@}}*/ - -/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} - @ingroup CM3_nvic_isrprototypes - - @{{*/ - -BEGIN_DECLS - -{isrprototypes} - -END_DECLS - -/**@}}*/ - -#endif /* {includeguard} */ -''' - -template_vector_nvic_c = '''\ -/* This file is part of the libopencm3 project. - * - * It was generated by the irq2nvic_h script. - * - * This part needs to get included in the compilation unit where - * blocking_handler gets defined due to the way #pragma works. - */ - - -/** @defgroup CM3_nvic_isrdecls_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} - @ingroup CM3_nvic_isrdecls - - @{{*/ - -{isrdecls} - -/**@}}*/ - -/* Initialization template for the interrupt vector table. This definition is - * used by the startup code generator (vector.c) to set the initial values for - * the interrupt handling routines to the chip family specific _isr weak - * symbols. */ - -#define IRQ_HANDLERS \\ - {vectortableinitialization} -''' - -template_cmsis_h = '''\ -/* This file is part of the libopencm3 project. - * - * It was generated by the irq2nvic_h script. - * - * These definitions bend every interrupt handler that is defined CMSIS style - * to the weak symbol exported by libopencm3. - */ - -{cmsisbends} -''' - -def convert(infile, outfile_nvic, outfile_vectornvic, outfile_cmsis): - data = json.load(infile) - - irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) - irqnames = [v for (k,v) in irq2name] - - if isinstance(data['irqs'], list): - data['irqcount'] = len(irq2name) - else: - data['irqcount'] = max([int(x) for x in data['irqs'].keys()]) + 1 - - data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),int(k)) for (k,v) in irq2name) - data['isrprototypes'] = "\n".join('void %s_isr(void);'%name.lower() for name in irqnames) - data['isrdecls'] = "\n".join('void %s_isr(void) __attribute__((weak, alias("blocking_handler")));'%name.lower() for name in irqnames) - data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - data['cmsisbends'] = "\n".join("#define %s_IRQHandler %s_isr"%(name.upper(), name.lower()) for name in irqnames) - data['sourcefile'] = infile.name - - outfile_nvic.write(template_nvic_h.format(**data)) - outfile_vectornvic.write(template_vector_nvic_c.format(**data)) - outfile_cmsis.write(template_cmsis_h.format(**data)) - -def makeparentdir(filename): - try: - os.makedirs(os.path.dirname(filename)) - except OSError: - # where is my 'mkdir -p'? - pass - -def needs_update(infiles, outfiles): - timestamp = lambda filename: os.stat(filename).st_mtime - return any(not os.path.exists(o) for o in outfiles) or max(map(timestamp, infiles)) > min(map(timestamp, outfiles)) - -def main(): - if sys.argv[1] == '--remove': - remove = True - del sys.argv[1] - else: - remove = False - infile = sys.argv[1] - if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.json'): - raise ValueError("Argument must match ./include/libopencm3/**/irq.json") - nvic_h = infile.replace('irq.json', 'nvic.h') - vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.json', 'vector_nvic.c') - cmsis = infile.replace('irq.json', 'irqhandlers.h').replace('/libopencm3/', '/libopencmsis/') - - if remove: - if os.path.exists(nvic_h): - os.unlink(nvic_h) - if os.path.exists(vector_nvic_c): - os.unlink(vector_nvic_c) - if os.path.exists(cmsis): - os.unlink(cmsis) - sys.exit(0) - - if not needs_update([__file__, infile], [nvic_h, vector_nvic_c]): - sys.exit(0) - - makeparentdir(nvic_h) - makeparentdir(vector_nvic_c) - makeparentdir(cmsis) - - convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'), open(cmsis, 'w')) - -if __name__ == "__main__": - main() diff --git a/libopencm3/scripts/lpcvtcksum b/libopencm3/scripts/lpcvtcksum deleted file mode 100755 index 27dc8a7..0000000 --- a/libopencm3/scripts/lpcvtcksum +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/python -# -# Compute and insert the vector table checksum required for booting the -# LPC43xx and some other NXP ARM microcontrollers. -# -# usage: lpcvtcksum firmware.bin -# -# This file is part of the libopencm3 project. -# -# Copyright (C) 2012 Michael Ossmann -# -# This library is free software: you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this library. If not, see . - -import sys, struct - -binfile = open(sys.argv[1], 'r+b') -rawvectors = binfile.read(32) -vectors = list(struct.unpack('. -## - -BOARD = efm32hg309-generic -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c -CFILES += delay_efm32.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/efm32/hg/efm32hg309f64.ld -OPENCM3_LIB = opencm3_efm32hg -OPENCM3_DEFS = -DEFM32HG -FP_FLAGS ?= -mfloat-abi=soft -ARCH_FLAGS = -mthumb -mcpu=cortex-m0plus $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2-1 -#OOCD_TARGET = efm32 -OOCD_FILE = openocd.efm32hg309-generic.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32f072disco b/libopencm3/tests/gadget-zero/Makefile.stm32f072disco deleted file mode 100644 index e155a52..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32f072disco +++ /dev/null @@ -1,44 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32f072disco -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/f0/stm32f07xzb.ld -OPENCM3_LIB = opencm3_stm32f0 -OPENCM3_DEFS = -DSTM32F0 -#FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ARCH_FLAGS = -mthumb -mcpu=cortex-m0 $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2 -#OOCD_TARGET = stm32f4x -OOCD_FILE = openocd.stm32f072disco.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32f103-generic b/libopencm3/tests/gadget-zero/Makefile.stm32f103-generic deleted file mode 100644 index a27dd60..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32f103-generic +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32f103-generic -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../../ - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/f1/stm32f103x8.ld -OPENCM3_LIB = opencm3_stm32f1 -OPENCM3_DEFS = -DSTM32F1 -ARCH_FLAGS = -mthumb -mcpu=cortex-m3 -#OOCD_INTERFACE = jlink -#OOCD_TARGET = stm32f1x -OOCD_FILE = openocd.stm32f103-generic.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32f3-disco b/libopencm3/tests/gadget-zero/Makefile.stm32f3-disco deleted file mode 100644 index 3a60392..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32f3-disco +++ /dev/null @@ -1,44 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32f3-disco -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/f3/stm32f303xc.ld -OPENCM3_LIB = opencm3_stm32f3 -OPENCM3_DEFS = -DSTM32F3 -FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ARCH_FLAGS = -mthumb -mcpu=cortex-m4 $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2 -#OOCD_TARGET = stm32f3x -OOCD_FILE = openocd.stm32f3-disco.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32f429i-disco b/libopencm3/tests/gadget-zero/Makefile.stm32f429i-disco deleted file mode 100644 index d1c432f..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32f429i-disco +++ /dev/null @@ -1,44 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32f429i-disco -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/f4/stm32f405x6.ld -OPENCM3_LIB = opencm3_stm32f4 -OPENCM3_DEFS = -DSTM32F4 -FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ARCH_FLAGS = -mthumb -mcpu=cortex-m4 $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2 -#OOCD_TARGET = stm32f4x -OOCD_FILE = openocd.$(BOARD).cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32f4disco b/libopencm3/tests/gadget-zero/Makefile.stm32f4disco deleted file mode 100644 index ca737cb..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32f4disco +++ /dev/null @@ -1,44 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32f4disco -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/f4/stm32f405x6.ld -OPENCM3_LIB = opencm3_stm32f4 -OPENCM3_DEFS = -DSTM32F4 -FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ARCH_FLAGS = -mthumb -mcpu=cortex-m4 $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2 -#OOCD_TARGET = stm32f4x -OOCD_FILE = openocd.stm32f4disco.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32l053disco b/libopencm3/tests/gadget-zero/Makefile.stm32l053disco deleted file mode 100644 index 9c79127..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32l053disco +++ /dev/null @@ -1,44 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32l053disco -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/l0/stm32l0xx8.ld -OPENCM3_LIB = opencm3_stm32l0 -OPENCM3_DEFS = -DSTM32L0 -#FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ARCH_FLAGS = -mthumb -mcpu=cortex-m0plus $(FP_FLAGS) -#OOCD_INTERFACE = stlink-v2-1 -#OOCD_TARGET = stm32l0 -OOCD_FILE = openocd.stm32l053disco.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.stm32l1-generic b/libopencm3/tests/gadget-zero/Makefile.stm32l1-generic deleted file mode 100644 index 9a410de..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.stm32l1-generic +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = stm32l1-generic -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -LDSCRIPT = ../../lib/stm32/l1/stm32l15xx8.ld -OPENCM3_LIB = opencm3_stm32l1 -OPENCM3_DEFS = -DSTM32L1 -ARCH_FLAGS = -mthumb -mcpu=cortex-m3 -#OOCD_INTERFACE = jlink -#OOCD_TARGET = stm32l1x -OOCD_FILE = openocd.stm32l1-generic.cfg - -include ../rules.mk diff --git a/libopencm3/tests/gadget-zero/Makefile.tilm4f120xl b/libopencm3/tests/gadget-zero/Makefile.tilm4f120xl deleted file mode 100644 index d458b33..0000000 --- a/libopencm3/tests/gadget-zero/Makefile.tilm4f120xl +++ /dev/null @@ -1,42 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -BOARD = tilm4f120xl -PROJECT = usb-gadget0-$(BOARD) -BUILD_DIR = bin-$(BOARD) - -SHARED_DIR = ../shared - -CFILES = main-$(BOARD).c -CFILES += usb-gadget0.c trace.c trace_stdio.c -#CFILES += delay.c - -VPATH += $(SHARED_DIR) - -INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR)) - -OPENCM3_DIR=../.. - -### This section can go to an arch shared rules eventually... -DEVICE=lm4f120xl -OOCD_FILE = openocd.$(BOARD).cfg - -include $(OPENCM3_DIR)/mk/genlink-config.mk -#include $(OPENCM3_DIR)/mk/gcc-config.mk -include $(OPENCM3_DIR)/mk/genlink-rules.mk -include ../rules.mk -#include $(OPENCM3_DIR)/mk/gcc-rules.mk diff --git a/libopencm3/tests/gadget-zero/README.md b/libopencm3/tests/gadget-zero/README.md deleted file mode 100644 index 564056e..0000000 --- a/libopencm3/tests/gadget-zero/README.md +++ /dev/null @@ -1,70 +0,0 @@ -This project, inspired by [usbtest](http://www.linux-usb.org/usbtest/) and -the linux usb gadget zero driver is used for regression testing changes to the -libopencm3 usb stack. - -The firmware itself is meant to be portable to any supported hardware, and then -identical unit test code is run against all platforms. This project can and -should be built for multiple devices. - -## Requirements: - * [pyusb](https://walac.github.io/pyusb/) for running the tests. - * [OpenOCD](http://openocd.org/) >= 0.9 for automated flashing of specific boards - * python3 for running the tests at the command line. - -### Building the device firmware -There are Makefile.xxxxx files for all the currently tested targets. -``` -make -f Makefile.stm32f4disco clean all V=1 -``` -The ```V=1``` is optional, and turns on verbose mode, which can be useful if -things don't work. This will give you a .elf file you can program using your -own toolchain, but if you have a functional OpenOCD installed, then... -``` -make -f Makefile.stm32f4disco clean all flash -``` -Will handle flashing as well. - -### Setting up the test runner (using python virtual environments) -``` -pyvenv .env # ensures a python3 virtual env -. .env/bin/activate -pip install pyusb -``` - -If you have multiple test boards connected, have a look at opencd.common.cfg -for some tips on selectively matching the right board. For people with just -a single matching board, you don't need to do anything. - -Tests marked as @unittest.skip are either for functionality that is known to be -broken, and are awaiting code fixes, or are long running performance tests - -### Access rights -On some systems (most linux systems) you probably won't have access to the -usb vendor id being used/hijacked by the test cases. See 70-libopencm3.rules -for installation instructions, or, if you have your own system, grant yourself -access to the usb vid: 0xcafe - -## Running the tests -Below is an example of running the full suite of tests from the command line. -The argument specifies the serial number to look for in the usb gadget, if -you have more than one. No argument will the tests against all -gadget-zero's found. -``` -$ python test_gadget0.py -Running tests for DUT: stm32f072disco -.........ss................ ----------------------------------------------------------------------- -Ran 27 tests in 0.388s - -OK (skipped=2) -``` - -To be even more brutal, run this in a shell loop. -``` -$ while true; do python test_gadget0.py stm32f072disco; done -``` - -You can also run individual tests, or individual sets of tests, see the [unittest documentation](https://docs.python.org/3/library/unittest.html) for more information. - -Many development environments, such as [PyCharm](https://www.jetbrains.com/pycharm/) can -also be used to edit and run the tests, in whole or individually, with a nice visual test runner. diff --git a/libopencm3/tests/gadget-zero/delay.c b/libopencm3/tests/gadget-zero/delay.c deleted file mode 100644 index 1fb369e..0000000 --- a/libopencm3/tests/gadget-zero/delay.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This file implements some simple busy timers. They are designed to be - * portable, not performant. - * TIM6 is appropriated for usage. - */ -#include -#include -#include - -#include "delay.h" - -void delay_setup(void) -{ - /* set up a microsecond free running timer for ... things... */ - rcc_periph_clock_enable(RCC_TIM6); - /* microsecond counter */ - timer_set_prescaler(TIM6, rcc_apb1_frequency / 1000000 - 1); - timer_set_period(TIM6, 0xffff); - timer_one_shot_mode(TIM6); -} - -void delay_us(uint16_t us) -{ - TIM_ARR(TIM6) = us; - TIM_EGR(TIM6) = TIM_EGR_UG; - TIM_CR1(TIM6) |= TIM_CR1_CEN; - //timer_enable_counter(TIM6); - while (TIM_CR1(TIM6) & TIM_CR1_CEN); -} - - diff --git a/libopencm3/tests/gadget-zero/delay.h b/libopencm3/tests/gadget-zero/delay.h deleted file mode 100644 index b091554..0000000 --- a/libopencm3/tests/gadget-zero/delay.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2017 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - - /** - * Initialize the timers used for delays. - */ - void delay_setup(void); - - /** - * busy wait for a number of usecs. - * @param us number of usecs to delay. - */ - void delay_us(uint16_t us); - -#ifdef __cplusplus -} -#endif \ No newline at end of file diff --git a/libopencm3/tests/gadget-zero/delay_efm32.c b/libopencm3/tests/gadget-zero/delay_efm32.c deleted file mode 100644 index 0e94d26..0000000 --- a/libopencm3/tests/gadget-zero/delay_efm32.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -#include "delay.h" - -extern const uint32_t ahb_frequency; - -void delay_setup(void) -{ - cmu_periph_clock_enable(CMU_TIMER2); - /* efm32hg doesn't support a nice 1us prescaler */ - timer_start(TIMER2); -} - -void delay_us(uint16_t us) -{ - volatile uint16_t time_now = 0; - /* Convert microseconds into timer ticks */ - uint16_t delay_ahb_cycles = us * (ahb_frequency / 1000000); - - TIMER2_CNT = 0; - while (time_now < delay_ahb_cycles) { - time_now = TIMER2_CNT; - } -} diff --git a/libopencm3/tests/gadget-zero/main-efm32hg309-generic.c b/libopencm3/tests/gadget-zero/main-efm32hg309-generic.c deleted file mode 100644 index 503ef19..0000000 --- a/libopencm3/tests/gadget-zero/main-efm32hg309-generic.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * Copyright (C) 2018 Seb Holzapfel - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include -#include - -#include -#include "usb-gadget0.h" - -/* no trace on cm0 #define ER_DEBUG */ -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -const uint32_t ahb_frequency = 14000000; - -#include "trace.h" -void trace_send_blocking8(int stimulus_port, char c) -{ - (void)stimulus_port; - (void)c; -} - -int main(void) -{ - usbd_device *usbd_dev = gadget0_init(&efm32hg_usb_driver, - "efm32hg309-generic"); - - ER_DPRINTF("bootup complete\n"); - - while (1) { - gadget0_run(usbd_dev); - } -} diff --git a/libopencm3/tests/gadget-zero/main-stm32f072disco.c b/libopencm3/tests/gadget-zero/main-stm32f072disco.c deleted file mode 100644 index 4ee02b8..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32f072disco.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include -#include - -#include -#include "usb-gadget0.h" - -/* no trace on cm0 #define ER_DEBUG */ -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -#include "trace.h" -void trace_send_blocking8(int stimulus_port, char c) -{ - (void)stimulus_port; - (void)c; -} - - -int main(void) -{ - rcc_clock_setup_in_hsi48_out_48mhz(); - crs_autotrim_usb_enable(); - rcc_set_usbclk_source(RCC_HSI48); - - /* LED on for boot progress */ - rcc_periph_clock_enable(RCC_GPIOC); - gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7); - gpio_set(GPIOC, GPIO7); - - usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver, - "stm32f072disco"); - - ER_DPRINTF("bootup complete\n"); - gpio_clear(GPIOC, GPIO7); - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32f103-generic.c b/libopencm3/tests/gadget-zero/main-stm32f103-generic.c deleted file mode 100644 index 5e701de..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32f103-generic.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -#include -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -int main(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - /* LED to indicate boot process */ - rcc_periph_clock_enable(RCC_GPIOC); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); - gpio_set(GPIOC, GPIO13); - - rcc_periph_clock_enable(RCC_GPIOA); - /* - * Vile hack to reenumerate, physically _drag_ d+ low. - * do NOT do this if you're board has proper usb pull up control! - * (need at least 2.5us to trigger usb disconnect) - */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - gpio_clear(GPIOA, GPIO12); - for (unsigned int i = 0; i < 800000; i++) { - __asm__("nop"); - } - - rcc_periph_clock_enable(RCC_OTGFS); - - - usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver, - "stm32f103-generic"); - - ER_DPRINTF("bootup complete\n"); - gpio_clear(GPIOC, GPIO13); - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32f3-disco.c b/libopencm3/tests/gadget-zero/main-stm32f3-disco.c deleted file mode 100644 index 4c8d3d0..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32f3-disco.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* "generic" could be any L1 board, but this file is pre-configured for the - * libopencm3-tests "hw1" board, with an stm32l151c8-A part. - */ - -#include -#include -#include -#include -#include - -#include -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -int main(void) -{ - rcc_periph_clock_enable(RCC_GPIOE); - gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO11|GPIO12); - gpio_set(GPIOE, GPIO12); - rcc_clock_setup_pll(&rcc_hse8mhz_configs[RCC_CLOCK_HSE8_72MHZ]); - - rcc_periph_clock_enable(RCC_GPIOA); - /* - * Vile hack to reenumerate, physically _drag_ d+ low. - * do NOT do this if you're board has proper usb pull up control! - * (need at least 2.5us to trigger usb disconnect) - */ - gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO12); - gpio_clear(GPIOA, GPIO12); - for (unsigned int i = 0; i < 800000; i++) { - __asm__("nop"); - } - /* now return PA11/PA12 to usb AF */ - gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11|GPIO12); - gpio_set_af(GPIOA, GPIO_AF14, GPIO11|GPIO12); - - usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver, - "stm32f3-disco"); - - ER_DPRINTF("bootup complete\n"); - gpio_clear(GPIOE, GPIO12); - static int i = 0; - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32f429i-disco.c b/libopencm3/tests/gadget-zero/main-stm32f429i-disco.c deleted file mode 100644 index 7d4fd8f..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32f429i-disco.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -#include -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -int main(void) -{ - rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); - rcc_periph_clock_enable(RCC_GPIOB); - rcc_periph_clock_enable(RCC_OTGHS); - - gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, - GPIO13 | GPIO14 | GPIO15); - gpio_set_af(GPIOB, GPIO_AF12, GPIO13 | GPIO14 | GPIO15); - - /* LEDS on discovery board */ - rcc_periph_clock_enable(RCC_GPIOD); - gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, - GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); - - usbd_device *usbd_dev = gadget0_init(&otghs_usb_driver, "stm32f429i-disco"); - - ER_DPRINTF("bootup complete\n"); - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32f4disco.c b/libopencm3/tests/gadget-zero/main-stm32f4disco.c deleted file mode 100644 index 37f901d..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32f4disco.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - -#include -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -int main(void) -{ - rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); - rcc_periph_clock_enable(RCC_GPIOA); - rcc_periph_clock_enable(RCC_OTGFS); - - gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12); - gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12); - - /* LEDS on discovery board */ - rcc_periph_clock_enable(RCC_GPIOD); - gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, - GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); - - usbd_device *usbd_dev = gadget0_init(&otgfs_usb_driver, "stm32f4disco"); - - ER_DPRINTF("bootup complete\n"); - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32l053disco.c b/libopencm3/tests/gadget-zero/main-stm32l053disco.c deleted file mode 100644 index c90d739..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32l053disco.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include -#include -#include - -#include -#include "usb-gadget0.h" - -/* no trace on cm0 #define ER_DEBUG */ -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -#include "trace.h" -void trace_send_blocking8(int stimulus_port, char c) -{ - (void)stimulus_port; - (void)c; -} - -int main(void) -{ - /* LED for boot progress */ - rcc_periph_clock_enable(RCC_GPIOA); - gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5); - gpio_set(GPIOA, GPIO5); - - /* PLL from HSI16, just to exercise that code */ - struct rcc_clock_scale myclock = { - .ahb_frequency = 32e6, - .apb1_frequency = 32e6, - .apb2_frequency = 32e6, - .flash_waitstates = 1, - .pll_source = RCC_CFGR_PLLSRC_HSI16_CLK, /* not even sure there's hse on l053 disco */ - /* .msi_range doesn't matter */ - .pll_mul = RCC_CFGR_PLLMUL_MUL4, - .pll_div = RCC_CFGR_PLLDIV_DIV2, - .hpre = RCC_CFGR_HPRE_NODIV, - .ppre1 = RCC_CFGR_PPRE1_NODIV, - .ppre2 = RCC_CFGR_PPRE2_NODIV, - }; - rcc_clock_setup_pll(&myclock); - - /* HSI48 needs the vrefint turned on */ - rcc_periph_clock_enable(RCC_SYSCFG); - SYSCFG_CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT; - while (!(SYSCFG_CFGR3 & SYSCFG_CFGR3_REF_HSI48_RDYF)); - - /* For USB, but can't use HSI48 as a sysclock on L0 */ - crs_autotrim_usb_enable(); - rcc_set_hsi48_source_rc48(); - - rcc_osc_on(RCC_HSI48); - rcc_wait_for_osc_ready(RCC_HSI48); - - usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver, - "stm32l053disco"); - - ER_DPRINTF("bootup complete\n"); - gpio_clear(GPIOA, GPIO5); - while (1) { - gadget0_run(usbd_dev); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-stm32l1-generic.c b/libopencm3/tests/gadget-zero/main-stm32l1-generic.c deleted file mode 100644 index 7e56c8e..0000000 --- a/libopencm3/tests/gadget-zero/main-stm32l1-generic.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* "generic" could be any L1 board, but this file is pre-configured for the - * libopencm3-tests "hw1" board, with an stm32l151c8-A part. - */ - -#include -#include -#include -#include -#include - -#include -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -const struct rcc_clock_scale this_clock_config = { - /* 32MHz PLL from 16MHz HSE, 96MHz for USB on PLL VCO out */ - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .pll_mul = RCC_CFGR_PLLMUL_MUL6, - .pll_div = RCC_CFGR_PLLDIV_DIV3, - .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, - .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, - .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, - .voltage_scale = PWR_SCALE1, - .flash_waitstates = 1, - .ahb_frequency = 32000000, - .apb1_frequency = 32000000, - .apb2_frequency = 32000000, - }; - - -int main(void) -{ - rcc_periph_clock_enable(RCC_GPIOB); - gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO8|GPIO9); - gpio_set(GPIOB, GPIO8); - rcc_clock_setup_pll(&this_clock_config); - - /* Enable built in USB pullup on L1 */ - rcc_periph_clock_enable(RCC_SYSCFG); - SYSCFG_PMC |= SYSCFG_PMC_USB_PU; - - usbd_device *usbd_dev = gadget0_init(&st_usbfs_v1_usb_driver, - "stm32l1-generic"); - - ER_DPRINTF("bootup complete\n"); - gpio_clear(GPIOB, GPIO8); - while (1) { - gpio_set(GPIOB, GPIO9); - gadget0_run(usbd_dev); - gpio_clear(GPIOB, GPIO9); - } - -} - diff --git a/libopencm3/tests/gadget-zero/main-tilm4f120xl.c b/libopencm3/tests/gadget-zero/main-tilm4f120xl.c deleted file mode 100644 index 7d9e78d..0000000 --- a/libopencm3/tests/gadget-zero/main-tilm4f120xl.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2018 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include -#include - -#include -#include "delay.h" -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - - -/* FIXME - implement delay functionality for better test coverage */ -void delay_setup(void) { -} - -void delay_us(uint16_t us) { - (void)us; -} - -int main(void) -{ - gpio_enable_ahb_aperture(); -#define PLL_DIV_80MHZ 5 - rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLL_DIV_80MHZ); - periph_clock_enable(RCC_GPIOD); - gpio_mode_setup(GPIOD, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4 | GPIO5); - - /* blue LED on board */ - periph_clock_enable(RCC_GPIOF); - gpio_mode_setup(GPIOF, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO2); - gpio_set_output_config(GPIOF, GPIO_OTYPE_PP, GPIO_DRIVE_2MA, GPIO2); - - usbd_device *usbd_dev = gadget0_init(&lm4f_usb_driver, "tilm4f120xl"); - - ER_DPRINTF("bootup complete\n"); - while (1) { - gpio_set(GPIOF, GPIO2); - gadget0_run(usbd_dev); - gpio_clear(GPIOF, GPIO2); - } - -} - diff --git a/libopencm3/tests/gadget-zero/openocd.common.cfg b/libopencm3/tests/gadget-zero/openocd.common.cfg deleted file mode 100644 index b601cde..0000000 --- a/libopencm3/tests/gadget-zero/openocd.common.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# Shared openocd script helpers - -# put things like "hla_serial 'asdfadfa'" in openocd..local.cfg to support -# multiple simultaneously connected boards. -proc optional_local { LOCAL_FILE } { - if { [ file exists $LOCAL_FILE ] } { - puts "Loading custom local settings from $LOCAL_FILE" - source $LOCAL_FILE - } -} diff --git a/libopencm3/tests/gadget-zero/openocd.efm32hg309-generic.cfg b/libopencm3/tests/gadget-zero/openocd.efm32hg309-generic.cfg deleted file mode 100644 index 39d2c03..0000000 --- a/libopencm3/tests/gadget-zero/openocd.efm32hg309-generic.cfg +++ /dev/null @@ -1,14 +0,0 @@ -# Generic efm32hg309 on Tomu board, using stm32l053-disco as debugger -source [find interface/stlink-v2-1.cfg] -transport select hla_swd -adapter_khz 1000 -set CHIPNAME efm32hg309 -set CPUTAPID 0x0bc11477 -source [find target/efm32.cfg] - -source openocd.common.cfg -optional_local "openocd.efm32hg309-generic.local.cfg" - -init -targets -reset halt diff --git a/libopencm3/tests/gadget-zero/openocd.stm32f072disco.cfg b/libopencm3/tests/gadget-zero/openocd.stm32f072disco.cfg deleted file mode 100644 index b7cc25b..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32f072disco.cfg +++ /dev/null @@ -1,14 +0,0 @@ -source [find interface/stlink-v2.cfg] -set WORKAREASIZE 0x4000 -source [find target/stm32f0x.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32f072disco.local.cfg" - -# no trace on cm0 -#tpiu config internal swodump.stm32f4disco.log uart off 168000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32f103-generic.cfg b/libopencm3/tests/gadget-zero/openocd.stm32f103-generic.cfg deleted file mode 100644 index c4d1183..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32f103-generic.cfg +++ /dev/null @@ -1,15 +0,0 @@ -# Unfortunately, with no f103 disco, we're currently -# using a separate disco board -source [find interface/stlink-v2.cfg] -set WORKAREASIZE 0x2000 -source [find target/stm32f1x.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32f103-generic.local.cfg" - -tpiu config internal swodump.stm32f103-generic.log uart off 72000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32f3-disco.cfg b/libopencm3/tests/gadget-zero/openocd.stm32f3-disco.cfg deleted file mode 100644 index 835d466..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32f3-disco.cfg +++ /dev/null @@ -1,13 +0,0 @@ -source [find interface/stlink-v2.cfg] -set WORKAREASIZE 0x4000 -source [find target/stm32f3x.cfg] - -# serial of my f3 disco board. -hla_serial "S?n\x06gePQ6G%g" - -tpiu config internal swodump.stm32f3-disco.log uart off 72000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32f429i-disco.cfg b/libopencm3/tests/gadget-zero/openocd.stm32f429i-disco.cfg deleted file mode 100644 index a0b99e6..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32f429i-disco.cfg +++ /dev/null @@ -1,13 +0,0 @@ -source [find interface/stlink-v2.cfg] -set WORKAREASIZE 0x4000 -source [find target/stm32f4x.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32f429i-disco.local.cfg" - -tpiu config internal swodump.stm32f429i-disco.log uart off 168000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32f4disco.cfg b/libopencm3/tests/gadget-zero/openocd.stm32f4disco.cfg deleted file mode 100644 index f2f5406..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32f4disco.cfg +++ /dev/null @@ -1,13 +0,0 @@ -source [find interface/stlink-v2.cfg] -set WORKAREASIZE 0x4000 -source [find target/stm32f4x.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32f4disco.local.cfg" - -tpiu config internal swodump.stm32f4disco.log uart off 168000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32l053disco.cfg b/libopencm3/tests/gadget-zero/openocd.stm32l053disco.cfg deleted file mode 100644 index b1173e0..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32l053disco.cfg +++ /dev/null @@ -1,14 +0,0 @@ -source [find interface/stlink-v2-1.cfg] -set WORKAREASIZE 0x1000 -source [find target/stm32l0.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32l053disco.local.cfg" - -# no trace on cm0 -#tpiu config internal swodump.stm32f4disco.log uart off 168000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst - diff --git a/libopencm3/tests/gadget-zero/openocd.stm32l1-generic.cfg b/libopencm3/tests/gadget-zero/openocd.stm32l1-generic.cfg deleted file mode 100644 index 33b032e..0000000 --- a/libopencm3/tests/gadget-zero/openocd.stm32l1-generic.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# l1 generic, using a l4 disco board -source [find interface/stlink-v2-1.cfg] -set WORKAREASIZE 0x2000 -source [find target/stm32l1.cfg] - -source openocd.common.cfg -optional_local "openocd.stm32l1-generic.local.cfg" - -tpiu config internal swodump.stm32l1-generic.log uart off 32000000 - -# Uncomment to reset on connect, for grabbing under WFI et al -reset_config srst_only srst_nogate -# reset_config srst_only srst_nogate connect_assert_srst diff --git a/libopencm3/tests/gadget-zero/stub.py b/libopencm3/tests/gadget-zero/stub.py deleted file mode 100644 index de0439e..0000000 --- a/libopencm3/tests/gadget-zero/stub.py +++ /dev/null @@ -1,4 +0,0 @@ -__author__ = 'karlp' - -def config_switch(): - pass diff --git a/libopencm3/tests/gadget-zero/test_gadget0.py b/libopencm3/tests/gadget-zero/test_gadget0.py deleted file mode 100644 index 064545f..0000000 --- a/libopencm3/tests/gadget-zero/test_gadget0.py +++ /dev/null @@ -1,508 +0,0 @@ -import array -import datetime -import random -import usb.core -import usb.util as uu -import random -import sys - -import unittest - -VENDOR_ID=0xcafe -PRODUCT_ID=0xcafe - -# you only need to worry about these if you are trying to explicitly test -# a single target. Normally, the test will autofind the attached target -#DUT_SERIAL = "stm32f429i-disco" -DUT_SERIAL = "stm32f4disco" -#DUT_SERIAL = "stm32f103-generic" -#DUT_SERIAL = "stm32l1-generic" -#DUT_SERIAL = "stm32f072disco" -#DUT_SERIAL = "stm32l053disco" - -GZ_REQ_SET_PATTERN=1 -GZ_REQ_PRODUCE=2 -GZ_REQ_SET_ALIGNED=3 -GZ_REQ_SET_UNALIGNED=4 -GZ_REQ_WRITE_LOOPBACK_BUFFER=10 -GZ_REQ_READ_LOOPBACK_BUFFER=11 -GZ_REQ_INTEL_WRITE=0x5b -GZ_REQ_INTEL_READ=0x5c - -class find_by_serial(object): - def __init__(self, serial): - self._serial = serial - - def __call__(self, device): - return usb.util.get_string(device, device.iSerialNumber) - - -class TestGadget0(unittest.TestCase): - # TODO - parameterize this with serial numbers so we can find - # gadget 0 code for different devices. (or use different PIDs?) - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - self.longMessage = True - - def tearDown(self): - uu.dispose_resources(self.dev) - - def test_sanity(self): - self.assertEqual(2, self.dev.bNumConfigurations, "Should have 2 configs") - - def test_config_switch_2(self): - """ - Uses the API if you're interested in the cfg block - """ - cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(cfg, "Config 2 should exist") - self.dev.set_configuration(cfg) - - def test_config_switch_3(self): - """ - Uses the simple API - """ - self.dev.set_configuration(3) - - def test_config_zero_addressed(self): - self.dev.set_configuration(0) - x = self.dev.ctrl_transfer(0x80, 0x08, 0, 0, 1) - self.assertEqual(0, x[0], "Should be configuration 0 before configuration is set") - - - def test_fetch_config(self): - self.dev.set_configuration(3) - # FIXME - find a way to get the defines for these from pyusb - x = self.dev.ctrl_transfer(0x80, 0x08, 0, 0, 1) - self.assertEqual(3, x[0], "Should get the actual bConfigurationValue back") - - def test_invalid_config(self): - try: - # FIXME - find a way to get the defines for these from pyusb - self.dev.ctrl_transfer(0x00, 0x09, 99) - self.fail("Request of invalid cfg should have failed") - except usb.core.USBError as e: - # Note, this might not be as portable as we'd like. - self.assertIn("Pipe", e.strerror) - -class TestIntelCompliance(unittest.TestCase): - """ - Part of intel's usb 2.0 compliance is writing and reading back control transfers - """ - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(self.cfg, "Config 2 should exist") - self.dev.set_configuration(self.cfg) - - def tearDown(self): - uu.dispose_resources(self.dev) - - def inner_t(self, mylen): - data = [random.randrange(255) for x in range(mylen)] - written = self.dev.ctrl_transfer(uu.CTRL_OUT | uu.CTRL_RECIPIENT_INTERFACE | uu.CTRL_TYPE_VENDOR, GZ_REQ_INTEL_WRITE, 0, 0, data) - self.assertEqual(written, len(data), "Should have written all bytes plz") - # now. in _theory_ I should be able to make a bulk transfer here and have it not "interfere" - # fixme - try this out? - read = self.dev.ctrl_transfer(uu.CTRL_IN | uu.CTRL_RECIPIENT_INTERFACE | uu.CTRL_TYPE_VENDOR, GZ_REQ_INTEL_READ, 0, 0, mylen) - self.assertEqual(mylen, len(read)) - expected = array.array('B', [x for x in data]) - self.assertEqual(expected, read, "should have read back what we wrote") - - def test_ctrl_loopbacks(self): - self.inner_t(0) - self.inner_t(10) - self.inner_t(63) - self.inner_t(64) - self.inner_t(65) - self.inner_t(140) - self.inner_t(183) - - -class TestConfigSourceSink(unittest.TestCase): - """ - We could inherit, but it doesn't save much, and this saves me from remembering how to call super. - """ - - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(self.cfg, "Config 2 should exist") - self.dev.set_configuration(self.cfg) - self.intf = self.cfg[(0, 0)] - # heh, kinda gross... - self.ep_out = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_OUT][0] - self.ep_in = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_IN][0] - - def tearDown(self): - uu.dispose_resources(self.dev) - - def test_write_simple(self): - """ - here we go, start off with just a simple write of < bMaxPacketSize and just make sure it's accepted - :return: - """ - data = [x for x in range(int(self.ep_out.wMaxPacketSize / 2))] - written = self.dev.write(self.ep_out, data) - self.assertEqual(written, len(data), "Should have written all bytes plz") - - def test_write_zlp(self): - written = self.ep_out.write([]) - self.assertEqual(0, written, "should have written zero for a zero length write y0") - - def test_write_batch(self): - """ - Write 50 max sized packets. Should not stall. Will stall if firmware isn't consuming data properly - :return: - """ - for i in range(50): - data = [x for x in range(int(self.ep_out.wMaxPacketSize))] - written = self.dev.write(self.ep_out, data) - self.assertEqual(written, len(data), "Should have written all bytes plz") - - def test_write_mixed(self): - for i in range(int(self.ep_out.wMaxPacketSize / 4), self.ep_out.wMaxPacketSize * 10, 11): - data = [x & 0xff for x in range(i)] - written = self.ep_out.write(data) - self.assertEqual(written, len(data), "should have written all bytes plz") - - def test_read_zeros(self): - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 0) - self.ep_in.read(self.ep_in.wMaxPacketSize) # Clear out any prior pattern data - # unless, you know _exactly_ how much will be written by the device, always read - # an integer multiple of max packet size, to avoid overflows. - # the returned data will have the actual length. - # You can't just magically read out less than the device wrote. - read_size = self.ep_in.wMaxPacketSize * 10 - data = self.dev.read(self.ep_in, read_size) - self.assertEqual(len(data), read_size, "Should have read as much as we asked for") - expected = array.array('B', [0 for x in range(read_size)]) - self.assertEqual(data, expected, "In pattern 0, all source data should be zeros: ") - - def test_read_sequence(self): - # switching to the mod63 pattern requires resynching carefully to read out any zero frames already - # queued, but still make sure we start the sequence at zero. - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 1) - self.ep_in.read(self.ep_in.wMaxPacketSize) # Potentially queued zeros, or would have been safe. - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 1) - self.ep_in.read(self.ep_in.wMaxPacketSize) # definitely right pattern now, but need to restart at zero. - read_size = self.ep_in.wMaxPacketSize * 3 - data = self.dev.read(self.ep_in, read_size) - self.assertEqual(len(data), read_size, "Should have read as much as we asked for") - expected = array.array('B', [x % 63 for x in range(read_size)]) - self.assertEqual(data, expected, "In pattern 1, Should be % 63") - - def test_read_write_interleaved(self): - for i in range(1, 20): - ii = self.ep_in.read(self.ep_in.wMaxPacketSize * i) - dd = [x & 0xff for x in range(i * 20 + 3)] - oo = self.ep_out.write(dd) - self.assertEqual(len(ii), self.ep_in.wMaxPacketSize * i, "should have read full packet") - self.assertEqual(oo, len(dd), "should have written full packet") - - def test_control_known(self): - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 0) - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 1) - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 99) - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, GZ_REQ_SET_PATTERN, 0) - - def test_control_unknown(self): - try: - self.dev.ctrl_transfer(uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE, 42, 69) - self.fail("Should have got a stall") - except usb.core.USBError as e: - # Note, this might not be as portable as we'd like. - self.assertIn("Pipe", e.strerror) - - -class TestConfigLoopBack(unittest.TestCase): - """ - We could inherit, but it doesn't save much, and this saves me from remembering how to call super. - """ - - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=3) - self.assertIsNotNone(self.cfg, "Config 3 should exist") - self.dev.set_configuration(self.cfg) - self.intf = self.cfg[(0, 0)] - # heh, kinda gross... - self.eps_out = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_OUT] - self.eps_in = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_IN] - - def tearDown(self): - uu.dispose_resources(self.dev) - - def _inner_basic(self, ep_out, ep_in, data): - written = self.dev.write(ep_out, data) - self.assertEqual(written, len(data), "Should have written all bytes plz") - read = self.dev.read(ep_in, len(data)) - self.assertEqual(len(data), len(read)) - expected = array.array('B', [x for x in data]) - self.assertEqual(expected, read, "should have read back what we wrote") - - - def test_simple_loop(self): - """Plain simple loopback, does it work at all""" - eout = self.eps_out[0] - ein = self.eps_in[0] - data = [random.randrange(255) for _ in range(eout.wMaxPacketSize)] - self._inner_basic(eout, ein, data) - - def test_dual_loop(self): - """Testing that we don't mix our data up, just plain and simple""" - dlen = self.eps_out[0].wMaxPacketSize - data = [ - [0xaa for _ in range(dlen)], - [0xbb for _ in range(dlen)], - ] - for epo, epi, data in zip(self.eps_out, self.eps_in, data): - self._inner_basic(epo, epi, data) - - def test_dual_loop_back_to_back(self): - """ - write to both, _before_ we read back... - This can expose problems with buffer management - """ - dlen = self.eps_out[0].wMaxPacketSize - data = [ - [0xaa for _ in range(dlen)], - [0xbb for _ in range(dlen)], - ] - written = [ - self.dev.write(self.eps_out[0], data[0]), - self.dev.write(self.eps_out[1], data[1]), - ] - read = [ - self.dev.read(self.eps_in[0], dlen), - self.dev.read(self.eps_in[1], dlen), - ] - - for w, r, dat in zip(written, read, data): - self.assertEqual(w, len(dat), "Should have written all bytes plz") - self.assertEqual(len(dat), len(r), "Should have read back same size") - expected = array.array('B', [x for x in dat]) - self.assertEqual(expected, r, "should have read back what we wrote") - - -@unittest.skip("Perf tests only on demand (comment this line!)") -class TestConfigSourceSinkPerformance(unittest.TestCase): - """ - Read/write throughput, roughly - """ - - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(self.cfg, "Config 2 should exist") - self.dev.set_configuration(self.cfg) - self.intf = self.cfg[(0, 0)] - # heh, kinda gross... - self.ep_out = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_OUT][0] - self.ep_in = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_IN][0] - - def tearDown(self): - uu.dispose_resources(self.dev) - - def tput(self, xc, te): - return (xc / 1024 / max(1, te.seconds + te.microseconds / - 1000000.0)) - - def test_read_perf(self): - # I get around 990kps here... - ts = datetime.datetime.now() - rxc = 0 - while rxc < 5 * 1024 * 1024: - desired = 100 * 1024 - data = self.ep_in.read(desired, timeout=0) - self.assertEqual(desired, len(data), "Should have read all bytes plz") - rxc += len(data) - te = datetime.datetime.now() - ts - print("read %s bytes in %s for %s kps" % (rxc, te, self.tput(rxc, te))) - - def test_write_perf(self): - # caps out around 420kps? - ts = datetime.datetime.now() - txc = 0 - data = [x & 0xff for x in range(100 * 1024)] - while txc < 5 * 1024 * 1024: - w = self.ep_out.write(data, timeout=0) - self.assertEqual(w, len(data), "Should have written all bytes plz") - txc += w - te = datetime.datetime.now() - ts - print("wrote %s bytes in %s for %s kps" % (txc, te, self.tput(txc, te))) - - -class TestControlTransfer_Reads(unittest.TestCase): - """ - https://github.com/libopencm3/libopencm3/pull/194 - and - https://github.com/libopencm3/libopencm3/pull/505 - """ - - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(self.cfg, "Config 2 should exist") - self.dev.set_configuration(self.cfg) - self.req = uu.CTRL_IN | uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE - - def inner_t(self, wVal, read_len): - wVal = int(wVal) - read_len = int(read_len) - q = self.dev.ctrl_transfer(self.req, GZ_REQ_PRODUCE, wVal, 0, read_len) - self.assertEqual(len(q), wVal, "Should have read as much as we asked for?") - - def tearDown(self): - uu.dispose_resources(self.dev) - - def test_basic(self): - x = self.dev.ctrl_transfer(self.req, GZ_REQ_PRODUCE, 32, 0, 32) - self.assertEqual(32, len(x)) - - def test_matching_sizes(self): - """ - Can we request x control in when we tell the device to produce x? - :return: - """ - def inner(x): - x = int(x) - q = self.dev.ctrl_transfer(self.req, GZ_REQ_PRODUCE, x, 0, x) - self.assertEqual(len(q), x, "Should have read as much as we asked for") - - ep0_size = self.dev.bMaxPacketSize0 - inner(ep0_size) - inner(ep0_size * 3) - inner(ep0_size / 3) - inner(ep0_size - 7) - inner(ep0_size + 11) - inner(ep0_size * 4 + 11) - - def test_waytoobig(self): - """ - monster reads should fail, but not fatally. - (Don't make them too, big, or libusb will reject you outright, see MAX_CTRL_BUFFER_LENGTH in libusb sources) - """ - try: - self.dev.ctrl_transfer(self.req, GZ_REQ_PRODUCE, 10 * self.dev.bMaxPacketSize0, 0, 10 * self.dev.bMaxPacketSize0) - self.fail("Should have got a stall") - except usb.core.USBError as e: - # Note, this might not be as portable as we'd like. - self.assertIn("Pipe", e.strerror) - - def test_read_longer(self): - """ - Attempt to read more than the device replied with. - This is explicitly allowed by spec: - "On an input request, a device must never return more data than is indicated - by the wLength value; it may return less" - """ - - ep0_size = self.dev.bMaxPacketSize0 - self.inner_t(ep0_size / 2, ep0_size) - self.inner_t(ep0_size / 2, ep0_size * 2) - self.inner_t(ep0_size + 31, ep0_size * 5) - - def test_read_needs_zlp(self): - ep0_size = self.dev.bMaxPacketSize0 - self.inner_t(ep0_size, ep0_size + 10) - self.inner_t(ep0_size * 2, ep0_size * 5) - - def test_read_zero(self): - """ - try and read > 0, but have the device only produce 0 - """ - self.inner_t(0, self.dev.bMaxPacketSize0) - self.inner_t(0, 200) - - def test_read_nothing(self): - """ - Don't read anything, don't create anything (no data stage) - """ - self.inner_t(0, 0) - - def test_mean_limits(self): - """ - tell the device to produce more than we ask for. - Note, this doesn't test the usb stack, it tests the application code behaves. - """ - q = self.dev.ctrl_transfer(self.req, GZ_REQ_PRODUCE, 100, 0, 10) - self.assertEqual(len(q), 10, "In this case, should have gotten wLen back") - - -class TestUnaligned(unittest.TestCase): - """ - M0 and M0+ cores don't support unaligned memory accesses. These test - how the stack behaves with aligned vs unaligned buffers. - https://github.com/libopencm3/libopencm3/issues/401 - https://github.com/libopencm3/libopencm3/issues/461 - """ - - def setUp(self): - self.dev = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, custom_match=find_by_serial(DUT_SERIAL)) - self.assertIsNotNone(self.dev, "Couldn't find locm3 gadget0 device") - - self.cfg = uu.find_descriptor(self.dev, bConfigurationValue=2) - self.assertIsNotNone(self.cfg, "Config 2 should exist") - self.dev.set_configuration(self.cfg); - self.req = uu.CTRL_OUT | uu.CTRL_TYPE_VENDOR | uu.CTRL_RECIPIENT_INTERFACE - self.intf = self.cfg[(0, 0)] - # heh, kinda gross... - self.ep_out = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_OUT][0] - self.ep_in = [ep for ep in self.intf if uu.endpoint_direction(ep.bEndpointAddress) == uu.ENDPOINT_IN][0] - - def tearDown(self): - uu.dispose_resources(self.dev) - - def set_unaligned(self): - # GZ_REQ_SET_UNALIGNED - self.dev.ctrl_transfer(self.req, GZ_REQ_SET_UNALIGNED, 0, 0) - - def set_aligned(self): - # GZ_REQ_SET_ALIGNED - self.dev.ctrl_transfer(self.req, GZ_REQ_SET_ALIGNED, 0, 0) - - def do_readwrite(self): - """ - transfer garbage data to/from bulk EP; alignment issues will hardfault the target - """ - data = [x for x in range(int(self.ep_out.wMaxPacketSize / 2))] - written = self.dev.write(self.ep_out, data) - self.assertEqual(written, len(data), "Should have written all bytes plz") - - read_size = self.ep_in.wMaxPacketSize * 10 - data = self.dev.read(self.ep_in, read_size) - self.assertEqual(len(data), read_size, "Should have read as much as we asked for") - - def test_aligned(self): - self.set_aligned() - self.do_readwrite() - - def test_unaligned(self): - self.set_unaligned() - self.do_readwrite() - - -if __name__ == "__main__": - if len(sys.argv) > 1: - DUT_SERIAL = sys.argv.pop() - print("Running tests for DUT: ", DUT_SERIAL) - unittest.main() - else: - # scan for available and try them all! - devs = usb.core.find(idVendor=VENDOR_ID, idProduct=PRODUCT_ID, find_all=True) - for dev in devs: - DUT_SERIAL = dev.serial_number - print("Running tests for DUT: ", DUT_SERIAL) - unittest.main(exit=False) diff --git a/libopencm3/tests/gadget-zero/usb-gadget0.c b/libopencm3/tests/gadget-zero/usb-gadget0.c deleted file mode 100644 index 6e98143..0000000 --- a/libopencm3/tests/gadget-zero/usb-gadget0.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* - * This file implements linux's "Gadget zero" functionality, both the - * "source sink" functional interface, and the "loopback" interface. - * It _only_ uses usb includes, do _not_ include any target specific code here! - */ -#include -#include -#include -#include - -#include "trace.h" -#include "delay.h" -#include "usb-gadget0.h" - -#define ER_DEBUG -#ifdef ER_DEBUG -#include -#define ER_DPRINTF(fmt, ...) \ - do { printf(fmt, ## __VA_ARGS__); } while (0) -#else -#define ER_DPRINTF(fmt, ...) \ - do { } while (0) -#endif - -/* - * USB Vendor:Interface control requests. - */ -#define GZ_REQ_SET_PATTERN 1 -#define GZ_REQ_PRODUCE 2 -#define GZ_REQ_SET_ALIGNED 3 -#define GZ_REQ_SET_UNALIGNED 4 -#define INTEL_COMPLIANCE_WRITE 0x5b -#define INTEL_COMPLIANCE_READ 0x5c - -/* USB configurations */ -#define GZ_CFG_SOURCESINK 2 -#define GZ_CFG_LOOPBACK 3 - -#define BULK_EP_MAXPACKET 64 - -static const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = USB_CLASS_VENDOR, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = BULK_EP_MAXPACKET, - - /* when we're compatible with gadget 0 - * #define DRIVER_VENDOR_NUM 0x0525 - * #define DRIVER_PRODUCT_NUM 0xa4a0 - */ - .idVendor = 0xcafe, - .idProduct = 0xcafe, - .bcdDevice = 0x0001, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 2, -}; - -static const struct usb_endpoint_descriptor endp_bulk[] = { - { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x01, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = BULK_EP_MAXPACKET, - .bInterval = 1, - }, - { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x81, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = BULK_EP_MAXPACKET, - .bInterval = 1, - }, - { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x2, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = BULK_EP_MAXPACKET, - .bInterval = 1, - }, - { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x82, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = BULK_EP_MAXPACKET, - .bInterval = 1, - }, -}; - -static const struct usb_interface_descriptor iface_sourcesink[] = { - { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR, - .iInterface = 0, - .endpoint = endp_bulk, - } -}; - -static const struct usb_interface_descriptor iface_loopback[] = { - { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, /* still 0, as it's a different config...? */ - .bAlternateSetting = 0, - .bNumEndpoints = 4, - .bInterfaceClass = USB_CLASS_VENDOR, - .iInterface = 0, - .endpoint = endp_bulk, - } -}; - -static const struct usb_interface ifaces_sourcesink[] = { - { - .num_altsetting = 1, - .altsetting = iface_sourcesink, - } -}; - -static const struct usb_interface ifaces_loopback[] = { - { - .num_altsetting = 1, - .altsetting = iface_loopback, - } -}; - -static const struct usb_config_descriptor config[] = { - { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = GZ_CFG_SOURCESINK, - .iConfiguration = 4, /* string index */ - .bmAttributes = 0x80, - .bMaxPower = 0x32, - .interface = ifaces_sourcesink, - }, - { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = GZ_CFG_LOOPBACK, - .iConfiguration = 5, /* string index */ - .bmAttributes = 0x80, - .bMaxPower = 0x32, - .interface = ifaces_loopback, - } -}; - -static char serial[] = "0123456789.0123456789.0123456789"; -static const char *usb_strings[] = { - "libopencm3", - "Gadget-Zero", - serial, - "source and sink data", - "loop input to output" -}; - -/* Buffer to be used for control requests. */ -static uint8_t usbd_control_buffer[5*BULK_EP_MAXPACKET]; -static usbd_device *our_dev; - -/* Private global for state */ -static struct { - uint8_t pattern; - int pattern_counter; - int test_unaligned; /* If 0 (default), use 16-bit aligned buffers. This should not be declared as bool */ -} state = { - .pattern = 0, - .pattern_counter = 0, - .test_unaligned = 0, -}; - -static void gadget0_ss_out_cb(usbd_device *usbd_dev, uint8_t ep) -{ - (void) ep; - uint16_t x; - /* TODO - if you're really keen, perf test this. tiva implies it matters */ - /* char buf[64] __attribute__ ((aligned(4))); */ - uint8_t buf[BULK_EP_MAXPACKET + 1] __attribute__ ((aligned(2))); - uint8_t *dest; - - trace_send_blocking8(0, 'O'); - if (state.test_unaligned) { - dest = buf + 1; - } else { - dest = buf; - } - x = usbd_ep_read_packet(usbd_dev, ep, dest, BULK_EP_MAXPACKET); - trace_send_blocking8(1, x); -} - -static void gadget0_ss_in_cb(usbd_device *usbd_dev, uint8_t ep) -{ - (void) usbd_dev; - uint8_t buf[BULK_EP_MAXPACKET + 1] __attribute__ ((aligned(2))); - uint8_t *src; - - trace_send_blocking8(0, 'I'); - if (state.test_unaligned) { - src = buf + 1; - } else { - src = buf; - } - - switch (state.pattern) { - case 0: - memset(src, 0, BULK_EP_MAXPACKET); - break; - case 1: - for (unsigned i = 0; i < BULK_EP_MAXPACKET; i++) { - src[i] = state.pattern_counter++ % 63; - } - break; - } - - uint16_t x = usbd_ep_write_packet(usbd_dev, ep, src, BULK_EP_MAXPACKET); - /* As we are calling write in the callback, this should never fail */ - trace_send_blocking8(2, x); - if (x != BULK_EP_MAXPACKET) { - ER_DPRINTF("failed to write?: %d\n", x); - } - /*assert(x == sizeof(buf));*/ -} - -static void gadget0_in_cb_loopback(usbd_device *usbd_dev, uint8_t ep) -{ - (void) usbd_dev; - ER_DPRINTF("loop IN %x\n", ep); - /* Nothing to do here, basically just indicates they read us. */ -} - -static void gadget0_out_cb_loopback(usbd_device *usbd_dev, uint8_t ep) -{ - uint8_t buf[BULK_EP_MAXPACKET]; - /* Copy data we received on OUT ep back to the paired IN ep */ - int x = usbd_ep_read_packet(usbd_dev, ep, buf, BULK_EP_MAXPACKET); - int y = usbd_ep_write_packet(usbd_dev, 0x80 | ep, buf, x); - ER_DPRINTF("loop OUT %x got %d => %d\n", ep, x, y); -} - -static enum usbd_request_return_codes gadget0_control_request(usbd_device *usbd_dev, - struct usb_setup_data *req, - uint8_t **buf, - uint16_t *len, - usbd_control_complete_callback *complete) -{ - (void) usbd_dev; - (void) complete; - (void) buf; - ER_DPRINTF("ctrl breq: %x, bmRT: %x, windex :%x, wlen: %x, wval :%x\n", - req->bRequest, req->bmRequestType, req->wIndex, req->wLength, - req->wValue); - - /* TODO - what do the return values mean again? */ - switch (req->bRequest) { - case GZ_REQ_SET_PATTERN: - state.pattern_counter = 0; - state.pattern = req->wValue; - return USBD_REQ_HANDLED; - case INTEL_COMPLIANCE_WRITE: - /* accept correctly formed ctrl writes */ - if (req->bmRequestType != (USB_REQ_TYPE_VENDOR|USB_REQ_TYPE_INTERFACE)) { - return USBD_REQ_NOTSUPP; - } - if (req->wValue || req->wIndex) { - return USBD_REQ_NOTSUPP; - } - if (req->wLength > sizeof(usbd_control_buffer)) { - return USBD_REQ_NOTSUPP; - } - /* ok, mark it as accepted. */ - return USBD_REQ_HANDLED; - case INTEL_COMPLIANCE_READ: - if (req->bmRequestType != (USB_REQ_TYPE_IN|USB_REQ_TYPE_VENDOR|USB_REQ_TYPE_INTERFACE)) { - return USBD_REQ_NOTSUPP; - } - if (req->wValue || req->wIndex) { - return USBD_REQ_NOTSUPP; - } - if (req->wLength > sizeof(usbd_control_buffer)) { - return USBD_REQ_NOTSUPP; - } - /* ok, return what they left there earlier */ - *len = req->wLength; - return USBD_REQ_HANDLED; - case GZ_REQ_SET_UNALIGNED: - state.test_unaligned = 1; - return USBD_REQ_HANDLED; - case GZ_REQ_SET_ALIGNED: - state.test_unaligned = 0; - return USBD_REQ_HANDLED; - case GZ_REQ_PRODUCE: - ER_DPRINTF("fake loopback of %d\n", req->wValue); - if (req->wValue > sizeof(usbd_control_buffer)) { - ER_DPRINTF("Can't write more than out control buffer! %d > %d\n", - req->wValue, sizeof(usbd_control_buffer)); - return USBD_REQ_NOTSUPP; - } - /* Don't produce more than asked for! */ - if (req->wValue > req->wLength) { - ER_DPRINTF("Truncating reply to match wLen\n"); - *len = req->wLength; - } else { - *len = req->wValue; - } - return USBD_REQ_HANDLED; - default: - ER_DPRINTF("Unhandled request!\n"); - return USBD_REQ_NOTSUPP; - } - return USBD_REQ_NEXT_CALLBACK; -} - -static void gadget0_set_config(usbd_device *usbd_dev, uint16_t wValue) -{ - ER_DPRINTF("set cfg %d\n", wValue); - switch (wValue) { - case GZ_CFG_SOURCESINK: - state.test_unaligned = 0; - usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_ss_out_cb); - usbd_ep_setup(usbd_dev, 0x81, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_ss_in_cb); - usbd_register_control_callback( - usbd_dev, - USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - gadget0_control_request); - /* Prime source for IN data. */ - gadget0_ss_in_cb(usbd_dev, 0x81); - break; - case GZ_CFG_LOOPBACK: - /* - * The ordering here is important, as it defines the addresses - * locality. We want to have both out endpoints in sequentially, - * so we can test for overrunning our memory space, if that's a - * concern on the usb peripheral. - */ - usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_out_cb_loopback); - usbd_ep_setup(usbd_dev, 0x02, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_out_cb_loopback); - usbd_ep_setup(usbd_dev, 0x81, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_in_cb_loopback); - usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, BULK_EP_MAXPACKET, - gadget0_in_cb_loopback); - break; - default: - ER_DPRINTF("set configuration unknown: %d\n", wValue); - } -} - -usbd_device *gadget0_init(const usbd_driver *driver, const char *userserial) -{ -#ifdef ER_DEBUG - setbuf(stdout, NULL); -#endif - if (userserial) { - usb_strings[2] = userserial; - } - our_dev = usbd_init(driver, &dev, config, - usb_strings, 5, - usbd_control_buffer, sizeof(usbd_control_buffer)); - - usbd_register_set_config_callback(our_dev, gadget0_set_config); - delay_setup(); - - return our_dev; -} - -void gadget0_run(usbd_device *usbd_dev) -{ - usbd_poll(usbd_dev); - /* This should be more than allowable! */ - delay_us(100); -} \ No newline at end of file diff --git a/libopencm3/tests/gadget-zero/usb-gadget0.h b/libopencm3/tests/gadget-zero/usb-gadget0.h deleted file mode 100644 index 9ed332a..0000000 --- a/libopencm3/tests/gadget-zero/usb-gadget0.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2015 Karl Palsson - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef USB_GADGET0_H -#define USB_GADGET0_H - -#include - -/** - * Start up the gadget0 framework. - * @param driver which usbd hardware driver to use. - * @param userserial if non-null, will become the serial number. - * You should provide this to help the test code find something particular - * to the hardware. - * @return the usbd_device created. -*/ -usbd_device *gadget0_init(const usbd_driver *driver, const char *userserial); - -/** - * Call this forever. - * @param usbd_dev the object returned in _init. - * @sa gadget0_init - */ -void gadget0_run(usbd_device *usbd_dev); - -#endif diff --git a/libopencm3/tests/rules.mk b/libopencm3/tests/rules.mk deleted file mode 100644 index dbc17d1..0000000 --- a/libopencm3/tests/rules.mk +++ /dev/null @@ -1,178 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## This library is free software: you can redistribute it and/or modify -## it under the terms of the GNU Lesser General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This library is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU Lesser General Public License for more details. -## -## You should have received a copy of the GNU Lesser General Public License -## along with this library. If not, see . -## - -# This version of rules.mk expects the following to be defined before -# inclusion.. -### REQUIRED ### -# OPENCM3_DIR - duh -# OPENCM3_LIB - the basename, eg: opencm3_stm32f4 -# OPENCM3_DEFS - the target define eg: -DSTM32F4 -# ARCH_FLAGS - eg, -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -# (ie, the full set of cpu arch flags, _none_ are defined in this file) -# PROJECT - will be the basename of the output elf, eg usb-gadget0-stm32f4disco -# CFILES - basenames only, eg main.c blah.c -# LDSCRIPT - full path, eg ../../examples/stm32/f4/stm32f4-discovery/stm32f4-discovery.ld -# -### OPTIONAL ### -# INCLUDES - fully formed -I paths, if you want extra, eg -I../shared -# BUILD_DIR - defaults to bin, should set this if you are building multiarch -# OPT - full -O flag, defaults to -Os -# CSTD - defaults -std=c99 -# CXXSTD - no default. -# OOCD_INTERFACE - eg stlink-v2 -# OOCD_TARGET - eg stm32f4x -# both only used if you use the "make flash" target. -# OOCD_FILE - eg my.openocd.cfg -# This overrides interface/target above, and is used as just -f FILE -### TODO/FIXME/notes ### -# No support for stylecheck. -# No support for BMP/texane/random flash methods, no plans either -# No support for magically finding the library. -# C++ hasn't been actually tested with this..... sorry bout that. ;) -# Second expansion/secondary not set, add this if you need them. - -BUILD_DIR ?= bin -OPT ?= -Os -CSTD ?= -std=c99 - -# Be silent per default, but 'make V=1' will show all compiler calls. -# If you're insane, V=99 will print out all sorts of things. -V?=0 -ifeq ($(V),0) -Q := @ -NULL := 2>/dev/null -endif - -# Tool paths. -PREFIX ?= arm-none-eabi- -CC = $(PREFIX)gcc -LD = $(PREFIX)gcc -OBJCOPY = $(PREFIX)objcopy -OBJDUMP = $(PREFIX)objdump -OOCD ?= openocd - -OPENCM3_INC = $(OPENCM3_DIR)/include - -# Inclusion of library header files -INCLUDES += $(patsubst %,-I%, . $(OPENCM3_INC) ) - -OBJS = $(CFILES:%.c=$(BUILD_DIR)/%.o) -GENERATED_BINS = $(PROJECT).elf $(PROJECT).bin $(PROJECT).map $(PROJECT).list $(PROJECT).lss - -TGT_CPPFLAGS += -MD -TGT_CPPFLAGS += -Wall -Wundef $(INCLUDES) -TGT_CPPFLAGS += $(INCLUDES) $(OPENCM3_DEFS) - -TGT_CFLAGS += $(OPT) $(CSTD) -ggdb3 -TGT_CFLAGS += $(ARCH_FLAGS) -TGT_CFLAGS += -fno-common -TGT_CFLAGS += -ffunction-sections -fdata-sections -TGT_CFLAGS += -Wextra -Wshadow -Wno-unused-variable -Wimplicit-function-declaration -TGT_CFLAGS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes - -TGT_CXXFLAGS += $(OPT) $(CXXSTD) -ggdb3 -TGT_CXXFLAGS += $(ARCH_FLAGS) -TGT_CXXFLAGS += -fno-common -TGT_CXXFLAGS += -ffunction-sections -fdata-sections -TGT_CXXFLAGS += -Wextra -Wshadow -Wredundant-decls -Weffc++ - -TGT_LDFLAGS += -T$(LDSCRIPT) -L$(OPENCM3_DIR)/lib -nostartfiles -TGT_LDFLAGS += $(ARCH_FLAGS) -TGT_LDFLAGS += -specs=nano.specs -TGT_LDFLAGS += -Wl,--gc-sections -# OPTIONAL -#TGT_LDFLAGS += -Wl,-Map=$(PROJECT).map -ifeq ($(V),99) -TGT_LDFLAGS += -Wl,--print-gc-sections -endif - -# Linker script generator fills this in for us. -ifeq (,$(DEVICE)) -LDLIBS += -l$(OPENCM3_LIB) -endif -# nosys is only in newer gcc-arm-embedded... -#LDLIBS += -specs=nosys.specs -LDLIBS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group - -# Burn in legacy hell fortran modula pascal yacc idontevenwat -.SUFFIXES: -.SUFFIXES: .c .h .o .cxx .elf .bin .list .lss - -# Bad make, never *ever* try to get a file out of source control by yourself. -%: %,v -%: RCS/%,v -%: RCS/% -%: s.% -%: SCCS/s.% - -all: $(PROJECT).elf $(PROJECT).bin -flash: $(PROJECT).flash - -# error if not using linker script generator -ifeq (,$(DEVICE)) -$(LDSCRIPT): -ifeq (,$(wildcard $(LDSCRIPT))) - $(error Unable to find specified linker script: $(LDSCRIPT)) -endif -endif - -# Need a special rule to have a bin dir -$(BUILD_DIR)/%.o: %.c - @printf " CC\t$<\n" - @mkdir -p $(dir $@) - $(Q)$(CC) $(TGT_CFLAGS) $(CFLAGS) $(TGT_CPPFLAGS) $(CPPFLAGS) -o $@ -c $< - -$(BUILD_DIR)/%.o: %.cxx - @printf " CXX\t$<\n" - @mkdir -p $(dir $@) - $(Q)$(CC) $(TGT_CXXFLAGS) $(CXXFLAGS) $(TGT_CPPFLAGS) $(CPPFLAGS) -o $@ -c $< - -$(PROJECT).elf: $(OBJS) $(LDSCRIPT) $(LIBDEPS) - @printf " LD\t$@\n" - $(Q)$(LD) $(TGT_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $@ - -%.bin: %.elf - @printf " OBJCOPY\t$@\n" - $(Q)$(OBJCOPY) -O binary $< $@ - -%.lss: %.elf - $(OBJDUMP) -h -S $< > $@ - -%.list: %.elf - $(OBJDUMP) -S $< > $@ - -%.flash: %.elf - @printf " FLASH\t$<\n" -ifeq (,$(OOCD_FILE)) - $(Q)(echo "halt; program $(realpath $(*).elf) verify reset" | nc -4 localhost 4444 2>/dev/null) || \ - $(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ - -f target/$(OOCD_TARGET).cfg \ - -c "program $(realpath $(*).elf) verify reset exit" \ - $(NULL) -else - $(Q)(echo "halt; program $(realpath $(*).elf) verify reset" | nc -4 localhost 4444 2>/dev/null) || \ - $(Q)$(OOCD) -f $(OOCD_FILE) \ - -c "program $(realpath $(*).elf) verify reset exit" \ - $(NULL) -endif - -clean: - rm -rf $(BUILD_DIR) $(GENERATED_BINS) - -.PHONY: all clean flash --include $(OBJS:.o=.d) - diff --git a/libopencm3/tests/shared/trace.c b/libopencm3/tests/shared/trace.c deleted file mode 100644 index 54bee45..0000000 --- a/libopencm3/tests/shared/trace.c +++ /dev/null @@ -1,57 +0,0 @@ -#include -#include -#include -#include -#include "trace.h" - -void trace_send_blocking8(int stimulus_port, char c) -{ - if (!(ITM_TER[0] & (1< - -#ifdef __cplusplus -extern "C" { -#endif - -void trace_send_blocking8(int stimulus_port, char c); -void trace_send8(int stimulus_port, char c); - -void trace_send_blocking16(int stimulus_port, uint16_t val); -void trace_send16(int stimulus_port, uint16_t val); - -void trace_send_blocking32(int stimulus_port, uint32_t val); -void trace_send32(int stimulus_port, uint32_t val); - - -#ifdef __cplusplus -} -#endif - -#endif /* TRACE_H */ - diff --git a/libopencm3/tests/shared/trace_stdio.c b/libopencm3/tests/shared/trace_stdio.c deleted file mode 100644 index 2710942..0000000 --- a/libopencm3/tests/shared/trace_stdio.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * support for stdio output to a trace port - * Karl Palsson, 2014 - */ - -#include -#include -#include - -#include "trace.h" - -#ifndef STIMULUS_STDIO -#define STIMULUS_STDIO 0 -#endif - -int _write(int file, char *ptr, int len); -int _write(int file, char *ptr, int len) -{ - int i; - - if (file == STDOUT_FILENO || file == STDERR_FILENO) { - for (i = 0; i < len; i++) { - if (ptr[i] == '\n') { - trace_send_blocking8(STIMULUS_STDIO, '\r'); - } - trace_send_blocking8(STIMULUS_STDIO, ptr[i]); - } - return i; - } - errno = EIO; - return -1; -} - - diff --git a/libopeninv b/libopeninv new file mode 160000 index 0000000..0bef3c1 --- /dev/null +++ b/libopeninv @@ -0,0 +1 @@ +Subproject commit 0bef3c1fdb6b30ed6cb79b55c51871576f9c199f diff --git a/libopeninv/LICENSE b/libopeninv/LICENSE deleted file mode 100644 index 0a04128..0000000 --- a/libopeninv/LICENSE +++ /dev/null @@ -1,165 +0,0 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - - This version of the GNU Lesser General Public License incorporates -the terms and conditions of version 3 of the GNU General Public -License, supplemented by the additional permissions listed below. - - 0. Additional Definitions. - - As used herein, "this License" refers to version 3 of the GNU Lesser -General Public License, and the "GNU GPL" refers to version 3 of the GNU -General Public License. - - "The Library" refers to a covered work governed by this License, -other than an Application or a Combined Work as defined below. - - An "Application" is any work that makes use of an interface provided -by the Library, but which is not otherwise based on the Library. -Defining a subclass of a class defined by the Library is deemed a mode -of using an interface provided by the Library. - - A "Combined Work" is a work produced by combining or linking an -Application with the Library. The particular version of the Library -with which the Combined Work was made is also called the "Linked -Version". - - The "Minimal Corresponding Source" for a Combined Work means the -Corresponding Source for the Combined Work, excluding any source code -for portions of the Combined Work that, considered in isolation, are -based on the Application, and not on the Linked Version. - - The "Corresponding Application Code" for a Combined Work means the -object code and/or source code for the Application, including any data -and utility programs needed for reproducing the Combined Work from the -Application, but excluding the System Libraries of the Combined Work. - - 1. Exception to Section 3 of the GNU GPL. - - You may convey a covered work under sections 3 and 4 of this License -without being bound by section 3 of the GNU GPL. - - 2. Conveying Modified Versions. - - If you modify a copy of the Library, and, in your modifications, a -facility refers to a function or data to be supplied by an Application -that uses the facility (other than as an argument passed when the -facility is invoked), then you may convey a copy of the modified -version: - - a) under this License, provided that you make a good faith effort to - ensure that, in the event an Application does not supply the - function or data, the facility still operates, and performs - whatever part of its purpose remains meaningful, or - - b) under the GNU GPL, with none of the additional permissions of - this License applicable to that copy. - - 3. Object Code Incorporating Material from Library Header Files. - - The object code form of an Application may incorporate material from -a header file that is part of the Library. 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Combined Libraries. - - You may place library facilities that are a work based on the -Library side by side in a single library together with other library -facilities that are not Applications and are not covered by this -License, and convey such a combined library under terms of your -choice, if you do both of the following: - - a) Accompany the combined library with a copy of the same work based - on the Library, uncombined with any other library facilities, - conveyed under the terms of this License. - - b) Give prominent notice with the combined library that part of it - is a work based on the Library, and explaining where to find the - accompanying uncombined form of the same work. - - 6. Revised Versions of the GNU Lesser General Public License. - - The Free Software Foundation may publish revised and/or new versions -of the GNU Lesser General Public License from time to time. Such new -versions will be similar in spirit to the present version, but may -differ in detail to address new problems or concerns. - - Each version is given a distinguishing version number. If the -Library as you received it specifies that a certain numbered version -of the GNU Lesser General Public License "or any later version" -applies to it, you have the option of following the terms and -conditions either of that published version or of any later version -published by the Free Software Foundation. If the Library as you -received it does not specify a version number of the GNU Lesser -General Public License, you may choose any version of the GNU Lesser -General Public License ever published by the Free Software Foundation. - - If the Library as you received it specifies that a proxy can decide -whether future versions of the GNU Lesser General Public License shall -apply, that proxy's public statement of acceptance of any version is -permanent authorization for you to choose that version for the -Library. diff --git a/libopeninv/README.md b/libopeninv/README.md deleted file mode 100644 index 48ba7b9..0000000 --- a/libopeninv/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# libopeninv -Generic modules that can be used in many projects diff --git a/libopeninv/include/anain.h b/libopeninv/include/anain.h deleted file mode 100644 index 1b20847..0000000 --- a/libopeninv/include/anain.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef ANAIO_H_INCLUDED -#define ANAIO_H_INCLUDED - -#include -#include "anain_prj.h" - - -class AnaIn -{ -public: - AnaIn(int chan): firstValue(&values[chan]) {} - - #define ANA_IN_ENTRY(name, port, pin) static AnaIn name; - ANA_IN_LIST - #undef ANA_IN_ENTRY - - #define ANA_IN_ENTRY(name, port, pin) +1 - static const int ANA_IN_COUNT = ANA_IN_LIST; - #undef ANA_IN_ENTRY - - static void Start(); - void Configure(uint32_t port, uint8_t pin); - uint16_t Get(); - -private: - static uint16_t values[]; - static uint8_t channel_array[]; - - uint16_t GetIndex() { return firstValue - values; } - static uint8_t AdcChFromPort(uint32_t command_port, int command_bit); - static int median3(int a, int b, int c); - - uint16_t* const firstValue; -}; - -//Configure all AnaIn objects from the given list -#define ANA_IN_ENTRY(name, port, pin) AnaIn::name.Configure(port, pin); -#define ANA_IN_CONFIGURE(l) l - -#endif // ANAIO_H_INCLUDED diff --git a/libopeninv/include/crc8.h b/libopeninv/include/crc8.h deleted file mode 100644 index a475cb8..0000000 --- a/libopeninv/include/crc8.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the stm32-sine project. - * - * Copyright (C) 2021 David J. Fiddes - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __CRC8_H_ -#define __CRC8_H_ - -#include - -/* - * Precalculated look up table for CRC calculation - */ -extern const uint8_t crc_table[256]; - -/** - * \brief Calculate 8-bit CRC - * - * - * Calculate an 8-bit CRC of a block of data. The algorithm used depends on - * library configuration. - * - * \param[in] p pointer to the data to take we wish to compute the CRC of - * \param[in] len length of the data - * \param[in] crc Initial value for the CRC algorithm (or CRC of previous data) - * - * \return Calculated CRC value - */ -inline uint8_t crc8(uint8_t* p, uint8_t len, uint8_t crc) -{ - while (len--) - { - crc = crc_table[crc ^ *p++]; - } - - return crc; -} - -/** - * \brief Calculate 8-bit CRC of a byte - * - * Calculate an 8-bit CRC of a single byte. The algorithm used depends on - * library configuration. - * - * \param[in] input data byte to compute the CRC of - * \param[in] crc Initial value for the CRC algorithm (or CRC of previous data) - * - * \return Calculated CRC value - */ -inline uint8_t crc8(uint8_t input, uint8_t crc) -{ - crc = crc_table[crc ^ input]; - - return crc; -} - -#endif /* __CRC8_H_ */ diff --git a/libopeninv/include/delay.h b/libopeninv/include/delay.h deleted file mode 100644 index e7ef51f..0000000 --- a/libopeninv/include/delay.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the stm32-sine project. - * - * Copyright (C) 2021 David J. Fiddes - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef DELAY_H -#define DELAY_H - -/** - * \brief Blocking delay for a period - * - * \param[in] period Length of the delay in micro-seconds - */ -inline void uDelay(int period) -{ - // Empirically determined constant by measurement of GPIO toggle - // of 1000 uS delay on a 72MHz STM32F103 processor - static const int CyclesPerMicroSecond = 12; - - int iterations = period * CyclesPerMicroSecond; - - for (int i = 0; i < iterations; i++) - { - __asm__("nop"); - } -} - -#endif // DELAY_H diff --git a/libopeninv/include/digio.h b/libopeninv/include/digio.h deleted file mode 100644 index cfc7652..0000000 --- a/libopeninv/include/digio.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef DIGIO_H_INCLUDED -#define DIGIO_H_INCLUDED - -#include -#include "digio_prj.h" - -namespace PinMode { - enum PinMode - { - INPUT_PD, - INPUT_PU, - INPUT_FLT, - INPUT_AIN, - OUTPUT, - OUTPUT_OD, - LAST - }; -} - -class DigIo -{ -public: - #define DIG_IO_ENTRY(name, port, pin, mode) static DigIo name; - DIG_IO_LIST - #undef DIG_IO_ENTRY - - /** Map GPIO pin object to hardware pin. - * @param[in] port port to use for this pin - * @param[in] pin port-pin to use for this pin - * @param[in] mode pinmode to use - */ - void Configure(uint32_t port, uint16_t pin, PinMode::PinMode pinMode); - - /** - * Get pin value - * - * @param[in] io pin index - * @return pin value - */ - bool Get() { return gpio_get(_port, _pin) > 0; } - - /** - * Set pin high - * - * @param[in] io pin index - */ - void Set() { gpio_set(_port, _pin); } - - /** - * Set pin low - * - * @param[in] io pin index - */ - void Clear() { gpio_clear(_port, _pin); } - - /** - * Toggle pin - * - * @param[in] io pin index - */ - void Toggle() { gpio_toggle(_port, _pin); } - -private: - uint32_t _port; - uint16_t _pin; -}; -//Configure all digio objects from the given list -#define DIG_IO_ENTRY(name, port, pin, mode) DigIo::name.Configure(port, pin, mode); -#define DIG_IO_CONFIGURE(l) l - -#endif // DIGIO_H_INCLUDED diff --git a/libopeninv/include/errormessage.h b/libopeninv/include/errormessage.h deleted file mode 100644 index b9f0560..0000000 --- a/libopeninv/include/errormessage.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef ERRORMESSAGE_H -#define ERRORMESSAGE_H - -#include "errormessage_prj.h" -#include - -#define ERROR_MESSAGE_ENTRY(id, type) ERR_##id, -typedef enum -{ - ERROR_NONE, - ERROR_MESSAGE_LIST - ERROR_MESSAGE_LAST -} ERROR_MESSAGE_NUM; -#undef ERROR_MESSAGE_ENTRY - -typedef enum -{ - ERROR_STOP, - ERROR_DERATE, - ERROR_DISPLAY, - ERROR_LAST -} ERROR_TYPE; - -class ErrorMessage -{ - public: - static void SetTime(uint32_t time); - static void Post(ERROR_MESSAGE_NUM err); - static void UnpostAll(); - static void PrintAllErrors(); - static void PrintNewErrors(); - static ERROR_MESSAGE_NUM GetLastError(); - protected: - private: - static void PrintError(uint32_t time, ERROR_MESSAGE_NUM err); - - static uint32_t timeTick; - static uint32_t currentBufIdx; - static uint32_t lastPrintIdx; - static bool posted[ERROR_MESSAGE_LAST]; - static ERROR_MESSAGE_NUM lastError; -}; - -#endif // ERRORMESSAGE_H diff --git a/libopeninv/include/foc.h b/libopeninv/include/foc.h deleted file mode 100644 index 1a171c3..0000000 --- a/libopeninv/include/foc.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef FOC_H -#define FOC_H - -#include -#include "my_fp.h" - -class FOC -{ - public: - static void SetAngle(uint16_t angle); - static void ParkClarke(s32fp il1, s32fp il2); - static int32_t GetQLimit(int32_t maxVd); - static int32_t GetTotalVoltage(int32_t ud, int32_t uq); - static void InvParkClarke(int32_t ud, int32_t uq); - static void Mtpa(int32_t is, int32_t& idref, int32_t& iqref); - static int32_t GetMaximumModulationIndex(); - static s32fp id; - static s32fp iq; - static int32_t DutyCycles[3]; - - protected: - private: - static uint32_t sqrt(uint32_t rad); - static u32fp fpsqrt(u32fp rad); - static s32fp sin; - static s32fp cos; -}; - -#endif // FOC_H diff --git a/libopeninv/include/fu.h b/libopeninv/include/fu.h deleted file mode 100644 index 14fa292..0000000 --- a/libopeninv/include/fu.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef FU_H_INCLUDED -#define FU_H_INCLUDED - -#include -#include "my_fp.h" - -class MotorVoltage -{ -public: - static void SetBoost(uint32_t boost); - static void SetWeakeningFrq(float frq); - static void SetMaxAmp(uint32_t maxAmp); - static uint32_t GetAmp(u32fp frq); - static uint32_t GetAmpPerc(u32fp frq, u32fp perc); - -private: - static void CalcFac(); - static uint32_t boost; - static u32fp fac; - static uint32_t maxAmp; - static u32fp endFrq; - static u32fp maxFrq; -}; - -#endif // FU_H_INCLUDED diff --git a/libopeninv/include/linbus.h b/libopeninv/include/linbus.h deleted file mode 100644 index f7a4981..0000000 --- a/libopeninv/include/linbus.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the stm32-car project. - * - * Copyright (C) 2021 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef LINBUS_H -#define LINBUS_H - - -class LinBus -{ - public: - /** Default constructor */ - LinBus(uint32_t usart, int baudrate); - void Request(uint8_t id, uint8_t* data, uint8_t len); - bool HasReceived(uint8_t pid, uint8_t requiredLen); - uint8_t* GetReceivedBytes() { return &recvBuffer[payloadIndex]; } - - protected: - - private: - struct HwInfo - { - uint32_t usart; - uint8_t dmatx; - uint8_t dmarx; - uint32_t port; - uint16_t pin; - }; - - static uint8_t Checksum(uint8_t pid, uint8_t* data, int len); - static uint8_t Parity(uint8_t id); - - static const HwInfo hwInfo[]; - static const int payloadIndex = 3; - static const int pidIndex = 2; - uint32_t usart; - const HwInfo* hw; - uint8_t sendBuffer[11]; - uint8_t recvBuffer[12]; -}; - -#endif // LINBUS_H diff --git a/libopeninv/include/my_fp.h b/libopeninv/include/my_fp.h deleted file mode 100644 index 1d88a67..0000000 --- a/libopeninv/include/my_fp.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef MY_FP_H_INCLUDED -#define MY_FP_H_INCLUDED - -#include - -#define FRAC_DIGITS 5 - -#ifndef CST_DIGITS -#define CST_DIGITS FRAC_DIGITS -#endif - -#define FRAC_FAC (1 << CST_DIGITS) - -#define CST_CONVERT(a) ((a) << (CST_DIGITS - FRAC_DIGITS)) -#define CST_ICONVERT(a) ((a) >> (CST_DIGITS - FRAC_DIGITS)) - -#define UTOA_FRACDEC 100 -#define FP_DECIMALS 2 - -#define FP_TOFLOAT(a) (((float)a) / FRAC_FAC) -#define FP_FROMINT(a) ((s32fp)((a) << CST_DIGITS)) -#define FP_TOINT(a) ((s32fp)((a) >> CST_DIGITS)) -#define FP_FROMFLT(a) ((s32fp)((a) * FRAC_FAC)) - -#define FP_MUL(a, b) (((a) * (b)) >> CST_DIGITS) -#define FP_DIV(a, b) (((a) << CST_DIGITS) / (b)) - -typedef uint32_t u32fp; -typedef int32_t s32fp; -typedef int16_t s16fp; -typedef uint16_t u16fp; - -#ifdef __cplusplus -extern "C" -{ -#endif - -char* fp_itoa(char * buf, s32fp a); -s32fp fp_atoi(const char *str, int fracDigits); -u32fp fp_sqrt(u32fp rad); -s32fp fp_ln(unsigned int x); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libopeninv/include/my_math.h b/libopeninv/include/my_math.h deleted file mode 100644 index 59db436..0000000 --- a/libopeninv/include/my_math.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef MY_MATH_H_INCLUDED -#define MY_MATH_H_INCLUDED - -#define ABS(a) ((a) < 0?(-(a)) : (a)) -#define MIN(a,b) ((a) < (b)?(a):(b)) -#define MAX(a,b) ((a) > (b)?(a):(b)) -#define RAMPUP(current, target, rate) ((target < current || (current + rate) > target) ? target : current + rate) -#define RAMPDOWN(current, target, rate) ((target > current || (current - rate) < target) ? target : current - rate) -#define IIRFILTER(l,n,c) (((n) + ((l) << (c)) - (l)) >> (c)) -#define IIRFILTERF(l,n,c) (((n) + (l) * ((1 << (c)) - 1)) / (1 << (c))) -#define MEDIAN3(a,b,c) ((a) > (b) ? ((b) > (c) ? (b) : ((a) > (c) ? (c) : (a))) \ - : ((a) > (c) ? (a) : ((b) > (c) ? (c) : (b)))) -#define CHK_BIPOLAR_OFS(ofs) ((ofs < (2048 - 512)) || (ofs > (2048 + 512))) - -#endif // MY_MATH_H_INCLUDED diff --git a/libopeninv/include/my_string.h b/libopeninv/include/my_string.h deleted file mode 100644 index 3de5189..0000000 --- a/libopeninv/include/my_string.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef MY_STRING_H -#define MY_STRING_H - -#ifndef NULL -#define NULL 0L -#endif - -#define TOSTR_(...) #__VA_ARGS__ -#define STRINGIFY(x) TOSTR_(x) - -#ifdef __cplusplus -extern "C" -{ -#endif - -int my_strcmp(const char *str1, const char *str2); -void my_strcat(char *str1, const char *str2); -int my_strlen(const char *str); -const char *my_strchr(const char *str, const char c); -int my_ltoa(char *buf, int val, int base); -int my_atoi(const char *str); -char *my_trim(char *str); -void memcpy32(int* target, int *source, int length); -void memset32(int* target, int value, int length); -void my_strcpy(char *str1, const char *str2); - -#ifdef __cplusplus -} -#endif -#endif // MY_STRING_H diff --git a/libopeninv/include/param_save.h b/libopeninv/include/param_save.h deleted file mode 100644 index 3f89e35..0000000 --- a/libopeninv/include/param_save.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef PARAM_SAVE_H_INCLUDED -#define PARAM_SAVE_H_INCLUDED - -#ifdef __cplusplus -extern "C" -{ -#endif - -uint32_t parm_save(void); -int parm_load(void); - -#ifdef __cplusplus -} -#endif - -#endif // PARAM_SAVE_H_INCLUDED diff --git a/libopeninv/include/params.h b/libopeninv/include/params.h deleted file mode 100644 index fb70a60..0000000 --- a/libopeninv/include/params.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef PARAM_H_INCLUDED -#define PARAM_H_INCLUDED - -#include "param_prj.h" -#include "my_fp.h" - -namespace Param -{ - #define PARAM_ENTRY(category, name, unit, min, max, def, id) name, - #define VALUE_ENTRY(name, unit, id) name, - typedef enum - { - PARAM_LIST - PARAM_LAST, - PARAM_INVALID - } PARAM_NUM; - #undef PARAM_ENTRY - #undef VALUE_ENTRY - - typedef enum - { - TYPE_PARAM, - TYPE_VALUE, - TYPE_LAST - } PARAM_TYPE; - - typedef enum - { - FLAG_NONE = 0, - FLAG_HIDDEN = 1 - } PARAM_FLAG; - - typedef struct - { - char const *category; - char const *name; - char const *unit; - s32fp min; - s32fp max; - s32fp def; - uint32_t id; - } Attributes; - - int Set(PARAM_NUM ParamNum, s32fp ParamVal); - s32fp Get(PARAM_NUM ParamNum); - int GetInt(PARAM_NUM ParamNum); - float GetFloat(PARAM_NUM ParamNum); - bool GetBool(PARAM_NUM ParamNum); - void SetInt(PARAM_NUM ParamNum, int ParamVal); - void SetFixed(PARAM_NUM ParamNum, s32fp ParamVal); - void SetFloat(PARAM_NUM ParamNum, float ParamVal); - PARAM_NUM NumFromString(const char *name); - PARAM_NUM NumFromId(uint32_t id); - const Attributes *GetAttrib(PARAM_NUM ParamNum); - int IsParam(PARAM_NUM ParamNum); - void LoadDefaults(); - void SetFlagsRaw(PARAM_NUM param, uint8_t rawFlags); - void SetFlag(PARAM_NUM param, PARAM_FLAG flag); - void ClearFlag(PARAM_NUM param, PARAM_FLAG flag); - PARAM_FLAG GetFlag(PARAM_NUM param); - - //User defined callback - void Change(Param::PARAM_NUM ParamNum); -} - -#endif //PARAM_H_INCLUDED diff --git a/libopeninv/include/picontroller.h b/libopeninv/include/picontroller.h deleted file mode 100644 index 964f0bf..0000000 --- a/libopeninv/include/picontroller.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2018 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef PIREGULATOR_H -#define PIREGULATOR_H - -#include "my_fp.h" -#include "my_math.h" - -class PiController -{ - public: - /** Default constructor */ - PiController(); - - /** Set regulator proportional and integral gain. - * \param kp New value to set for proportional gain - * \param ki New value for integral gain - */ - void SetGains(int kp, int ki) - { - this->kp = kp; - this->ki = ki; - } - - void SetProportionalGain(int kp) { this->kp = kp; } - void SetIntegralGain(int ki) { this->ki = ki; } - - /** Set regulator target set point - * \param val regulator target - */ - void SetRef(s32fp val) { refVal = val; } - - s32fp GetRef() { return refVal; } - - /** Set maximum controller output - * \param val actuator saturation value - */ - void SetMinMaxY(int32_t valMin, int32_t valMax) { minY = valMin; maxY = valMax; } - - /** Set calling frequency - * \param val New value to set - */ - void SetCallingFrequency(int val) { frequency = val; } - - /** Run controller to obtain a new actuator value - * \param curVal currently measured value - * \return new actuator value - */ - int32_t Run(s32fp curVal); - - /** Run controller to obtain a new actuator value, run only proportional part - * \param curVal currently measured value - * \return new actuator value - */ - int32_t RunProportionalOnly(s32fp curVal); - - /** Reset integrator to 0 */ - void ResetIntegrator() { esum = 0; } - - /** Preload Integrator to yield a certain output - * @pre SetCallingFrequency() and SetGains() must be called first - */ - void PreloadIntegrator(int32_t yieldedOutput) { esum = ki != 0 ? FP_FROMINT((yieldedOutput * frequency) / ki) : 0; } - - protected: - - private: - int32_t kp; //!< Proportional controller gain - int32_t ki; //!< Integral controller gain - s32fp esum; //!< Integrator - s32fp refVal; //!< control target - int32_t frequency; //!< Calling frequency - int32_t maxY; //!< upper actuator saturation value - int32_t minY; //!< lower actuator saturation value -}; - -#endif // PIREGULATOR_H diff --git a/libopeninv/include/printf.h b/libopeninv/include/printf.h deleted file mode 100644 index f4d1e1f..0000000 --- a/libopeninv/include/printf.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef PRINTF_H_INCLUDED -#define PRINTF_H_INCLUDED - -#if T_DEBUG -#define debugf(...) printf(__VA_ARGS__) -#else -#define debugf(...) -#endif - -class IPutChar -{ -public: - virtual void PutChar(char c) = 0; -}; - - -int printf(const char *format, ...); -int sprintf(char *out, const char *format, ...); -int fprintf(IPutChar* put, const char *format, ...); - - -#endif // PRINTF_H_INCLUDED diff --git a/libopeninv/include/sine_core.h b/libopeninv/include/sine_core.h deleted file mode 100644 index 55f9c20..0000000 --- a/libopeninv/include/sine_core.h +++ /dev/null @@ -1,2107 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef SINE_CORE_H_INCLUDED -#define SINE_CORE_H_INCLUDED - -#include "my_fp.h" - -class SineCore -{ - public: - static void Calc(uint16_t angle); - static s32fp Sine(uint16_t angle); - static s32fp Cosine(uint16_t angle); - static uint16_t Atan2(int32_t cos, int32_t sin); - static void SetAmp(uint32_t amp); - static uint32_t GetAmp(); - static int32_t CalcSVPWMOffset(int32_t a, int32_t b, int32_t c); - static uint32_t DutyCycles[3]; - static uint32_t Offset; - static const int BITS; - static const uint16_t MAXAMP; - - private: - static int32_t SineLookup(uint16_t Arg); - static int32_t MultiplyAmplitude(uint16_t Amplitude, int32_t Baseval); - static int32_t min(int32_t a, int32_t b); - static int32_t max(int32_t a, int32_t b); - - /** Minimum pulse width in normalized digits */ - static const uint32_t minPulse; - static uint32_t ampl; - static const int16_t SinTab[]; /* sine LUT */ - static const uint16_t ZERO_OFFSET; -}; - -/* Domain of lookup function */ -#define SINLU_ARGDIGITS 16 -#define SINLU_ONEREV (1U << SINLU_ARGDIGITS) - -#define SINTAB \ -0 ,\ -101 ,\ -201 ,\ -302 ,\ -402 ,\ -503 ,\ -603 ,\ -704 ,\ -804 ,\ -905 ,\ -1005 ,\ -1106 ,\ -1206 ,\ -1307 ,\ -1407 ,\ -1507 ,\ -1608 ,\ -1708 ,\ -1809 ,\ -1909 ,\ -2009 ,\ -2110 ,\ -2210 ,\ -2310 ,\ -2410 ,\ -2511 ,\ -2611 ,\ -2711 ,\ -2811 ,\ -2911 ,\ -3012 ,\ -3112 ,\ -3212 ,\ -3312 ,\ -3412 ,\ -3512 ,\ -3612 ,\ -3712 ,\ -3811 ,\ -3911 ,\ -4011 ,\ -4111 ,\ -4210 ,\ -4310 ,\ -4410 ,\ -4509 ,\ -4609 ,\ -4708 ,\ -4808 ,\ -4907 ,\ -5007 ,\ -5106 ,\ -5205 ,\ -5305 ,\ -5404 ,\ -5503 ,\ -5602 ,\ -5701 ,\ -5800 ,\ -5899 ,\ -5998 ,\ -6096 ,\ -6195 ,\ -6294 ,\ -6393 ,\ -6491 ,\ -6590 ,\ -6688 ,\ -6786 ,\ -6885 ,\ -6983 ,\ -7081 ,\ -7179 ,\ -7277 ,\ -7375 ,\ -7473 ,\ -7571 ,\ -7669 ,\ -7767 ,\ -7864 ,\ -7962 ,\ -8059 ,\ -8157 ,\ -8254 ,\ -8351 ,\ -8448 ,\ -8545 ,\ -8642 ,\ -8739 ,\ -8836 ,\ -8933 ,\ -9030 ,\ -9126 ,\ -9223 ,\ -9319 ,\ -9416 ,\ -9512 ,\ -9608 ,\ -9704 ,\ -9800 ,\ -9896 ,\ -9992 ,\ -10087 ,\ -10183 ,\ -10278 ,\ -10374 ,\ -10469 ,\ -10564 ,\ -10659 ,\ -10754 ,\ -10849 ,\ -10944 ,\ -11039 ,\ -11133 ,\ -11228 ,\ -11322 ,\ -11417 ,\ -11511 ,\ -11605 ,\ -11699 ,\ -11793 ,\ -11886 ,\ -11980 ,\ -12074 ,\ -12167 ,\ -12260 ,\ -12353 ,\ -12446 ,\ -12539 ,\ -12632 ,\ -12725 ,\ -12817 ,\ -12910 ,\ -13002 ,\ -13094 ,\ -13187 ,\ -13279 ,\ -13370 ,\ -13462 ,\ -13554 ,\ -13645 ,\ -13736 ,\ -13828 ,\ -13919 ,\ -14010 ,\ -14101 ,\ -14191 ,\ -14282 ,\ -14372 ,\ -14462 ,\ -14553 ,\ -14643 ,\ -14732 ,\ -14822 ,\ -14912 ,\ -15001 ,\ -15090 ,\ -15180 ,\ -15269 ,\ -15358 ,\ -15446 ,\ -15535 ,\ -15623 ,\ -15712 ,\ -15800 ,\ -15888 ,\ -15976 ,\ -16063 ,\ -16151 ,\ -16238 ,\ -16325 ,\ -16413 ,\ -16499 ,\ -16586 ,\ -16673 ,\ -16759 ,\ -16846 ,\ -16932 ,\ -17018 ,\ -17104 ,\ -17189 ,\ -17275 ,\ -17360 ,\ -17445 ,\ -17530 ,\ -17615 ,\ -17700 ,\ -17784 ,\ -17869 ,\ -17953 ,\ -18037 ,\ -18121 ,\ -18204 ,\ -18288 ,\ -18371 ,\ -18454 ,\ -18537 ,\ -18620 ,\ -18703 ,\ -18785 ,\ -18868 ,\ -18950 ,\ -19032 ,\ -19113 ,\ -19195 ,\ -19276 ,\ -19357 ,\ -19438 ,\ -19519 ,\ -19600 ,\ -19680 ,\ -19761 ,\ -19841 ,\ -19921 ,\ -20000 ,\ -20080 ,\ -20159 ,\ -20238 ,\ -20317 ,\ -20396 ,\ -20475 ,\ -20553 ,\ -20631 ,\ -20709 ,\ -20787 ,\ -20865 ,\ -20942 ,\ -21019 ,\ -21096 ,\ -21173 ,\ -21250 ,\ -21326 ,\ -21403 ,\ -21479 ,\ -21554 ,\ -21630 ,\ -21705 ,\ -21781 ,\ -21856 ,\ -21930 ,\ -22005 ,\ -22079 ,\ -22154 ,\ -22227 ,\ -22301 ,\ -22375 ,\ -22448 ,\ -22521 ,\ -22594 ,\ -22667 ,\ -22739 ,\ -22812 ,\ -22884 ,\ -22956 ,\ -23027 ,\ -23099 ,\ -23170 ,\ -23241 ,\ -23311 ,\ -23382 ,\ -23452 ,\ -23522 ,\ -23592 ,\ -23662 ,\ -23731 ,\ -23801 ,\ -23870 ,\ -23938 ,\ -24007 ,\ -24075 ,\ -24143 ,\ -24211 ,\ -24279 ,\ -24346 ,\ -24413 ,\ -24480 ,\ -24547 ,\ -24613 ,\ -24680 ,\ -24746 ,\ -24811 ,\ -24877 ,\ -24942 ,\ -25007 ,\ -25072 ,\ -25137 ,\ -25201 ,\ -25265 ,\ -25329 ,\ -25393 ,\ -25456 ,\ -25519 ,\ -25582 ,\ -25645 ,\ -25708 ,\ -25770 ,\ -25832 ,\ -25893 ,\ -25955 ,\ -26016 ,\ -26077 ,\ -26138 ,\ -26198 ,\ -26259 ,\ -26319 ,\ -26378 ,\ -26438 ,\ -26497 ,\ -26556 ,\ -26615 ,\ -26674 ,\ -26732 ,\ -26790 ,\ -26848 ,\ -26905 ,\ -26962 ,\ -27019 ,\ -27076 ,\ -27133 ,\ -27189 ,\ -27245 ,\ -27300 ,\ -27356 ,\ -27411 ,\ -27466 ,\ -27521 ,\ -27575 ,\ -27629 ,\ -27683 ,\ -27737 ,\ -27790 ,\ -27843 ,\ -27896 ,\ -27949 ,\ -28001 ,\ -28053 ,\ -28105 ,\ -28157 ,\ -28208 ,\ -28259 ,\ -28310 ,\ -28360 ,\ -28411 ,\ -28460 ,\ -28510 ,\ -28560 ,\ -28609 ,\ -28658 ,\ -28706 ,\ -28755 ,\ -28803 ,\ -28850 ,\ -28898 ,\ -28945 ,\ -28992 ,\ -29039 ,\ -29085 ,\ -29131 ,\ -29177 ,\ -29223 ,\ -29268 ,\ -29313 ,\ -29358 ,\ -29403 ,\ -29447 ,\ -29491 ,\ -29534 ,\ -29578 ,\ -29621 ,\ -29664 ,\ -29706 ,\ -29749 ,\ -29791 ,\ -29832 ,\ -29874 ,\ -29915 ,\ -29956 ,\ -29997 ,\ -30037 ,\ -30077 ,\ -30117 ,\ -30156 ,\ -30195 ,\ -30234 ,\ -30273 ,\ -30311 ,\ -30349 ,\ -30387 ,\ -30424 ,\ -30462 ,\ -30498 ,\ -30535 ,\ -30571 ,\ -30607 ,\ -30643 ,\ -30679 ,\ -30714 ,\ -30749 ,\ -30783 ,\ -30818 ,\ -30852 ,\ -30885 ,\ -30919 ,\ -30952 ,\ -30985 ,\ -31017 ,\ -31050 ,\ -31082 ,\ -31113 ,\ -31145 ,\ -31176 ,\ -31206 ,\ -31237 ,\ -31267 ,\ -31297 ,\ -31327 ,\ -31356 ,\ -31385 ,\ -31414 ,\ -31442 ,\ -31470 ,\ -31498 ,\ -31526 ,\ -31553 ,\ -31580 ,\ -31607 ,\ -31633 ,\ -31659 ,\ -31685 ,\ -31710 ,\ -31736 ,\ -31760 ,\ -31785 ,\ -31809 ,\ -31833 ,\ -31857 ,\ -31880 ,\ -31903 ,\ -31926 ,\ -31949 ,\ -31971 ,\ -31993 ,\ -32014 ,\ -32036 ,\ -32057 ,\ -32077 ,\ -32098 ,\ -32118 ,\ -32137 ,\ -32157 ,\ -32176 ,\ -32195 ,\ -32213 ,\ -32232 ,\ -32250 ,\ -32267 ,\ -32285 ,\ -32302 ,\ -32318 ,\ -32335 ,\ -32351 ,\ -32367 ,\ -32382 ,\ -32397 ,\ -32412 ,\ -32427 ,\ -32441 ,\ -32455 ,\ -32469 ,\ -32482 ,\ -32495 ,\ -32508 ,\ -32521 ,\ -32533 ,\ -32545 ,\ -32556 ,\ -32567 ,\ -32578 ,\ -32589 ,\ -32599 ,\ -32609 ,\ -32619 ,\ -32628 ,\ -32637 ,\ -32646 ,\ -32655 ,\ -32663 ,\ -32671 ,\ -32678 ,\ -32685 ,\ -32692 ,\ -32699 ,\ -32705 ,\ -32711 ,\ -32717 ,\ -32722 ,\ -32728 ,\ -32732 ,\ -32737 ,\ -32741 ,\ -32745 ,\ -32748 ,\ -32752 ,\ -32755 ,\ -32757 ,\ -32759 ,\ -32761 ,\ -32763 ,\ -32765 ,\ -32766 ,\ -32766 ,\ -32767 ,\ -32767 ,\ -32767 ,\ -32766 ,\ -32766 ,\ -32765 ,\ -32763 ,\ -32761 ,\ -32759 ,\ -32757 ,\ -32755 ,\ -32752 ,\ -32748 ,\ -32745 ,\ -32741 ,\ -32737 ,\ -32732 ,\ -32728 ,\ -32722 ,\ -32717 ,\ -32711 ,\ -32705 ,\ -32699 ,\ -32692 ,\ -32685 ,\ -32678 ,\ -32671 ,\ -32663 ,\ -32655 ,\ -32646 ,\ -32637 ,\ -32628 ,\ -32619 ,\ -32609 ,\ -32599 ,\ -32589 ,\ -32578 ,\ -32567 ,\ -32556 ,\ -32545 ,\ -32533 ,\ -32521 ,\ -32508 ,\ -32495 ,\ -32482 ,\ -32469 ,\ -32455 ,\ -32441 ,\ -32427 ,\ -32412 ,\ -32397 ,\ -32382 ,\ -32367 ,\ -32351 ,\ -32335 ,\ -32318 ,\ -32302 ,\ -32285 ,\ -32267 ,\ -32250 ,\ -32232 ,\ -32213 ,\ -32195 ,\ -32176 ,\ -32157 ,\ -32137 ,\ -32118 ,\ -32098 ,\ -32077 ,\ -32057 ,\ -32036 ,\ -32014 ,\ -31993 ,\ -31971 ,\ -31949 ,\ -31926 ,\ -31903 ,\ -31880 ,\ -31857 ,\ -31833 ,\ -31809 ,\ -31785 ,\ -31760 ,\ -31736 ,\ -31710 ,\ -31685 ,\ -31659 ,\ -31633 ,\ -31607 ,\ -31580 ,\ -31553 ,\ -31526 ,\ -31498 ,\ -31470 ,\ -31442 ,\ -31414 ,\ -31385 ,\ -31356 ,\ -31327 ,\ -31297 ,\ -31267 ,\ -31237 ,\ -31206 ,\ -31176 ,\ -31145 ,\ -31113 ,\ -31082 ,\ -31050 ,\ -31017 ,\ -30985 ,\ -30952 ,\ -30919 ,\ -30885 ,\ -30852 ,\ -30818 ,\ -30783 ,\ -30749 ,\ -30714 ,\ -30679 ,\ -30643 ,\ -30607 ,\ -30571 ,\ -30535 ,\ -30498 ,\ -30462 ,\ -30424 ,\ -30387 ,\ -30349 ,\ -30311 ,\ -30273 ,\ -30234 ,\ -30195 ,\ -30156 ,\ -30117 ,\ -30077 ,\ -30037 ,\ -29997 ,\ -29956 ,\ -29915 ,\ -29874 ,\ -29832 ,\ -29791 ,\ -29749 ,\ -29706 ,\ -29664 ,\ -29621 ,\ -29578 ,\ -29534 ,\ -29491 ,\ -29447 ,\ -29403 ,\ -29358 ,\ -29313 ,\ -29268 ,\ -29223 ,\ -29177 ,\ -29131 ,\ -29085 ,\ -29039 ,\ -28992 ,\ -28945 ,\ -28898 ,\ -28850 ,\ -28803 ,\ -28755 ,\ -28706 ,\ -28658 ,\ -28609 ,\ -28560 ,\ -28510 ,\ -28460 ,\ -28411 ,\ -28360 ,\ -28310 ,\ -28259 ,\ -28208 ,\ -28157 ,\ -28105 ,\ -28053 ,\ -28001 ,\ -27949 ,\ -27896 ,\ -27843 ,\ -27790 ,\ -27737 ,\ -27683 ,\ -27629 ,\ -27575 ,\ -27521 ,\ -27466 ,\ -27411 ,\ -27356 ,\ -27300 ,\ -27245 ,\ -27189 ,\ -27133 ,\ -27076 ,\ -27019 ,\ -26962 ,\ -26905 ,\ -26848 ,\ -26790 ,\ -26732 ,\ -26674 ,\ -26615 ,\ -26556 ,\ -26497 ,\ -26438 ,\ -26378 ,\ -26319 ,\ -26259 ,\ -26198 ,\ -26138 ,\ -26077 ,\ -26016 ,\ -25955 ,\ -25893 ,\ -25832 ,\ -25770 ,\ -25708 ,\ -25645 ,\ -25582 ,\ -25519 ,\ -25456 ,\ -25393 ,\ -25329 ,\ -25265 ,\ -25201 ,\ -25137 ,\ -25072 ,\ -25007 ,\ -24942 ,\ -24877 ,\ -24811 ,\ -24746 ,\ -24680 ,\ -24613 ,\ -24547 ,\ -24480 ,\ -24413 ,\ -24346 ,\ -24279 ,\ -24211 ,\ -24143 ,\ -24075 ,\ -24007 ,\ -23938 ,\ -23870 ,\ -23801 ,\ -23731 ,\ -23662 ,\ -23592 ,\ -23522 ,\ -23452 ,\ -23382 ,\ -23311 ,\ -23241 ,\ -23170 ,\ -23099 ,\ -23027 ,\ -22956 ,\ -22884 ,\ -22812 ,\ -22739 ,\ -22667 ,\ -22594 ,\ -22521 ,\ -22448 ,\ -22375 ,\ -22301 ,\ -22227 ,\ -22154 ,\ -22079 ,\ -22005 ,\ -21930 ,\ -21856 ,\ -21781 ,\ -21705 ,\ -21630 ,\ -21554 ,\ -21479 ,\ -21403 ,\ -21326 ,\ -21250 ,\ -21173 ,\ -21096 ,\ -21019 ,\ -20942 ,\ -20865 ,\ -20787 ,\ -20709 ,\ -20631 ,\ -20553 ,\ -20475 ,\ -20396 ,\ -20317 ,\ -20238 ,\ -20159 ,\ -20080 ,\ -20000 ,\ -19921 ,\ -19841 ,\ -19761 ,\ -19680 ,\ -19600 ,\ -19519 ,\ -19438 ,\ -19357 ,\ -19276 ,\ -19195 ,\ -19113 ,\ -19032 ,\ -18950 ,\ -18868 ,\ -18785 ,\ -18703 ,\ -18620 ,\ -18537 ,\ -18454 ,\ -18371 ,\ -18288 ,\ -18204 ,\ -18121 ,\ -18037 ,\ -17953 ,\ -17869 ,\ -17784 ,\ -17700 ,\ -17615 ,\ -17530 ,\ -17445 ,\ -17360 ,\ -17275 ,\ -17189 ,\ -17104 ,\ -17018 ,\ -16932 ,\ -16846 ,\ -16759 ,\ -16673 ,\ -16586 ,\ -16499 ,\ -16413 ,\ -16325 ,\ -16238 ,\ -16151 ,\ -16063 ,\ -15976 ,\ -15888 ,\ -15800 ,\ -15712 ,\ -15623 ,\ -15535 ,\ -15446 ,\ -15358 ,\ -15269 ,\ -15180 ,\ -15090 ,\ -15001 ,\ -14912 ,\ -14822 ,\ -14732 ,\ -14643 ,\ -14553 ,\ -14462 ,\ -14372 ,\ -14282 ,\ -14191 ,\ -14101 ,\ -14010 ,\ -13919 ,\ -13828 ,\ -13736 ,\ -13645 ,\ -13554 ,\ -13462 ,\ -13370 ,\ -13279 ,\ -13187 ,\ -13094 ,\ -13002 ,\ -12910 ,\ -12817 ,\ -12725 ,\ -12632 ,\ -12539 ,\ -12446 ,\ -12353 ,\ -12260 ,\ -12167 ,\ -12074 ,\ -11980 ,\ -11886 ,\ -11793 ,\ -11699 ,\ -11605 ,\ -11511 ,\ -11417 ,\ -11322 ,\ -11228 ,\ -11133 ,\ -11039 ,\ -10944 ,\ -10849 ,\ -10754 ,\ -10659 ,\ -10564 ,\ -10469 ,\ -10374 ,\ -10278 ,\ -10183 ,\ -10087 ,\ -9992 ,\ -9896 ,\ -9800 ,\ -9704 ,\ -9608 ,\ -9512 ,\ -9416 ,\ -9319 ,\ -9223 ,\ -9126 ,\ -9030 ,\ -8933 ,\ -8836 ,\ -8739 ,\ -8642 ,\ -8545 ,\ -8448 ,\ -8351 ,\ -8254 ,\ -8157 ,\ -8059 ,\ -7962 ,\ -7864 ,\ -7767 ,\ -7669 ,\ -7571 ,\ -7473 ,\ -7375 ,\ -7277 ,\ -7179 ,\ -7081 ,\ -6983 ,\ -6885 ,\ -6786 ,\ -6688 ,\ -6590 ,\ -6491 ,\ -6393 ,\ -6294 ,\ -6195 ,\ -6096 ,\ -5998 ,\ -5899 ,\ -5800 ,\ -5701 ,\ -5602 ,\ -5503 ,\ -5404 ,\ -5305 ,\ -5205 ,\ -5106 ,\ -5007 ,\ -4907 ,\ -4808 ,\ -4708 ,\ -4609 ,\ -4509 ,\ -4410 ,\ -4310 ,\ -4210 ,\ -4111 ,\ -4011 ,\ -3911 ,\ -3811 ,\ -3712 ,\ -3612 ,\ -3512 ,\ -3412 ,\ -3312 ,\ -3212 ,\ -3112 ,\ -3012 ,\ -2911 ,\ -2811 ,\ -2711 ,\ -2611 ,\ -2511 ,\ -2410 ,\ -2310 ,\ -2210 ,\ -2110 ,\ -2009 ,\ -1909 ,\ -1809 ,\ -1708 ,\ -1608 ,\ -1507 ,\ -1407 ,\ -1307 ,\ -1206 ,\ -1106 ,\ -1005 ,\ -905 ,\ -804 ,\ -704 ,\ -603 ,\ -503 ,\ -402 ,\ -302 ,\ -201 ,\ -101 ,\ -0 ,\ --101 ,\ --201 ,\ --302 ,\ --402 ,\ --503 ,\ --603 ,\ --704 ,\ --804 ,\ --905 ,\ --1005 ,\ --1106 ,\ --1206 ,\ --1307 ,\ --1407 ,\ --1507 ,\ --1608 ,\ --1708 ,\ --1809 ,\ --1909 ,\ --2009 ,\ --2110 ,\ --2210 ,\ --2310 ,\ --2410 ,\ --2511 ,\ --2611 ,\ --2711 ,\ --2811 ,\ --2911 ,\ --3012 ,\ --3112 ,\ --3212 ,\ --3312 ,\ --3412 ,\ --3512 ,\ --3612 ,\ --3712 ,\ --3811 ,\ --3911 ,\ --4011 ,\ --4111 ,\ --4210 ,\ --4310 ,\ --4410 ,\ --4509 ,\ --4609 ,\ --4708 ,\ --4808 ,\ --4907 ,\ --5007 ,\ --5106 ,\ --5205 ,\ --5305 ,\ --5404 ,\ --5503 ,\ --5602 ,\ --5701 ,\ --5800 ,\ --5899 ,\ --5998 ,\ --6096 ,\ --6195 ,\ --6294 ,\ --6393 ,\ --6491 ,\ --6590 ,\ --6688 ,\ --6786 ,\ --6885 ,\ --6983 ,\ --7081 ,\ --7179 ,\ --7277 ,\ --7375 ,\ --7473 ,\ --7571 ,\ --7669 ,\ --7767 ,\ --7864 ,\ --7962 ,\ --8059 ,\ --8157 ,\ --8254 ,\ --8351 ,\ --8448 ,\ --8545 ,\ --8642 ,\ --8739 ,\ --8836 ,\ --8933 ,\ --9030 ,\ --9126 ,\ --9223 ,\ --9319 ,\ --9416 ,\ --9512 ,\ --9608 ,\ --9704 ,\ --9800 ,\ --9896 ,\ --9992 ,\ --10087 ,\ --10183 ,\ --10278 ,\ --10374 ,\ --10469 ,\ --10564 ,\ --10659 ,\ --10754 ,\ --10849 ,\ --10944 ,\ --11039 ,\ --11133 ,\ --11228 ,\ --11322 ,\ --11417 ,\ --11511 ,\ --11605 ,\ --11699 ,\ --11793 ,\ --11886 ,\ --11980 ,\ --12074 ,\ --12167 ,\ --12260 ,\ --12353 ,\ --12446 ,\ --12539 ,\ --12632 ,\ --12725 ,\ --12817 ,\ --12910 ,\ --13002 ,\ --13094 ,\ --13187 ,\ --13279 ,\ --13370 ,\ --13462 ,\ --13554 ,\ --13645 ,\ --13736 ,\ --13828 ,\ --13919 ,\ --14010 ,\ --14101 ,\ --14191 ,\ --14282 ,\ --14372 ,\ --14462 ,\ --14553 ,\ --14643 ,\ --14732 ,\ --14822 ,\ --14912 ,\ --15001 ,\ --15090 ,\ --15180 ,\ --15269 ,\ --15358 ,\ --15446 ,\ --15535 ,\ --15623 ,\ --15712 ,\ --15800 ,\ --15888 ,\ --15976 ,\ --16063 ,\ --16151 ,\ --16238 ,\ --16325 ,\ --16413 ,\ --16499 ,\ --16586 ,\ --16673 ,\ --16759 ,\ --16846 ,\ --16932 ,\ --17018 ,\ --17104 ,\ --17189 ,\ --17275 ,\ --17360 ,\ --17445 ,\ --17530 ,\ --17615 ,\ --17700 ,\ --17784 ,\ --17869 ,\ --17953 ,\ --18037 ,\ --18121 ,\ --18204 ,\ --18288 ,\ --18371 ,\ --18454 ,\ --18537 ,\ --18620 ,\ --18703 ,\ --18785 ,\ --18868 ,\ --18950 ,\ --19032 ,\ --19113 ,\ --19195 ,\ --19276 ,\ --19357 ,\ --19438 ,\ --19519 ,\ --19600 ,\ --19680 ,\ --19761 ,\ --19841 ,\ --19921 ,\ --20000 ,\ --20080 ,\ --20159 ,\ --20238 ,\ --20317 ,\ --20396 ,\ --20475 ,\ --20553 ,\ --20631 ,\ --20709 ,\ --20787 ,\ --20865 ,\ --20942 ,\ --21019 ,\ --21096 ,\ --21173 ,\ --21250 ,\ --21326 ,\ --21403 ,\ --21479 ,\ --21554 ,\ --21630 ,\ --21705 ,\ --21781 ,\ --21856 ,\ --21930 ,\ --22005 ,\ --22079 ,\ --22154 ,\ --22227 ,\ --22301 ,\ --22375 ,\ --22448 ,\ --22521 ,\ --22594 ,\ --22667 ,\ --22739 ,\ --22812 ,\ --22884 ,\ --22956 ,\ --23027 ,\ --23099 ,\ --23170 ,\ --23241 ,\ --23311 ,\ --23382 ,\ --23452 ,\ --23522 ,\ --23592 ,\ --23662 ,\ --23731 ,\ --23801 ,\ --23870 ,\ --23938 ,\ --24007 ,\ --24075 ,\ --24143 ,\ --24211 ,\ --24279 ,\ --24346 ,\ --24413 ,\ --24480 ,\ --24547 ,\ --24613 ,\ --24680 ,\ --24746 ,\ --24811 ,\ --24877 ,\ --24942 ,\ --25007 ,\ --25072 ,\ --25137 ,\ --25201 ,\ --25265 ,\ --25329 ,\ --25393 ,\ --25456 ,\ --25519 ,\ --25582 ,\ --25645 ,\ --25708 ,\ --25770 ,\ --25832 ,\ --25893 ,\ --25955 ,\ --26016 ,\ --26077 ,\ --26138 ,\ --26198 ,\ --26259 ,\ --26319 ,\ --26378 ,\ --26438 ,\ --26497 ,\ --26556 ,\ --26615 ,\ --26674 ,\ --26732 ,\ --26790 ,\ --26848 ,\ --26905 ,\ --26962 ,\ --27019 ,\ --27076 ,\ --27133 ,\ --27189 ,\ --27245 ,\ --27300 ,\ --27356 ,\ --27411 ,\ --27466 ,\ --27521 ,\ --27575 ,\ --27629 ,\ --27683 ,\ --27737 ,\ --27790 ,\ --27843 ,\ --27896 ,\ --27949 ,\ --28001 ,\ --28053 ,\ --28105 ,\ --28157 ,\ --28208 ,\ --28259 ,\ --28310 ,\ --28360 ,\ --28411 ,\ --28460 ,\ --28510 ,\ --28560 ,\ --28609 ,\ --28658 ,\ --28706 ,\ --28755 ,\ --28803 ,\ --28850 ,\ --28898 ,\ --28945 ,\ --28992 ,\ --29039 ,\ --29085 ,\ --29131 ,\ --29177 ,\ --29223 ,\ --29268 ,\ --29313 ,\ --29358 ,\ --29403 ,\ --29447 ,\ --29491 ,\ --29534 ,\ --29578 ,\ --29621 ,\ --29664 ,\ --29706 ,\ --29749 ,\ --29791 ,\ --29832 ,\ --29874 ,\ --29915 ,\ --29956 ,\ --29997 ,\ --30037 ,\ --30077 ,\ --30117 ,\ --30156 ,\ --30195 ,\ --30234 ,\ --30273 ,\ --30311 ,\ --30349 ,\ --30387 ,\ --30424 ,\ --30462 ,\ --30498 ,\ --30535 ,\ --30571 ,\ --30607 ,\ --30643 ,\ --30679 ,\ --30714 ,\ --30749 ,\ --30783 ,\ --30818 ,\ --30852 ,\ --30885 ,\ --30919 ,\ --30952 ,\ --30985 ,\ --31017 ,\ --31050 ,\ --31082 ,\ --31113 ,\ --31145 ,\ --31176 ,\ --31206 ,\ --31237 ,\ --31267 ,\ --31297 ,\ --31327 ,\ --31356 ,\ --31385 ,\ --31414 ,\ --31442 ,\ --31470 ,\ --31498 ,\ --31526 ,\ --31553 ,\ --31580 ,\ --31607 ,\ --31633 ,\ --31659 ,\ --31685 ,\ --31710 ,\ --31736 ,\ --31760 ,\ --31785 ,\ --31809 ,\ --31833 ,\ --31857 ,\ --31880 ,\ --31903 ,\ --31926 ,\ --31949 ,\ --31971 ,\ --31993 ,\ --32014 ,\ --32036 ,\ --32057 ,\ --32077 ,\ --32098 ,\ --32118 ,\ --32137 ,\ --32157 ,\ --32176 ,\ --32195 ,\ --32213 ,\ --32232 ,\ --32250 ,\ --32267 ,\ --32285 ,\ --32302 ,\ --32318 ,\ --32335 ,\ --32351 ,\ --32367 ,\ --32382 ,\ --32397 ,\ --32412 ,\ --32427 ,\ --32441 ,\ --32455 ,\ --32469 ,\ --32482 ,\ --32495 ,\ --32508 ,\ --32521 ,\ --32533 ,\ --32545 ,\ --32556 ,\ --32567 ,\ --32578 ,\ --32589 ,\ --32599 ,\ --32609 ,\ --32619 ,\ --32628 ,\ --32637 ,\ --32646 ,\ --32655 ,\ --32663 ,\ --32671 ,\ --32678 ,\ --32685 ,\ --32692 ,\ --32699 ,\ --32705 ,\ --32711 ,\ --32717 ,\ --32722 ,\ --32728 ,\ --32732 ,\ --32737 ,\ --32741 ,\ --32745 ,\ --32748 ,\ --32752 ,\ --32755 ,\ --32757 ,\ --32759 ,\ --32761 ,\ --32763 ,\ --32765 ,\ --32766 ,\ --32766 ,\ --32767 ,\ --32767 ,\ --32767 ,\ --32766 ,\ --32766 ,\ --32765 ,\ --32763 ,\ --32761 ,\ --32759 ,\ --32757 ,\ --32755 ,\ --32752 ,\ --32748 ,\ --32745 ,\ --32741 ,\ --32737 ,\ --32732 ,\ --32728 ,\ --32722 ,\ --32717 ,\ --32711 ,\ --32705 ,\ --32699 ,\ --32692 ,\ --32685 ,\ --32678 ,\ --32671 ,\ --32663 ,\ --32655 ,\ --32646 ,\ --32637 ,\ --32628 ,\ --32619 ,\ --32609 ,\ --32599 ,\ --32589 ,\ --32578 ,\ --32567 ,\ --32556 ,\ --32545 ,\ --32533 ,\ --32521 ,\ --32508 ,\ --32495 ,\ --32482 ,\ --32469 ,\ --32455 ,\ --32441 ,\ --32427 ,\ --32412 ,\ --32397 ,\ --32382 ,\ --32367 ,\ --32351 ,\ --32335 ,\ --32318 ,\ --32302 ,\ --32285 ,\ --32267 ,\ --32250 ,\ --32232 ,\ --32213 ,\ --32195 ,\ --32176 ,\ --32157 ,\ --32137 ,\ --32118 ,\ --32098 ,\ --32077 ,\ --32057 ,\ --32036 ,\ --32014 ,\ --31993 ,\ --31971 ,\ --31949 ,\ --31926 ,\ --31903 ,\ --31880 ,\ --31857 ,\ --31833 ,\ --31809 ,\ --31785 ,\ --31760 ,\ --31736 ,\ --31710 ,\ --31685 ,\ --31659 ,\ --31633 ,\ --31607 ,\ --31580 ,\ --31553 ,\ --31526 ,\ --31498 ,\ --31470 ,\ --31442 ,\ --31414 ,\ --31385 ,\ --31356 ,\ --31327 ,\ --31297 ,\ --31267 ,\ --31237 ,\ --31206 ,\ --31176 ,\ --31145 ,\ --31113 ,\ --31082 ,\ --31050 ,\ --31017 ,\ --30985 ,\ --30952 ,\ --30919 ,\ --30885 ,\ --30852 ,\ --30818 ,\ --30783 ,\ --30749 ,\ --30714 ,\ --30679 ,\ --30643 ,\ --30607 ,\ --30571 ,\ --30535 ,\ --30498 ,\ --30462 ,\ --30424 ,\ --30387 ,\ --30349 ,\ --30311 ,\ --30273 ,\ --30234 ,\ --30195 ,\ --30156 ,\ --30117 ,\ --30077 ,\ --30037 ,\ --29997 ,\ --29956 ,\ --29915 ,\ --29874 ,\ --29832 ,\ --29791 ,\ --29749 ,\ --29706 ,\ --29664 ,\ --29621 ,\ --29578 ,\ --29534 ,\ --29491 ,\ --29447 ,\ --29403 ,\ --29358 ,\ --29313 ,\ --29268 ,\ --29223 ,\ --29177 ,\ --29131 ,\ --29085 ,\ --29039 ,\ --28992 ,\ --28945 ,\ --28898 ,\ --28850 ,\ --28803 ,\ --28755 ,\ --28706 ,\ --28658 ,\ --28609 ,\ --28560 ,\ --28510 ,\ --28460 ,\ --28411 ,\ --28360 ,\ --28310 ,\ --28259 ,\ --28208 ,\ --28157 ,\ --28105 ,\ --28053 ,\ --28001 ,\ --27949 ,\ --27896 ,\ --27843 ,\ --27790 ,\ --27737 ,\ --27683 ,\ --27629 ,\ --27575 ,\ --27521 ,\ --27466 ,\ --27411 ,\ --27356 ,\ --27300 ,\ --27245 ,\ --27189 ,\ --27133 ,\ --27076 ,\ --27019 ,\ --26962 ,\ --26905 ,\ --26848 ,\ --26790 ,\ --26732 ,\ --26674 ,\ --26615 ,\ --26556 ,\ --26497 ,\ --26438 ,\ --26378 ,\ --26319 ,\ --26259 ,\ --26198 ,\ --26138 ,\ --26077 ,\ --26016 ,\ --25955 ,\ --25893 ,\ --25832 ,\ --25770 ,\ --25708 ,\ --25645 ,\ --25582 ,\ --25519 ,\ --25456 ,\ --25393 ,\ --25329 ,\ --25265 ,\ --25201 ,\ --25137 ,\ --25072 ,\ --25007 ,\ --24942 ,\ --24877 ,\ --24811 ,\ --24746 ,\ --24680 ,\ --24613 ,\ --24547 ,\ --24480 ,\ --24413 ,\ --24346 ,\ --24279 ,\ --24211 ,\ --24143 ,\ --24075 ,\ --24007 ,\ --23938 ,\ --23870 ,\ --23801 ,\ --23731 ,\ --23662 ,\ --23592 ,\ --23522 ,\ --23452 ,\ --23382 ,\ --23311 ,\ --23241 ,\ --23170 ,\ --23099 ,\ --23027 ,\ --22956 ,\ --22884 ,\ --22812 ,\ --22739 ,\ --22667 ,\ --22594 ,\ --22521 ,\ --22448 ,\ --22375 ,\ --22301 ,\ --22227 ,\ --22154 ,\ --22079 ,\ --22005 ,\ --21930 ,\ --21856 ,\ --21781 ,\ --21705 ,\ --21630 ,\ --21554 ,\ --21479 ,\ --21403 ,\ --21326 ,\ --21250 ,\ --21173 ,\ --21096 ,\ --21019 ,\ --20942 ,\ --20865 ,\ --20787 ,\ --20709 ,\ --20631 ,\ --20553 ,\ --20475 ,\ --20396 ,\ --20317 ,\ --20238 ,\ --20159 ,\ --20080 ,\ --20000 ,\ --19921 ,\ --19841 ,\ --19761 ,\ --19680 ,\ --19600 ,\ --19519 ,\ --19438 ,\ --19357 ,\ --19276 ,\ --19195 ,\ --19113 ,\ --19032 ,\ --18950 ,\ --18868 ,\ --18785 ,\ --18703 ,\ --18620 ,\ --18537 ,\ --18454 ,\ --18371 ,\ --18288 ,\ --18204 ,\ --18121 ,\ --18037 ,\ --17953 ,\ --17869 ,\ --17784 ,\ --17700 ,\ --17615 ,\ --17530 ,\ --17445 ,\ --17360 ,\ --17275 ,\ --17189 ,\ --17104 ,\ --17018 ,\ --16932 ,\ --16846 ,\ --16759 ,\ --16673 ,\ --16586 ,\ --16499 ,\ --16413 ,\ --16325 ,\ --16238 ,\ --16151 ,\ --16063 ,\ --15976 ,\ --15888 ,\ --15800 ,\ --15712 ,\ --15623 ,\ --15535 ,\ --15446 ,\ --15358 ,\ --15269 ,\ --15180 ,\ --15090 ,\ --15001 ,\ --14912 ,\ --14822 ,\ --14732 ,\ --14643 ,\ --14553 ,\ --14462 ,\ --14372 ,\ --14282 ,\ --14191 ,\ --14101 ,\ --14010 ,\ --13919 ,\ --13828 ,\ --13736 ,\ --13645 ,\ --13554 ,\ --13462 ,\ --13370 ,\ --13279 ,\ --13187 ,\ --13094 ,\ --13002 ,\ --12910 ,\ --12817 ,\ --12725 ,\ --12632 ,\ --12539 ,\ --12446 ,\ --12353 ,\ --12260 ,\ --12167 ,\ --12074 ,\ --11980 ,\ --11886 ,\ --11793 ,\ --11699 ,\ --11605 ,\ --11511 ,\ --11417 ,\ --11322 ,\ --11228 ,\ --11133 ,\ --11039 ,\ --10944 ,\ --10849 ,\ --10754 ,\ --10659 ,\ --10564 ,\ --10469 ,\ --10374 ,\ --10278 ,\ --10183 ,\ --10087 ,\ --9992 ,\ --9896 ,\ --9800 ,\ --9704 ,\ --9608 ,\ --9512 ,\ --9416 ,\ --9319 ,\ --9223 ,\ --9126 ,\ --9030 ,\ --8933 ,\ --8836 ,\ --8739 ,\ --8642 ,\ --8545 ,\ --8448 ,\ --8351 ,\ --8254 ,\ --8157 ,\ --8059 ,\ --7962 ,\ --7864 ,\ --7767 ,\ --7669 ,\ --7571 ,\ --7473 ,\ --7375 ,\ --7277 ,\ --7179 ,\ --7081 ,\ --6983 ,\ --6885 ,\ --6786 ,\ --6688 ,\ --6590 ,\ --6491 ,\ --6393 ,\ --6294 ,\ --6195 ,\ --6096 ,\ --5998 ,\ --5899 ,\ --5800 ,\ --5701 ,\ --5602 ,\ --5503 ,\ --5404 ,\ --5305 ,\ --5205 ,\ --5106 ,\ --5007 ,\ --4907 ,\ --4808 ,\ --4708 ,\ --4609 ,\ --4509 ,\ --4410 ,\ --4310 ,\ --4210 ,\ --4111 ,\ --4011 ,\ --3911 ,\ --3811 ,\ --3712 ,\ --3612 ,\ --3512 ,\ --3412 ,\ --3312 ,\ --3212 ,\ --3112 ,\ --3012 ,\ --2911 ,\ --2811 ,\ --2711 ,\ --2611 ,\ --2511 ,\ --2410 ,\ --2310 ,\ --2210 ,\ --2110 ,\ --2009 ,\ --1909 ,\ --1809 ,\ --1708 ,\ --1608 ,\ --1507 ,\ --1407 ,\ --1307 ,\ --1206 ,\ --1106 ,\ --1005 ,\ --905 ,\ --804 ,\ --704 ,\ --603 ,\ --503 ,\ --402 ,\ --302 ,\ --201 ,\ --101 - - -#endif // SINE_CORE_H_INCLUDED diff --git a/libopeninv/include/stm32_can.h b/libopeninv/include/stm32_can.h deleted file mode 100644 index a9f2f64..0000000 --- a/libopeninv/include/stm32_can.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2016 Nail Güzel - * Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef STM32_CAN_H_INCLUDED -#define STM32_CAN_H_INCLUDED -#include "params.h" - -#define CAN_ERR_INVALID_ID -1 -#define CAN_ERR_INVALID_OFS -2 -#define CAN_ERR_INVALID_LEN -3 -#define CAN_ERR_MAXMESSAGES -4 -#define CAN_ERR_MAXITEMS -5 - -#ifndef MAX_ITEMS -#define MAX_ITEMS 70 -#endif // MAX_ITEMS_PER_MESSAGE - -#ifndef MAX_MESSAGES -#define MAX_MESSAGES 10 -#endif // MAX_MESSAGES - -#ifndef SENDBUFFER_LEN -#define SENDBUFFER_LEN 20 -#endif // SENDBUFFER_LEN - -#ifndef MAX_USER_MESSAGES -#define MAX_USER_MESSAGES 10 -#endif // MAX_USER_MESSAGES - - -class CANIDMAP; -class SENDBUFFER; - -class Can -{ -public: - enum baudrates - { - Baud125, Baud250, Baud500, Baud800, Baud1000, BaudLast - }; - - Can(uint32_t baseAddr, enum baudrates baudrate, bool remap = false); - void Clear(void); - void SetBaudrate(enum baudrates baudrate); - void Send(uint32_t canId, uint32_t data[2]) { Send(canId, data, 8); } - void Send(uint32_t canId, uint8_t data[8], uint8_t len) { Send(canId, (uint32_t*)data, len); } - void Send(uint32_t canId, uint32_t data[2], uint8_t len); - void SendAll(); - void SDOWrite(uint8_t remoteNodeId, uint16_t index, uint8_t subIndex, uint32_t data); - void Save(); - void SetReceiveCallback(void (*recv)(uint32_t, uint32_t*)); - bool RegisterUserMessage(uint32_t canId); - void ClearUserMessages(); - uint32_t GetLastRxTimestamp(); - int AddSend(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain); - int AddRecv(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain); - int AddSend(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset); - int AddRecv(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset); - int Remove(Param::PARAM_NUM param); - bool FindMap(Param::PARAM_NUM param, uint32_t& canId, uint8_t& offset, uint8_t& length, float& gain, bool& rx); - void IterateCanMap(void (*callback)(Param::PARAM_NUM, uint32_t, uint8_t, uint8_t, float, bool)); - void HandleRx(int fifo); - void HandleTx(); - void SetNodeId(uint8_t id) { nodeId = id; } - static Can* GetInterface(int index); - -private: - static volatile bool isSaving; - - struct CANPOS - { - float gain; - uint16_t mapParam; - int8_t offset; - uint8_t offsetBits; - uint8_t numBits; - uint8_t next; - }; - - struct CANIDMAP - { - #ifdef CAN_EXT - uint32_t canId; - #else - uint16_t canId; - #endif // CAN_EXT - uint8_t first; - }; - - struct SENDBUFFER - { - uint32_t id; - uint32_t len; - uint32_t data[2]; - }; - - CANIDMAP canSendMap[MAX_MESSAGES]; - CANIDMAP canRecvMap[MAX_MESSAGES]; - CANPOS canPosMap[MAX_ITEMS + 1]; //Last item is a "tail" - uint32_t lastRxTimestamp; - SENDBUFFER sendBuffer[SENDBUFFER_LEN]; - int sendCnt; - void (*recvCallback)(uint32_t, uint32_t*); - uint16_t userIds[MAX_USER_MESSAGES]; - int nextUserMessageIndex; - uint32_t canDev; - uint8_t nodeId; - - void ProcessSDO(uint32_t data[2]); - void ClearMap(CANIDMAP *canMap); - int RemoveFromMap(CANIDMAP *canMap, Param::PARAM_NUM param); - int Add(CANIDMAP *canMap, Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset); - uint32_t SaveToFlash(uint32_t baseAddress, uint32_t* data, int len); - int LoadFromFlash(); - CANIDMAP *FindById(CANIDMAP *canMap, uint32_t canId); - int CopyIdMapExcept(CANIDMAP *source, CANIDMAP *dest, Param::PARAM_NUM param); - void ReplaceParamEnumByUid(CANIDMAP *canMap); - void ReplaceParamUidByEnum(CANIDMAP *canMap); - void ConfigureFilters(); - void SetFilterBank(int& idIndex, int& filterId, uint16_t* idList); - void SetFilterBank29(int& idIndex, int& filterId, uint32_t* idList); - uint32_t GetFlashAddress(); - - static Can* interfaces[]; -}; - - -#endif diff --git a/libopeninv/include/stm32_loader.h b/libopeninv/include/stm32_loader.h deleted file mode 100644 index f15357d..0000000 --- a/libopeninv/include/stm32_loader.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2018 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef STM32_LOADER_H_INCLUDED -#define STM32_LOADER_H_INCLUDED -#include - -#define PINDEF_BLKNUM 3 //3rd to last flash page -#define PINDEF_BLKSIZE 1024 -#define NUM_PIN_COMMANDS 10 -#define PIN_IN 0 -#define PIN_OUT 1 - -struct pindef -{ - uint32_t port; - uint16_t pin; - uint8_t inout; - uint8_t level; -}; - -struct pincommands -{ - struct pindef pindef[NUM_PIN_COMMANDS]; - uint32_t crc; -}; - -#define PINDEF_NUMWORDS (sizeof(struct pindef) * NUM_PIN_COMMANDS / 4) - - -#endif // STM32_LOADER_H_INCLUDED diff --git a/libopeninv/include/stm32scheduler.h b/libopeninv/include/stm32scheduler.h deleted file mode 100644 index 9007070..0000000 --- a/libopeninv/include/stm32scheduler.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2017 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef STM32SCHEDULER_H -#define STM32SCHEDULER_H -#include -#include -#include -#include - -#define MAX_TASKS 4 - -/** @brief Schedules up to 4 tasks using a timer peripheral */ -class Stm32Scheduler -{ - public: - /** @brief construct a new scheduler using given timer - * @pre Timer clock and NVIC interrupt must be enabled - * @param timer Address of timer peripheral to use - */ - Stm32Scheduler(uint32_t timer); - - /** @brief Add a periodic task, can be called up to 4 times - * @param function the task function - * @param period The calling period in 100*ms - */ - void AddTask(void (*function)(void), uint16_t period); - - /** @brief Run the scheduler, must be called by the scheduler timer ISR */ - void Run(); - - /** @brief Return CPU load caused by scheduler tasks - * @return load in 0.1% - */ - int GetCpuLoad(); - - protected: - private: - static const enum tim_oc_id ocMap[MAX_TASKS]; - void (*functions[MAX_TASKS]) (void); - uint16_t periods[MAX_TASKS]; - uint16_t execTicks[MAX_TASKS]; - uint32_t timer; - int nextTask; -}; - -#endif // STM32SCHEDULER_H diff --git a/libopeninv/include/terminal.h b/libopeninv/include/terminal.h deleted file mode 100644 index 4a29635..0000000 --- a/libopeninv/include/terminal.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef TERMINAL_H -#define TERMINAL_H -#include -#include "printf.h" - -class Terminal; - -typedef struct -{ - char const *cmd; - void (*CmdFunc)(Terminal*, char*); -} TERM_CMD; - -class Terminal: public IPutChar -{ -public: - Terminal(uint32_t usart, const TERM_CMD* commands, bool remap = false); - void SetNodeId(uint8_t id); - void Run(); - void PutChar(char c); - bool KeyPressed(); - void FlushInput(); - void DisableTxDMA(); - static Terminal* defaultTerminal; - -private: - struct HwInfo - { - uint32_t usart; - uint8_t dmatx; - uint8_t dmarx; - uint32_t port; - uint16_t pin; - uint32_t port_re; - uint16_t pin_re; - }; - - void ResetDMA(); - const TERM_CMD *CmdLookup(char *buf); - void EnableUart(char* arg); - void FastUart(char* arg); - void Send(const char *str); - - static const int bufSize = 128; - static const HwInfo hwInfo[]; - const HwInfo* hw; - uint32_t usart; - bool remap; - const TERM_CMD* termCmds; - uint8_t nodeId; - bool enabled; - bool txDmaEnabled; - const TERM_CMD *pCurCmd; - int lastIdx; - uint8_t curBuf; - uint32_t curIdx; - bool firstSend; - char inBuf[bufSize]; - char outBuf[2][bufSize]; //double buffering - char args[bufSize]; -}; - -#endif // TERMINAL_H diff --git a/libopeninv/include/terminalcommands.h b/libopeninv/include/terminalcommands.h deleted file mode 100644 index 8a8909a..0000000 --- a/libopeninv/include/terminalcommands.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2021 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef TERMINALCOMMANDS_H -#define TERMINALCOMMANDS_H - - -class TerminalCommands -{ - public: - static void ParamSet(Terminal* term, char* arg); - static void ParamGet(Terminal* term, char *arg); - static void ParamFlag(Terminal* term, char *arg); - static void ParamStream(Terminal* term, char *arg); - static void PrintParamsJson(Terminal* term, char *arg); - static void MapCan(Terminal* term, char *arg); - static void SaveParameters(Terminal* term, char *arg); - static void LoadParameters(Terminal* term, char *arg); - static void Reset(Terminal* term, char *arg); - - protected: - - private: - static void PrintCanMap(Param::PARAM_NUM param, uint32_t canid, uint8_t offset, uint8_t length, float gain, bool rx); -}; - -#endif // TERMINALCOMMANDS_H diff --git a/libopeninv/libopeninv.a b/libopeninv/libopeninv.a deleted file mode 100644 index fa7118d896ed11a3c4a61dfd2fd4cfb83e421580..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 58174 zcmeHw4R~C|dG3*9V__U5i1`U|U@?C-7_lq)M*;&Y>|@rcWh=Jj7y?LZX>AE)Nm=b0 zIYq`qIQ2$#>r0Z>X=&po+=irWpuGuo2|+S&ZKrip(Lm}Z&W!*k6_J}L7bhr*6W{Nh z`Mz^zN9WjU12=7-&hzZf%=`V!H$P`)&YYQZE?<~TH@Dt0^@d2kiyBcKHvc1$%Id0W z&C)d0ahx{CIp@wZ|DFFa$2pVV)%QA%`HTIj;}r6{<>QX?R)1Y<9Ov!${n7c3Bfrm{ z>o{-c?>pBzj{j@CbNRf*Z5x($)}%U;>)KO|Z5^)TgPGQJD%F(_E@)4+GL#KjEzT|TVp|bn_DY`;i_Ob7OcB67_Q2LYdexl zJF1&eHtlU2b)FSAH=E4%xK1ja?o2Oh>&~poq}w_+==g2f_3Kk+*?qhvC7+1nPpzK!xM&Cs0k#zo?3LKGYLPL>1>1F{o!;5 zetU3sntfso)0VdAcB#v) zhD@)`Q0cC-QuYNGEbUfB9Lf-@T-KRvS)5v*%(iE^A!_Zh81mJg+|a!;dA}v!YNWti z76%nYEUN2s$uhc3e1V!p?WtrMiVGG&9R&zLXRONY$)wU9_1Vm#)?|7C`>ray>ZKfA zRH-hp)oVNivR-6SjIY2dUHHCKJ@l+z6U!&)g!6f0uHq$w^6)%^=69jLT2EE`5muXL zJYfsEnWdST7OZE$GghRRS}8#zVYbHAOFc<&tO}4KY=YD(Qz}-I&NMe}NM#zEJF^{B z+>M)(?dV=&bJ2;X6=^-y=)LGQW2$G@U|Ta-v#EP)h_R7kZ7sw>BSC%JqRx&?y0g7K zm5xQJ4b`=E)FpfFaNE?CWiiZKnd(+oVQNE~dX==UEouNFnv}M{lI~1W(5!Q6JXK1)H5R5N0XJBPWaB-?Vxf$_ln6omKR4G?RRkqil z0K1oVtXRLkuCqleioyn0%~F(_YLyhOfDNhi5_K&zPJFe^i}Yx^tZiePPL^y|tYmd2 zRhMjTZR=2qt(xKM#zy6G$*aYxmDvv6Z(EgDLxlQtXIEz$C6jDl(b2w{7+cylv~@Oa z>}}@1*T=Fd7TZ!8t%%O8h|Sixl7_l+`b~!D@&>2a zaRz~v(C=gpwoP(=aw3SQB+zo`B<%sNBqX&GWz|H166dUmAR#4Wk?oMT^9=n`rdKg8 zaq(|tTr3s5j&Ug$!PhY^DGR=tag-~Z;QbVaJ(2^#KgYPLLxcZm#!JbE6aE(|3_WKn z)W=5{$1NJ1@S~!@e~vRP*6#w9Mk+4!5gy3i&5_nn7d3NgCb zIlVg%r=olF#!PY@`I)r#TP2i9^<-hTa zOtSetj&JD5R&-H!l}cyOEZ-LQUebcLCGA+0#wB3+;5FUl6agmJlhEQEkoGRP*UlKY zhJ5hY@(HHDi+%Cz^yd%(SX3C;7kSW4C-UOYBcg;&zKj_$!Zxooz z%@{3DHCE1xR#l$vSUIcAHz2Npap!!p{Ef0pf6ZQ(g4VyPw~gk0*8| zc3c3dvZp4M_l*@jJeW!ME8cB`nO09wL%G4kj%oiJ+$;q8r1Scf0%rMVVtLtM0o^_B zC9`i*d6DMq8!YM@E}3Z8e)l-U`+AR;+&>+n+CCC=`rPA1qd%ZbNFL0TYo5z|z&CR` zo2jzWKfTzeNCq@zQc><(x&0$ZaiUqHpE1)?0)Es~3q5~}4~cD&ymr;^?~JSmZTF0n%yoamoM z>L$SblZsI%c@`y5PE@1&CS+#k*Plnm@|@jQKySs8x?Q#h&scl%c+Hu#e z1{S?}`HJQ4oJj0upK(s4QeujCPNeE)%|6FjwR%Opv)El(yV`X=Si5q$v%E8+S3}-4 z)%nm>*}HFyT-6=9p8hCqxS;FbAiwqC+dLPY&K4DYWTjKoQ(pAmX;VsfQpYlbaQxsd z!k>F?`NxVEz3Z&y#6VHd76K>thxikE@$V@H(C-3HPWAgjZ}#OM&}63_zR-&`1LPlN zI_8@m{dQme8K%=Rv`;U7$V>k)(>LbPTeJeE*&h1T)1QL}*Lu+08R?zQ9GsT5X-xEI z1aT-}SE5ECiD`cpc}0Y)GNZ7JO`!TSRm6Pf&s2R3p%TX)@io1K?v89%Nx*rAJ!m6v zx6u!CVQ~=-EGPdwZwBnoh3{otu6OZ&mvPZ6_+K$TjeI!4|DM9oFXbTk5yHr&V+m^YFRHx>Wp>8SCb};os`1lF!uH%LT9DTpw3k}@l zUuxj*HuzTD zD0(ijaOvkO3>;&|H2T5aV&KRZJ#tqr!ML3-CaV!c&2Slz>kH-rXS1CM(*>7wqZW?5 znNIj44BGnZ8JF=%_!}4(Il=F;aAc3Os3>u!3od$_Ec{81Z?$k4_jX&jjBkS$F5}y< zh08d3vZa|ct$SBYSf5FE>ctvGMX-WG73t23_Ri*HyMtI#t>-A5!P8jO(F#(njqB;* zV~Wjw%U*;uppN_*omLswp0mQNB*LtygEbp?FaFUCdM6Cgw-^p^hYdDL>k-5}5v0PJb55iznBy#6LiRp!9nJ(ns2M`s)cp z{-g9W-Q%1->c@28g%iKi2rB~ry<`_C<02=#4^kj#jqMQ2M}(1mv0q@!tD)1b|8bTd z7e@AN`9}y3D!)Tqevh*p>JN~}OZ^3<4UsW!s6%WR>W#J$O^^>=~2I<%hXL zP*HD1V&wizd)~h-Pa7rHcj-rAYU%D&YkZZ}QE!J?q0htia9&_UTv-yQvYh6v@zDxU zG?D8)l*_)<*ZY#QdCDHlEk`Hsfw4LFXuo^3> zM9v-W>pkjho<_0pea`iXK6kvRzitfCr*VIo`$mG7%4q4Rh}M)8Uxnh^?~Z__uXm(q zQ$@df>?U`ln-xX1B6lSB+@60tc<^AN?1|?Rdq*OBM@n+;$mqfTI;1}#2{Or8;>z`o z_^@tY%5ZF?dV?du(nlr17#Tr30TTw3)#x_5Xo9<4cVX30cC z$wcteBHwjX+2ciY*w?*-{nYg6!)( z=4^?P(PVpyTGrt!+%Z}XJr~(Pvs3tC_+AOQ$40-t=Q5JLPT5C>?%jC!5)yqDvo>mA z7_f?9{_*<;FI4RlVWTbd9gR?#4{)R`F`Dc3`-Cx^#064kF@aL`l z{jn$iC~$H+@#oQh=Qp}`hrYj@d`^foEpLJaROY{x`iF$s}+8u~NYlAZg zH`lCGoe*{<{ZPNQ!}Ina{5Ha&N92#Q;QJZ>E;=@Hs?Nw?Nk8x}<@~C;0)rleu<2=8 zEY{w+p|UaAMGr%JXjhJG6bxReAVIb5FL)ba2D-_i-A<#Q+~fTVKyo%7QK+6vu!#zZ zTe#%6$-*VSTP59 z?K#)gj9bY#U$X($W2Zldb=vHO%F8{6*vZLw=|jKiBz^I5JxSQ)d)+pOi8e2;ub?^e z7|TaYr4*L(6L=j3pwn#Qpq1l-Ag9J19aR6eJl1Z&8dp^RZ;0!!hauD-WJUf|bLIn_ z{#MQ~_Q8k_s1*6IIdg*3Ukhf#+2t2DXHM`uRr)JYVarpmL%Td^t2xh`Pc>(*s+@b; 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See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include -#include -#include "anain.h" -#include "my_math.h" - -#define ADC_DMA_CHAN 1 -#define MEDIAN3_FROM_ADC_ARRAY(a) median3(*a, *(a + ANA_IN_COUNT), *(a + 2*ANA_IN_COUNT)) - -uint8_t AnaIn::channel_array[ANA_IN_COUNT]; -uint16_t AnaIn::values[NUM_SAMPLES*ANA_IN_COUNT]; - -#undef ANA_IN_ENTRY -#define ANA_IN_ENTRY(name, port, pin) AnaIn AnaIn::name(__COUNTER__); -ANA_IN_LIST -#undef ANA_IN_ENTRY - -/** -* Initialize ADC hardware and start DMA based conversion process -*/ -void AnaIn::Start() -{ - adc_power_off(ADC1); - adc_enable_scan_mode(ADC1); - adc_set_continuous_conversion_mode(ADC1); - adc_set_right_aligned(ADC1); - adc_set_sample_time_on_all_channels(ADC1, SAMPLE_TIME); - - adc_power_on(ADC1); - /* wait for adc starting up*/ - for (int i = 0; i < 80000; i++); - - adc_reset_calibration(ADC1); - adc_calibrate(ADC1); - - adc_set_regular_sequence(ADC1, ANA_IN_COUNT, channel_array); - adc_enable_dma(ADC1); - - dma_set_peripheral_address(DMA1, ADC_DMA_CHAN, (uint32_t)&ADC_DR(ADC1)); - dma_set_memory_address(DMA1, ADC_DMA_CHAN, (uint32_t)values); - dma_set_peripheral_size(DMA1, ADC_DMA_CHAN, DMA_CCR_PSIZE_16BIT); - dma_set_memory_size(DMA1, ADC_DMA_CHAN, DMA_CCR_MSIZE_16BIT); - dma_set_number_of_data(DMA1, ADC_DMA_CHAN, NUM_SAMPLES * ANA_IN_COUNT); - dma_enable_memory_increment_mode(DMA1, ADC_DMA_CHAN); - dma_enable_circular_mode(DMA1, ADC_DMA_CHAN); - dma_enable_channel(DMA1, ADC_DMA_CHAN); - - //adc_start_conversion_regular(ADC1); - //ADC_CR2(ADC1) |= ADC_CR2_JSWSTART; - adc_start_conversion_direct(ADC1); -} - -void AnaIn::Configure(uint32_t port, uint8_t pin) -{ - gpio_set_mode(port, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, 1 << pin); - channel_array[GetIndex()] = AdcChFromPort(port, pin); -} - -/** -* Get filtered value of given channel -* -* - NUM_SAMPLES = 1: Most recent sample is returned -* - NUM_SAMPLES = 3: Median of last 3 samples is returned -* - NUM_SAMPLES = 9: Median of last 3 medians is returned -* - NUM_SAMPLES = 12: Average of last 4 medians is returned -* - NUM_SAMPLES = 64: Average of last 64 samples is returned -* -* @return Filtered value -*/ -uint16_t AnaIn::Get() -{ - #if NUM_SAMPLES == 1 - return *firstValue; - #elif NUM_SAMPLES == 3 - return MEDIAN3_FROM_ADC_ARRAY(firstValue); - #elif NUM_SAMPLES == 9 - uint16_t *curVal = firstValue; - uint16_t med[3]; - - for (int i = 0; i < 3; i++, curVal += 3*ANA_IN_COUNT) - { - med[i] = MEDIAN3_FROM_ADC_ARRAY(curVal); - } - - return MEDIAN3(med[0], med[1], med[2]); - #elif NUM_SAMPLES == 12 - uint16_t *curVal = firstValue; - uint16_t med[4]; - - for (int i = 0; i < 4; i++, curVal += 3*ANA_IN_COUNT) - { - med[i] = MEDIAN3_FROM_ADC_ARRAY(curVal); - } - - return (med[0] + med[1] + med[2] + med[3]) >> 2; - #elif NUM_SAMPLES == 64 - uint16_t *curVal = firstValue; - uint32_t sum = 0; - - for (int i = 0; i < NUM_SAMPLES; i++, curVal += ANA_IN_COUNT) - { - sum += *curVal; - } - - return sum >> 6; - #else - #error NUM_SAMPLES must be 1, 3, 9, 12 or 64 - #endif -} - -int AnaIn::median3(int a, int b, int c) -{ - return MEDIAN3(a,b,c); -} - -uint8_t AnaIn::AdcChFromPort(uint32_t command_port, int command_bit) -{ - /* - PA0 ADC12_IN0 - PA1 ADC12_IN1 - PA2 ADC12_IN2 - PA3 ADC12_IN3 - PA4 ADC12_IN4 - PA5 ADC12_IN5 - PA6 ADC12_IN6 - PA7 ADC12_IN7 - PB0 ADC12_IN8 - PB1 ADC12_IN9 - PC0 ADC12_IN10 - PC1 ADC12_IN11 - PC2 ADC12_IN12 - PC3 ADC12_IN13 - PC4 ADC12_IN14 - PC5 ADC12_IN15 - temp ADC12_IN16 - */ - switch (command_port) - { - case GPIOA: /* port A */ - if (command_bit<8) return command_bit; - break; - case GPIOB: /* port B */ - if (command_bit<2) return command_bit+8; - break; - case GPIOC: /* port C */ - if (command_bit<6) return command_bit+10; - break; - } - adc_enable_temperature_sensor(); - return 16; -} diff --git a/libopeninv/src/crc8.cpp b/libopeninv/src/crc8.cpp deleted file mode 100644 index aaf9ee0..0000000 --- a/libopeninv/src/crc8.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the stm32-sine project. - * - * Copyright (C) 2021 David J. Fiddes - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * Generated table driven CRC-8-CCITT code from: - * https://stackoverflow.com/a/27843120/6353 - */ - -#include "crc8.h" -#include - -/* - * Just change this define to whatever polynomial is in use - * A polynomial of 0x07 corresponds to x^8 + x^2 + x + 1 - */ -#define CRC1B(b) ((uint8_t)((b) << 1) ^ ((b)&0x80 ? 0x07 : 0)) // MS first - -/* - * 8+1 entry enum lookup table define - */ -#define CRC(b) CRC_##b // or CRC8B(b) - -enum -{ - CRC(0x01) = CRC1B(0x80), - CRC(0x02) = CRC1B(CRC(0x01)), - CRC(0x04) = CRC1B(CRC(0x02)), - CRC(0x08) = CRC1B(CRC(0x04)), - CRC(0x10) = CRC1B(CRC(0x08)), - CRC(0x20) = CRC1B(CRC(0x10)), - CRC(0x40) = CRC1B(CRC(0x20)), - CRC(0x80) = CRC1B(CRC(0x40)), - // Add 0x03 to optimise in CRCTAB1 - CRC(0x03) = CRC(0x02) ^ CRC(0x01) -}; - -/* - * Build a 256 byte CRC constant lookup table, built from from a reduced - * constant lookup table, namely CRC of each bit, 0x00 to 0x80. These will be - * defined as enumerations to take it easy on the compiler. This depends on the - * relation: CRC(a^b) = CRC(a)^CRC(b) In other words, we can build up each byte - * CRC as the xor of the CRC of each bit. So CRC(0x05) = CRC(0x04)^CRC(0x01). We - * include the CRC of 0x03 for a little more optimisation, since CRCTAB1 can use - * it instead of CRC(0x01)^CRC(0x02), again a little easier on the compiler. - */ - -#define CRCTAB1(ex) CRC(0x01) ex, CRC(0x02) ex, CRC(0x03) ex, -#define CRCTAB2(ex) CRCTAB1(ex) CRC(0x04) ex, CRCTAB1(^CRC(0x04) ex) -#define CRCTAB3(ex) CRCTAB2(ex) CRC(0x08) ex, CRCTAB2(^CRC(0x08) ex) -#define CRCTAB4(ex) CRCTAB3(ex) CRC(0x10) ex, CRCTAB3(^CRC(0x10) ex) -#define CRCTAB5(ex) CRCTAB4(ex) CRC(0x20) ex, CRCTAB4(^CRC(0x20) ex) -#define CRCTAB6(ex) CRCTAB5(ex) CRC(0x40) ex, CRCTAB5(^CRC(0x40) ex) - -/* - * This is the final lookup table. It is rough on the compiler, but generates - * the required lookup table automagically at compile time. - */ -const uint8_t crc_table[256] = { 0, CRCTAB6() CRC(0x80), CRCTAB6(^CRC(0x80)) }; diff --git a/libopeninv/src/digio.cpp b/libopeninv/src/digio.cpp deleted file mode 100644 index 87ca264..0000000 --- a/libopeninv/src/digio.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2010 Johannes Huebner - * Copyright (C) 2010 Edward Cheeseman - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "digio.h" - -#define DIG_IO_OFF 0 -#define DIG_IO_ON 1 - -#undef DIG_IO_ENTRY -#define DIG_IO_ENTRY(name, port, pin, mode) DigIo DigIo::name; -DIG_IO_LIST - -void DigIo::Configure(uint32_t port, uint16_t pin, PinMode::PinMode pinMode) -{ - uint8_t mode = GPIO_MODE_INPUT; - uint8_t cnf = GPIO_CNF_INPUT_PULL_UPDOWN; - uint16_t val = DIG_IO_OFF; - - _port = port; - _pin = pin; - - switch (pinMode) - { - default: - case PinMode::INPUT_PD: - /* use defaults */ - break; - case PinMode::INPUT_PU: - val = DIG_IO_ON; - break; - case PinMode::INPUT_FLT: - cnf = GPIO_CNF_INPUT_FLOAT; - break; - case PinMode::INPUT_AIN: - cnf = GPIO_CNF_INPUT_ANALOG; - break; - case PinMode::OUTPUT: - mode = GPIO_MODE_OUTPUT_50_MHZ; - cnf = GPIO_CNF_OUTPUT_PUSHPULL; - break; - case PinMode::OUTPUT_OD: - mode = GPIO_MODE_OUTPUT_50_MHZ; - cnf = GPIO_CNF_OUTPUT_OPENDRAIN; - val = DIG_IO_ON; - break; - } - - if (DIG_IO_ON == val) - { - gpio_set(port, pin); - } - gpio_set_mode(port, mode, cnf, pin); -} - diff --git a/libopeninv/src/errormessage.cpp b/libopeninv/src/errormessage.cpp deleted file mode 100644 index 313fd72..0000000 --- a/libopeninv/src/errormessage.cpp +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "errormessage.h" -#include "printf.h" -#include "my_string.h" - -struct ErrorDescriptor -{ - const char* msg; - ERROR_TYPE type; -}; - -struct BufferEntry -{ - ERROR_MESSAGE_NUM msg; - uint32_t time; -}; - -#define ERROR_MESSAGE_ENTRY(id, type) { #id, type }, -static const struct ErrorDescriptor errorDescriptors[] = -{ - { "", ERROR_LAST }, - ERROR_MESSAGE_LIST -}; -#undef ERROR_MESSAGE_ENTRY - -#define EXPANDED_LIST ERROR_MESSAGE_ENTRY(NONE, ERROR_DISPLAY) ERROR_MESSAGE_LIST -#define ERROR_MESSAGE_ENTRY(id, type) __COUNTER__=id, -const char* errorListString = STRINGIFY(EXPANDED_LIST); -#undef ERROR_MESSAGE_ENTRY - -static const char* types[ERROR_LAST] = -{ - "STOP", - "DERATE", - "WARN" -}; - -struct BufferEntry errorBuffer[ERROR_BUF_SIZE] = { { ERROR_MESSAGE_LAST, 0 } }; - -uint32_t ErrorMessage::timeTick = 0; -uint32_t ErrorMessage::currentBufIdx = 0; -uint32_t ErrorMessage::lastPrintIdx = 0; -ERROR_MESSAGE_NUM ErrorMessage::lastError = ERROR_NONE; -bool ErrorMessage::posted[ERROR_MESSAGE_LAST] = { false }; - -/** Set timestamp for error message -* @param time Current timestamp, will be displayed as is in message */ -void ErrorMessage::SetTime(uint32_t time) -{ - timeTick = time; -} - -/** Post an error message. - Every message can only be posted once, then UnpostAll() must be called to post it again - @post Message is displayed and written to error memory - @param msg message number */ -void ErrorMessage::Post(ERROR_MESSAGE_NUM msg) -{ - if (!posted[msg] && timeTick > 0) - { - lastError = msg; - errorBuffer[currentBufIdx].msg = msg; - errorBuffer[currentBufIdx].time = timeTick; - posted[msg] = true; - currentBufIdx = (currentBufIdx + 1) % ERROR_BUF_SIZE; - } -} - -/** Unpost all error message, i.e. make them postable again. - Does not reset the error buffer */ -void ErrorMessage::UnpostAll() -{ - for (uint32_t i = 0; i < ERROR_MESSAGE_LAST; i++) - posted[i] = false; -} - -/** Print errors that have been posted since last print */ -void ErrorMessage::PrintNewErrors() -{ - while (lastPrintIdx != currentBufIdx) - { - PrintError(errorBuffer[lastPrintIdx].time, errorBuffer[lastPrintIdx].msg); - lastPrintIdx = (lastPrintIdx + 1) % ERROR_BUF_SIZE; - } -} - -ERROR_MESSAGE_NUM ErrorMessage::GetLastError() -{ - return lastError; -} - -/** Print all errors currently in error memory */ -void ErrorMessage::PrintAllErrors() -{ - if (errorBuffer[0].time == 0) - { - printf("No Errors\r\n"); - return; - } - - for (uint32_t i = 0; i < ERROR_BUF_SIZE && errorBuffer[i].time > 0; i++) - PrintError(errorBuffer[i].time, errorBuffer[i].msg); -} - -void ErrorMessage::PrintError(uint32_t time, ERROR_MESSAGE_NUM msg) -{ - printf("[%u]: %s - %s\r\n", time, types[errorDescriptors[msg].type], errorDescriptors[msg].msg); -} diff --git a/libopeninv/src/foc.cpp b/libopeninv/src/foc.cpp deleted file mode 100644 index 46a8eaf..0000000 --- a/libopeninv/src/foc.cpp +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#define CST_DIGITS 15 -#include "my_fp.h" -#include "my_math.h" -#include "foc.h" -#include "sine_core.h" - -#define SQRT3 FP_FROMFLT(1.732050807568877293527446315059) -#define R1 FP_FROMFLT(0.03) -#define S1 FP_FROMFLT(0.15) -#define R2 FP_FROMFLT(0.5) -#define S2 FP_FROMFLT(0.5) -#define S3 FP_FROMFLT(1) -#define RADSTART(x) x < R1 ? S1 : (x < R2 ? S2 : S3) - -static const s32fp fluxLinkage = FP_FROMFLT(0.09); -static const s32fp fluxLinkage2 = FP_MUL(fluxLinkage, fluxLinkage); -static const s32fp lqminusldSquaredBs10 = FP_FROMFLT(0.01722); //additional 10-bit left shift because otherwise it can't be represented -static const s32fp lqminusld = FP_FROMFLT(0.0058); -static const u32fp sqrt3 = SQRT3; -static const s32fp sqrt3inv1 = FP_FROMFLT(0.57735026919); //1/sqrt(3) -static const s32fp zeroOffset = FP_FROMINT(1); -static const int32_t modMax = FP_DIV(FP_FROMINT(2U), sqrt3); -static const int32_t modMaxPow2 = modMax * modMax; -static const int32_t minPulse = 1000; -static const int32_t maxPulse = FP_FROMINT(2) - 1000; - -s32fp FOC::id; -s32fp FOC::iq; -s32fp FOC::DutyCycles[3]; -s32fp FOC::sin; -s32fp FOC::cos; - -/** @brief Set angle for Park und inverse Park transformation - * @param angle uint16_t rotor angle - */ -void FOC::SetAngle(uint16_t angle) -{ - sin = SineCore::Sine(angle); - cos = SineCore::Cosine(angle); -} - -/** @brief Transform current to rotor system using Clarke and Park transformation - * @pre Call SetAngle to specify angle for Park transformation - * @post flux producing (id) and torque producing (iq) current are written - * to FOC::id and FOC::iq - */ -void FOC::ParkClarke(s32fp il1, s32fp il2) -{ - //Clarke transformation - s32fp ia = il1; - s32fp ib = FP_MUL(sqrt3inv1, il1 + 2 * il2); - //Park transformation - id = FP_MUL(cos, ia) + FP_MUL(sin, ib); - iq = FP_MUL(cos, ib) - FP_MUL(sin, ia); -} - -/** \brief distribute motor current in magnetic torque and reluctance torque with the least total current - * - * \param[in] is int32_t total motor current - * \param[out] idref int32_t& resulting direct current reference - * \param[out] iqref int32_t& resulting quadrature current reference - * - */ -void FOC::Mtpa(int32_t is, int32_t& idref, int32_t& iqref) -{ - int32_t isSquared = is * is; - int32_t sign = is < 0 ? -1 : 1; - s32fp term1 = fpsqrt(fluxLinkage2 + ((lqminusldSquaredBs10 * isSquared) >> 10)); - idref = FP_TOINT(FP_DIV(fluxLinkage - term1, lqminusld)); - iqref = sign * (int32_t)sqrt(isSquared - idref * idref); -} - -int32_t FOC::GetQLimit(int32_t ud) -{ - return sqrt(modMaxPow2 - ud * ud); -} - -/** \brief Returns the resulting modulation index from uq and ud - * - * \param ud d voltage modulation index - * \param uq q voltage modulation index - * \return sqrt(ud²+uq²) - * - */ -int32_t FOC::GetTotalVoltage(int32_t ud, int32_t uq) -{ - return sqrt((uint32_t)(ud * ud) + (uint32_t)(uq * uq)); -} - -/** \brief Calculate duty cycles for generating ud and uq at given angle - * - * @pre Call SetAngle to specify angle for inverse Park transformation - * - * \param ud int32_t direct voltage - * \param uq int32_t quadrature voltage - * - */ -void FOC::InvParkClarke(int32_t ud, int32_t uq) -{ - //Inverse Park transformation - s32fp ua = (cos * ud - sin * uq) >> CST_DIGITS; - s32fp ub = (cos * uq + sin * ud) >> CST_DIGITS; - //Inverse Clarke transformation - DutyCycles[0] = ua; - DutyCycles[1] = (-ua + FP_MUL(SQRT3, ub)) / 2; - DutyCycles[2] = (-ua - FP_MUL(SQRT3, ub)) / 2; - - int32_t offset = SineCore::CalcSVPWMOffset(DutyCycles[0], DutyCycles[1], DutyCycles[2]); - - for (int i = 0; i < 3; i++) - { - /* subtract it from all 3 phases -> no difference in phase-to-phase voltage */ - DutyCycles[i] -= offset; - /* Shift above 0 */ - DutyCycles[i] += zeroOffset; - /* Short pulse suppression */ - if (DutyCycles[i] < minPulse) - { - DutyCycles[i] = 0U; - } - else if (DutyCycles[i] > maxPulse) - { - DutyCycles[i] = FP_FROMINT(2); - } - } -} - -int32_t FOC::GetMaximumModulationIndex() -{ - return modMax; -} - -uint32_t FOC::sqrt(uint32_t rad) -{ - uint32_t radshift = (rad < 10000 ? 5 : (rad < 10000000 ? 9 : (rad < 1000000000 ? 13 : 15))); - uint32_t sqrt = (rad >> radshift) + 1; //Starting value for newton iteration - uint32_t sqrtl; - - do { - sqrtl = sqrt; - sqrt = (sqrt + rad / sqrt) / 2; - } while ((sqrtl - sqrt) > 1); - - return sqrt; -} - -u32fp FOC::fpsqrt(u32fp rad) -{ - u32fp sqrt = RADSTART(rad); - u32fp sqrtl; - - do { - sqrtl = sqrt; - sqrt = (sqrt + FP_DIV(rad, sqrt)) >> 1; - } while ((sqrtl - sqrt) > 1); - - return sqrt; -} - diff --git a/libopeninv/src/fu.cpp b/libopeninv/src/fu.cpp deleted file mode 100644 index 162571a..0000000 --- a/libopeninv/src/fu.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2016 Nail Güzel - * Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "fu.h" - -uint32_t MotorVoltage::boost = 0; -u32fp MotorVoltage::fac; -uint32_t MotorVoltage::maxAmp; -u32fp MotorVoltage::endFrq = 1; //avoid division by 0 when not set - -/** Set 0 Hz boost to overcome winding resistance */ -void MotorVoltage::SetBoost(uint32_t boost /**< amplitude in digit */) -{ - MotorVoltage::boost = boost; - CalcFac(); -} - -/** Set frequency where the full amplitude is to be provided */ -void MotorVoltage::SetWeakeningFrq(float frq) -{ - endFrq = FP_FROMFLT(frq); - CalcFac(); -} - -/** Get amplitude for a given frequency */ -uint32_t MotorVoltage::GetAmp(u32fp frq) -{ - return MotorVoltage::GetAmpPerc(frq, FP_FROMINT(100)); -} - -/** Get amplitude for given frequency multiplied with given percentage */ -uint32_t MotorVoltage::GetAmpPerc(u32fp frq, u32fp perc) -{ - uint32_t amp = FP_MUL(perc, (FP_TOINT(FP_MUL(fac, frq)) + boost)) / 100; - if (frq < FP_FROMFLT(0.2)) - { - amp = 0; - } - if (amp > maxAmp) - { - amp = maxAmp; - } - - return amp; -} - -void MotorVoltage::SetMaxAmp(uint32_t maxAmp) -{ - MotorVoltage::maxAmp = maxAmp; - CalcFac(); -} - -/** Calculate slope of u/f */ -void MotorVoltage::CalcFac() -{ - fac = FP_DIV(FP_FROMINT(maxAmp - boost), endFrq); -} diff --git a/libopeninv/src/linbus.cpp b/libopeninv/src/linbus.cpp deleted file mode 100644 index adcd978..0000000 --- a/libopeninv/src/linbus.cpp +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the stm32-... project. - * - * Copyright (C) 2021 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include -#include -#include "linbus.h" - -#define HWINFO_ENTRIES (sizeof(hwInfo) / sizeof(struct HwInfo)) - -const LinBus::HwInfo LinBus::hwInfo[] = -{ - { USART1, DMA_CHANNEL4, DMA_CHANNEL5, GPIOA, GPIO_USART1_TX }, - { USART2, DMA_CHANNEL7, DMA_CHANNEL6, GPIOA, GPIO_USART2_TX }, - { USART3, DMA_CHANNEL2, DMA_CHANNEL3, GPIOB, GPIO_USART3_TX }, -}; - - -/** \brief Create a new LIN bus object and initialize USART, GPIO and DMA - * \pre According USART, GPIO and DMA clocks must be enabled - * \param usart USART base address - * \param baudrate 9600 or 19200 - * - */ -LinBus::LinBus(uint32_t usart, int baudrate) - : usart(usart) -{ - hw = hwInfo; - - for (uint32_t i = 0; i < HWINFO_ENTRIES; i++) - { - if (hw->usart == usart) break; - hw++; - } - - gpio_set_mode(hw->port, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, hw->pin); - - usart_set_baudrate(usart, baudrate); - usart_set_databits(usart, 8); - usart_set_stopbits(usart, USART_STOPBITS_1); - usart_set_mode(usart, USART_MODE_TX_RX); - usart_set_parity(usart, USART_PARITY_NONE); - usart_set_flow_control(usart, USART_FLOWCONTROL_NONE); - USART_CR2(usart) |= USART_CR2_LINEN; - usart_enable_tx_dma(usart); - usart_enable_rx_dma(usart); - - dma_channel_reset(DMA1, hw->dmatx); - dma_set_read_from_memory(DMA1, hw->dmatx); - dma_set_peripheral_address(DMA1, hw->dmatx, (uint32_t)&USART_DR(usart)); - dma_set_memory_address(DMA1, hw->dmatx, (uint32_t)sendBuffer); - dma_set_peripheral_size(DMA1, hw->dmatx, DMA_CCR_PSIZE_8BIT); - dma_set_memory_size(DMA1, hw->dmatx, DMA_CCR_MSIZE_8BIT); - dma_enable_memory_increment_mode(DMA1, hw->dmatx); - - dma_channel_reset(DMA1, hw->dmarx); - dma_set_peripheral_address(DMA1, hw->dmarx, (uint32_t)&USART_DR(usart)); - dma_set_peripheral_size(DMA1, hw->dmarx, DMA_CCR_PSIZE_8BIT); - dma_set_memory_size(DMA1, hw->dmarx, DMA_CCR_MSIZE_8BIT); - dma_enable_memory_increment_mode(DMA1, hw->dmarx); - - usart_enable(usart); -} - -/** \brief Send data on LIN bus - * - * \param id feature ID - * \param data payload data, if any - * \param len length of payload, if any - * - */ -void LinBus::Request(uint8_t id, uint8_t* data, uint8_t len) -{ - int sendLen = len == 0 ? 2 : len + 3; - - if (len > 8) return; - - dma_disable_channel(DMA1, hw->dmatx); - dma_set_number_of_data(DMA1, hw->dmatx, sendLen); - dma_disable_channel(DMA1, hw->dmarx); - dma_set_memory_address(DMA1, hw->dmarx, (uint32_t)recvBuffer); - dma_set_number_of_data(DMA1, hw->dmarx, sizeof(recvBuffer)); - - sendBuffer[0] = 0x55; //Sync - sendBuffer[1] = Parity(id); - - for (uint8_t i = 0; i < len; i++) - sendBuffer[i + 2] = data[i]; - - sendBuffer[len + 2] = Checksum(sendBuffer[1], data, len); - - dma_clear_interrupt_flags(DMA1, hw->dmatx, DMA_TCIF); - - USART_CR1(usart) |= USART_CR1_SBK; - dma_enable_channel(DMA1, hw->dmatx); - dma_enable_channel(DMA1, hw->dmarx); -} - -/** \brief Check whether we received valid data with given PID and length - * - * \param pid Feature ID to check for - * \param requiredLen Length of data we expect - * \return true if data with given properties was received - * - */ -bool LinBus::HasReceived(uint8_t id, uint8_t requiredLen) -{ - int numRcvd = dma_get_number_of_data(DMA1, hw->dmarx); - int receiveIdx = sizeof(recvBuffer) - numRcvd; - - if (requiredLen > 8) return false; - - uint8_t pid = Parity(id); - - if (receiveIdx == (requiredLen + payloadIndex + 1) && recvBuffer[pidIndex] == pid) - { - uint8_t checksum = Checksum(recvBuffer[pidIndex], &recvBuffer[payloadIndex], requiredLen); - - return checksum == recvBuffer[requiredLen + payloadIndex]; - } - - return false; -} - -/** \brief Calculate LIN checksum - * - * \param pid ID with parity - * \param data uint8_t* - * \param len int - * \return checksum - * - */ -uint8_t LinBus::Checksum(uint8_t pid, uint8_t* data, int len) -{ - uint8_t checksum = pid; - - for (int i = 0; i < len; i++) - { - uint16_t tmp = (uint16_t)checksum + (uint16_t)data[i]; - if (tmp > 256) tmp -= 255; - checksum = tmp; - } - return checksum ^ 0xff; -} - -uint8_t LinBus::Parity(uint8_t id) -{ - bool p1 = !(((id & 0x2) > 0) ^ ((id & 0x8) > 0) ^ ((id & 0x10) > 0) ^ ((id & 0x20) > 0)); - bool p0 = ((id & 0x1) > 0) ^ ((id & 0x2) > 0) ^ ((id & 0x4) > 0) ^ ((id & 0x10) > 0); - - return id | p1 << 7 | p0 << 6; -} diff --git a/libopeninv/src/my_fp.c b/libopeninv/src/my_fp.c deleted file mode 100644 index 5a6ba0d..0000000 --- a/libopeninv/src/my_fp.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "my_string.h" -#include "my_fp.h" - -#define FRAC_MASK ((1 << FRAC_DIGITS) - 1) - -static s32fp log2_approx(s32fp x, int loopLimit); - -char* fp_itoa(char * buf, s32fp a) -{ - int sign = a < 0?-1:1; - int32_t nat = (sign * a) >> FRAC_DIGITS; - uint32_t frac = ((UTOA_FRACDEC * ((sign * a) & FRAC_MASK))) >> FRAC_DIGITS; - char *p = buf; - if (sign < 0) - { - *p = '-'; - p++; - } - p += my_ltoa(p, nat, 10); - *p = '.'; - p++; - for (uint32_t dec = UTOA_FRACDEC / 10; dec > 1; dec /= 10) - { - if ((frac / dec) == 0) - { - *p = '0'; - p++; - } - } - my_ltoa(p, frac, 10); - return buf; -} - -s32fp fp_atoi(const char *str, int fracDigits) -{ - int nat = 0; - int frac = 0; - int div = 10; - int sign = 1; - if ('-' == *str) - { - sign = -1; - str++; - } - for (; *str >= '0' && *str <= '9'; str++) - { - nat *= 10; - nat += *str - '0'; - } - if (*str != 0) - { - for (str++; *str >= '0' && *str <= '9'; str++) - { - frac += (div / 2 + ((*str - '0') << fracDigits)) / div; - div *= 10; - } - } - - return sign * ((nat << fracDigits) + frac); -} - -u32fp fp_sqrt(u32fp rad) -{ - u32fp sqrt = rad >> (rad<1000?4:8); //Starting value for newton iteration - u32fp sqrtl; - sqrt = sqrt>FP_FROMINT(1)?sqrt:FP_FROMINT(1); //Must be > 0 - - do { - sqrtl = sqrt; - sqrt = (sqrt + FP_DIV(rad, sqrt)) >> 1; - } while ((sqrtl - sqrt) > 1); - - return sqrt; -} - -s32fp fp_ln(unsigned int x) -{ - int n = 0; - const s32fp ln2 = FP_FROMFLT(0.6931471806); - - if (x == 0) - { - return -1; - } - else - { //count leading zeros - uint32_t mask = 0xFFFFFFFF; - for (int i = 16; i > 0; i /= 2) - { - mask <<= i; - if ((x & mask) == 0) - { - n += i; - x <<= i; - } - } - } - - s32fp ln = FP_FROMINT(31 - n); - x >>= 32 - FRAC_DIGITS - 1; //will result in fixed point number in [1,2) - ln += log2_approx(x, 5); - ln = FP_MUL(ln2, ln); - return ln; -} - -static s32fp log2_approx(s32fp x, int loopLimit) -{ - int m = 0; - s32fp result = 0; - - if (loopLimit == 0) return FP_FROMINT(1); - if (x == FP_FROMINT(1)) return 0; - - while (x < FP_FROMINT(2)) - { - x = FP_MUL(x, x); - m++; - } - s32fp p = FRAC_FAC >> m; - result = FP_MUL(p, FP_FROMINT(1) + log2_approx(x / 2, loopLimit - 1)); - - return result; -} diff --git a/libopeninv/src/my_string.c b/libopeninv/src/my_string.c deleted file mode 100644 index 465b741..0000000 --- a/libopeninv/src/my_string.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the slibopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - #include "my_string.h" - -int my_strcmp(const char *str1, const char *str2) -{ - int res = 0; - for (; *str1 > 0 && *str2 > 0; str1++, str2++) - { - if (*str1 != *str2) - { - break; - } - } - if (*str1 != *str2) - { - res = 1; - } - return res; -} - -void my_strcat(char *str1, const char *str2) -{ - for (; *str1 > 0; str1++); - my_strcpy(str1, str2); -} - -void my_strcpy(char *str1, const char *str2) -{ - for (; *str2 > 0; str1++, str2++) - *str1 = *str2; - *str1 = 0; -} - -int my_strlen(const char *str) -{ - int len = 0; - for (; *str > 0; str++, len++); - return len; -} - -const char *my_strchr(const char *str, const char c) -{ - for (; *str > 0 && *str != c; str++); - return str; -} - -int my_ltoa(char *buf, int val, int base) -{ - char *start = buf; - char temp; - int len = 0; - - if (val < 0) - { - *buf = '-'; - buf++; - start++; - len++; - val = -val; - } - else if (0 == val) - { - *buf = '0'; - *(buf + 1) = 0; - return 1; - } - - for (; val > 0; val /= base, buf++, len++) - { - *buf = (val % base) + '0'; - } - *buf = 0; - buf--; - for (; buf > start; buf--, start++) - { - temp = *start; - *start = *buf; - *buf = temp; - } - return len; -} - -int my_atoi(const char *str) -{ - int Res = 0; - int sign = 1; - if ('-' == *str) - { - sign = -1; - str++; - } - for (; *str >= '0' && *str <= '9'; str++) - { - Res *= 10; - Res += *str - '0'; - } - - return sign * Res; -} - -char *my_trim(char *str) -{ - char *end; - - // Trim leading space - while (' ' == *str || '\n' == *str || '\r' == *str) str++; - - if(0 == *str) // All spaces? - return str; - - // Trim trailing space - end = str + my_strlen(str) - 1; - while(end > str && (' ' == *end || '\n' == *end || '\r' == *end)) end--; - - // Write new null terminator - *(end+1) = 0; - - return str; -} - -void memcpy32(int* target, int *source, int length) -{ - while (length--) - *target++ = *source++; -} - -void memset32(int* target, int value, int length) -{ - while (length--) - *target++ = value; -} diff --git a/libopeninv/src/param_save.cpp b/libopeninv/src/param_save.cpp deleted file mode 100644 index f2b6844..0000000 --- a/libopeninv/src/param_save.cpp +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include "params.h" -#include "param_save.h" -#include "hwdefs.h" -#include "my_string.h" - -#define NUM_PARAMS ((PARAM_BLKSIZE - 8) / sizeof(PARAM_ENTRY)) -#define PARAM_WORDS (PARAM_BLKSIZE / 4) - -typedef struct -{ - uint16_t key; - uint8_t dummy; - uint8_t flags; - uint32_t value; -} PARAM_ENTRY; - -typedef struct -{ - PARAM_ENTRY data[NUM_PARAMS]; - uint32_t crc; - uint32_t padding; -} PARAM_PAGE; - -static uint32_t GetFlashAddress() -{ - uint32_t flashSize = desig_get_flash_size(); - - //Always save parameters to last flash page - return FLASH_BASE + flashSize * 1024 - PARAM_BLKNUM * PARAM_BLKSIZE; -} - -/** -* Save parameters to flash -* -* @return CRC of parameter flash page -*/ -uint32_t parm_save() -{ - PARAM_PAGE parmPage; - uint32_t idx; - uint32_t paramAddress = GetFlashAddress(); - uint32_t check = 0xFFFFFFFF; - uint32_t* baseAddress = (uint32_t*)paramAddress; - - for (int i = 0; i < PARAM_WORDS; i++, baseAddress++) - check &= *baseAddress; - - crc_reset(); - memset32((int*)&parmPage, 0xFFFFFFFF, PARAM_WORDS); - - //Copy parameter values and keys to block structure - for (idx = 0; Param::IsParam((Param::PARAM_NUM)idx) && idx < NUM_PARAMS; idx++) - { - const Param::Attributes *pAtr = Param::GetAttrib((Param::PARAM_NUM)idx); - parmPage.data[idx].flags = (uint8_t)Param::GetFlag((Param::PARAM_NUM)idx); - parmPage.data[idx].key = pAtr->id; - parmPage.data[idx].value = Param::Get((Param::PARAM_NUM)idx); - } - - parmPage.crc = crc_calculate_block(((uint32_t*)&parmPage), (2 * NUM_PARAMS)); - flash_unlock(); - - if (check != 0xFFFFFFFF) - flash_erase_page(paramAddress); - - for (idx = 0; idx < PARAM_WORDS; idx++) - { - uint32_t* pData = ((uint32_t*)&parmPage) + idx; - flash_program_word(paramAddress + idx * sizeof(uint32_t), *pData); - } - flash_lock(); - return parmPage.crc; -} - -/** -* Load parameters from flash -* -* @retval 0 Parameters loaded successfully -* @retval -1 CRC error, parameters not loaded -*/ -int parm_load() -{ - uint32_t paramAddress = GetFlashAddress(); - PARAM_PAGE *parmPage = (PARAM_PAGE *)paramAddress; - - crc_reset(); - uint32_t crc = crc_calculate_block(((uint32_t*)parmPage), (2 * NUM_PARAMS)); - - if (crc == parmPage->crc) - { - for (unsigned int idxPage = 0; idxPage < NUM_PARAMS; idxPage++) - { - Param::PARAM_NUM idx = Param::NumFromId(parmPage->data[idxPage].key); - if (idx != Param::PARAM_INVALID && parmPage->data[idxPage].key > 0) - { - Param::SetFixed(idx, parmPage->data[idxPage].value); - Param::SetFlagsRaw(idx, parmPage->data[idxPage].flags); - } - } - return 0; - } - - return -1; -} diff --git a/libopeninv/src/params.cpp b/libopeninv/src/params.cpp deleted file mode 100644 index e35e2ed..0000000 --- a/libopeninv/src/params.cpp +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "params.h" -#include "my_string.h" - -namespace Param -{ - -#define PARAM_ENTRY(category, name, unit, min, max, def, id) { category, #name, unit, FP_FROMFLT(min), FP_FROMFLT(max), FP_FROMFLT(def), id }, -#define VALUE_ENTRY(name, unit, id) { 0, #name, unit, 0, 0, 0, id }, -static const Attributes attribs[] = -{ - PARAM_LIST -}; -#undef PARAM_ENTRY -#undef VALUE_ENTRY - -#define PARAM_ENTRY(category, name, unit, min, max, def, id) FP_FROMFLT(def), -#define VALUE_ENTRY(name, unit, id) 0, -static s32fp values[] = -{ - PARAM_LIST -}; -#undef PARAM_ENTRY -#undef VALUE_ENTRY - -#define PARAM_ENTRY(category, name, unit, min, max, def, id) 0, -#define VALUE_ENTRY(name, unit, id) 0, -static uint8_t flags[] = -{ - PARAM_LIST -}; -#undef PARAM_ENTRY -#undef VALUE_ENTRY - -/** -* Set a parameter -* -* @param[in] ParamNum Parameter index -* @param[in] ParamVal New value of parameter -* @return 0 if set ok, -1 if ParamVal outside of allowed range -*/ -int Set(PARAM_NUM ParamNum, s32fp ParamVal) -{ - char res = -1; - - if (ParamVal >= attribs[ParamNum].min && ParamVal <= attribs[ParamNum].max) - { - values[ParamNum] = ParamVal; - Change(ParamNum); - res = 0; - } - return res; -} - -/** -* Get a parameters fixed point value -* -* @param[in] ParamNum Parameter index -* @return Parameters value -*/ -s32fp Get(PARAM_NUM ParamNum) -{ - return values[ParamNum]; -} - -/** -* Get a parameters integer value -* -* @param[in] ParamNum Parameter index -* @return Parameters value -*/ -int GetInt(PARAM_NUM ParamNum) -{ - return FP_TOINT(values[ParamNum]); -} - -/** -* Get a parameters float value -* -* @param[in] ParamNum Parameter index -* @return Parameters value -*/ -float GetFloat(PARAM_NUM ParamNum) -{ - return FP_TOFLOAT(values[ParamNum]); -} - -/** -* Get a parameters boolean value, 1.00=True -* -* @param[in] ParamNum Parameter index -* @return Parameters value -*/ -bool GetBool(PARAM_NUM ParamNum) -{ - return FP_TOINT(values[ParamNum]) == 1; -} - -/** -* Set a parameters digit value -* -* @param[in] ParamNum Parameter index -* @param[in] ParamVal New value of parameter -*/ -void SetInt(PARAM_NUM ParamNum, int ParamVal) -{ - values[ParamNum] = FP_FROMINT(ParamVal); -} - -/** -* Set a parameters fixed point value without range check and callback -* -* @param[in] ParamNum Parameter index -* @param[in] ParamVal New value of parameter -*/ -void SetFixed(PARAM_NUM ParamNum, s32fp ParamVal) -{ - values[ParamNum] = ParamVal; -} - -/** -* Set a parameters floating point value without range check and callback -* -* @param[in] ParamNum Parameter index -* @param[in] ParamVal New value of parameter -*/ -void SetFloat(PARAM_NUM ParamNum, float ParamVal) -{ - values[ParamNum] = FP_FROMFLT(ParamVal); -} - -/** -* Get the paramater index from a parameter name -* -* @param[in] name Parameters name -* @return Parameter index if found, PARAM_INVALID otherwise -*/ -PARAM_NUM NumFromString(const char *name) -{ - PARAM_NUM paramNum = PARAM_INVALID; - const Attributes *pCurAtr = attribs; - - for (int i = 0; i < PARAM_LAST; i++, pCurAtr++) - { - if (0 == my_strcmp(pCurAtr->name, name)) - { - paramNum = (PARAM_NUM)i; - break; - } - } - return paramNum; -} - -/** -* Get the paramater index from a parameters unique id -* -* @param[in] id Parameters unique id -* @return Parameter index if found, PARAM_INVALID otherwise -*/ -PARAM_NUM NumFromId(uint32_t id) -{ - PARAM_NUM paramNum = PARAM_INVALID; - const Attributes *pCurAtr = attribs; - - for (int i = 0; i < PARAM_LAST; i++, pCurAtr++) - { - if (pCurAtr->id == id) - { - paramNum = (PARAM_NUM)i; - break; - } - } - return paramNum; -} - -/** -* Get the parameter attributes -* -* @param[in] ParamNum Parameter index -* @return Parameter attributes -*/ -const Attributes *GetAttrib(PARAM_NUM ParamNum) -{ - return &attribs[ParamNum]; -} - -/** Find out if ParamNum is a parameter or display value - * @retval 1 it is a parameter - * @retval 0 otherwise - */ -int IsParam(PARAM_NUM ParamNum) -{ - return attribs[ParamNum].min != attribs[ParamNum].max; -} - -/** Load default values for all parameters */ -void LoadDefaults() -{ - const Attributes *curAtr = attribs; - - for (int idx = 0; idx < PARAM_LAST; idx++, curAtr++) - { - if (curAtr->id > 0) - SetFixed((PARAM_NUM)idx, curAtr->def); - } -} - -void SetFlagsRaw(PARAM_NUM param, uint8_t rawFlags) -{ - flags[param] = rawFlags; -} - -void SetFlag(PARAM_NUM param, PARAM_FLAG flag) -{ - flags[param] |= (uint8_t)flag; -} - -void ClearFlag(PARAM_NUM param, PARAM_FLAG flag) -{ - flags[param] &= (uint8_t)~flag; -} - -PARAM_FLAG GetFlag(PARAM_NUM param) -{ - return (PARAM_FLAG)flags[param]; -} - -} diff --git a/libopeninv/src/picontroller.cpp b/libopeninv/src/picontroller.cpp deleted file mode 100644 index ba4802b..0000000 --- a/libopeninv/src/picontroller.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2018 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "picontroller.h" -#include "my_math.h" - -PiController::PiController() - : kp(0), ki(0), esum(0), refVal(0), frequency(1), maxY(0), minY(0) -{ -} - -int32_t PiController::Run(s32fp curVal) -{ - s32fp err = refVal - curVal; - s32fp esumTemp = esum + err; - - int32_t y = FP_TOINT(err * kp + (esumTemp / frequency) * ki); - int32_t ylim = MAX(y, minY); - ylim = MIN(ylim, maxY); - - if (ylim == y) - { - esum = esumTemp; //anti windup, only integrate when not saturated - } - - return ylim; -} - -int32_t PiController::RunProportionalOnly(s32fp curVal) -{ - s32fp err = refVal - curVal; - - int32_t y = FP_TOINT(err * kp); - int32_t ylim = MAX(y, minY); - ylim = MIN(ylim, maxY); - - return ylim; -} diff --git a/libopeninv/src/printf.cpp b/libopeninv/src/printf.cpp deleted file mode 100644 index 66050d3..0000000 --- a/libopeninv/src/printf.cpp +++ /dev/null @@ -1,239 +0,0 @@ -/* - Copyright 2001, 2002 Georges Menie (www.menie.org) - stdarg version contributed by Christian Ettinger - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU Lesser General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -/* - putchar is the only external dependency for this file, - if you have a working putchar, leave it commented out. - If not, uncomment the define below and - replace outbyte(c) by your own function call. - -#define putchar(c) outbyte(c) -*/ - -#include -#include "printf.h" -#include "my_fp.h" - -#define PAD_RIGHT 1 -#define PAD_ZERO 2 - -extern "C" void putchar(char c); - -class ExternPutChar: public IPutChar -{ -public: - void PutChar(char c) - { - putchar(c); - } -}; - -class StringPutChar: public IPutChar -{ -public: - StringPutChar(char *s) : s(s) {} - void PutChar(char c) { *(s++) = c; } - -private: - char *s; -}; - -static int prints(IPutChar* put, const char *string, int width, int pad) -{ - int pc = 0, padchar = ' '; - - if (width > 0) { - int len = 0; - const char *ptr; - for (ptr = string; *ptr; ++ptr) ++len; - if (len >= width) width = 0; - else width -= len; - if (pad & PAD_ZERO) padchar = '0'; - } - if (!(pad & PAD_RIGHT)) { - for ( ; width > 0; --width) { - put->PutChar(padchar); - ++pc; - } - } - for ( ; *string ; ++string) { - put->PutChar(*string); - ++pc; - } - for ( ; width > 0; --width) { - put->PutChar(padchar); - ++pc; - } - - return pc; -} - -/* the following should be enough for 32 bit int */ -#define PRINT_BUF_LEN 12 - -static int printi(IPutChar* put, int i, int b, int sg, int width, int pad, int letbase) -{ - char print_buf[PRINT_BUF_LEN]; - char *s; - int t, neg = 0, pc = 0; - unsigned int u = i; - - if (i == 0) { - print_buf[0] = '0'; - print_buf[1] = '\0'; - return prints (put, print_buf, width, pad); - } - - if (sg && b == 10 && i < 0) { - neg = 1; - u = -i; - } - - s = print_buf + PRINT_BUF_LEN-1; - *s = '\0'; - - while (u) { - t = u % b; - if( t >= 10 ) - t += letbase - '0' - 10; - *--s = t + '0'; - u /= b; - } - - if (neg) { - if( width && (pad & PAD_ZERO) ) { - put->PutChar('-'); - ++pc; - --width; - } - else { - *--s = '-'; - } - } - - return pc + prints (put, s, width, pad); -} - -static int printfp(IPutChar* put, int i, int width, int pad) -{ - char print_buf[PRINT_BUF_LEN]; - - fp_itoa(print_buf, i); - - return prints (put, print_buf, width, pad); -} - -static int print(IPutChar* put, const char *format, va_list args ) -{ - int width, pad; - int pc = 0; - char scr[2]; - - for (; *format != 0; ++format) { - if (*format == '%') { - ++format; - width = pad = 0; - if (*format == '\0') break; - if (*format == '%') goto out; - if (*format == '-') { - ++format; - pad = PAD_RIGHT; - } - while (*format == '0') { - ++format; - pad |= PAD_ZERO; - } - for ( ; *format >= '0' && *format <= '9'; ++format) { - width *= 10; - width += *format - '0'; - } - if( *format == 's' ) { - char *s = (char *)va_arg( args, int ); - pc += prints (put, s?s:"(null)", width, pad); - continue; - } - if( *format == 'd' ) { - pc += printi (put, va_arg( args, int ), 10, 1, width, pad, 'a'); - continue; - } - if( *format == 'x' ) { - pc += printi (put, va_arg( args, int ), 16, 0, width, pad, 'a'); - continue; - } - if( *format == 'X' ) { - pc += printi (put, va_arg( args, int ), 16, 0, width, pad, 'A'); - continue; - } - if( *format == 'u' ) { - pc += printi (put, va_arg( args, int ), 10, 0, width, pad, 'a'); - continue; - } - if ( *format == 'f' ) { - pc += printfp (put, va_arg( args, int ), width, pad); - continue; - } - if( *format == 'c' ) { - /* char are converted to int then pushed on the stack */ - scr[0] = (char)va_arg( args, int ); - scr[1] = '\0'; - pc += prints (put, scr, width, pad); - continue; - } - } - else { - out: - put->PutChar(*format); - ++pc; - } - } - va_end( args ); - return pc; -} - -int printf(const char *format, ...) -{ - ExternPutChar pc; - va_list args; - - va_start( args, format ); - return print( &pc, format, args ); -} - -int sprintf(char *out, const char *format, ...) -{ - StringPutChar pc(out); - va_list args; - - va_start( args, format ); - - int ret = print( &pc, format, args ); - - pc.PutChar(0); - - return ret; -} - -int fprintf(IPutChar* put, const char *format, ...) -{ - va_list args; - - va_start( args, format ); - - return print( put, format, args ); -} diff --git a/libopeninv/src/sine_core.cpp b/libopeninv/src/sine_core.cpp deleted file mode 100644 index 46a4cb4..0000000 --- a/libopeninv/src/sine_core.cpp +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2012 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - /** @addtogroup G_sine Sine wave generation - * @{ - */ -#include "sine_core.h" - -#define SINTAB_ARGDIGITS 11 -#define SINTAB_ENTRIES (1 << SINTAB_ARGDIGITS) -/* Value range of sine lookup table */ -#define SINTAB_MAX (1 << BITS) -#define BRAD_PI (1 << (BITS - 1)) - -#define PHASE_SHIFT90 ((uint32_t)( SINLU_ONEREV / 4)) -#define PHASE_SHIFT120 ((uint32_t)( SINLU_ONEREV / 3)) -#define PHASE_SHIFT240 ((uint32_t)(2 * (SINLU_ONEREV / 3))) - -const uint32_t SineCore::minPulse = 1000; -uint32_t SineCore::ampl = 0; -const int16_t SineCore::SinTab[] = { SINTAB };/* sine LUT */ -const uint16_t SineCore::ZERO_OFFSET = SINTAB_MAX / 2; -const int SineCore::BITS = 16; -const uint16_t SineCore::MAXAMP = 37813; -uint32_t SineCore::DutyCycles[3]; - -/** Calculate the next dutycyles. - * This function is meant to be called by your timer interrupt handler - */ -void SineCore::Calc(uint16_t angle) -{ - int32_t Ofs; - uint32_t Idx; - - int32_t sine[3]; - - /* 1. Calculate sine */ - sine[0] = SineLookup(angle); - sine[1] = SineLookup((angle + PHASE_SHIFT120) & 0xFFFF); - sine[2] = SineLookup((angle + PHASE_SHIFT240) & 0xFFFF); - - for (Idx = 0; Idx < 3; Idx++) - { - /* 2. Set desired amplitude */ - sine[Idx] = MultiplyAmplitude(ampl, sine[Idx]); - } - - /* 3. Calculate the offset of SVPWM */ - Ofs = CalcSVPWMOffset(sine[0], sine[1], sine[2]); - - for (Idx = 0; Idx < 3; Idx++) - { - /* 4. subtract it from all 3 phases -> no difference in phase-to-phase voltage */ - sine[Idx] -= Ofs; - /* Shift above 0 */ - DutyCycles[Idx] = sine[Idx] + ZERO_OFFSET; - /* Short pulse supression */ - if (DutyCycles[Idx] < minPulse) - { - DutyCycles[Idx] = 0U; - } - else if (DutyCycles[Idx] > (SINTAB_MAX - minPulse)) - { - DutyCycles[Idx] = SINTAB_MAX; - } - } -} - -s32fp SineCore::Sine(uint16_t angle) -{ - return SineLookup(angle); -} - -s32fp SineCore::Cosine(uint16_t angle) -{ - return SineLookup((PHASE_SHIFT90 + angle) & 0xFFFF); -} - -//Found here: http://www.coranac.com/documents/arctangent/ -uint16_t SineCore::Atan2(int32_t x, int32_t y) -{ - if(y==0) - return (x>=0 ? 0 : BRAD_PI); - - static const int fixShift = 15; - int phi = 0, t, t2, dphi; - - if (y < 0) - { - x = -x; - y = -y; - phi += 4; - } - if (x <= 0) - { - int temp = x; - x = y; - y = -temp; - phi += 2; - } - if (x <= y) - { - int temp = y - x; - x = x + y; - y = temp; - phi += 1; - } - - phi *= BRAD_PI/4; - - t= (y << fixShift) / x; - t2= -t*t>>fixShift; - - dphi= 0x0470; - dphi= 0x1029 + (t2*dphi>>fixShift); - dphi= 0x1F0B + (t2*dphi>>fixShift); - dphi= 0x364C + (t2*dphi>>fixShift); - dphi= 0xA2FC + (t2*dphi>>fixShift); - dphi= dphi*t>>fixShift; - - return phi + ((dphi+2)>>2); -} - -/** Set amplitude of the synthesized sine wave */ -void SineCore::SetAmp(uint32_t amp /**< amplitude in digit. Largest value is 37813 */) -{ - ampl = amp; -} - -uint32_t SineCore::GetAmp() -{ - return ampl; -} - -/* Performs a lookup in the sine table */ -/* 0 = 0, 2Pi = 65535 */ -int32_t SineCore::SineLookup(uint16_t Arg) -{ - /* No interpolation for now */ - /* We divide arg by 2^(SINTAB_ARGDIGITS) */ - /* No we can directly address the lookup table */ - Arg >>= SINLU_ARGDIGITS - SINTAB_ARGDIGITS; - return (int32_t)SinTab[Arg]; -} - -/* 0 = 0, 1 = 32767 */ -int32_t SineCore::MultiplyAmplitude(uint16_t Amplitude, int32_t Baseval) -{ - int32_t temp = (int32_t)((uint32_t)Amplitude * Baseval); - /* Divide by 32768 */ - /* -> Allow overmodulation, for SVPWM or FTPWM */ - temp >>= (BITS - 1); - return temp; -} - - -int32_t SineCore::CalcSVPWMOffset(int32_t a, int32_t b, int32_t c) -{ - int32_t Minimum = min(min(a, b), c); - int32_t Maximum = max(max(a, b), c); - int32_t Offset = Minimum + Maximum; - - return (Offset >> 1); -} - -int32_t SineCore::min(int32_t a, int32_t b) -{ - return (a <= b)?a:b; -} - -int32_t SineCore::max(int32_t a, int32_t b) -{ - return (a >= b)?a:b; -} - -/** @} */ diff --git a/libopeninv/src/stm32_can.cpp b/libopeninv/src/stm32_can.cpp deleted file mode 100644 index 023a1c6..0000000 --- a/libopeninv/src/stm32_can.cpp +++ /dev/null @@ -1,978 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2016 Nail Güzel - * Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include "hwdefs.h" -#include "my_string.h" -#include "my_math.h" -#include "printf.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "stm32_can.h" - -#define MAX_INTERFACES 2 -#define IDS_PER_BANK 4 -#define EXT_IDS_PER_BANK 2 -#define SDO_WRITE 0x40 -#define SDO_READ 0x22 -#define SDO_ABORT 0x80 -#define SDO_WRITE_REPLY 0x23 -#define SDO_READ_REPLY 0x43 -#define SDO_ERR_INVIDX 0x06020000 -#define SDO_ERR_RANGE 0x06090030 -#define SENDMAP_ADDRESS(b) b -#define RECVMAP_ADDRESS(b) (b + sizeof(canSendMap)) -#define POSMAP_ADDRESS(b) (b + sizeof(canSendMap) + sizeof(canRecvMap)) -#define CRC_ADDRESS(b) (b + sizeof(canSendMap) + sizeof(canRecvMap) + sizeof(canPosMap)) -#define SENDMAP_WORDS (sizeof(canSendMap) / (sizeof(uint32_t))) -#define RECVMAP_WORDS (sizeof(canRecvMap) / (sizeof(uint32_t))) -#define POSMAP_WORDS ((sizeof(CANPOS) * MAX_ITEMS) / (sizeof(uint32_t))) -#define ITEM_UNSET 0xff -#define forEachCanMap(c,m) for (CANIDMAP *c = m; (c - m) < MAX_MESSAGES && c->first != MAX_ITEMS; c++) -#define forEachPosMap(c,m) for (CANPOS *c = &canPosMap[m->first]; c->next != ITEM_UNSET; c = &canPosMap[c->next]) - -#ifdef CAN_EXT -#define IDMAPSIZE 8 -#else -#define IDMAPSIZE 4 -#endif // CAN_EXT -#if (MAX_ITEMS * 12 + 2 * MAX_MESSAGES * IDMAPSIZE + 4) > FLASH_PAGE_SIZE -#error CANMAP will not fit in one flash page -#endif - -struct CAN_SDO -{ - uint8_t cmd; - uint16_t index; - uint8_t subIndex; - uint32_t data; -} __attribute__((packed)); - -struct CANSPEED -{ - uint32_t ts1; - uint32_t ts2; - uint32_t prescaler; -}; - -Can* Can::interfaces[MAX_INTERFACES]; -volatile bool Can::isSaving = false; - -static void DummyCallback(uint32_t i, uint32_t* d) { i=i; d=d; } -static const CANSPEED canSpeed[Can::BaudLast] = -{ - { CAN_BTR_TS1_9TQ, CAN_BTR_TS2_6TQ, 18}, //125kbps - { CAN_BTR_TS1_9TQ, CAN_BTR_TS2_6TQ, 9 }, //250kbps - { CAN_BTR_TS1_4TQ, CAN_BTR_TS2_3TQ, 9 }, //500kbps - { CAN_BTR_TS1_5TQ, CAN_BTR_TS2_3TQ, 5 }, //800kbps - { CAN_BTR_TS1_6TQ, CAN_BTR_TS2_5TQ, 3 }, //1000kbps -}; - -/** \brief Add periodic CAN message - * - * \param param Parameter index of parameter to be sent - * \param canId CAN identifier of generated message - * \param offset bit offset within the 64 message bits - * \param length number of bits - * \param gain Fixed point gain to be multiplied before sending - * \return success: number of active messages - * Fault: - * - CAN_ERR_INVALID_ID ID was > 0x1fffffff - * - CAN_ERR_INVALID_OFS Offset > 63 - * - CAN_ERR_INVALID_LEN Length > 32 - * - CAN_ERR_MAXMESSAGES Already 10 send messages defined - * - CAN_ERR_MAXITEMS Already than MAX_ITEMS items total defined - */ -int Can::AddSend(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset) -{ - return Add(canSendMap, param, canId, offsetBits, length, gain, offset); -} - -int Can::AddSend(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain) -{ - return Add(canSendMap, param, canId, offsetBits, length, gain, 0); -} - -/** \brief Map data from CAN bus to parameter - * - * \param param Parameter index of parameter to be received - * \param canId CAN identifier of consumed message - * \param offset bit offset within the 64 message bits - * \param length number of bits - * \param gain Fixed point gain to be multiplied after receiving - * \return success: number of active messages - * Fault: - * - CAN_ERR_INVALID_ID ID was > 0x1fffffff - * - CAN_ERR_INVALID_OFS Offset > 63 - * - CAN_ERR_INVALID_LEN Length > 32 - * - CAN_ERR_MAXMESSAGES Already 10 receive messages defined - * - CAN_ERR_MAXITEMS Already than MAX_ITEMS items total defined - */ -int Can::AddRecv(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset) -{ - int res = Add(canRecvMap, param, canId, offsetBits, length, gain, offset); - ConfigureFilters(); - return res; -} - -int Can::AddRecv(Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain) -{ - return Can::AddRecv(param, canId, offsetBits, length, gain, 0); -} - -/** \brief Set function to be called for user handled CAN messages - * - * \param recv Function pointer to void func(uint32_t, uint32_t[2]) - ID, Data - */ -void Can::SetReceiveCallback(void (*recv)(uint32_t, uint32_t*)) -{ - recvCallback = recv; -} - -/** \brief Add CAN Id to user message list - * \post Receive callback will be called when a message with this Id id received - * \param canId CAN identifier of message to be user handled - * \return true: success, false: already 10 messages registered - * - */ -bool Can::RegisterUserMessage(uint32_t canId) -{ - if (nextUserMessageIndex < MAX_USER_MESSAGES) - { - userIds[nextUserMessageIndex] = canId; - nextUserMessageIndex++; - ConfigureFilters(); - return true; - } - return false; -} - -/** \brief Remove all CAN Id from user message list - */ -void Can::ClearUserMessages() -{ - nextUserMessageIndex = 0; - ConfigureFilters(); -} - -/** \brief Find first occurence of parameter in CAN map and output its mapping info - * - * Memory layout: SendMap, RecvMap, PosMap, CRC - * Send/Recv maps point to items in PosMap. PosMap may point to next item - * - * \param[in] param Index of parameter to be looked up - * \param[out] canId CAN identifier that the parameter is mapped to - * \param[out] offset bit offset that the parameter is mapped to - * \param[out] length number of bits that the parameter is mapped to - * \param[out] gain Parameter gain - * \param[out] rx true: Parameter is received via CAN, false: sent via CAN - * \return true: parameter is mapped, false: not mapped - */ -bool Can::FindMap(Param::PARAM_NUM param, uint32_t& canId, uint8_t& offset, uint8_t& length, float& gain, bool& rx) -{ - rx = false; - bool done = false; - - for (CANIDMAP *map = canSendMap; !done; map = canRecvMap) - { - forEachCanMap(curMap, map) - { - forEachPosMap(curPos, curMap) - { - if (curPos->mapParam == param) - { - canId = curMap->canId; - offset = curPos->offsetBits; - length = curPos->numBits; - gain = curPos->gain; - return true; - } - } - } - done = rx; - rx = true; - } - return false; -} - -/** \brief Save CAN mapping to flash - */ -void Can::Save() -{ - uint32_t crc; - uint32_t check = 0xFFFFFFFF; - uint32_t baseAddress = GetFlashAddress(); - uint32_t *checkAddress = (uint32_t*)baseAddress; - - isSaving = true; - - for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++, checkAddress++) - check &= *checkAddress; - - crc_reset(); - - flash_unlock(); - flash_set_ws(2); - - if (check != 0xFFFFFFFF) //Only erase when needed - flash_erase_page(baseAddress); - - ReplaceParamEnumByUid(canSendMap); - ReplaceParamEnumByUid(canRecvMap); - - SaveToFlash(SENDMAP_ADDRESS(baseAddress), (uint32_t *)canSendMap, SENDMAP_WORDS); - crc = SaveToFlash(RECVMAP_ADDRESS(baseAddress), (uint32_t *)canRecvMap, RECVMAP_WORDS); - crc = SaveToFlash(POSMAP_ADDRESS(baseAddress), (uint32_t *)canPosMap, POSMAP_WORDS); - SaveToFlash(CRC_ADDRESS(baseAddress), &crc, 1); - flash_lock(); - - ReplaceParamUidByEnum(canSendMap); - ReplaceParamUidByEnum(canRecvMap); - - isSaving = false; -} - -/** \brief Send all defined messages - */ -void Can::SendAll() -{ - forEachCanMap(curMap, canSendMap) - { - uint32_t data[2] = { 0 }; //Had an issue with uint64_t, otherwise would have used that - - forEachPosMap(curPos, curMap) - { - if (isSaving) return; //Only send mapped messages when not currently saving to flash - - float val = Param::GetFloat((Param::PARAM_NUM)curPos->mapParam); - - val *= curPos->gain; - val += curPos->offset; - int ival = val; - ival &= ((1 << curPos->numBits) - 1); - - if (curPos->offsetBits > 31) - { - data[1] |= ival << (curPos->offsetBits - 32); - } - else - { - data[0] |= ival << curPos->offsetBits; - } - } - - Send(curMap->canId, data); - } -} - -/** \brief Clear all defined messages - */ -void Can::Clear() -{ - ClearMap(canSendMap); - ClearMap(canRecvMap); - ConfigureFilters(); -} - -/** \brief Remove all occurences of given parameter from CAN map - * - * \param param Parameter index to be removed - * \return int number of removed items - * - */ -int Can::Remove(Param::PARAM_NUM param) -{ - int removed = RemoveFromMap(canSendMap, param); - removed += RemoveFromMap(canRecvMap, param); - - return removed; -} - -/** \brief Init can hardware with given baud rate - * Initializes the following sub systems: - * - CAN hardware itself - * - Appropriate GPIO pins - * - Enables appropriate interrupts in NVIC - * - * \param baseAddr base address of CAN peripheral, CAN1 or CAN2 - * \param baudrate enum baudrates - * \param remap use remapped IO pins - * \return void - * - */ -Can::Can(uint32_t baseAddr, enum baudrates baudrate, bool remap) - : lastRxTimestamp(0), sendCnt(0), recvCallback(DummyCallback), nextUserMessageIndex(0), canDev(baseAddr) -{ - Clear(); - LoadFromFlash(); - - switch (baseAddr) - { - case CAN1: - if (remap) - { - // Configure CAN pin: RX (input pull-up). - gpio_set_mode(GPIO_BANK_CAN1_PB_RX, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN1_PB_RX); - gpio_set(GPIO_BANK_CAN1_PB_RX, GPIO_CAN1_PB_RX); - // Configure CAN pin: TX.- - gpio_set_mode(GPIO_BANK_CAN1_PB_TX, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN1_PB_TX); - } - else - { - // Configure CAN pin: RX (input pull-up). - gpio_set_mode(GPIO_BANK_CAN1_RX, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN1_RX); - gpio_set(GPIO_BANK_CAN1_RX, GPIO_CAN1_RX); - // Configure CAN pin: TX.- - gpio_set_mode(GPIO_BANK_CAN1_TX, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN1_TX); - } - - //CAN1 RX and TX IRQs - nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ); //CAN RX - nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 0xf << 4); //lowest priority - nvic_enable_irq(NVIC_CAN_RX1_IRQ); //CAN RX - nvic_set_priority(NVIC_CAN_RX1_IRQ, 0xf << 4); //lowest priority - nvic_enable_irq(NVIC_USB_HP_CAN_TX_IRQ); //CAN TX - nvic_set_priority(NVIC_USB_HP_CAN_TX_IRQ, 0xf << 4); //lowest priority - interfaces[0] = this; - break; - case CAN2: - if (remap) - { - // Configure CAN pin: RX (input pull-up). - gpio_set_mode(GPIO_BANK_CAN2_RE_RX, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN2_RE_RX); - gpio_set(GPIO_BANK_CAN2_RE_RX, GPIO_CAN2_RE_RX); - // Configure CAN pin: TX.- - gpio_set_mode(GPIO_BANK_CAN2_RE_TX, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN2_RE_TX); - } - else - { - // Configure CAN pin: RX (input pull-up). - gpio_set_mode(GPIO_BANK_CAN2_RX, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN2_RX); - gpio_set(GPIO_BANK_CAN2_RX, GPIO_CAN2_RX); - // Configure CAN pin: TX.- - gpio_set_mode(GPIO_BANK_CAN2_TX, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN2_TX); - } - - //CAN2 RX and TX IRQs - nvic_enable_irq(NVIC_CAN2_RX0_IRQ); //CAN RX - nvic_set_priority(NVIC_CAN2_RX0_IRQ, 0xf << 4); //lowest priority - nvic_enable_irq(NVIC_CAN2_RX1_IRQ); //CAN RX - nvic_set_priority(NVIC_CAN2_RX1_IRQ, 0xf << 4); //lowest priority - nvic_enable_irq(NVIC_CAN2_TX_IRQ); //CAN RX - nvic_set_priority(NVIC_CAN2_TX_IRQ, 0xf << 4); //lowest priority - interfaces[1] = this; - break; - } - - nodeId = 1; - // Reset CAN - can_reset(canDev); - - SetBaudrate(baudrate); - ConfigureFilters(); - // Enable CAN RX interrupts. - can_enable_irq(canDev, CAN_IER_FMPIE0); - can_enable_irq(canDev, CAN_IER_FMPIE1); -} - -/** \brief Set baud rate to given value - * - * \param baudrate enum baudrates - * \return void - * - */ -void Can::SetBaudrate(enum baudrates baudrate) -{ - // CAN cell init. - // Setting the bitrate to 250KBit. APB1 = 36MHz, - // prescaler = 9 -> 4MHz time quanta frequency. - // 1tq sync + 9tq bit segment1 (TS1) + 6tq bit segment2 (TS2) = - // 16time quanto per bit period, therefor 4MHz/16 = 250kHz - // - can_init(canDev, - false, // TTCM: Time triggered comm mode? - true, // ABOM: Automatic bus-off management? - false, // AWUM: Automatic wakeup mode? - false, // NART: No automatic retransmission? - false, // RFLM: Receive FIFO locked mode? - false, // TXFP: Transmit FIFO priority? - CAN_BTR_SJW_1TQ, - canSpeed[baudrate].ts1, - canSpeed[baudrate].ts2, - canSpeed[baudrate].prescaler, // BRP+1: Baud rate prescaler - false, - false); -} - -/** \brief Get RTC time when last message was received - * - * \return uint32_t RTC time - * - */ -uint32_t Can::GetLastRxTimestamp() -{ - return lastRxTimestamp; -} - -/** \brief Send a user defined CAN message - * - * \param canId uint32_t - * \param data[2] uint32_t - * \param len message length - * \return void - * - */ -void Can::Send(uint32_t canId, uint32_t data[2], uint8_t len) -{ - can_disable_irq(canDev, CAN_IER_TMEIE); - - if (can_transmit(canDev, canId, canId > 0x7FF, false, len, (uint8_t*)data) < 0 && sendCnt < SENDBUFFER_LEN) - { - /* enqueue in send buffer if all TX mailboxes are full */ - sendBuffer[sendCnt].id = canId; - sendBuffer[sendCnt].len = len; - sendBuffer[sendCnt].data[0] = data[0]; - sendBuffer[sendCnt].data[1] = data[1]; - sendCnt++; - } - - if (sendCnt > 0) - { - can_enable_irq(canDev, CAN_IER_TMEIE); - } -} - -void Can::IterateCanMap(void (*callback)(Param::PARAM_NUM, uint32_t, uint8_t, uint8_t, float, bool)) -{ - bool done = false, rx = false; - - for (CANIDMAP *map = canSendMap; !done; map = canRecvMap) - { - forEachCanMap(curMap, map) - { - forEachPosMap(curPos, curMap) - { - callback((Param::PARAM_NUM)curPos->mapParam, curMap->canId, curPos->offsetBits, curPos->numBits, curPos->gain, rx); - } - } - done = rx; - rx = true; - } -} - -Can* Can::GetInterface(int index) -{ - if (index < MAX_INTERFACES) - { - return interfaces[index]; - } - return 0; -} - -void Can::HandleRx(int fifo) -{ - uint32_t id; - bool ext, rtr; - uint8_t length, fmi; - uint32_t data[2]; - - while (can_receive(canDev, fifo, true, &id, &ext, &rtr, &fmi, &length, (uint8_t*)data, NULL) > 0) - { - //printf("fifo: %d, id: %x, len: %d, data[0]: %x, data[1]: %x\r\n", fifo, id, length, data[0], data[1]); - if (id == (0x600U + nodeId) && length == 8) //SDO request - { - ProcessSDO(data); - } - else - { - if (isSaving) continue; //Only handle mapped messages when not currently saving to flash - - CANIDMAP *recvMap = FindById(canRecvMap, id); - - if (0 != recvMap) - { - forEachPosMap(curPos, recvMap) - { - float val; - - if (curPos->offsetBits > 31) - { - val = (data[1] >> (curPos->offsetBits - 32)) & ((1 << curPos->numBits) - 1); - } - else - { - val = (data[0] >> curPos->offsetBits) & ((1 << curPos->numBits) - 1); - } - val += curPos->offset; - val *= curPos->gain; - - if (Param::IsParam((Param::PARAM_NUM)curPos->mapParam)) - Param::Set((Param::PARAM_NUM)curPos->mapParam, FP_FROMFLT(val)); - else - Param::SetFloat((Param::PARAM_NUM)curPos->mapParam, val); - } - lastRxTimestamp = rtc_get_counter_val(); - } - else //Now it must be a user message, as filters block everything else - { - recvCallback(id, data); - } - } - } -} - -void Can::HandleTx() -{ - SENDBUFFER* b = sendBuffer; //alias - - while (sendCnt > 0 && can_transmit(canDev, b[sendCnt - 1].id, b[sendCnt - 1].id > 0x7FF, false, b[sendCnt - 1].len, (uint8_t*)b[sendCnt - 1].data) >= 0) - sendCnt--; - - if (sendCnt == 0) - { - can_disable_irq(canDev, CAN_IER_TMEIE); - } -} - -void Can::SDOWrite(uint8_t remoteNodeId, uint16_t index, uint8_t subIndex, uint32_t data) -{ - uint32_t d[2]; - CAN_SDO *sdo = (CAN_SDO*)d; - - sdo->cmd = SDO_WRITE; - sdo->index = index; - sdo->subIndex = subIndex; - sdo->data = data; - - Send(0x600 + remoteNodeId, d); -} - -/****************** Private methods and ISRs ********************/ - -//http://www.byteme.org.uk/canopenparent/canopen/sdo-service-data-objects-canopen/ -void Can::ProcessSDO(uint32_t data[2]) -{ - CAN_SDO *sdo = (CAN_SDO*)data; - if (sdo->index >= 0x2000 && sdo->index <= 0x2001 && sdo->subIndex < Param::PARAM_LAST) - { - Param::PARAM_NUM paramIdx = (Param::PARAM_NUM)sdo->subIndex; - - //SDO index 0x2001 will lookup the parameter by its unique ID - if (sdo->index == 0x2001) - paramIdx = Param::NumFromId(sdo->subIndex); - - if (sdo->cmd == SDO_WRITE) - { - if (Param::Set(paramIdx, sdo->data) == 0) - { - sdo->cmd = SDO_WRITE_REPLY; - } - else - { - sdo->cmd = SDO_ABORT; - sdo->data = SDO_ERR_RANGE; - } - } - else if (sdo->cmd == SDO_READ) - { - sdo->data = Param::Get(paramIdx); - sdo->cmd = SDO_READ_REPLY; - } - } - else if (sdo->index >= 0x3000 && sdo->index < 0x4800 && sdo->subIndex < Param::PARAM_LAST) - { - if (sdo->cmd == SDO_WRITE) - { - int result; - int offset = sdo->data & 0xFF; - int len = (sdo->data >> 8) & 0xFF; - s32fp gain = sdo->data >> 16; - - if ((sdo->index & 0x4000) == 0x4000) - { - result = Can::AddRecv((Param::PARAM_NUM)sdo->subIndex, sdo->index & 0x7FF, offset, len, gain); - } - else - { - result = Can::AddSend((Param::PARAM_NUM)sdo->subIndex, sdo->index & 0x7FF, offset, len, gain); - } - - if (result >= 0) - { - sdo->cmd = SDO_WRITE_REPLY; - } - else - { - sdo->cmd = SDO_ABORT; - sdo->data = SDO_ERR_RANGE; - } - } - } - else - { - sdo->cmd = SDO_ABORT; - sdo->data = SDO_ERR_INVIDX; - } - Can::Send(0x580 + nodeId, data); -} - -void Can::SetFilterBank(int& idIndex, int& filterId, uint16_t* idList) -{ - can_filter_id_list_16bit_init( - filterId, - idList[0] << 5, //left align - idList[1] << 5, - idList[2] << 5, - idList[3] << 5, - filterId & 1, - true); - idIndex = 0; - filterId++; - idList[0] = idList[1] = idList[2] = idList[3] = 0; -} - -void Can::SetFilterBank29(int& idIndex, int& filterId, uint32_t* idList) -{ - can_filter_id_list_32bit_init( - filterId, - (idList[0] << 3) | 0x4, //filter extended - (idList[1] << 3) | 0x4, - filterId & 1, - true); - idIndex = 0; - filterId++; - idList[0] = idList[1] = 0; -} - -void Can::ConfigureFilters() -{ - uint16_t idList[IDS_PER_BANK] = { 0, 0, 0, 0 }; - uint32_t extIdList[EXT_IDS_PER_BANK] = { 0, 0 }; - int idIndex = 1, extIdIndex = 0; - int filterId = canDev == CAN1 ? 0 : ((CAN_FMR(CAN2) >> 8) & 0x3F); - - for (int i = 0; i < nextUserMessageIndex; i++) - { - if (userIds[i] > 0x7ff) - { - extIdList[extIdIndex] = userIds[i]; - extIdIndex++; - } - else - { - idList[idIndex] = userIds[i]; - idIndex++; - } - - if (idIndex == IDS_PER_BANK) - { - SetFilterBank(idIndex, filterId, idList); - } - if (extIdIndex == EXT_IDS_PER_BANK) - { - SetFilterBank29(extIdIndex, filterId, extIdList); - } - } - - forEachCanMap(curMap, canRecvMap) - { - if (curMap->canId > 0x7ff) - { - extIdList[extIdIndex] = curMap->canId; - extIdIndex++; - } - else - { - idList[idIndex] = curMap->canId; - idIndex++; - } - - if (idIndex == IDS_PER_BANK) - { - SetFilterBank(idIndex, filterId, idList); - } - if (extIdIndex == EXT_IDS_PER_BANK) - { - SetFilterBank29(extIdIndex, filterId, extIdList); - } - } - - //loop terminates before adding last set of filters - if (idIndex > 0) - { - SetFilterBank(idIndex, filterId, idList); - } - if (extIdIndex > 0) - { - SetFilterBank29(extIdIndex, filterId, extIdList); - } -} - -int Can::LoadFromFlash() -{ - uint32_t baseAddress = GetFlashAddress(); - uint32_t storedCrc = *(uint32_t*)CRC_ADDRESS(baseAddress); - uint32_t crc; - - crc_reset(); - crc = crc_calculate_block((uint32_t*)baseAddress, SENDMAP_WORDS + RECVMAP_WORDS + POSMAP_WORDS); - - if (storedCrc == crc) - { - memcpy32((int*)canSendMap, (int*)SENDMAP_ADDRESS(baseAddress), SENDMAP_WORDS); - memcpy32((int*)canRecvMap, (int*)RECVMAP_ADDRESS(baseAddress), RECVMAP_WORDS); - memcpy32((int*)canPosMap, (int*)POSMAP_ADDRESS(baseAddress), POSMAP_WORDS); - ReplaceParamUidByEnum(canSendMap); - ReplaceParamUidByEnum(canRecvMap); - return 1; - } - return 0; -} - -int Can::RemoveFromMap(CANIDMAP *canMap, Param::PARAM_NUM param) -{ - int removed = 0; - CANPOS *lastPosMap; - - forEachCanMap(curMap, canMap) - { - lastPosMap = 0; - - forEachPosMap(curPos, curMap) - { - if (curPos->mapParam == param) - { - if (lastPosMap != 0) - { - lastPosMap->next = curPos->next; - } - else - { - curMap->first = curPos->next; - } - } - lastPosMap = curPos; - } - } - - return removed; -} - -int Can::Add(CANIDMAP *canMap, Param::PARAM_NUM param, uint32_t canId, uint8_t offsetBits, uint8_t length, float gain, int8_t offset) -{ - if (canId > 0x1fffffff) return CAN_ERR_INVALID_ID; - if (offsetBits > 63) return CAN_ERR_INVALID_OFS; - if (length > 32) return CAN_ERR_INVALID_LEN; - - CANIDMAP *existingMap = FindById(canMap, canId); - - if (0 == existingMap) - { - for (int i = 0; i < MAX_MESSAGES; i++) - { - if (canMap[i].first == MAX_ITEMS) - { - existingMap = &canMap[i]; - break; - } - } - - if (0 == existingMap) - return CAN_ERR_MAXMESSAGES; - - existingMap->canId = canId; - } - - int freeIndex; - - for (freeIndex = 0; freeIndex < MAX_ITEMS && canPosMap[freeIndex].next != ITEM_UNSET; freeIndex++); - - if (freeIndex == MAX_ITEMS) - return CAN_ERR_MAXITEMS; - - CANPOS* precedingItem = 0; - - for (int precedingIndex = existingMap->first; precedingIndex != MAX_ITEMS; precedingIndex = canPosMap[precedingIndex].next) - precedingItem = &canPosMap[precedingIndex]; - - CANPOS* freeItem = &canPosMap[freeIndex]; - freeItem->mapParam = param; - freeItem->gain = gain; - freeItem->offset = offset; - freeItem->offsetBits = offsetBits; - freeItem->numBits = length; - freeItem->next = MAX_ITEMS; - - if (precedingItem == 0) //first item for this can ID - { - existingMap->first = freeIndex; - } - else - { - precedingItem->next = freeIndex; - } - - int count = 0; - - forEachCanMap(curMap, canMap) - count++; - - return count; -} - -void Can::ClearMap(CANIDMAP *canMap) -{ - for (int i = 0; i < MAX_MESSAGES; i++) - { - canMap[i].first = MAX_ITEMS; - } - - //Initialize also tail to ITEM_UNSET - for (int i = 0; i < (MAX_ITEMS + 1); i++) - { - canPosMap[i].next = ITEM_UNSET; - } -} - -Can::CANIDMAP* Can::FindById(CANIDMAP *canMap, uint32_t canId) -{ - forEachCanMap(curMap, canMap) - { - if (curMap->canId == canId) - return curMap; - } - return 0; -} - -uint32_t Can::SaveToFlash(uint32_t baseAddress, uint32_t* data, int len) -{ - uint32_t crc = 0; - - for (int idx = 0; idx < len; idx++) - { - crc = crc_calculate(*data); - flash_program_word(baseAddress + idx * sizeof(uint32_t), *data); - data++; - } - - return crc; -} - -int Can::CopyIdMapExcept(CANIDMAP *source, CANIDMAP *dest, Param::PARAM_NUM param) -{ - int i = 0, removed = 0; - int j = 0; - - forEachCanMap(curMap, source) - { - bool discardId = true; - - forEachPosMap(curPos, curMap) - { - if (curPos->mapParam != param) - { - discardId = false; - canPosMap[j] = *curPos; - j++; - } - else - { - removed++; - } - } - - if (!discardId) - { - dest[i].canId = curMap->canId; - i++; - } - } - - return removed; -} - -void Can::ReplaceParamEnumByUid(CANIDMAP *canMap) -{ - forEachCanMap(curMap, canMap) - { - forEachPosMap(curPos, curMap) - { - const Param::Attributes* attr = Param::GetAttrib((Param::PARAM_NUM)curPos->mapParam); - curPos->mapParam = (uint16_t)attr->id; - } - } -} - -void Can::ReplaceParamUidByEnum(CANIDMAP *canMap) -{ - forEachCanMap(curMap, canMap) - { - forEachPosMap(curPos, curMap) - { - Param::PARAM_NUM param = Param::NumFromId(curPos->mapParam); - curPos->mapParam = param; - } - } -} - -uint32_t Can::GetFlashAddress() -{ - uint32_t flashSize = desig_get_flash_size(); - - //Always save CAN mapping to second-to-last flash page - return FLASH_BASE + flashSize * 1024 - FLASH_PAGE_SIZE * (canDev == CAN1 ? CAN1_BLKNUM : CAN2_BLKNUM); -} - -/* Interrupt service routines */ -extern "C" void usb_lp_can_rx0_isr(void) -{ - Can::GetInterface(0)->HandleRx(0); -} - -extern "C" void can_rx1_isr() -{ - Can::GetInterface(0)->HandleRx(1); -} - -extern "C" void usb_hp_can_tx_isr() -{ - Can::GetInterface(0)->HandleTx(); -} - -extern "C" void can2_rx0_isr() -{ - Can::GetInterface(1)->HandleRx(0); -} - -extern "C" void can2_rx1_isr() -{ - Can::GetInterface(1)->HandleRx(1); -} - -extern "C" void can2_tx_isr() -{ - Can::GetInterface(1)->HandleTx(); -} diff --git a/libopeninv/src/stm32scheduler.cpp b/libopeninv/src/stm32scheduler.cpp deleted file mode 100644 index 150d2c1..0000000 --- a/libopeninv/src/stm32scheduler.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2017 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include "stm32scheduler.h" - -/* return CCRc of TIMt */ -#define TIM_CCR(t,c) (*(uint32_t *)(&TIM_CCR1(t) + (c))) - -const enum tim_oc_id Stm32Scheduler::ocMap[MAX_TASKS] = { TIM_OC1, TIM_OC2, TIM_OC3, TIM_OC4 }; - -Stm32Scheduler::Stm32Scheduler(uint32_t timer) -{ - this->timer = timer; - /* Setup timers upcounting and auto preload enable */ - timer_enable_preload(timer); - timer_direction_up(timer); - /* Set prescaler to count at 100 kHz = 72 MHz/7200 - 1 */ - timer_set_prescaler(timer, 719); - /* Maximum counter value */ - timer_set_period(timer, 0xFFFF); - - nextTask = 0; -} - -void Stm32Scheduler::AddTask(void (*function)(void), uint16_t period) -{ - if (nextTask >= MAX_TASKS) return; - /* Disable timer */ - timer_disable_counter(timer); - - timer_set_oc_mode(timer, ocMap[nextTask], TIM_OCM_ACTIVE); - timer_set_oc_value(timer, ocMap[nextTask], 0); - - /* Assign task function and period */ - functions[nextTask] = function; - periods [nextTask] = period * 100; - - /* Enable interrupt for that channel */ - timer_enable_irq(timer, TIM_DIER_CC1IE << nextTask); - - /* Reset counter */ - timer_set_counter(timer, 0); - - /* Enable timer */ - timer_enable_counter(timer); - - nextTask++; -} - -void Stm32Scheduler::Run() -{ - for (int i = 0; i < nextTask; i++) - { - if (timer_get_flag(timer, TIM_SR_CC1IF << i)) - { - uint16_t start = timer_get_counter(timer); - - TIM_CCR(timer, i) += periods[i]; - functions[i](); - execTicks[i] = timer_get_counter(timer) - start; - } - } - timer_clear_flag(timer, TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF); -} - -int Stm32Scheduler::GetCpuLoad() -{ - int totalLoad = 0; - for (int i = 0; i < nextTask; i++) - { - int load = (10 * execTicks[i]) / periods[i]; - totalLoad += load; - } - return totalLoad; -} diff --git a/libopeninv/src/terminal.cpp b/libopeninv/src/terminal.cpp deleted file mode 100644 index 4b430f3..0000000 --- a/libopeninv/src/terminal.cpp +++ /dev/null @@ -1,310 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2011 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "my_string.h" -#include -#include -#include -#include -#include "terminal.h" -#include "printf.h" - -#define HWINFO_ENTRIES (sizeof(hwInfo) / sizeof(struct HwInfo)) - -#ifndef USART_BAUDRATE -#define USART_BAUDRATE 115200 -#endif // USART_BAUDRATE - -const Terminal::HwInfo Terminal::hwInfo[] = -{ - { USART1, DMA_CHANNEL4, DMA_CHANNEL5, GPIOA, GPIO_USART1_TX, GPIOB, GPIO_USART1_RE_TX }, - { USART2, DMA_CHANNEL7, DMA_CHANNEL6, GPIOA, GPIO_USART2_TX, GPIOD, GPIO_USART2_RE_TX }, - { USART3, DMA_CHANNEL2, DMA_CHANNEL3, GPIOB, GPIO_USART3_TX, GPIOC, GPIO_USART3_PR_TX }, -}; - -Terminal* Terminal::defaultTerminal; - -Terminal::Terminal(uint32_t usart, const TERM_CMD* commands, bool remap) -: usart(usart), - remap(remap), - termCmds(commands), - nodeId(1), - enabled(true), - txDmaEnabled(true), - pCurCmd(NULL), - lastIdx(0), - curBuf(0), - curIdx(0), - firstSend(true) -{ - //Search info entry - hw = hwInfo; - for (uint32_t i = 0; i < HWINFO_ENTRIES; i++) - { - if (hw->usart == usart) break; - hw++; - } - - defaultTerminal = this; - - gpio_set_mode(remap ? hw->port_re : hw->port, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, remap ? hw->pin_re : hw->pin); - - usart_set_baudrate(usart, USART_BAUDRATE); - usart_set_databits(usart, 8); - usart_set_stopbits(usart, USART_STOPBITS_2); - usart_set_mode(usart, USART_MODE_TX_RX); - usart_set_parity(usart, USART_PARITY_NONE); - usart_set_flow_control(usart, USART_FLOWCONTROL_NONE); - usart_enable_rx_dma(usart); - usart_enable_tx_dma(usart); - - dma_channel_reset(DMA1, hw->dmatx); - dma_set_read_from_memory(DMA1, hw->dmatx); - dma_set_peripheral_address(DMA1, hw->dmatx, (uint32_t)&USART_DR(usart)); - dma_set_peripheral_size(DMA1, hw->dmatx, DMA_CCR_PSIZE_8BIT); - dma_set_memory_size(DMA1, hw->dmatx, DMA_CCR_MSIZE_8BIT); - dma_enable_memory_increment_mode(DMA1, hw->dmatx); - - dma_channel_reset(DMA1, hw->dmarx); - dma_set_peripheral_address(DMA1, hw->dmarx, (uint32_t)&USART_DR(usart)); - dma_set_peripheral_size(DMA1, hw->dmarx, DMA_CCR_PSIZE_8BIT); - dma_set_memory_size(DMA1, hw->dmarx, DMA_CCR_MSIZE_8BIT); - dma_enable_memory_increment_mode(DMA1, hw->dmarx); - dma_enable_channel(DMA1, hw->dmarx); - - ResetDMA(); - - usart_enable(usart); -} - -/** Run the terminal */ -void Terminal::Run() -{ - int numRcvd = dma_get_number_of_data(DMA1, hw->dmarx); - int currentIdx = bufSize - numRcvd; - - if (0 == numRcvd) - ResetDMA(); - - while (lastIdx < currentIdx) //echo - usart_send_blocking(usart, inBuf[lastIdx++]); - - if (currentIdx > 0) - { - if (inBuf[currentIdx - 1] == '\n' || inBuf[currentIdx - 1] == '\r') - { - inBuf[currentIdx] = 0; - lastIdx = 0; - char *space = (char*)my_strchr(inBuf, ' '); - - if (0 == *space) //No args after command, look for end of line - { - space = (char*)my_strchr(inBuf, '\n'); - args[0] = 0; - } - else //There are arguments, copy everything behind the space - { - my_strcpy(args, space + 1); - } - - if (0 == *space) //No \n found? try \r - space = (char*)my_strchr(inBuf, '\r'); - - *space = 0; - pCurCmd = NULL; - - if (my_strcmp(inBuf, "enableuart") == 0) - { - EnableUart(args); - currentIdx = 0; //Prevent unknown command message - } - else if (my_strcmp(inBuf, "fastuart") == 0) - { - FastUart(args); - currentIdx = 0; - } - else - { - pCurCmd = CmdLookup(inBuf); - } - - ResetDMA(); - - if (NULL != pCurCmd) - { - usart_wait_send_ready(usart); - pCurCmd->CmdFunc(this, args); - } - else if (currentIdx > 1 && enabled) - { - Send("Unknown command sequence\r\n"); - } - } - else if (inBuf[0] == '!' && NULL != pCurCmd) - { - ResetDMA(); - lastIdx = 0; - pCurCmd->CmdFunc(this, args); - } - } -} - -void Terminal::SetNodeId(uint8_t id) -{ - char one[] = { '1', 0 }; - char buf[4]; - nodeId = id; - - if (nodeId != 1) - { - Send("Disabling terminal, type 'enableuart "); - my_ltoa(buf, id, 10); - Send(buf); - Send("' to re-enable\r\n"); - } - - EnableUart(one); -} - -/* - * Revision 1 hardware can only use synchronous sending as the DMA channel is - * occupied by the encoder timer (TIM3, channel 3). - * All other hardware can use DMA for seamless sending of data. We use double - * buffering, so while one buffer is sent by DMA we can prepare the other - * buffer to go next. -*/ -void Terminal::PutChar(char c) -{ - if (!txDmaEnabled) - { - usart_send_blocking(usart, c); - } - else if (c == '\n' || curIdx == (bufSize - 1)) - { - outBuf[curBuf][curIdx] = c; - - while (!dma_get_interrupt_flag(DMA1, hw->dmatx, DMA_TCIF) && !firstSend); - - dma_disable_channel(DMA1, hw->dmatx); - dma_set_number_of_data(DMA1, hw->dmatx, curIdx + 1); - dma_set_memory_address(DMA1, hw->dmatx, (uint32_t)outBuf[curBuf]); - dma_clear_interrupt_flags(DMA1, hw->dmatx, DMA_TCIF); - dma_enable_channel(DMA1, hw->dmatx); - - curBuf = !curBuf; //switch buffers - firstSend = false; //only needed once so we don't get stuck in the while loop above - curIdx = 0; - } - else - { - outBuf[curBuf][curIdx] = c; - curIdx++; - } -} - -bool Terminal::KeyPressed() -{ - return usart_get_flag(usart, USART_SR_RXNE); -} - -void Terminal::FlushInput() -{ - usart_recv(usart); -} - -void Terminal::DisableTxDMA() -{ - txDmaEnabled = false; - dma_disable_channel(DMA1, hw->dmatx); - usart_disable_tx_dma(usart); -} - -void Terminal::ResetDMA() -{ - dma_disable_channel(DMA1, hw->dmarx); - dma_set_memory_address(DMA1, hw->dmarx, (uint32_t)inBuf); - dma_set_number_of_data(DMA1, hw->dmarx, bufSize); - dma_enable_channel(DMA1, hw->dmarx); -} - -void Terminal::EnableUart(char* arg) -{ - arg = my_trim(arg); - int val = my_atoi(arg); - - if (val == nodeId) - { - enabled = true; - gpio_set_mode(remap ? hw->port_re : hw->port, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, remap ? hw->pin_re : hw->pin); - Send("OK\r\n"); - } - else - { - enabled = false; - gpio_set_mode(remap ? hw->port_re : hw->port, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, remap ? hw->pin_re : hw->pin); - } -} - -void Terminal::FastUart(char *arg) -{ - arg = my_trim(arg); - int baud = arg[0] == '0' ? USART_BAUDRATE : 921600; - if (enabled) - { - Send("OK\r\n"); - Send("Baud rate now 921600\r\n"); - } - usart_set_baudrate(usart, baud); - usart_set_stopbits(usart, USART_STOPBITS_1); -} - -const TERM_CMD* Terminal::CmdLookup(char *buf) -{ - const TERM_CMD *pCmd = termCmds; - - if (!enabled) return NULL; - - for (; NULL != pCmd->cmd; pCmd++) - { - if (0 == my_strcmp(buf, pCmd->cmd)) - { - break; - } - } - if (NULL == pCmd->cmd) - { - pCmd = NULL; - } - return pCmd; -} - -void Terminal::Send(const char *str) -{ - for (;*str > 0; str++) - usart_send_blocking(usart, *str); -} - -//Backward compatibility for printf -extern "C" void putchar(int c) -{ - Terminal::defaultTerminal->PutChar(c); -} diff --git a/libopeninv/src/terminalcommands.cpp b/libopeninv/src/terminalcommands.cpp deleted file mode 100644 index 01a19af..0000000 --- a/libopeninv/src/terminalcommands.cpp +++ /dev/null @@ -1,426 +0,0 @@ -/* - * This file is part of the libopeninv project. - * - * Copyright (C) 2021 Johannes Huebner - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include "hwdefs.h" -#include "terminal.h" -#include "params.h" -#include "my_string.h" -#include "my_fp.h" -#include "printf.h" -#include "param_save.h" -#include "stm32_can.h" -#include "terminalcommands.h" - -static Terminal* curTerm = NULL; - -void TerminalCommands::ParamSet(Terminal* term, char* arg) -{ - char *pParamVal; - s32fp val; - Param::PARAM_NUM idx; - - arg = my_trim(arg); - pParamVal = (char *)my_strchr(arg, ' '); - - if (*pParamVal == 0) - { - fprintf(term, "No parameter value given\r\n"); - return; - } - - *pParamVal = 0; - pParamVal++; - - val = fp_atoi(pParamVal, FRAC_DIGITS); - idx = Param::NumFromString(arg); - - if (Param::PARAM_INVALID != idx) - { - if (0 == Param::Set(idx, val)) - { - fprintf(term, "Set OK\r\n"); - } - else - { - fprintf(term, "Value out of range\r\n"); - } - } - else - { - fprintf(term, "Unknown parameter %s\r\n", arg); - } -} - -void TerminalCommands::ParamGet(Terminal* term, char* arg) -{ - Param::PARAM_NUM idx; - s32fp val; - char* comma; - char orig; - - arg = my_trim(arg); - - do - { - comma = (char*)my_strchr(arg, ','); - orig = *comma; - *comma = 0; - - idx = Param::NumFromString(arg); - - if (Param::PARAM_INVALID != idx) - { - val = Param::Get(idx); - fprintf(term, "%f\r\n", val); - } - else - { - fprintf(term, "Unknown parameter: '%s'\r\n", arg); - } - - *comma = orig; - arg = comma + 1; - } while (',' == *comma); -} - -void TerminalCommands::ParamFlag(Terminal* term, char *arg) -{ - char *pFlagVal; - Param::PARAM_NUM idx; - - arg = my_trim(arg); - pFlagVal = (char *)my_strchr(arg, ' '); - - if (*pFlagVal == 0) - { - fprintf(term, "No flag given\r\n"); - return; - } - - *pFlagVal = 0; - pFlagVal++; - - idx = Param::NumFromString(arg); - - if (Param::PARAM_INVALID != idx) - { - bool clearFlag = false; - Param::PARAM_FLAG flag = Param::FLAG_NONE; - - if (pFlagVal[0] == '!' || pFlagVal[0] == '~' || pFlagVal[0] == '/') - { - clearFlag = true; - pFlagVal++; - } - - if (my_strcmp("hidden", pFlagVal) == 0) - { - flag = Param::FLAG_HIDDEN; - } - - if (flag != Param::FLAG_NONE) - { - if (clearFlag) - { - Param::ClearFlag(idx, flag); - } - else - { - Param::SetFlag(idx, flag); - } - fprintf(term, "Flag change OK\r\n"); - } - else - { - fprintf(term, "Unknown flag\r\n"); - } - } - else - { - fprintf(term, "Unknown parameter %s\r\n", arg); - } -} - -void TerminalCommands::ParamStream(Terminal* term, char *arg) -{ - Param::PARAM_NUM indexes[10]; - int maxIndex = sizeof(indexes) / sizeof(Param::PARAM_NUM); - int curIndex = 0; - int repetitions = -1; - char* comma; - char orig; - - arg = my_trim(arg); - repetitions = my_atoi(arg); - arg = (char*)my_strchr(arg, ' '); - - if (0 == *arg) - { - fprintf(term, "Usage: stream n val1,val2...\r\n"); - return; - } - arg++; //move behind space - - do - { - comma = (char*)my_strchr(arg, ','); - orig = *comma; - *comma = 0; - - Param::PARAM_NUM idx = Param::NumFromString(arg); - - *comma = orig; - arg = comma + 1; - - if (Param::PARAM_INVALID != idx) - { - indexes[curIndex] = idx; - curIndex++; - } - else - { - fprintf(term, "Unknown parameter\r\n"); - } - } while (',' == *comma && curIndex < maxIndex); - - maxIndex = curIndex; - term->FlushInput(); - - while (!term->KeyPressed() && (repetitions > 0 || repetitions == -1)) - { - comma = (char*)""; - for (curIndex = 0; curIndex < maxIndex; curIndex++) - { - s32fp val = Param::Get(indexes[curIndex]); - fprintf(term, "%s%f", comma, val); - comma = (char*)","; - } - fprintf(term, "\r\n"); - if (repetitions != -1) - repetitions--; - } -} - -void TerminalCommands::PrintParamsJson(Terminal* term, char *arg) -{ - arg = my_trim(arg); - - const Param::Attributes *pAtr; - char comma = ' '; - bool printHidden = arg[0] == 'h'; - - fprintf(term, "{"); - for (uint32_t idx = 0; idx < Param::PARAM_LAST; idx++) - { - uint32_t canId; - uint8_t canOffset, canLength; - bool isRx; - float canGain; - pAtr = Param::GetAttrib((Param::PARAM_NUM)idx); - - if ((Param::GetFlag((Param::PARAM_NUM)idx) & Param::FLAG_HIDDEN) == 0 || printHidden) - { - fprintf(term, "%c\r\n \"%s\": {\"unit\":\"%s\",\"value\":%f,",comma, pAtr->name, pAtr->unit, Param::Get((Param::PARAM_NUM)idx)); - - if (Can::GetInterface(0)->FindMap((Param::PARAM_NUM)idx, canId, canOffset, canLength, canGain, isRx)) - { - fprintf(term, "\"canid\":%d,\"canoffset\":%d,\"canlength\":%d,\"cangain\":%f,\"isrx\":%s,", - canId, canOffset, canLength, FP_FROMFLT(canGain), isRx ? "true" : "false"); - } - - if (Param::IsParam((Param::PARAM_NUM)idx)) - { - fprintf(term, "\"isparam\":true,\"minimum\":%f,\"maximum\":%f,\"default\":%f,\"category\":\"%s\",\"i\":%d}", - pAtr->min, pAtr->max, pAtr->def, pAtr->category, idx); - } - else - { - fprintf(term, "\"isparam\":false}"); - } - comma = ','; - } - } - fprintf(term, "\r\n}\r\n"); -} - -//cantx param id offset len gain -void TerminalCommands::MapCan(Terminal* term, char *arg) -{ - Param::PARAM_NUM paramIdx = Param::PARAM_INVALID; - int values[4]; - int result; - char op; - char *ending; - const int numArgs = 4; - - arg = my_trim(arg); - - if (arg[0] == 'p') - { - while (curTerm != NULL); //lock - curTerm = term; - Can::GetInterface(0)->IterateCanMap(PrintCanMap); - curTerm = NULL; - return; - } - - if (arg[0] == 'c') - { - Can::GetInterface(0)->Clear(); - fprintf(term, "All message definitions cleared\r\n"); - return; - } - - op = arg[0]; - arg = (char *)my_strchr(arg, ' '); - - if (0 == *arg) - { - fprintf(term, "Missing argument\r\n"); - return; - } - - arg = my_trim(arg); - ending = (char *)my_strchr(arg, ' '); - - if (*ending == 0 && op != 'd') - { - fprintf(term, "Missing argument\r\n"); - return; - } - - *ending = 0; - paramIdx = Param::NumFromString(arg); - arg = my_trim(ending + 1); - - if (Param::PARAM_INVALID == paramIdx) - { - fprintf(term, "Unknown parameter\r\n"); - return; - } - - if (op == 'd') - { - result = Can::GetInterface(0)->Remove(paramIdx); - fprintf(term, "%d entries removed\r\n", result); - return; - } - - for (int i = 0; i < numArgs; i++) - { - ending = (char *)my_strchr(arg, ' '); - - if (0 == *ending && i < (numArgs - 1)) - { - fprintf(term, "Missing argument\r\n"); - return; - } - - *ending = 0; - int iVal = my_atoi(arg); - - //allow gain values < 1 and re-interpret them - if (i == (numArgs - 1) && iVal == 0) - { - values[i] = fp_atoi(arg, 16); - //The can values interprets abs(values) < 32 as gain and > 32 as divider - //e.g. 0.25 means integer division by 4 so we need to calculate div = 1/value - //0.25 with 16 decimals is 16384, 65536/16384 = 4 - values[i] = (32 << 16) / values[i]; - } - else - { - values[i] = iVal; - } - - arg = my_trim(ending + 1); - } - - if (op == 't') - { - result = Can::GetInterface(0)->AddSend(paramIdx, values[0], values[1], values[2], values[3]); - } - else - { - result = Can::GetInterface(0)->AddRecv(paramIdx, values[0], values[1], values[2], values[3]); - } - - switch (result) - { - case CAN_ERR_INVALID_ID: - fprintf(term, "Invalid CAN Id %x\r\n", values[0]); - break; - case CAN_ERR_INVALID_OFS: - fprintf(term, "Invalid Offset %d\r\n", values[1]); - break; - case CAN_ERR_INVALID_LEN: - fprintf(term, "Invalid length %d\r\n", values[2]); - break; - case CAN_ERR_MAXITEMS: - fprintf(term, "Cannot map anymore items to CAN id %d\r\n", values[0]); - break; - case CAN_ERR_MAXMESSAGES: - fprintf(term, "Max message count reached\r\n"); - break; - default: - fprintf(term, "CAN map successful, %d message%s active\r\n", result, result > 1 ? "s" : ""); - } -} - -void TerminalCommands::SaveParameters(Terminal* term, char *arg) -{ - arg = arg; - Can::GetInterface(0)->Save(); - fprintf(term, "CANMAP stored\r\n"); - uint32_t crc = parm_save(); - fprintf(term, "Parameters stored, CRC=%x\r\n", crc); -} - -void TerminalCommands::LoadParameters(Terminal* term, char *arg) -{ - arg = arg; - if (0 == parm_load()) - { - Param::Change((Param::PARAM_NUM)0); - fprintf(term, "Parameters loaded\r\n"); - } - else - { - fprintf(term, "Parameter CRC error\r\n"); - } -} - -void TerminalCommands::Reset(Terminal* term, char *arg) -{ - term = term; - arg = arg; - scb_reset_system(); -} - -void TerminalCommands::PrintCanMap(Param::PARAM_NUM param, uint32_t canid, uint8_t offset, uint8_t length, float gain, bool rx) -{ - const char* name = Param::GetAttrib(param)->name; - fprintf(curTerm, "can "); - - if (rx) - fprintf(curTerm, "rx "); - else - fprintf(curTerm, "tx "); - fprintf(curTerm, "%s %d %d %d %f\r\n", name, canid, offset, length, FP_FROMFLT(gain)); -}